Memory structure with 4F2 optimized cell layout

Abstract

A 4F2 two-dimensional dynamic random access memory array may include vertical pillar transistors arranged in a honeycomb pattern to maximize available capacitor footprint on top of the memory array. Bit lines may partially intersect bottom source / drain regions of two adjacent rows of the vertical transistors, where the rows may be offset based on the honeycomb pattern. The word line may have a varying width that increases as the word line surrounds the gate region of the transistor and decreases between adjacent transistors. The transistor stages may each be individually and incrementally formed, first completing the bottom source / drain region and the bit line, then the gate region and the word line, and finally the top source / drain region and the capacitor.

Description

Technical Field

[0001] This application requests the patent filed on March 17, 2023, entitled "MEMORY STRUCTURE WITH 4F". 2 The rights and priorities of U.S. non-provisional application No. 18 / 186,091, entitled “OPTIMIZED CELL LAYOUT”, the entire substantive content of which is incorporated herein by reference.

[0002] This disclosure broadly describes the use of 4F 2 Design of a two-dimensional dynamic random access memory array. More specifically, this disclosure describes a design for a 4F... 2 A hexagonal layout for a memory array with increased bit and word line spacing. Background Technology

[0003] Over time, dynamic random access memory (DRAM) architectures have continued to shrink. For example, the DRAM cell architecture of one transistor and one capacitor (1T-1C) has been successfully scaled down from 8F. 2 Size reduced to 6F 2 Dimensions (where F is the minimum feature size). Methods for further reducing the element size to 4F have been proposed. 2 The design. However, with the continuous shrinking of feature sizes, challenges arise when rapidly reducing DRAM cell size. For example, the proposed 4F 2 The design often increases leakage current and reduces the spacing between word lines and bit lines in the memory array. This makes it difficult to isolate memory cells and reduces the size of the cell capacitors. Furthermore, the manufacturing process is not well-suited for such small dimensions, especially for 4F... 2 The units are patterned and formed. Therefore, improvements are needed to the technology in this field. Summary of the Invention

[0004] In some embodiments, a two-dimensional (2D) DRAM array may include: a plurality of bit lines arranged in a first horizontal direction; a plurality of word lines arranged in a second horizontal direction; and a plurality of transistors arranged in a vertical direction orthogonal to the first and second horizontal directions, such that the plurality of bit lines intersect the bottom source / drain regions of the plurality of transistors, and the plurality of word lines intersect the gate regions of the plurality of transistors. The plurality of transistors may be arranged in a honeycomb pattern.

[0005] In some embodiments, a 2D DRAM array may include: a plurality of bit lines arranged in a first horizontal direction; a plurality of word lines arranged in a second horizontal direction; and a plurality of transistors arranged in a vertical direction orthogonal to the first and second horizontal directions, such that the plurality of bit lines intersect the bottom source / drain regions of the plurality of transistors, and the plurality of word lines intersect the gate regions of the plurality of transistors. The spacing between the plurality of bit lines may be greater than 2F, where F is defined as a critical feature size, and the cell area of ​​the 2D DRAM array is defined as 4F. 2 .

[0006] In some embodiments, a method of forming a 2D DRAM array may include: forming first source / drain regions for a plurality of vertical transistors, and forming a plurality of bit lines in contact with the first source / drain regions. The method may further include: after forming the first source / drain regions and the plurality of bit lines, forming gate regions for the plurality of vertical transistors, and forming a plurality of word lines in contact with the gate regions. The method may further include: after forming the gate regions and the plurality of word lines, forming second source / drain regions for the plurality of vertical transistors, and forming a plurality of capacitors in contact with the second source / drain regions.

[0007] In any implementation, any and all of the following features may be implemented in any combination and without limitation. The plurality of bit lines may intersect only partially with the bottom source / drain regions of the plurality of transistors. The array may also include a plurality of spacers between the plurality of bit lines, wherein the plurality of spacers may also partially intersect with the bottom source / drain regions of the plurality of transistors. The spacing between the plurality of bit lines is greater than 2F. The cell area of ​​the 2D DRAM array may be 4F. 2 Where F can be defined as the feature size. The array may also include multiple capacitors disposed at the top source / drain regions of the plurality of transistors, wherein the plurality of capacitors may have a value greater than or approximately [value missing]. The honeycomb pattern can arrange the plurality of transistors such that one of the transistors can be adjacent to six other transistors. The plurality of word lines can have non-uniform widths, such that the plurality of bit lines have non-uniform widths within the 2D DRAM array. The plurality of word lines can be thinner between the plurality of transistors than around the plurality of transistors. The array can also include a plurality of spacers between the plurality of word lines, wherein the plurality of spacers can have a triangular wave pattern. The spacing of the plurality of word lines can be greater than 2F. The gate regions of the plurality of transistors can include epitaxial silicon, which can be formed from a silicon substrate below the plurality of transistors using an epitaxial growth process. Forming the plurality of first source / drain regions and the plurality of bit lines can include: forming a sacrificial layer over the silicon substrate; etching a plurality of holes in the sacrificial layer; forming the plurality of first source / drain regions in the plurality of holes; removing the sacrificial layer; forming bit line material around the plurality of first source / drain regions to replace the sacrificial layer; and forming the plurality of bit lines around the plurality of first source / drain regions from the bit line material. Forming the gate regions and the plurality of word lines may include: forming a sacrificial layer above the first source / drain regions and the plurality of word lines; etching a plurality of vias perpendicularly aligned to the first source / drain regions in the sacrificial layer; forming the gate regions in the plurality of vias; removing the sacrificial layer; forming word line material around the gate regions; and forming the plurality of word lines from the word line material around the gate regions. Forming the second source / drain regions and the plurality of capacitors may include: forming a sacrificial layer above the gate regions and the plurality of word lines; etching a plurality of vias perpendicularly aligned to the gate regions in the sacrificial layer; forming the second source / drain regions in the plurality of vias; and forming the plurality of capacitors above the second source / drain regions. The gate regions of the plurality of vertical transistors are formed by selective epitaxial growth. Attached Figure Description

[0008] The nature and advantages of various embodiments can be further understood by referring to the remainder of this specification and the accompanying drawings, in which similar reference numerals are used in several drawings to refer to similar parts. In some cases, sub-labels are associated with reference numerals to indicate one of a plurality of similar parts. When a reference numeral is mentioned without referring to an existing sub-label, it is intended to refer to all such plurality of similar parts.

[0009] Figure 1A-Figure 1B It shows the traditional 4F 2 Top view and 3D view of the memory array.

[0010] Figures 2A-2C This illustrates a 4F system with optimized memory cell spacing, according to some embodiments. 2 Top view and 3D view of the memory array.

[0011] Figure 3 A flowchart 300 is shown illustrating a method for forming a 2D DRAM array according to some embodiments.

[0012] Figures 4A-4Q The diagram illustrates the incremental stages of a process for forming a 2D DRAM array, according to some implementation methods. Detailed Implementation

[0013] This disclosure describes 4F 2 A two-dimensional dynamic random access memory (DRAM) array can include vertical pillar transistors arranged in a honeycomb pattern to maximize the available capacitor footprint at the top of the memory array. Bit lines may partially intersect the bottom source / drain regions of two adjacent rows of vertical transistors, where rows may be offset based on the honeycomb pattern. Word lines may have varying widths, increasing as the word lines surround the gate region of the transistors and decreasing between adjacent transistors. Transistor stages can be formed individually and incrementally, first completing the bottom source / drain regions and bit lines, then the gate regions and word lines, and finally the top source / drain regions and capacitors.

[0014] Classified as 4F 2 DRAM arrays are important because they increase the density of DRAM cells in memory arrays. However, as the minimum or critical feature size (called "F") continues to shrink, these existing 4F arrays are becoming increasingly inadequate. 2 Memory array design is becoming increasingly problematic. Specifically, as F approaches below 10 nanometers, these existing 4F... 2 Designs face handling and manufacturing challenges in achieving high density and small device size. These existing 4F... 2 The design may also have performance issues, such as RC delay, increased leakage current, deterioration of isolation between memory cells, reduced capacitor size, and floating body effect of vertical transistors.

[0015] The embodiments described in this disclosure propose a more efficient 4F method for vertical 1T-1C DRAM memory cells. 2 Memory cell layout. Each memory cell region can be defined as a non-rectangular parallelogram, rather than arranging the vertical pillar transistors and capacitors into an orthogonal or rectangular grid. The resulting memory array arranges the vertical memory cells in an offset arrangement, which more efficiently separates the memory cells while still maintaining a 4F. 2Cell area. Offset arrangement of memory cells results in a larger capacitor area and increases the isolation distance between capacitors. Furthermore, the spacing between word lines and bit lines can be increased without increasing the cell area. This reduces the RC latency of charging / discharging memory cells. Additionally, a processing technique is described that eliminates the need for manufacturing existing 4F... 2 Many problems with memory units.

[0016] Figure 1A-Figure 1B It shows the traditional 4F 2 Top view and perspective view of memory array 100. Memory array 100 may include a plurality of word lines 102 arranged in a first layer on a substrate. The word lines 102 may be conductive traces used to select word lines of memory cells in memory array 100. Memory array 100 may also include a plurality of bit lines 104 arranged in a second layer on a substrate. The plurality of bit lines may be conductive traces used to select bit lines of memory cells in memory array 100. Activating one of the plurality of bit lines 104 and one of the plurality of word lines 102 can select an individual cell in memory array 100. The first layer and the second layer may include different metal layers formed at different times during the manufacturing process. For example, the first layer with word lines 102 may be formed over the second layer with bit lines 104 such that the two layers do not intersect.

[0017] Multiple vertical memory cells can be directly arranged at the intersections between the multiple word lines 102 and the multiple bit lines 104. Each of the multiple vertical memory cells may include a vertical transistor, which may be referred to as a vertical pillar transistor. The channel material of the transistor may be formed from a single-crystal silicon pillar. This silicon pillar is formed by etching a substrate. Since the aspect ratio of the etched holes tends to increase as the capacitor diameter and channel diameter decrease, forming such silicon pillars presents difficulties in controlling the size of the silicon pillars. Each of the multiple vertical memory cells may also include a vertical capacitor 106. The vertical memory cell can operate by storing charge on the vertical capacitor 106 to indicate the saved memory state.

[0018] For this traditional 4F 2 Characterizing the cell area 116 of the memory array is useful for comparison with optimized memory arrays described below. For example, the capacitor footprint 108 can be defined as a circular region surrounding each vertical capacitor 106. The capacitor footprint 108 may include the horizontal cross-sectional area of ​​the capacitor, which extends until it contacts the capacitor region of the adjacent memory cell. Assuming the diameter of the vertical capacitor 106 is approximately equal to the critical feature size F, Figure 1A The size of a capacitor with a footprint of 10⁸ can be defined as πF.2 Or, a capacitor with radius F occupies a circular cross-sectional area of ​​108. The word line spacing of the plurality of word lines 102 and the bit line spacing 114 of the plurality of bit lines 104 can be defined as 2F. This makes the total cross-sectional area of ​​the unit cell 116 4F. 2 .

[0019] Figures 2A-2C This illustrates a 4F system with optimized memory cell spacing, according to some embodiments. 2 Top view and perspective view of the memory array. The memory array 200 may include a plurality of bit lines arranged in a first horizontal direction. The first horizontal direction may be located in a layer or plane substantially parallel to the underlying substrate on which the memory array 200 is formed. The memory array 200 may also include a plurality of word lines arranged in a second horizontal direction. The second horizontal direction may also be located in a layer or plane substantially parallel to the underlying substrate and / or the plurality of bit lines. Figure 2B As shown, the second horizontal direction can be approximately orthogonal to the first horizontal direction. Furthermore, the memory array 200 may also include multiple transistors, such as vertical transistors or vertical pillar transistors, arranged in a vertical direction orthogonal to the first and second horizontal directions. Each memory cell in the memory array 200 may include a vertical transistor and a capacitor.

[0020] The arrangement of memory cells in memory array 200 can be characterized and distinguished from the arrangement of memory cells in conventional memory array 100 in several different ways. First, the spacing and arrangement of vertical transistors 220 and capacitors 206 do not necessarily follow a rectangular orthogonal grid pattern as in conventional memory array 100. Instead, capacitors 206 (along with vertical transistors 220) can be spaced in alternating columns, offset by half the distance between vertical transistors 220. For example, the first column of memory cells 230 can be arranged in a first direction (e.g.,...). Figure 2B The memory cells 230 in the first column are arranged in a regular row from left to right. The second column of memory cells 232 can also be arranged in a regular row in the first direction, but the second column of memory cells 232 can be offset from the first column of memory cells 230. For example, as... Figure 2B As shown, the vertical transistor 220 and capacitor 206 in the second column memory cell 232 can be aligned in the middle between the vertical transistor 220 and capacitor 206 in the first column memory cell 230.

[0021] Overall, compared to the orthogonal grid pattern of the conventional memory array 100, the capacitors 206 can be arranged in a "honeycomb" pattern. Figure 2CThis arrangement is illustrated, in which a honeycomb pattern 233 is superimposed on the memory array 200. The honeycomb pattern can be arranged such that each memory cell is surrounded or adjacent to six other memory cells. As shown, each memory cell can be enclosed in a virtual hexagon. Note that the hexagon does not have to be regular and can be vertically or horizontally compressed based on the desired spacing between the memory cells. Other implementations can use regular hexagons (i.e., with interior angles of 60°) to achieve uniform spacing.

[0022] The cell area 216 of memory array 200 can also differ from the rectangular cell area 116 in traditional memory array 100. The cell area 216 can be defined as... Figure 2C One of the hexagons in the diagram. Alternatively, the unit cell area of ​​216 can be defined as the shape formed by connecting the center points of four adjacent capacitors. For example... Figure 2B As shown, the shape of the unit cell area 216 can be a non-rectangular parallelogram. Regardless of the definition used, the unit cell area can still have 4F. 2 The area of ​​the capacitor. However, the cross-sectional area of ​​the capacitor, which occupies an area of ​​208, can be given by the following equation.

[0023]

[0024] Please note that this capacitor occupies an area of ​​208, which is larger than the 100 πF of a traditional memory array. 2 The capacitor footprint is 108. The capacitor footprint of 208 can be defined as the area in which the capacitor has space to be formed within the memory array 200. These capacitors are shown below. Figures 4P-4Q In this embodiment, the capacitor footprint 208 can generally have a larger diameter than the vertical transistor 220. However, the capacitor footprint 208 may be limited by the spacing of the vertical transistors 220. The honeycomb arrangement in these embodiments maximizes the available capacitor footprint 208 without increasing the overall size of the cell area 216. Therefore, one of the many advantages offered by these embodiments is a larger capacitor area while still maintaining a 4F... 2 The area of ​​a single cell.

[0025] Another way to characterize memory array 200 and distinguish it from conventional memory array 100 is by the alignment of reference bit line 204 with respect to the vertical pillars of capacitor 206 and vertical transistor 220. Specifically, in conventional memory array 100, capacitor 106 and vertical transistor 120 are aligned with the intersection point between word line 102 and bit line 104. Vertical transistor 120 is completely surrounded by both word line 102 and bit line 104, such that these lines intersect vertical transistor 120 completely, rather than only partially. In contrast, vertical transistor 220 is not aligned with bit line 204 in memory array 200. Specifically, bit line 204 intersects vertical transistor 220, such that vertical transistor 220 is only about half-surrounded by bit line 204. For example, in Figure 2B In the provided top view, bit lines 204 intersect only the two offset row portions of transistor 220 (below capacitor 206). Therefore, each bit line 204 can intersect the two misaligned row portions of the transistor. The spacer layer 205 between bit lines 204 also intersects the two offset row portions of transistor 220. Since transistors 220 and capacitor 206 do not form linear rows of transistors 220 in a honeycomb arrangement, bit lines 204 can conversely be formed such that they are wide enough to intersect the two offset rows of transistors 220. For example, bit lines 204 can intersect the first side of a pillar in the first column of memory cells 230 and the opposite second side of a pillar in the second column of memory cells 232.

[0026] Since bit line 204 only needs to intersect the row portion of vertical transistor 220, this allows bit line spacing 214 to be larger than bit line spacing 114 of conventional memory array 100. Specifically, bit line spacing 214 can be larger than 2F bit line spacing 114 of conventional memory array 100. When bit line 204 is aligned with the midpoint of vertical transistor 220, bit line spacing can be greater than or approximately 2.31F. Furthermore, bit line 204 can be connected to or contact the sidewalls of bottom source / drain connections 242 (e.g., n-doped source / drain). As will be shown below, the semiconductor pillars of vertical transistor 220 can also be connected to substrate 243, which alleviates the "floating body" problem in DRAM transistors, where the transistor body is not connected to voltage, resulting in floating body or unstable conditions.

[0027] Another way to characterize the memory array 200 is by utilizing the shape of the spacer layers 203 between the word lines 202. To accommodate offset rows of memory cells, the spacer layers 203 between the word lines can be shaped into a "Z" pattern. The spacer layers 203 can also be described as triangular patterns, non-linear patterns, and / or wavy patterns. The spacer layers 203 can also be characterized as following an approximate outline of the vertical transistors 220. For example, the spacer layers 203 can be drawn such that they maintain at least one minimum distance from each vertical transistor 220.

[0028] The memory array 200 can also be characterized by the shape of the word lines 202 themselves. For example, the word lines 202 can also be described as non-uniform, or having a non-uniform width (i.e., the width or distance of word lines 202 between adjacent columns of spacers 203). The width of the word lines 202 can increase around the vertical transistors 220 to a maximum width aligned with the center of the vertical transistors 220, and decrease between the vertical transistors 220 to a thinner minimum width aligned with the midpoint between two adjacent vertical transistors 220 in the same column (e.g., the first column of memory cells 230). The shape of the word lines 202 can also be described as maintaining at least one minimum distance between the vertical transistors 220 and the spacers 203 (e.g., at the midpoint of the vertical transistors 220), and at least one minimum distance between adjacent spacers 203 (e.g., at the midpoint between adjacent vertical transistors 220). The width of the word lines 202 can reach a maximum at the midpoint of the vertical pillars of each vertical transistor 220, and can reach a minimum at the midpoint between the vertical pillars of the vertical transistors 220. This arrangement also increases the word line spacing of memory array 200, making it larger than the 2F spacing of traditional memory array 100.

[0029] Figure 3 A flowchart 300 is shown illustrating a method for forming a 2D DRAM array according to some embodiments. Figures 4A-4Q The diagram illustrates the incremental stages of a process for forming a 2D DRAM array, according to some implementation methods. Figure 3 Examples of each operation described in the text can be found below. Figure 4A-4Q The figures are depicted in the illustrations. However, these figures do not imply any interpretation of the illustrations. Figure 3 The operations described in the flowchart 300 are subject to limitations. Instead, when describing the operations in the flowchart 300, reference will be made only to the example figures below by way of example.

[0030] The method may include: forming a first source / drain region for a plurality of vertical transistors, and forming a plurality of bit lines (302) in contact with the first source / drain region. In summary, this process may incrementally form each stage of the transistor on top of previously completed stages. For example, the first source / drain region and bit lines may be formed during a first processing stage, then the gate region and word lines may be formed during a second processing stage, and the second source / drain region and capacitors may be formed during a third processing stage, wherein each processing stage is completed before the start of the next processing stage.

[0031] Figure 4AA first stack deposition with a first via pattern is shown. The first stack can be formed on a silicon substrate 402. An etch stop layer 404 can be formed above the silicon substrate 402. The etch stop layer 404 can be formed of SiN or other similar materials, and its thickness can be between about 2 nanometers and about 20 nanometers, where the thickness is measured in the vertical direction depicted in the figure. A sacrificial layer 406 can be formed above the etch stop layer 404. The sacrificial layer 406 can be formed of SiO or other similar materials, and its thickness can be between about 5 nanometers and about 50 nanometers. A chemical mechanical polishing (CMP) stop layer 408 can be formed above the sacrificial layer 406. The CMP stop layer 408 can be formed of silicon nitride or other similar materials, and its thickness can be between about 2 nanometers and about 20 nanometers. These layers can be formed using various processes, such as damascene processes, deposition processes, etc.

[0032] like Figure 4A As shown, the surface of the stack can be patterned using a first hole pattern. These holes can represent patterns of transistor pillars for vertical transistors. As shown, these holes 410 can be patterned in a honeycomb pattern as described above. The holes can be patterned using a lithography process, and then etched to form the holes 410. When F is about 10 nanometers, the critical size (CD) of the holes 410 can be between about 5 nanometers and about 15 nanometers (i.e., between about 0.5F and about 1.5F relative to the critical feature size F). Note that the holes 410 can be etched at least to the level of the silicon substrate 402. For example, the holes 410 can be etched to at least expose the top surface of the silicon substrate 402. In some embodiments, the holes 410 can be etched to a level below the top surface of the silicon substrate 402. This allows silicon pillars for vertical transistors to be attached to and / or grown from the silicon substrate 402, as described below.

[0033] Figure 4B This illustrates how the hole 410 can be filled with pillar material 412. For example, a variety of different materials can be used for the pillar material 412 for the vertical pillars of transistors based on this process. For example, the pillar material 412 can include crystalline semiconductors such as silicon, germanium, silicon-germanium, and / or other similar materials. These materials can also be used in the form of polycrystalline semiconductors. In some embodiments, metal oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), can be used for the pillar material 412. In some embodiments, the pillar material 412 can be formed by epitaxially growing epitaxial silicon in the hole 410. The silicon substrate 402 can be used as a bed for growing epitaxial silicon in the hole 410 to achieve a selective epitaxial growth (SEG) process. Alternatively, the pillar material 412 can be formed by conformally filling the hole 410 with a polycrystalline semiconductor layer.

[0034] Figure 4CThe results of a planarization process for removing any overlay caused by filling the hole 410 with strut material 412 are shown. Growing or forming strut material 412 can extend strut material 412 above the top of the hole 410. To create a uniform height for strut material 412, the stack can undergo a planarization process, such as a CMP process, to remove the top portion of the stack. For example, a planarization process can remove any overlay of strut material 412 as well as CMP stop layer 408 until sacrificial layer 406 is exposed.

[0035] Figure 4D The removal of sacrificial layer 406 is illustrated. Sacrificial layer 406 can be removed using a selective etching process. Note that the SiO in sacrificial layer 406 exhibits high selectivity relative to the SiN in etch stop layer 404. These materials are used only by way of example and are not intended to be limiting. Other materials with sufficient selectivity differences to the etching process can be used. The etching process can include a wet etching process or a dry etching process. For example, a wet etching process using diluted HF can be used to selectively remove SiO.

[0036] After removing the sacrificial layer 406, the surface of the pillar material 412 can be doped to form source / drain regions and contacts for bit lines. For example, N-type dopants can be used to dope the surface of the silicon pillar. Dopants can include phosphorus, arsenic, and / or other similar materials. In some embodiments, the doping concentration can be between about 1e19 cm⁻¹. 3 With approximately 1e21 cm 3 The resulting N+ region can be located at a depth ranging from approximately 1 nanometer to approximately 7 nanometers within the pillar material 412.

[0037] Figure 4E The formation of bit line material 416, which can be used for bit lines in memory cells, is illustrated. After the doping process described above, bit line material 416 can be formed to cover etch stop layer 404. In some embodiments, barrier materials such as titanium nitride or tantalum nitride can also be used to form a barrier layer. The barrier layer can be formed prior to the formation of bit line material 416. Bit line material 416 can be formed using any type of deposition process. Bit line material 416 can include N+ polysilicon, titanium, molybdenum, ruthenium, iridium, and / or other similar materials. In some cases, bit line material 416 can be formed such that bit line material 416 extends over or even covers pillar material 412. Therefore, the process can also include performing another planarization process, such as a CMP process, which removes any overlay of bit line material 416 down to the level of pillar material 412.

[0038] Figure 4FThe patterning and formation of individual bit lines 420 in bit line material 416 is illustrated. The patterning process can be performed using any lithography process, and the bit line material 416 can be selectively etched relative to the etch stop layer 404. For example, a SiO mask can be used to selectively pattern and / or etch the bit lines 420. The bit line material 416 can be removed up to the etch stop layer 404. As described above, each bit line 420 can intersect an offset row of pillar material 412. The bit line 420 can intersect the pillar material 412 at approximately the midpoint of the pillar material 412 of each vertical transistor. In other embodiments, the intersection point can be increased or decreased to intersect more than half or less than half of the pillar material 412 of each vertical transistor. Selective etching can leave gaps 418 between the bit lines 420 to be filled with an insulating material.

[0039] Figure 4G The insulating material 422 between bit lines 420 is shown. The insulating material 422 can be used with... Figure 2B The spacer layer 205 corresponds to this. Insulating material 422 isolates the bit lines 420 from each other. In some embodiments, the width of insulating material 422 may be approximately equal to the width of the bit line 420. Other embodiments may allow for wider or narrower insulating material lines 422, corresponding to narrower or wider bit lines 420. Insulating material 422 can be implemented using any insulator, such as SiO. At this stage, the bit lines 420 are formed, isolated, and positioned such that the bit lines 420 intersect with the source / drain regions formed by the pillar material 412 for each vertical transistor.

[0040] Briefly back Figure 3 The method may further include: forming gate regions for the plurality of vertical transistors, and forming a plurality of word lines (304) in contact with the gate regions. Note that this second processing stage can be performed after the formation of the first source / drain regions and the plurality of bit lines. For example, the gate regions and word lines can be formed on top of a flat surface including the completed first source / drain regions and the plurality of bit lines. As described below, the gate regions can be formed such that they are directly aligned with the first source / drain regions from the first processing stage.

[0041] Figure 4HA second stack deposition process for forming a channel for a vertical transistor above the source / drain region is shown. The etch stop layer 424 can be formed using SiN or other similar materials, with a thickness between about 2 nm and about 20 nm. The sacrificial layer 426 can be formed using SiO or other similar materials, exhibiting high etch selectivity relative to the etch stop layer 424. The thickness of the sacrificial layer 426 can be between about 20 nm and about 1000 nm. The CMP stop layer 428 can be formed using SiN or other similar materials and can have a thickness between about 2 nm and about 20 nm. These layers can be deposited as described above. Figure 4A It is formed as described above. Similarly, hole 440 can be formed using the above-described... Figure 4A The same pattern described above is used to pattern the hole 440 so that it is aligned above the pillar material 412 forming the aforementioned source / drain regions. Various etching processes can be used to form the hole 440, each selectively employing the CMP stop layer 428, sacrificial layer 426, and etch stop layer 424. For example, a series of SiN / SiO / SiN etching processes can be used. As described above, the CD range of the hole 440 can be from about 0.5F to about 1.5F.

[0042] Figure 4I The formation of a channel for a vertical transistor is shown above. Figures 4B-4D As described, various different processes and / or materials can be used to fill the via 440. For example, the channel material 442 can be formed from epitaxial silicon using a SEG process. The channel material 442 can include conformal filling of the polysilicon semiconductor layer in the via 440. The filling material can include metal oxides such as Si, Ge, SiGe, IGZO, and / or other suitable materials. A planarization process can be performed to remove the CMP stop layer 428 and any overlays of the channel material 442 extending over the via 440. This can create a uniform height for all channels of the vertical transistor. The sacrificial layer 426 can then be removed up to the etch stop layer 424 to expose the vertical pillars for the channels formed by the channel material 442.

[0043] Figure 4J The formation of gate oxide 444 around each vertical pillar formed by channel material 442 is shown. Gate oxide 444 can be formed from materials such as SiO or other similar materials. For example, SiO can be oxidized from the vertical pillars of pillar material 412 to serve as gate oxide 444. The thickness of the gate oxide can be between about 1 nanometer and about 10 nanometers. Although size limitations exist... Figure 4J It is not explicitly shown, but the gate metal can also be formed on the gate oxide 444.

[0044] Figure 4KThe formation of word line material 453 is illustrated. Word line material 453 can be formed from any material used to form bit line 420. For example, word line material 453 can be formed from tungsten, molybdenum, and other similar conductors. Similar to bit line material 416 described above, word line material 453 can be formed to extend beyond or over channel material 442. A planarization process can be performed to remove any overlays on word line material 453. Figure 4K As shown, the planarization process can also remove the gate oxide 444 from the top of the channel pillar to expose the channel material 442.

[0045] Figure 4L The formation of word line 446 is shown. As described above for the process used to form bit line 420, spacer layer 203 and... Figure 2B A pattern or mask can be used to form gaps 441 between word lines 446 formed by the etching process. As described above, these gaps 441 can have triangular, zigzag, or wavy patterns with uniform width. The resulting word lines 446 can have a non-uniform width, which increases as the word lines 446 surround the channel material 442 and decreases as the word lines 446 are routed between adjacent pillars of the channel material 442 within a column of memory cells. The gaps 441 can be used to isolate adjacent word lines.

[0046] Figure 4M It shows Figure 2B The spacer layer 203 is formed between the word lines 446. The spacer layer 443 can be formed of any insulating material, such as SiO, dielectric, or other similar material. In some embodiments, a planarization process may be performed to create a flat surface at the top of the stack for the formation of subsequent layers.

[0047] Briefly back Figure 3 The method may further include: forming second source / drain regions for the plurality of vertical transistors, and forming a plurality of capacitors (306) in contact with the second source / drain regions. Note that this third processing stage can be performed after the formation of the gate regions and the plurality of word lines. For example, the second source / drain regions can be formed on top of a flat surface including the completed gate regions and the plurality of word lines. As described below, the second source / drain regions can be formed such that they are directly aligned with the gate regions from the second processing stage.

[0048] Figure 4NA third stack deposition process is illustrated. The third stack deposition process can be implemented similarly to the first and / or second stack deposition processes described above. For example, an etch stop layer 443 (e.g., SiN) with a thickness of about 2 nm to about 20 nm can be formed. A sacrificial layer 447 (e.g., SiO) with a thickness of about 2 nm to about 20 nm can be formed. A CMP stop layer 449 (e.g., SiN) with a thickness of about 2 nm to about 20 nm can be formed. The via 450 can be patterned and etched down through the etch stop layer 443 to expose the channel material 442 from the underlying layer. The etching process can be selected sequentially for each of the etch stop layer 443, sacrificial layer 447, and CMP stop layer 449. The size of the via 450 can be as described above to conform to existing vertical transistor pillars.

[0049] Figure 4O The formation of the source / drain region at the top of the vertical transistor is illustrated. The via 450 can be filled with pillar material 452 as described above for the bottom source / drain region. For example, pillar material 452 can be formed from epitaxial silicon doped with phosphorus, arsenic, or other similar materials through an implantation process. In some embodiments, the stack 454 can then be planarized to create a flat surface. At this stage, pillar material 412, channel material 442, and pillar material 452 can form a continuous and uniform vertical pillar for the vertical transistor, even if each portion of the pillar is individually fabricated in a different processing stage.

[0050] Figure 4P and Figure 4Q The diagram illustrates the formation of capacitor 456 on top of a vertical transistor as part of each individual memory cell. Capacitor 456 can be formed using conventional techniques, such as forming a bottom electrode, forming a dielectric, and forming a top electrode. Note that the capacitor footprint of capacitor 456 is maximized, and its diameter is typically larger than the diameter of the corresponding vertical transistor.

[0051] It should be understood that, Figure 3 The specific steps illustrated provide a particular method for forming a 2D DRAM array according to various embodiments. According to alternative embodiments, other sequences of steps may also be performed. For example, alternative embodiments may perform the steps outlined above in a different order. Furthermore, Figure 3 The steps shown may include multiple sub-steps, which can be executed in various orders depending on the specific steps. Furthermore, additional steps may be added or removed depending on the application. Many variations, modifications, and alternatives also fall within the scope of this disclosure.

[0052] As used herein, the terms “about” or “approximately” or “substantially” can be interpreted as being within the range that a person skilled in the art would expect from the specification.

[0053] In the foregoing description, numerous specific details have been set forth for illustrative purposes to provide a comprehensive understanding of the various implementations. However, it will be apparent that some implementations can be carried out without some of these specific details. In other instances, well-known structures and devices are shown in block diagram form.

[0054] The foregoing description provides only exemplary embodiments and is not intended to limit the scope, applicability, or configuration of this disclosure. Rather, the foregoing description of various embodiments provides a disclosure that can be used to implement at least one embodiment. It should be understood that various changes may be made to the function and arrangement of the components without departing from the spirit and scope of some of the embodiments set forth in the appended claims.

[0055] Specific details have been provided in the foregoing description to provide a comprehensive understanding of the implementation. However, it is understood that the implementation may be carried out without these specific details. For example, circuits, systems, networks, processes, and other components may have been shown as components in block diagram form so as not to obscure the implementation with unnecessary detail. In other cases, well-known circuits, processes, algorithms, structures, and techniques may have been shown without unnecessary detail to avoid obscuring the implementation.

[0056] Furthermore, it should be noted that various implementations may have been described as a process, which may be depicted as a flowchart, flow diagram, structure diagram, or block diagram. Although the flowchart may have described the operations as a sequential process, many operations may also be performed in parallel or concurrently. Moreover, the order of operations may be rearranged. A process terminates upon completion of its operations, but there may be additional steps not included in the accompanying drawings. A process may correspond to a method, function, program, subroutine, subroutine, etc. When a process corresponds to a function, its termination may correspond to a postback from that function to the calling function or the main function.

[0057] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instructions and / or data. A code segment or machine-executable instruction can represent a program, function, subroutine, program, routine, subroutine, module, software package, category, or any combination of instructions, data structures, or program statements. A code segment can be coupled to another code segment or hardware circuitry by passing and / or receiving information, data, arguments, parameters, or memory contents. Information, arguments, parameters, data, etc., can be passed, forwarded, or transmitted by any suitable means, including memory sharing, message passing, symbol passing, network transmission, etc.

[0058] Furthermore, the implementation can be carried out by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented as software, firmware, middleware, or microcode, the program code or code segments used to perform the necessary tasks can be stored in a machine-readable medium. The processor can then perform the necessary tasks.

[0059] In the foregoing description, specific embodiments of the features have been described with reference to them; however, it should be understood that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used alone or in combination. Furthermore, without departing from the broader spirit and scope of this specification, the embodiments can be used in any number of environments and applications beyond those described herein. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0060] Furthermore, for illustrative purposes, the methods are described in a specific order. It should be understood that in alternative embodiments, these methods may be performed in a different order than described. It should also be understood that the methods described above can be executed by hardware components or by a sequence of machine-executable instructions that can cause a machine (e.g., a general-purpose or special-purpose processor or logic circuit encoded with these instructions) to perform these methods. These machine-executable instructions may be stored on one or more machine-readable media, such as CD-ROMs or other types of optical discs, floppy disks, ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, flash memory, or other types of machine-readable media suitable for storing electronic instructions. Alternatively, these methods may be executed by a combination of hardware and software.

Claims

1. A two-dimensional (2D) dynamic random access memory (DRAM) array, the 2D DRAM array comprising: Multiple bit lines, the multiple bit lines being arranged in a first horizontal direction; Multiple character lines, said multiple character lines being arranged in a second horizontal direction; as well as A plurality of transistors are arranged in a vertical direction, which is orthogonal to a first horizontal direction and a second horizontal direction, such that the plurality of bit lines intersect the bottom source / drain regions of the plurality of transistors, and the plurality of word lines intersect the gate regions of the plurality of transistors. The plurality of transistors are arranged in a honeycomb pattern.

2. The 2D DRAM array of claim 1, wherein the plurality of bit lines intersect only partially with the bottom source / drain regions of the plurality of transistors.

3. The 2D DRAM array of claim 2, wherein the 2D DRAM array further includes a plurality of spacers between the plurality of bit lines, wherein the plurality of spacers also partially intersect the bottom source / drain regions of the plurality of transistors.

4. The 2D DRAM array of claim 1, wherein the spacing between the plurality of bit lines is greater than 2F, wherein F is defined as the feature size, and the cell area of ​​the 2D DRAM array is defined as 4F. 2 .

5. The 2D DRAM array as claimed in claim 1, wherein the cell area of ​​the 2D DRAM array is 4F. 2 F is defined as the characteristic dimension, and the cell area is defined as a non-rectangular parallelogram or a hexagon in the honeycomb pattern.

6. The 2D DRAM array of claim 1, further comprising a plurality of capacitors disposed at the top source / drain regions of the plurality of transistors, wherein the plurality of capacitors have a... The area occupied by F is defined as the feature size.

7. The 2D DRAM array of claim 1, wherein the honeycomb pattern arranges the plurality of transistors such that one of the plurality of transistors is adjacent to six other transistors.

8. A two-dimensional (2D) dynamic random access memory (DRAM) array, the 2D DRAM array comprising: Multiple bit lines, the multiple bit lines being arranged in a first horizontal direction; Multiple character lines, said multiple character lines being arranged in a second horizontal direction; as well as A plurality of transistors are arranged in a vertical direction, which is orthogonal to a first horizontal direction and a second horizontal direction, such that the plurality of bit lines intersect the bottom source / drain regions of the plurality of transistors, and the plurality of word lines intersect the gate regions of the plurality of transistors. The spacing between the plurality of bit lines is greater than 2F, where F is defined as the feature size, and the cell area of ​​the 2DDRAM array is defined as 4F. 2 .

9. The 2D DRAM array of claim 8, wherein the plurality of word lines have non-uniform widths such that the plurality of bit lines have non-uniform widths within the 2D DRAM array.

10. The 2D DRAM array of claim 9, wherein the plurality of word lines are thinner between the plurality of transistors than around the plurality of transistors.

11. The 2D DRAM array of claim 8, wherein the plurality of transistors are arranged in a honeycomb pattern.

12. The 2D DRAM array of claim 8, further comprising a plurality of spacers between the plurality of word lines, wherein the plurality of spacers have a triangular wave pattern.

13. The 2D DRAM array of claim 8, wherein the spacing between the plurality of word lines is greater than 2F.

14. The 2D DRAM array of claim 8, wherein the gate regions of the plurality of transistors comprise epitaxial silicon formed from a silicon substrate beneath the plurality of transistors using an epitaxial growth process.

15. A method for forming a two-dimensional (2D) dynamic random access memory (DRAM) array, the method comprising: A first source / drain region is formed for multiple vertical transistors, and multiple bit lines are formed in contact with the first source / drain region; After forming the first source / drain region and the plurality of bit lines, a gate region for the plurality of vertical transistors is formed, and a plurality of word lines are formed in contact with the gate region; as well as After forming the gate region and the plurality of word lines, a second source / drain region for the plurality of vertical transistors is formed, and a plurality of capacitors are formed in contact with the second source / drain region.

16. The method of claim 15, wherein the plurality of vertical transistors are arranged in a honeycomb pattern.

17. The method of claim 15, wherein forming the first source / drain region and the plurality of bit lines comprises: A sacrificial layer is formed on top of the silicon substrate; Multiple holes are etched in the sacrificial layer; The first source / drain region is formed in the plurality of holes; Remove the sacrificial layer; Bit line material is formed around the first source / drain region to replace the sacrificial layer; as well as The plurality of bit lines are formed from the bit line material around the first source / drain region.

18. The method of claim 15, wherein forming the gate region and the plurality of word lines comprises: A sacrificial layer is formed above the first source / drain region and the plurality of bit lines; A plurality of holes perpendicularly aligned with the first source / drain region are etched in the sacrificial layer; The gate region is formed in the plurality of holes; Remove the sacrificial layer; Word line material is formed around the gate region; as well as The plurality of word lines are formed from the word line material around the gate region.

19. The method of claim 15, wherein forming the second source / drain region and the plurality of capacitors comprises: A sacrificial layer is formed above the gate region and the plurality of word lines; A plurality of holes perpendicularly aligned with the gate region are etched in the sacrificial layer; The second source / drain region is formed in the plurality of holes; as well as The plurality of capacitors are formed above the second source / drain region.

20. The method of claim 15, wherein the gate regions of the plurality of vertical transistors are formed by selective epitaxial growth.

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