Routing method and system based on time sequence criticality

Abstract

The invention relates to the technical field of chip design, and particularly discloses a routing method and system based on time sequence criticality, and the method comprises the steps: abstracting a physical layout into a node network, and constructing a weighted cost function of a total wiring length and a critical path length; iteratively expanding the path by adopting a minimum spanning tree algorithm and recording parasitic parameters; and calculating a merging cost value based on the product of the coincidence path length and the node time sequence criticality, merging the maximum-income node pair to generate a virtual node, and performing loop optimization until a convergence condition is met, thereby realizing dual targets of wiring resource optimization and time sequence critical path delay reduction. According to the method, on the basis of a more accurate time delay model, a target function which comprehensively considers the total routing cost and the routing cost of a time sequence key load node is defined, so that time sequence analysis is more accurate. The overall routing cost can be reduced, meanwhile, the signal delay of the load node and the clock period are reduced according to the criticality degree, and the running speed of a chip is effectively increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chip design, and in particular to a routing method and system based on timing criticality. BACKGROUND

[0002] With the integrated circuit technology entering the deep sub-micron and nanometer era, the physical implementation in chip design is facing increasingly severe timing convergence challenges. In complex high-speed digital circuit design, the delay of interconnection lines has gradually exceeded the gate delay, becoming the core factor affecting chip performance. Traditional routing algorithms are mostly based on Manhattan distance optimization or congestion control strategies, but ignore the timing characteristics of critical paths, resulting in frequent setup time violations in the later design stage. Especially in high-performance computing chips, the coupling effect of clock networks and data paths makes the collaborative optimization of static timing analysis and physical design more urgent.

[0003] In the prior art, in the process of calculating the routing cost, one of the common methods is to take the total length of the Net (circuit line) as the main cost, that is, to take the total delay time as the target. This ignores the setup time margin of the timing critical load node, which will directly determine the size of the final clock cycle, so that the overall design timing performance is reduced due to the excessive delay of some signals. Another method is to optimize the routing route of the timing critical load node, which can effectively reduce the routing length of the timing critical load node, but cannot effectively consider the total routing length of the Net, resulting in excessive parasitic resistance and parasitic capacitance of the routing line, which in turn affects the overall timing performance of the load node.

[0004] Therefore, there is an urgent need for a routing method and system based on timing criticality to solve the above problems. SUMMARY

[0005] The purpose of the present application is to provide a routing method based on timing criticality, comprising the following steps: S1, based on the chip design layout result, abstracting the chip physical area into a node set and the routing channel between adjacent areas into an edge set, each node corresponding to the physical coordinates of the device, and the weight of each edge being determined by the congestion of the channel, which is determined by the number of wires that have passed through the channel and the number of signals that have passed through the channel; S2, generating a routing cost function for the target network, the cost function being the weighted sum of the total wire length and the critical path length; S3, taking the driving node as a root node, iteratively expanding the routing path by using a minimum spanning tree algorithm, selecting a node connected by an edge with the minimum sum of path weight and distance from the current node to join the routing tree each time, until all load nodes are covered, and recording parasitic resistance and capacitance parameters of each path, the parasitic resistance and capacitance parameters being used to calculate timing delay from the driving node to the load node; S4, performing path merging optimization, including: traversing all load node pairs, calculating a merging generation value of coincident paths of the load node pairs, the merging generation value being a product of a length of the coincident paths and a sum of timing criticalities of the two nodes, selecting a node pair with the maximum product value to be merged, and a merging position being a common node farthest from the driving node on the coincident paths, and generating a virtual node after merging and updating a timing criticality of the virtual node as an arithmetic mean of original node criticalities; S5, repeatedly performing step S3 and step S4 until the merging generation value is lower than a preset threshold or a maximum iteration number is reached, and outputting a final routing tree structure, the routing tree simultaneously satisfying dual constraints of minimum total wire length and timing optimization of a critical path.

[0006] Further, a weight coefficient of the total wire length is k; The critical path length is obtained by weighted summation of timing criticalities of the load nodes, a weight coefficient of the critical path length being 1-k, and the timing criticality being calculated according to a setup time margin of the load node.

[0007] Further, the step of path merging optimization in step S4 further includes: S41, calculating a merging generation value of all load node pairs, the merging generation value being a product of a length of coincident paths of the two nodes in the routing tree and a sum of timing criticalities of the two nodes; S42, selecting a node pair with the maximum merging generation value to be merged, and placing a virtual node after merging at a terminal node of the coincident paths; S43, setting a timing criticality of the virtual node as an arithmetic mean of original criticalities of the two nodes.

[0008] Further, the routing tree generation in step S3 further includes: S31, performing shortest path search according to weights of edges, the weights of the edges reflecting channel congestion degrees; S32, generating an initial routing tree by iteratively expanding minimum path cost nodes, and adding a node farthest from the driving node to the tree structure each time.

[0009] Further, the processing method of the virtual node in step S5 includes: S51, positioning a physical position of the virtual node at a terminal node of coincident paths; S52, inherit the setup time margin constraint of the original node, take the smaller value of the two nodes as the constraint value of the virtual node; S53, when the virtual node is merged with other nodes again, recalculate the merging generation value.

[0010] The application also discloses a routing system based on timing criticality, comprising: An abstract layout module is configured to abstract a chip physical region into a node set and a routing channel between adjacent regions into an edge set based on a chip design layout result, each node corresponds to a physical coordinate of a device, and the weight of each edge is determined by the congestion degree of the channel, which is determined by the number of wires that have passed through the channel and the number of signals that have passed through the channel; A generation module is configured to generate a routing cost function for a target network, and the cost function is a weighted sum of the total wire length and the critical path length; A connection module is configured to take a driving node as a root node, iteratively expand a routing path by using a minimum spanning tree algorithm, select a node connected by an edge that makes the sum of the path weight and the distance from the current node minimum each time, and add the node to the routing tree until all load nodes are covered, and record parasitic resistance and capacitance parameters of each path, wherein the parasitic resistance and capacitance parameters are used to calculate the timing delay from the driving node to the load node; A synthesis module is configured to perform path merging optimization, calculate the merging generation value of coincident paths of all load node pairs, select a node pair with the maximum product value for merging, and take the common node farthest from the driving node on the coincident path as the merging position, and generate a virtual node after merging and update the timing criticality of the virtual node to the arithmetic mean of the original node criticalities; An execution module is configured to repeatedly perform the above steps until the merging generation value is lower than a preset threshold or the maximum iteration number is reached, and output a final routing tree structure, wherein the routing tree meets the dual constraints of minimizing the total wire length and optimizing the critical path timing.

[0011] Further, the synthesis module further comprises: A calculation unit is configured to calculate the merging generation value of all load node pairs, and the merging generation value is the product of the coincident path length of the two nodes in the routing tree and the sum of the timing criticalities thereof; A merging unit is configured to select a node pair with the maximum merging generation value for merging, and place the virtual node after merging at the end node of the coincident path; An integration unit is configured to set the timing criticality of the virtual node to the arithmetic mean of the original two node criticalities.

[0012] The application further provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method when executing the computer program.

[0013] The application further provides a computer readable storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps of the method.

[0014] The application has the following beneficial effects: The application defines a target function which comprehensively considers the overall routing cost and the routing cost of the timing critical load node based on a more accurate time delay model, so that the timing analysis is more accurate. Meanwhile, a comprehensive routing method which comprehensively considers the optimization of the overall routing cost and the routing cost of the critical load node is designed, that is, an initial routing tree is established, then the node merging method is used in combination with the timing critical degree, so that the signal delay of the load node is reduced to the maximum extent according to the critical degree, the size of the clock cycle is reduced, and the operation speed of the chip is effectively increased. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 A method flowchart is provided for an embodiment of the application. Figure 2 A time delay model diagram is provided for an embodiment of the application. Figure 3 A cost function calculation example is provided for an embodiment of the application. Figure 4 A physical structure and Net node position diagram is provided for an embodiment of the application. Figure 5 An initial routing tree diagram is provided for an embodiment of the application. Figure 6 A diagram for calculating all distance values based on the timing critical degree is provided for an embodiment of the application. Figure 7 A node merging diagram is provided for an embodiment of the application. Figure 8 A final merging result diagram is provided for an embodiment of the application. Figure 9 A re-routing result diagram is provided for an embodiment of the application.

[0016] The implementation, functional features and advantages of the application will be further described with reference to the embodiments and the accompanying drawings. DETAILED DESCRIPTION

[0017] It is to be understood that the specific embodiments described herein are merely illustrative of the present application and should not be used to limit the scope of the present application.

[0018] The application provides a routing method based on timing criticality, comprising the following steps: S1, based on the chip design layout result, abstracting the chip physical region into a node set and the routing channel between adjacent regions into an edge set, each node corresponding to the physical coordinates of a device, and the weight of each edge being determined by the congestion degree of the channel, the congestion degree being determined by the number of wires that have passed through the channel and the number of signals that have passed through the channel; S2, generating a routing cost function for the target network, the cost function being the weighted sum of the total wire length and the critical path length; S3, taking the driving node as the root node, iteratively expanding the routing path by using the minimum spanning tree algorithm, each time selecting the node connected by the edge with the minimum sum of the path weight and the distance from the current node to join the routing tree, until all the load nodes are covered, and recording the parasitic resistance and capacitance parameters of each path, the parasitic resistance and capacitance parameters being used to calculate the timing delay from the driving node to the load node; S4, path merging optimization, comprising: traversing all the load node pairs, calculating the merging cost value of the coincident paths, the merging cost value being the product of the coincident path length and the sum of the timing criticalities of the two nodes, selecting the node pair with the maximum product value for merging, and the merging position being the common node farthest from the driving node on the coincident path, and generating a virtual node after merging and updating the timing criticality of the virtual node as the arithmetic mean of the original node criticalities; S5, repeatedly executing step S3 and step S4 until the merging cost value is lower than a preset threshold or the maximum iteration number is reached, and outputting the final routing tree structure, the routing tree simultaneously satisfying the dual constraints of minimizing the total wire length and optimizing the critical path timing.

[0019] As shown in the time delay model, Figure 2 The definition of the cost function of the application is: ; Where no is the driving device, rd is the output resistance of the previous driving device, Cno is the equivalent total capacitance at the output end of the driving device looking towards Net, and the capacitance is the equivalent sum of all the capacitances on Net, including the parasitic capacitance and the input capacitance of the output end device.

[0020] ej is the edge of the path from no to nj, rej and Cej are the parasitic resistance and capacitance on each edge, and Cj is the equivalent capacitance looking backward along each edge, i.e. in the direction from n0 to ni.

[0021] As shown in the time delay model, Figure 2As shown, n1, n2, n3 are load devices, wherein re0, re1, Ce0, Ce1 are parasitic resistance and parasitic capacitance, and C1, C2, C3 are input resistances of the three load devices respectively.

[0022] Therefore, if T(n1) is to be obtained, n0 to n1 are to be divided into different edges according to the parasitic resistance, and the equivalent capacitance is obtained according to the circuit analysis result at the end of each edge, and the equivalent capacitance corresponding to re0 is the capacitance equivalent sum from the k node to n0, n1 and n2.

[0023] According to the formula, the time delay from the driving node to a certain load node is related to two factors, one is the total routing length, the larger the routing length, the larger the parasitic capacitance and parasitic resistance. The other is the path length from the driving node to the load node. If the output resistance rd is larger, the former has a greater impact on the time length, and vice versa.

[0024] Therefore, the scheme simultaneously influences the routing algorithm from two angles and gives a unified cost calculation function, and the calculation formula of the cost function is: ; Wherein, D is the total routing length, is the total routing length of Net, is the timing criticality of the load node, is the routing length from the driving node to the load node, and the calculation method of a is: the timing criticality of the load node with the minimum required time R (MinR) is assigned as 1, the timing criticality of the load node with the maximum required time R (MaxR) is assigned as 0, and the timing criticality of the load node between the minimum (MinR) and the maximum (MaxR) is: (MaxR-R) / (MaxR-MinR); For example Figure 3 As shown, Net and routing result, the numbers on the edges represent the length, a represents the timing criticality, the circle represents the node on the Net, S is the driving node, and the rest are load nodes.

[0025] The total routing length weight coefficient is k, and the critical path length is obtained by weighted summation of the timing criticality of each load node, and the critical path length weight coefficient is 1-k, and the timing criticality is calculated according to the setup time margin of the load node.

[0026] Specifically, the weight coefficient of the total wiring length is k; The critical path length is obtained by weighted summation of the timing criticality of each load node, and the critical path length weight coefficient is 1-k, and the timing criticality is calculated according to the setup time margin of the load node.

[0027] The value of k is a real number greater than or equal to 0 and less than or equal to 1, and is dynamically adjusted according to the design stage; The critical path length is obtained by weighted summation of the temporal criticality of each load node. The weighting coefficient of the critical path length is 1-k, and the temporal criticality is calculated based on the establishment time margin of the load node.

[0028] Specifically, the path merging optimization steps in step S4 further include: S41. Calculate the merging cost of all load node pairs, where the merging cost is the product of the length of the overlapping path between the two nodes in the routing tree and their temporal criticality. S42. Select the node pair with the highest merging value and merge them. Place the merged virtual node at the end of the overlapping path. S43. Set the temporal criticality of the virtual node to the arithmetic mean of the criticalities of the original two nodes.

[0029] Specifically, the virtual node processing method in step S5 includes: S51. Position the physical location of the virtual node at the end node of the overlapping path; S52. Inherit the creation time margin constraint of the original node, and take the smaller value of the two nodes as the constraint value of the virtual node. S53. When a virtual node merges with other nodes again, the merge cost is recalculated.

[0030] like Figure 4 As shown, after understanding the calculation formula of the cost function, it is necessary to model the physical structure diagram. The design layout results, that is, the physical location of each device in the chip, are input as known conditions. The physical regions in the chip that house the devices are abstracted as nodes, and the routing channels between the physical regions are regarded as edges, forming a physical structure diagram composed of nodes and edges. The devices in the design are all located between the above nodes. As shown in the figure below, the solid nodes in the figure represent nodes on a certain Net (in chip design and routing methods, Net refers to the electrical connection structure connecting multiple logical or physical components in the circuit, and will be referred to as Net in the following text). α represents the timing criticality of the load node. Here, it is assumed that node D is the driving node of the Net, and the other solid nodes represent the load nodes of the Net. The weight of the edge in the figure represents the congestion of the current routing channel when routing the Net. The larger the edge weight, the more severe the congestion. The weight can be determined by the number of signals that have passed through the channel.

[0031] Furthermore, the generation of the routing tree in step S3 further includes: S31. Perform shortest path search based on the edge weights, where the edge weights reflect the congestion level of the channel. S32. Generate an initial routing tree by iteratively expanding the minimum path cost node. In each iteration, add the unconnected node closest to the driving node to the tree structure.

[0032] Regarding the initial routing tree, a path merging method is used for Net routing. The input layout design results are used to route the Net, which means connecting the driver nodes and load nodes on the Net in the physical structure diagram. The connection routes will form a tree structure, with the root node of the tree being the driver node and the leaf nodes being the load nodes.

[0033] like Figure 5 As shown, routing a Net can be divided into the following steps: Step 1: Starting from the driving node, initialize the distance Dis=0. Initialize the distance Dis=0 for all nodes except the driving node; set set S to empty, and set the complement of set S to S-, which is initialized to include all nodes in the physical structure graph.

[0034] Step 2: Add node D to S and remove node D from S-. Then update the distance of each node in S- that is connected to a node in S by an edge, using the method Dis_S- = Min(W + Dis_S), where Dis_S- represents the distance value of the node in S- that is connected to a node in S, W represents the weight value of the edge, Dis_S represents the distance value of the node in S that is connected to it, and Min represents the minimum value of all the above distance values.

[0035] Step 3: Take the node with the smallest Dis_S- in the previous step, and record the node with the smallest distance in S that is connected to it as its predecessor node. Add it to S and remove it from S-.

[0036] Step 4: Repeat steps 2 and 3 until all nodes in S- are empty.

[0037] Thus, the initial routing tree with the driver node as the source is obtained, as follows: Figure 5 As shown, the dashed lines represent the routing paths.

[0038] Step 5: Iterate through the load nodes and combine them in pairs. Take the corresponding overlapping path value Merged_Dis. For example, if the overlapping route range of load nodes B and F is from D to E to C, then Merged_Dis(B, F) = 1 + 2 = 3. For another example, if the overlapping route range of load nodes G and H is from D to M, then Merged_Dis(G, H) = 2.

[0039] Step 6: After calculating the Merged_Dis for all the above combinations, calculate the distance value MD based on temporal criticality. The calculation method is as follows: MD = Merged_Dis × (α1 + α2), Where α1 and α2 represent the timing criticality of the corresponding two load nodes.

[0040] For example, MD(B,F) = (1+2)×(0.1+0.7) = 2.4. The legend shows the calculation results for all MD values. Figure 6 As shown.

[0041] Step 7, select the pair with the largest MD value, such as Figure 6 As shown, this represents a combination of nodes F and G. These two nodes are merged, and the merged node becomes the new load node, placed on the overlapping path between the two nodes, at the point furthest from the driver node. Specifically, the overlapping route range for load nodes F and G is from D to E, and node E is the furthest node on their overlapping path. The criticality α of the merged node is equal to the average criticality of the two combined nodes. The original two nodes, F and G, are then deleted. The merging process is recorded. Figure 7 As shown, the solid black nodes represent deleted nodes that have been merged, and the gray nodes at node E represent newly added load nodes.

[0042] Step 8: Repeat steps 5, 6 and 7 above until all load nodes have been merged and only driver node D remains. Figure 8 This is the final result after the merger is completed.

[0043] Step 9: Based on the recorded results of the merging process, re-route the Net. Determining the routing path is the reverse process of merging; that is, the merging node will route along the path from the merging node to the load node, as shown below. Figure 9 As shown, the new routing result is based on the previously defined cost calculation function, taking into account not only the total route length (or cost) but also the routing paths of critical load nodes according to the time sequence criticality.

[0044] Compared to existing technologies, this invention, based on a more accurate time delay model, defines an objective function that comprehensively considers both the overall routing cost and the routing cost of time-critical load nodes, resulting in more accurate time series analysis. Simultaneously, it designs a comprehensive routing method that optimizes both the overall routing cost and the routing cost of critical load nodes. This method first establishes an initial routing tree, then combines time criticality with a node merging approach. This reduces the overall routing cost while maximizing the reduction of signal delay at load nodes according to their criticality, thereby decreasing the clock cycle size and effectively increasing the chip's operating speed.

[0045] This invention also discloses a routing system based on time-series criticality, comprising: The abstract layout module is used to abstract the chip physical area into a set of nodes and the routing channels between adjacent areas into a set of edges based on the chip design layout results. Each node corresponds to the physical coordinates of the device, and the weight of each edge is determined by the congestion of the channel. The congestion is determined by the number of wirings that have passed through the channel and the number of signals that have passed through the channel. The generation module generates a routing cost function for the target network, wherein the cost function is a weighted sum of the total cabling length and the critical path length; The connection module is used to iteratively expand the routing path with the driver node as the root node and the minimum spanning tree algorithm. Each time, the node connected by the edge that minimizes the sum of the path weight and the distance to the current node is selected and added to the routing tree until all load nodes are covered. The parasitic resistance and capacitance parameters of each path are recorded. The parasitic resistance and capacitance parameters are used to calculate the timing delay from the driver node to the load node. The synthesis module is used to optimize path merging. It traverses all load node pairs, calculates the merging cost of their overlapping paths, and the merging cost is the product of the overlapping path length and the sum of the temporal criticality of the two nodes. The node pair with the largest product value is selected for merging. The merging position is the common node on the overlapping path that is farthest from the driver node. After merging, a virtual node is generated and its temporal criticality is updated to the arithmetic mean of the criticality of the original node. The execution module is used to repeatedly execute the above steps until the merged cost is lower than a preset threshold or the maximum number of iterations is reached, and outputs the final routing tree structure. The routing tree simultaneously satisfies the dual constraints of minimizing the total wiring length and optimizing the timing of the critical path.

[0046] Furthermore, the synthesis module also includes: The calculation unit is used to calculate the merging cost of all load node pairs, wherein the merging cost is the product of the sum of the lengths of the overlapping paths of the two nodes in the routing tree and their temporal criticality. The merging unit is used to select the node pair with the highest merging cost and merge them, placing the merged virtual node at the end of the overlapping path. The integration unit is used to set the temporal criticality of the virtual node to the arithmetic mean of the criticalities of the original two nodes.

[0047] This application also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the above-described method.

[0048] This application also provides a computer-readable storage medium having a computer program stored thereon, characterized in that the computer program, when executed by a processor, implements the steps of the above-described method.

[0049] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in this application and in the embodiments can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual-speed SDRAM (SSRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), RAMbus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0050] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, apparatus, article, or method that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, apparatus, article, or method. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, apparatus, article, or method that includes that element.

[0051] The above description is merely a preferred embodiment of the present invention and does not limit the scope of this application. Any equivalent results or equivalent process transformations made based on the content of the present invention's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of protection of this application.

Claims

1. A routing method based on temporal criticality, characterized in that, Includes the following steps: S1. Based on the chip design layout results, the chip physical area is abstracted into a set of nodes, and the routing channels between adjacent areas are abstracted into a set of edges. Each node corresponds to the physical coordinates of the device, and the weight of each edge is determined by the congestion of the channel. The congestion is determined by the number of wirings that have passed through the channel and the number of signals that have passed through the channel. S2. Generate a routing cost function for the target network, wherein the cost function is a weighted sum of the total cabling length and the critical path length; S3. Using the driver node as the root node, the minimum spanning tree algorithm is used to iteratively expand the routing path. Each time, the node connected by the edge that minimizes the sum of the path weight and the distance to the current node is selected and added to the routing tree until all load nodes are covered. The parasitic resistance and capacitance parameters of each path are recorded. The parasitic resistance and capacitance parameters are used to calculate the timing delay from the driver node to the load node. S4. Path merging optimization includes: traversing all load node pairs, calculating the merging cost of their overlapping paths, wherein the merging cost is the product of the overlapping path length and the sum of the temporal criticality of the two nodes, selecting the node pair with the largest product value for merging, and merging the common node on the overlapping path that is farthest from the driving node. After merging, a virtual node is generated and its temporal criticality is updated to the arithmetic mean of the criticality of the original node. S5. Repeat steps S3 and S4 until the merged cost is lower than the preset threshold or the maximum number of iterations is reached, and output the final routing tree structure. The routing tree simultaneously satisfies the dual constraints of minimizing the total wiring length and optimizing the timing of the critical path.

2. The routing method based on time-series criticality according to claim 1, characterized in that, The weighting coefficient for the total wiring length is k; The critical path length is obtained by weighted summation of the temporal criticality of each load node. The weighting coefficient of the critical path length is 1-k, and the temporal criticality is calculated based on the establishment time margin of the load node.

3. The routing method based on temporal criticality according to claim 1, characterized in that, The path merging optimization steps in step S4 also include: S41. Calculate the merging cost of all load node pairs, where the merging cost is the product of the length of the overlapping path between the two nodes in the routing tree and their temporal criticality. S42. Select the node pair with the highest merging value and merge them. Place the merged virtual node at the end of the overlapping path. S43. Set the temporal criticality of the virtual node to the arithmetic mean of the criticalities of the original two nodes.

4. The routing method based on temporal criticality according to claim 1, characterized in that, The generation of the routing tree in step S3 further includes: S31. Perform shortest path search based on the edge weights, where the edge weights reflect the congestion level of the channel. S32. Generate an initial routing tree by iteratively expanding the minimum path cost node. In each iteration, add the unconnected node closest to the driving node to the tree structure.

5. The routing method based on temporal criticality according to claim 1, characterized in that, The virtual node processing method described in step S5 includes: S51. Position the physical location of the virtual node at the end node of the overlapping path; S52. Inherit the creation time margin constraint of the original node, and take the smaller value of the two nodes as the constraint value of the virtual node. S53. When a virtual node merges with other nodes again, the merge cost is recalculated.

6. A routing system based on temporal criticality, used to execute the routing method based on temporal criticality as described in claims 1-5, characterized in that, include: The abstract layout module is used to abstract the chip physical area into a set of nodes and the routing channels between adjacent areas into a set of edges based on the chip design layout results. Each node corresponds to the physical coordinates of the device, and the weight of each edge is determined by the congestion of the channel. The congestion is determined by the number of wirings that have passed through the channel and the number of signals that have passed through the channel. The generation module generates a routing cost function for the target network, wherein the cost function is a weighted sum of the total cabling length and the critical path length; The connection module is used to iteratively expand the routing path with the driver node as the root node and the minimum spanning tree algorithm. Each time, the node connected by the edge that minimizes the sum of the path weight and the distance to the current node is selected and added to the routing tree until all load nodes are covered. The parasitic resistance and capacitance parameters of each path are recorded. The parasitic resistance and capacitance parameters are used to calculate the timing delay from the driver node to the load node. The synthesis module is used to optimize path merging. It traverses all load node pairs, calculates the merging cost of their overlapping paths, and the merging cost is the product of the overlapping path length and the sum of the temporal criticality of the two nodes. The node pair with the largest product value is selected for merging. The merging position is the common node on the overlapping path that is farthest from the driving node. After merging, a virtual node is generated and its temporal criticality is updated to the arithmetic mean of the criticality of the original node. The execution module is used to repeatedly execute the above steps until the merged cost is lower than a preset threshold or the maximum number of iterations is reached, and outputs the final routing tree structure. The routing tree simultaneously satisfies the dual constraints of minimizing the total wiring length and optimizing the timing of the critical path.

7. A routing system based on time-series criticality according to claim 6, characterized in that, The synthesis module further includes: The calculation unit is used to calculate the merging cost of all load node pairs, wherein the merging cost is the product of the sum of the lengths of the overlapping paths of the two nodes in the routing tree and their temporal criticality. The merging unit is used to select the node pair with the highest merging cost and merge them, placing the merged virtual node at the end of the overlapping path. The integration unit is used to set the temporal criticality of the virtual node to the arithmetic mean of the criticalities of the original two nodes.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the routing method based on timing criticality as described in claims 1-5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the steps of the routing method based on time criticality as described in claims 1-5.

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