Signal preprocessing method, digital front-end device and storage medium

Abstract

The invention discloses a signal preprocessing method, a digital front-end device and a storage medium, and the method comprises the steps: obtaining the signal frequency of to-be-processed data, and determining two adjacent frequency indexes in a preset compensation coefficient table according to the signal frequency; determining a target compensation coefficient of the to-be-processed data based on the compensation coefficient corresponding to each frequency index in the preset compensation coefficient table; and performing data compensation on the to-be-processed data based on the target compensation coefficient. According to the embodiment of the invention, the problem that the compensation coefficient in the existing digital front-end device is fixed can be solved, the determination precision of the compensation coefficient can be improved, and the signal processing effect of the digital front-end is enhanced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of signal processing, and in particular to a signal preprocessing method, a digital front-end module and a storage medium. BACKGROUND

[0002] As a core module of modern communication systems, the digital front-end (DFE) has made significant breakthroughs in high speed, low latency and multi-band compatibility in recent years. With the evolution of 5G / 6G, satellite communication and terahertz technology, DFE gradually develops towards full digitalization, software reconfigurability and intelligence. By integrating high-performance ADC / DAC, adaptive equalization (such as DFE / FFE) and real-time signal processing algorithms, the digital front-end can effectively compensate for channel loss, suppress noise, and support flexible multi-standard signal processing.

[0003] However, there are still technical bottlenecks to be solved in the digital front-end. IQ compensation and RF frequency domain response compensation are key challenges. Current DFEs mostly use fixed compensation coefficients, which are difficult to adapt to dynamic channel environments such as Doppler shift, temperature drift or device aging, resulting in a decrease in compensation accuracy. Especially in the millimeter wave and terahertz frequency bands, channel nonlinearity is enhanced, and the limitations of fixed coefficients are more prominent. SUMMARY

[0004] The present application provides a signal preprocessing method, a digital front-end device and a storage medium to solve the problem of fixed compensation coefficients in the digital front-end device, which can improve the determination accuracy of the compensation coefficients and enhance the signal processing effect of the digital front-end.

[0005] According to an aspect of the present application, a signal preprocessing method is provided, wherein the method comprises:

[0006] obtaining the signal frequency of the data to be processed, and determining two adjacent frequency indexes in a preset compensation coefficient table according to the signal frequency;

[0007] determining the target compensation coefficient of the data to be processed based on the compensation coefficients corresponding to each frequency index in the preset compensation coefficient table;

[0008] performing data compensation on the data to be processed based on the target compensation coefficient.

[0009] According to another aspect of the present application, a digital front-end device is provided, wherein the device comprises:

[0010] a digital front-end processing unit for executing any of the methods described in the embodiments of the present application;

[0011] a register parameter configuration unit for providing parameter configuration for the digital front-end processing unit;

[0012] a state machine conversion unit for managing the timing logic and the behavior control of the digital front-end processing unit and the register parameter configuration unit.

[0013] According to another aspect of the present application, there is provided a computer readable storage medium storing computer instructions for causing a processor to implement the signal preprocessing method according to any of the embodiments of the present application.

[0014] The technical solution of the embodiment of the present application can obtain the signal frequency of the data to be processed, determine two adjacent frequency indexes in the preset compensation coefficient table according to the signal frequency, determine the target compensation coefficient of the data to be processed according to the compensation coefficient corresponding to the frequency index in the preset compensation coefficient table, and perform data compensation on the data to be processed according to the target compensation coefficient. The granularity of data compensation can be enhanced by the diversified preset compensation coefficient table, the accuracy of data compensation in the data processing process can be improved, the target compensation coefficient can be determined based on the adjacent frequency indexes, the degree of adaptation of the compensation coefficient to the signal frequency of the data to be processed can be enhanced, and the processing effect of the data can be improved.

[0015] It should be understood that the content described in this part is not intended to identify key or important features of the embodiments of the present application, nor is it used to limit the scope of the present application. Other features of the present application will become apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0017] Figure 1 is a flowchart of a signal preprocessing method according to an embodiment of the present application;

[0018] Figure 2 is a flowchart of another signal preprocessing method according to an embodiment of the present application;

[0019] Figure 3 is a structural schematic diagram of a digital front-end processing unit according to an embodiment of the present application;

[0020] Figure 4 is a structural schematic diagram of a digital front-end device according to an embodiment of the present application;

[0021] Figure 5is an application example diagram of a DFE unit according to the embodiment five of the present application;

[0022] Figure 6 is a structure diagram of a DFE unit according to the embodiment five of the present application;

[0023] Figure 7 is a structure diagram of a DFE processing unit according to the embodiment five of the present application;

[0024] Figure 8 is a flow chart of execution logic of a data storage error calibration unit according to the embodiment five of the present application;

[0025] Figure 9 is a flow chart of execution logic of a DC compensation unit according to the embodiment five of the present application;

[0026] Figure 10 is a flow chart of execution logic of a digital variable gain control unit according to the embodiment five of the present application;

[0027] Figure 11 is a flow chart of execution logic of a FIR2 unit according to the embodiment five of the present application;

[0028] Figure 12 is a flow chart of execution logic of a baseband frequency response compensation unit according to the embodiment five of the present application;

[0029] Figure 13 is a flow chart of execution logic of an IQ compensation unit according to the embodiment five of the present application;

[0030] Figure 14 is a flow chart of execution logic of a digital mixing unit according to the embodiment five of the present application;

[0031] Figure 15 is a flow chart of execution logic of a radio frequency frequency response compensation unit according to the embodiment five of the present application;

[0032] Figure 16 is a flow chart of execution logic of a pre-filtering unit according to the embodiment five of the present application;

[0033] Figure 17 is a flow chart of execution logic of a resampling unit according to the embodiment five of the present application;

[0034] Figure 18 is a flow chart of execution logic of a FIR4 unit according to the embodiment five of the present application;

[0035] Figure 19is a flow chart of the DC estimation unit execution logic provided according to the fifth embodiment of the present application. DETAILED DESCRIPTION

[0036] In order to make the persons skilled in the art better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by the persons skilled in the art without creative labor should belong to the protection scope of the present application.

[0037] It should be noted that the terms "first", "second", and the like in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily indicate a specific order or a chronological sequence. It should be understood that the data thus used can be interchanged under appropriate circumstances, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, a process, method, system, product or device that includes a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but can include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0038] Embodiment one

[0039] Figure 1 is a flow chart of a signal preprocessing method provided according to the first embodiment of the present application. The present embodiment can be applied to the case of coefficient compensation for the data to be processed in the DFE unit. The method can be executed by a digital front-end processing unit, which can be realized in the form of hardware and / or software. The digital front-end processing unit can be deployed independently as a chip, or integrated as a unit of other chips. As shown in the figure, the method comprises: Figure 1

[0040] Step 110, acquiring the signal frequency of the data to be processed, and determining two adjacent frequency indexes in the preset compensation coefficient table according to the signal frequency.

[0041] ​The to-be-processed data can be data that needs to be preprocessed through a data front end, can be specifically ADC data, can be binary data after digital quantization, and the signal frequency can be a physical frequency of an original signal corresponding to the to-be-processed data. The preset compensation coefficient table can be a configuration table used for coefficient compensation of the to-be-processed data in a DFE preprocessing process, and the preset compensation coefficient table can store corresponding compensation coefficients for a plurality of frequency indexes. It can be understood that the compensation coefficients stored in the preset compensation coefficient table for different frequency indexes can be different, and the difference can be specifically that the values of the compensation coefficients are different. The frequency index can be a frequency value associated with different compensation coefficients in the preset compensation coefficient table, and the frequency index in the preset compensation coefficient table can be determined by a frequency processing range of the to-be-processed data applicable to the DFE unit. The frequency index can be determined by uniformly or non-uniformly dividing the frequency processing range.

[0042] In the embodiment of the application, the DFE can obtain the signal frequency of the to-be-processed data, find two frequency indexes in the preset compensation coefficient table that are closest to the signal frequency, and the frequency difference between the frequency values corresponding to the two frequency indexes and the signal frequency of the to-be-processed data is less than the frequency difference between the frequency values corresponding to other frequency indexes in the compensation coefficient table and the signal frequency of the to-be-processed data. It can be understood that the preset compensation coefficient table can exist in the form of a lookup table.

[0043] Further, the preset compensation coefficient table can include a plurality of compensation coefficient tables used for data compensation of the to-be-processed data, and the preset compensation coefficient table can include an IQ mismatch compensation coefficient table for IQ compensation of the to-be-processed data and a radio frequency response compensation coefficient table for radio frequency response compensation of the to-be-processed data.

[0044] Step 120, determining a target compensation coefficient of the to-be-processed data based on the compensation coefficients corresponding to each frequency index in the preset compensation coefficient table.

[0045] The preset compensation coefficient table can be a lookup table configured in the DFE unit, and the preset compensation coefficient table can include a plurality of compensation coefficients. Each compensation coefficient can have a corresponding frequency index, and each compensation coefficient can be applied to data compensation of to-be-processed data at a frequency corresponding to the frequency index.

[0046] In the embodiment of the present application, the corresponding compensation coefficients in the preset compensation coefficient table can be searched according to the obtained frequency indexes, the target compensation coefficient of the to-be-processed data can be determined through the compensation coefficients corresponding to the two obtained frequency indexes, the determination can include taking the average value of the two compensation coefficients as the target compensation coefficient, or taking the weighted average value of the two compensation coefficients as the target compensation coefficient, or the compensation coefficients can be linearly interpolated based on the signal frequency of the to-be-processed data, and the linear interpolation result of the two compensation coefficients can be taken as the target compensation coefficient.

[0047] Step 130, data compensation is performed on the to-be-processed data based on the target compensation coefficient.

[0048] In the embodiment of the present application, the to-be-processed data can be compensated through the obtained target compensation coefficient, for example, the to-be-processed data can be multiplied by the target compensation coefficient for compensation, or the to-be-processed data can be added by the target compensation coefficient for compensation, etc.

[0049] In the embodiment of the present application, the signal frequency of the to-be-processed data is obtained, two adjacent frequency indexes in the preset compensation coefficient table are determined according to the signal frequency, the target compensation coefficient of the to-be-processed data is determined according to the compensation coefficients corresponding to the frequency indexes in the preset compensation coefficient table, and the to-be-processed data is compensated according to the target compensation coefficient. The granularity of data compensation can be enhanced by diversifying the preset compensation coefficient table, the accuracy of data compensation in the data processing process can be improved, the target compensation coefficient can be determined based on the adjacent frequency indexes, the adaptation degree of the compensation coefficient to the signal frequency of the to-be-processed data can be enhanced, and the processing effect of the data can be improved.

[0050] Embodiment two

[0051] Figure 2 is a flowchart of another signal preprocessing method provided by the embodiment two of the present application, and the embodiment of the present application describes the determination process of the target compensation coefficient in the DFE unit, referring to Figure 2 The method provided by the embodiment of the present application specifically includes the following steps:

[0052] Step 210, the enable indication parameter is set to an enabled state.

[0053] The enable indication parameter can be information indicating whether to continue data compensation on the to-be-processed data signal according to the target compensation coefficient. It can be understood that when the enable indication parameter is set to the enabled state, the to-be-processed data can be compensated according to the target compensation coefficient.

[0054] In the embodiments of the present application, the DFE can check the enablement indication parameter of whether to perform data compensation, determine whether the enablement indication parameter is set to an enablement state, if yes, continue the subsequent data compensation step, and if no, end the current data compensation process. Further, in some embodiments, when it is determined that the enablement indication parameter is not set to the enablement state, the data compensation can not be performed on the to-be-processed data according to the method provided in the embodiments of the present application, for example, the to-be-processed data can be compensated according to the existing data compensation manner, or the to-be-processed data can not be compensated.

[0055] In step 220, the initialization frequency parameter and the frequency step increment parameter of the register parameter configuration unit are read, and the signal frequency of the to-be-processed data is determined according to the initialization frequency parameter and the frequency step increment parameter.

[0056] The register parameter configuration unit can be responsible for hardware parameter configuration, input / output format control and the like in the DFE unit, and can save at least the initialization frequency parameter and the frequency step increment parameter. The initialization frequency parameter can be a starting frequency value of a signal source corresponding to the to-be-processed data in the DFE unit, and the frequency step increment parameter can be a minimum interval or step of frequency adjustment of the signal of the signal source by the DFE unit each time. The initialization frequency parameter and the frequency step increment parameter can jointly determine the signal frequency of the to-be-processed data.

[0057] Specifically, the DFE unit can access the register parameter configuration unit, extract the initialization frequency parameter and the frequency step increment parameter in the register configuration unit, and calculate the signal frequency of the to-be-processed data at the current time according to the initialization frequency parameter and the frequency step increment parameter. For example, the calculation process can be implemented through the following formula:

[0058] F=SB_INIT+SB_STEP*t, where F represents the signal frequency, SB_INIT represents the initialization frequency parameter, and SB_STEP represents the frequency step increment parameter.

[0059] In step 230, two adjacent frequency indexes in the preset compensation coefficient table are determined according to the signal frequency.

[0060] In the embodiments of the present application, the two frequency indexes in the preset compensation coefficient table closest to the frequency value of the signal frequency can be found.

[0061] For example, the working frequency range of the current DFE unit is 30-40 GHz, the frequency indexes in the preset compensation coefficient table can be divided according to the working frequency of the current DFE unit, the frequency indexes can include 30 GHz, 35 GHz, 40 GHz, etc., and the obtained signal frequency is 32 GHz, the two closest frequency indexes in the preset compensation coefficient table are 30 GHz and 35 GHz.

[0062] In step 240, the standard compensation coefficients corresponding to the frequency indexes in the preset compensation coefficient table are extracted.

[0063] The standard compensation coefficient can be the compensation coefficient corresponding to each frequency index in the preset compensation coefficient table, the standard compensation coefficient can be determined and generated according to the signal frequency corresponding to the frequency index, and the standard compensation coefficient can be determined by experience or experiment.

[0064] In the embodiment of the application, the standard compensation coefficients corresponding to each frequency index can be searched in the preset compensation coefficient table according to the two determined frequency indexes.

[0065] In step 250, linear interpolation is performed according to the signal frequency and the two standard compensation coefficients to obtain a target compensation coefficient.

[0066] Specifically, the standard compensation coefficients can be linearly interpolated and calculated according to the obtained signal frequency, the calculation result can be used as the target compensation coefficient, for example, the frequency difference corresponding to the frequency indexes of the two standard compensation coefficients and the coefficient difference of the two standard compensation coefficients can be determined, the ratio between the coefficient difference and the frequency difference can be calculated, the frequency difference value between the signal frequency and any one of the frequency indexes of the two standard compensation coefficients can be obtained, and the product of the frequency difference value and the ratio can be used as the target compensation coefficient of the to-be-processed data. In some embodiments of the application, the process of calculating the target compensation coefficient by linear interpolation can be determined by the following formula:

[0067] Wherein, y represents the target compensation coefficient, x represents the signal frequency, x1 and x0 represent the standard compensation coefficients, and y1 and y0 represent the determined frequency indexes.

[0068] In step 260, the to-be-processed data is compensated based on the target compensation coefficient.

[0069] In the embodiment of the present application, by determining that the enabling indication parameter of data compensation is set to an enabling state, the signal frequency of the to-be-processed data is calculated according to the initialization frequency parameter and the frequency step increment parameter of the register parameter configuration unit, two frequency indexes adjacent to the signal frequency in the preset compensation coefficient table are extracted, the standard compensation coefficient corresponding to each frequency index is obtained, the target compensation coefficient of the to-be-processed data is obtained by linear interpolation according to the signal frequency and the standard compensation coefficient, and the to-be-processed data is compensated by the target compensation coefficient. Flexible compensation coefficient configuration can be realized based on the preset compensation coefficient table, the adaptive compensation coefficient is determined for the signal frequency of the data, the accuracy of data compensation can be enhanced, and the preprocessing effect of the data can be enhanced.

[0070] Further, on the basis of the above-mentioned embodiment of the application, the preset compensation coefficient table at least includes an IQ mismatch compensation coefficient table and a radio frequency response compensation coefficient table, and the preset compensation coefficient table includes at least two frequency indexes and the standard compensation coefficient corresponding to each frequency index.

[0071] In the embodiment of the present application, the preset compensation coefficient table at least includes an IQ mismatch compensation coefficient table and a radio frequency response compensation coefficient table, and the IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient table can be a lookup table respectively. The IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient can include at least two groups of standard compensation coefficients respectively, and the standard compensation coefficients are used for IQ mismatch compensation and radio frequency response compensation in the IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient respectively. It can be understood that the number of frequency indexes corresponding to the standard compensation coefficients in the IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient and the frequency index values can be the same, that is, the IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient can include the same number of standard compensation coefficients, and the frequency index values in the IQ mismatch compensation coefficient table and the radio frequency response compensation coefficient can be the same.

[0072] On the basis of the above-mentioned embodiment of the application, the to-be-processed data is obtained, and error correction is performed on the to-be-processed data. The error correction at least includes at least one of high-low bit storage position correction, signal storage form correction, and positive-negative storage position correction.

[0073] In this embodiment of the invention, when the DFE unit acquires data to be processed, the data may become abnormal due to hardware routing errors or software configuration errors. The DFE unit can perform error correction on the acquired data. Specifically, the DFE unit can detect whether the high and low bits of the data to be processed are stored incorrectly. If so, it can correct the high and low storage positions of the data to be processed, thus reversing the high and low bits. The DFE unit can also detect whether the positive and negative bits of the data to be processed are stored incorrectly. If so, it can correct the signal storage format of the data to be processed, thus reversing the positive and negative bits. The DFE unit can also detect whether the real and imaginary parts of the data to be processed are stored incorrectly. If so, it can correct the real and imaginary parts of the data to be processed, thus reversing the real and imaginary parts.

[0074] Furthermore, based on the above embodiments, the invention also includes:

[0075] The equiripple filter is invoked to downsample the data to be processed according to the preset downsampling factor.

[0076] Among them, the equiripple filter is a filter that can be designed according to the maximum error minimization criterion. The equiripple filter can also be called the Chebyshev approximation filter. The equiripple filter can be implemented by relying on the Parks-McClellan algorithm. The equiripple filter can achieve optimal equiripple control and has the advantage of phase linearity in the passband.

[0077] In this embodiment of the invention, the data to be processed can be downsampled using an equal-ripple filter, and the preset downsampling factor can be pre-configured in the DFE unit. For example, the equal-ripple filter can be invoked to downsample the data to be processed by a factor of 2.

[0078] Furthermore, based on the above embodiments of the invention, the method further includes: determining the resampling interval according to the initial reference parameters configured by the register parameter configuration unit and the adjustment step size parameters; searching for the corresponding fractional delay filter coefficients in the fractional delay filter coefficient table according to the resampling interval; and resampling the data to be processed according to the fractional delay filter coefficients.

[0079] In the embodiment of the present application, the DFE unit can extract initial reference parameters and adjustment step parameters in the register parameter configuration unit, determine the current resampling interval of the to-be-processed data according to the initial reference parameters and the adjustment step parameters, find the corresponding fractional delay filter coefficients in the preset fractional delay filter coefficient table according to the resampling interval, and resample the to-be-processed data according to the found fractional delay filter coefficients. Further, the fractional delay filter coefficient table can further include multiple sets of fractional delay filter coefficients, each set of fractional delay filter coefficients can correspond to different resampling intervals, the target interval adjacent to the resampling interval of the to-be-processed data can be found in the fractional delay filter coefficient table, and the fractional delay filter coefficients associated with the target interval can be linearly interpolated, and the target fractional delay filter coefficients corresponding to the linear interpolation result can be used to resample the to-be-processed data.

[0080] Embodiment three

[0081] Figure 3 is another structural schematic diagram of a digital front-end processing unit provided according to the embodiment three of the present application, referring to Figure 3 , the digital front-end processing unit can include:

[0082] The coefficient table unit 310 is configured to acquire the signal frequency of the to-be-processed data, and determine two frequency indexes adjacent to each other in the preset compensation coefficient table according to the signal frequency.

[0083] The coefficient determination unit 320 is configured to determine the target compensation coefficient of the to-be-processed data based on the compensation coefficients corresponding to each of the frequency indexes in the preset compensation coefficient table.

[0084] The compensation execution unit 330 is configured to perform data compensation on the to-be-processed data based on the target compensation coefficient.

[0085] On the basis of the above-mentioned embodiment of the present application, the coefficient determination unit 320 is specifically configured to extract the standard compensation coefficients corresponding to the frequency indexes in the preset compensation coefficient table, and perform linear interpolation on the signal frequency and the two standard compensation coefficients to obtain the target compensation coefficient.

[0086] On the basis of the above-mentioned embodiment of the present application, the preset compensation coefficient table in the coefficient determination unit 320 at least includes an IQ mismatch compensation coefficient table and a radio frequency response compensation coefficient table, and the preset compensation coefficient table includes at least two frequency indexes and the standard compensation coefficients corresponding to each of the frequency indexes.

[0087] On the basis of the above-mentioned embodiment of the present application, the digital front-end processing unit further includes a data correction unit configured to acquire the to-be-processed data and perform error correction on the to-be-processed data, and the error correction at least includes at least one of high-low storage position correction, signal storage form correction, and positive-negative storage position correction.

[0088] On the basis of the above-mentioned embodiment of the application, the digital front-end processing unit further comprises an enabling indication unit configured to determine that an enabling indication parameter of data compensation is set to an enabling state.

[0089] On the basis of the above-mentioned embodiment of the application, the digital front-end processing unit further comprises a downsampling unit configured to call an equal-ripple filter to perform downsampling on the to-be-processed data according to a preset downsampling multiple.

[0090] On the basis of the above-mentioned embodiment of the application, the signal frequency of the to-be-processed data in the digital front-end processing unit comprises: reading an initialization frequency parameter and a frequency step increment parameter of a register parameter configuration unit; and determining the signal frequency of the to-be-processed data according to the initialization frequency parameter and the frequency step increment parameter.

[0091] On the basis of the above-mentioned embodiment of the application, the digital front-end processing unit further comprises a resampling unit configured to determine a resampling interval according to an initial reference parameter and an adjustment step parameter configured by the register parameter configuration unit; and to find corresponding fractional-delay filter coefficients in a fractional-delay filter coefficient table according to the resampling interval, and to perform resampling on the to-be-processed data according to the fractional-delay filter coefficients.

[0092] The digital front-end processing unit provided in the embodiment of the application can execute the signal preprocessing method provided in any embodiment of the application, and has the corresponding function modules and beneficial effects of the execution method.

[0093] Embodiment four

[0094] Figure 4 is a structural schematic diagram of a digital front-end device provided in the embodiment four of the application, referring to Figure 4 The digital front-end device can comprise:

[0095] The digital front-end processing unit 410 is configured to execute the signal preprocessing method described in any embodiment of the application, wherein the method comprises: acquiring a signal frequency of to-be-processed data, and determining two adjacent frequency indexes in a preset compensation coefficient table according to the signal frequency; determining a target compensation coefficient of the to-be-processed data based on compensation coefficients corresponding to the frequency indexes in the preset compensation coefficient table; and performing data compensation on the to-be-processed data based on the target compensation coefficient.

[0096] The register parameter configuration unit 420 is configured to provide parameter configuration for the digital front-end processing unit.

[0097] The state machine conversion unit 430 is configured to manage the timing logic and behavior control of the digital front-end processing unit and the register parameter configuration unit.

[0098] The digital front-end device provided by the embodiment of the application can perform the signal preprocessing method provided by any embodiment of the application, has the function modules and beneficial effects corresponding to the execution method.

[0099] Embodiment five

[0100] Figure 5 is an application example diagram of a DFE unit according to the embodiment of the application. The DFE unit is a key bridge connecting analog signals and digital processing, and is widely used in fields requiring high-speed and high-precision signal processing, such as wireless communication systems, radar and sensing systems, high-speed data interconnection, medical and industrial equipment, consumer electronics, etc. See Figure 5 Taking the application in a millimeter wave radar system as an example, after being received by a receiving end (RX), the radar echo signal first needs to pass through an amplifier (Low Noise Amplifier, LNA). The amplifier is generally a nonlinear device, and the frequency response of its amplitude and phase differs from the ideal model. In addition, due to reasons such as hardware error, spatial position error, and propagation error, the frequencies of echo signals of different RXs may not be consistent. Therefore, the frequency responses of echo signals of different RXs are inconsistent after passing through the LNA, and the DFE module performs radio frequency frequency response compensation to ensure that the radio frequency frequency responses of signals of different RXs are consistent.

[0101] After passing through the LNA, the echo signal needs to be mixed with a local oscillator (Local Oscillator, LO) signal to down-convert to an intermediate frequency signal. After normal mixing, an intermediate frequency signal and a high frequency signal are generated. The high frequency signal will be filtered out by a low pass filter at the intermediate frequency processing end. Due to the limited isolation of the hardware circuit, the LO signal will leak into the radar echo signal, resulting in self-mixing of the LO signal in addition to the normal mixing of the echo signal and the LO signal during mixing. The self-mixing of the LO signal produces a direct current (Direct Current, DC) signal, which reduces the dynamic range of the intermediate frequency signal and requires the DFE module to perform DC estimation and DC bias compensation.

[0102] After mixing, the echo signal passes through a low pass filter to obtain an intermediate frequency signal, and then the intermediate frequency signal is IQ quadrature sampled to obtain an ADC signal. Due to the non-ideal characteristics of the IQ quadrature sampling analog device, the signal after IQ sampling has amplitude and phase mismatches. This mismatch causes the existence of image frequencies in the spectrum of the ADC data, and the DFE module needs to perform IQ mismatch compensation.

[0103] When sampling the echo signal, due to the need to adapt to very flexible sampling rate requirements and the existence of excessively high sampling rate settings that result in a sampling bandwidth much larger than the actual signal bandwidth, there is a lot of redundant information in the ADC data, and a lot of memory is occupied by invalid data during later processing. Therefore, the DFE module needs to perform resampling and downsampling.

[0104] After the echo signal is sampled into ADC data, because the radar echo data power is related to the distance and target scattering characteristics, the ADC data amplitude changes greatly, which may cause ADC data saturation when the amplitude is high and ADC data loss when the amplitude is low. The DFE module needs to perform digital gain control to make the ADC data reach a higher dynamic range.

[0105] After the echo signal is sampled into ADC data, because the radar echo data power is related to the distance and target scattering characteristics, the ADC data amplitude changes greatly, which may cause ADC data saturation when the amplitude is high and ADC data loss when the amplitude is low. The DFE module needs to perform digital gain control to make the ADC data reach a higher dynamic range.

[0106] Because the length of the RX channel hardware trace may be different, the delay of the ADC data of different RXs is inconsistent, which causes the inconsistency of the baseband frequency response. The DFE module needs to perform baseband frequency response compensation to ensure the consistency of the baseband frequency response of the ADC data of different RXs.

[0107] When the ADC data is transmitted to the DFE module, due to hardware trace errors or software configuration errors, the ADC data may be stored incorrectly after being transmitted to the DFE module, such as high-low inversion, positive-negative inversion, real-imaginary inversion, and offset binary representation of binary complement. The DFE module needs to calibrate the ADC data storage error.

[0108] Referring to Figure 6 The DFE unit provided by the embodiment of the present application includes five units, namely, an input format unit (Input Formatter), a DFE processing unit (DFE Process), an output format unit (Output Formatter), a register parameter configuration unit (Common Register Parameter Set), and a state machine conversion unit (Finite State Machine). The state machine conversion unit is responsible for the overall operation of the DFE unit, and the overall operation includes starting, looping, stopping, and register parameter configuration. The register parameter configuration unit is responsible for corresponding parameter configuration of the input formatting unit, the DFE processing unit, and the output formatting unit. The input formatting unit is responsible for reading data from the local memory according to the configured format and sending the data to the DFE processing unit. The DFE processing unit is responsible for performing related DFE operations on the input data. The output formatting unit is responsible for receiving the data of the DFE processing unit and writing the data into the local memory according to the configured format.

[0109] Referring to Figure 7, the DFE processing unit can include 19 units, including a data storage error correction unit (ADC Board Error Correction), a DC compensation unit (DC Compensation), a digital variable gain control unit (Digital Variable Gain Amplifier, DVGA), a down-sampling unit, a baseband frequency response compensation unit (Baseband Frequency Response Compensation), an IQ compensation unit (Inphase Quadrature Compensation), a digital mixing unit (Digital Mixer), a radio frequency frequency response compensation unit (RF Frequency Response Compensation), a resampling prefilter unit (Resampler Prefilter), a resampling unit (Resampler), etc. The data storage error correction unit is responsible for correcting storage errors that occur after the ADC data is transmitted to the DFE module. The DC compensation unit is responsible for compensating for the ADC data by subtracting the DC estimate value. The digital variable gain control unit is responsible for digital gain control of the ADC data. The FIR 2 unit is a 2-fold down-sampling unit, responsible for anti-aliasing filtering and base-2 decimation of the ADC data, and ABCDEF represent the numbers of each down-sampling unit. The baseband frequency response compensation unit is responsible for baseband frequency response compensation of the ADC data. The IQCompensation is an IQ compensation unit responsible for compensating for amplitude mismatch and phase mismatch of the ADC data. The digital mixing unit is responsible for frequency offset compensation and spectrum shift of the ADC data, and ABC represents the numbers of each digital mixing unit. The radio frequency frequency response compensation unit is responsible for radio frequency frequency response compensation of the ADC data. The Resampler Prefilter is a resampling prefilter unit responsible for anti-aliasing filtering of the ADC data. The Resampler unit is a resampling unit responsible for resampling of the ADC data. The FIR 4 is a 4-fold down-sampling unit responsible for anti-aliasing filtering and base-4 decimation of the ADC data. The DCEstimation is a direct current estimation unit responsible for DC estimation of the ADC data.

[0110] See Figure 8, the ADC Board Error Correction unit receives input parameters and input data, and performs corresponding calibration logic according to the BYPASS variable, the ADC_BIT_REVERSE variable, the ADC_OB22COMP variable, the ADC_DIFF_ERROR variable, and the ADC_IQ_SWAP variable in the input variables. If the BYPASS is 1, the whole calibration logic is not performed, and if the BYPASS is 0, the calibration logic is performed. If the ADC_BIT_REVERSE is 1, it represents that the high and low bits of the ADC data are stored in error, and the high and low bits are calibrated by inversion, and if the ADC_BIT_REVERSE is 0, the high and low bit storage error calibration is not performed. If the ADC_OB22COMP is 1, it represents that the ADC data is stored in offset binary form, and the offset binary to two's complement is performed, and if the ADC_OB22COMP is 0, the offset binary conversion is not performed. If the ADC_DIFF_ERROR is 1, it represents that the positive and negative bits of the ADC data are stored in error, and the positive and negative bits are calibrated by inversion, and if the ADC_DIFF_ERROR is 0, the positive and negative bit storage error calibration is not performed. If the ADC_IQ_SWAP is 1, it represents that the real and imaginary parts of the ADC data are stored in error, and the real and imaginary parts are calibrated by inversion, and if the ADC_IQ_SWAP is 0, the real and imaginary part storage error calibration is not performed.

[0111] Referring to Figure 9 , the DC Compensation unit receives input parameters and input data, and performs DC compensation logic according to the BYPASS input variable, and the DC estimate value input variable is used for DC compensation. If the BYPASS is 1, the compensation logic is not performed, and if the BYPASS is 0, the DC estimate value is subtracted from the ADC data.

[0112] Referring to Figure 10 , the DVGA unit receives input parameters and input data, and performs gain control logic according to the BYPASS input variable, and the GAIN input variable is a gain coefficient. If the BYPASS is 1, the gain control is not performed, and if the BYPASS is 0, the gain coefficient GAIN is multiplied by the ADC data.

[0113] Referring to Figure 11 , the FIR 2 unit receives input parameters and input data, and performs 2 times decimation logic according to the BYPASS input variable. If the BYPASS is 1, the 2 times decimation is not performed, and if the BYPASS is 0, the ADC data is subjected to anti-aliasing filtering and base-2 decimation.

[0114] Referring to Figure 12, Baseband Frequency Response Compensation unit receives input parameters and input data, and performs baseband frequency response compensation logic according to input variable BYPASS, and input variable B_Coef is a frequency response compensation filter coefficient calculated according to each Rx baseband frequency response error. If BYPASS is 1, no baseband frequency response compensation is performed, and if BYPASS is 0, ADC data is baseband frequency response compensation filtered.

[0115] Referring to Figure 13 , the IQ Compensation unit receives input parameters and input data, and performs IQ compensation logic according to input variable BYPASS, and input variables SB_INIT and SB_STEP are used to calculate input data frequency, and input variable GPE is a LUT table storing IQ compensation coefficients calculated for different frequencies of reference signals. If BYPASS is 1, no IQ calibration is performed, and if BYPASS is 0, the input data frequency is obtained according to SB_INIT and SB_STEP, the frequency index interval corresponding to the frequency in GPE is found, and the IQ compensation coefficient matrix of the input signal is obtained through linear interpolation to perform compensation.

[0116] Referring to Figure 14 , the Digital Mixer unit receives input parameters and input data, and performs digital mixing logic according to input variable BYPASS, and input variables PH_INIT and PH_STEP are used to calculate the initial phase and frequency of mixing. If BYPASS is 1, no digital mixing is performed, and if BYPASS is 0, the real part and imaginary part of the mixed signal are obtained through a LUT lookup table to complete digital mixing.

[0117] Referring to Figure 15 , the RF Frequency Response Compensation unit receives input parameters and input data, and performs RF frequency response compensation logic according to input variable BYPASS, and input variables SB_INIT and SB_STEP are used to calculate input data frequency, and input variable BUF_ALPHA is a LUT table storing RF frequency response compensation coefficients calculated for different frequencies of reference signals. If BYPASS is 1, no RF frequency response compensation is performed, and if BYPASS is 0, the input data frequency is obtained according to SB_INIT and SB_STEP, the frequency index interval corresponding to the frequency in BUF_ALPHA is found, and the input data RF frequency response compensation coefficient is obtained through linear interpolation to perform compensation.

[0118] Referring to Figure 16The Resample Prefilter unit receives input parameters and input data, and performs resample prefiltering logic according to the input variable BYPASS. If BYPASS is 1, no resample prefiltering is performed, and if BYPASS is 0, anti-aliasing filtering is performed on the ADC data.

[0119] Referring to Figure 17 The Resample unit receives input parameters and input data, and performs resampling according to the input variable BYPASS. The input variables PH_INIT and PH_STEP are used to calculate the resampling interval. If BYPASS is 1, no resampling is performed, and if BYPASS is 0, the resampling interval is obtained according to PH_INIT and PH_STEP, the interval is found in the fractional delay filter LUT table, the fractional delay filter coefficients of the input signal are obtained by linear interpolation, and resampling is completed by fractional interpolation.

[0120] Referring to Figure 18 The FIR 4 unit receives input parameters and input data, and performs 4 times decimation logic according to the input variable BYPASS. If BYPASS is 1, no 4 times decimation is performed, and if BYPASS is 0, anti-aliasing filtering and base 4 decimation are performed on the ADC data.

[0121] Referring to Figure 19 The DC estimation unit receives input parameters and input data, and performs DC estimation logic according to the input variable BYPASS. If BYPASS is 1, no DC estimation is performed, and if BYPASS is 0, the DC estimation value is obtained by accumulating the mean value of the ADC data.

[0122] The embodiment of the present application calibrates high and low bit errors, offset binary storage, positive and negative bit errors and real and imaginary part errors caused by hardware or software problems in data transmission through a data storage error calibration unit; compensates for the IQ compensation coefficient matrix calculated according to the reference signal for all input signals through an IQ compensation unit, and the IQ compensation coefficients of actual signals of different frequencies are different. The present application divides the entire working frequency band into a plurality of sub-bands, each sub-band corresponds to a frequency index, estimates the amplitude and phase mismatch of the reference signals of all sub-bands, stores the compensation coefficient matrix in the LUT table according to the frequency index. The input signal can find its frequency index interval in the LUT table, and the IQ compensation coefficient matrix of the input signal is obtained through linear interpolation; the CIC filter used for the existing downsampling has the problems of non-ideal frequency response, large passband amplitude ripple and nonlinear phase frequency response, the FIR filter is designed according to the optimal equiripple criterion, the optimal solution is found through the Parks-Mcllan algorithm, and the frequency response of the filter has the advantages of stable passband ripple and linear phase in the passband; the anti-aliasing filter and the fractional delay filter are used to realize fractional interpolation, a plurality of sub-bands are divided according to a certain fractional delay interval, each sub-band corresponds to a fractional delay interval, the fractional delay filter coefficients of all sub-bands are calculated and stored in the lookup table (Look-Up Table, LUT) according to the fractional delay interval index, the input signal can find its fractional delay interval index interval in the LUT table, and the fractional delay filter coefficients of the input signal are obtained through linear interpolation to resample.

[0123] In some embodiments, the signal pre-processing method can be implemented as a computer program tangibly embodied in a computer readable storage medium, such as memory, registers, or cache memory, etc. In some embodiments, part or all of the computer program can be loaded and / or installed into the DFE unit or DFE device. When the computer program is loaded into the DFE unit or DFE device for execution, one or more steps of the signal pre-processing method described above can be performed. Alternatively, in other embodiments, the DFE unit or DFE device can be configured to perform the signal pre-processing method by any other appropriate means (e.g., by means of firmware).

[0124] The various embodiments of the systems and techniques described above can be implemented in digital electronic circuitry, integrated circuitry, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a system on a chip (SOC), a load programmable logic device (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include implementation in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be special or general purpose, coupled to receive data and instructions from, and to transmit data and instructions to, a storage system, at least one input device, and at least one output device.

[0125] Computer programs used to implement the processes of the application can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the computer program, when executed, implements the functions / acts specified in the flowcharts and / or block diagrams. The computer program can be executed entirely on a machine, partially on a machine, partially on a machine as a standalone software package and partially on a remote machine or entirely on a remote machine or server.

[0126] In the context of the present application, a computer-readable storage medium can be a tangible medium that can contain or store computer programs for use by or in connection with an instruction execution system, apparatus, or device. Computer-readable storage media can include, but are not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0127] To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can be used to provide for interaction with a user as well; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form, including acoustic, speech, or tactile input.

[0128] The systems and techniques described here can be implemented in a computing system that includes a back end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front end component (e.g., a user computer having a graphical user interface or a Web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back end, middleware, or front end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0129] The computing system can include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. A server can be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system, to solve the defects of large management difficulty and weak business scalability in traditional physical host and VPS service.

[0130] It should be understood that the various forms of flow shown above can be re-ordered, added to, or deleted from without departing from the scope of the present disclosure. For example, the steps recited in the present disclosure can be executed in parallel, executed in sequence, or executed in a different order, as long as the desired results of the present disclosure are achieved, and the present disclosure is not limited herein.

[0131] The specific embodiments described above are not intended to be limiting, and persons skilled in the art will appreciate that various modifications, combinations, sub-combinations and alternatives can be made to the specific embodiments without departing from the spirit and principles of the disclosure. Accordingly, the disclosure is not limited to the specific embodiments described above, but only by the scope of the appended claims.

Claims

1. A signal preprocessing method, characterized in that, The method includes: Obtain the signal frequency of the data to be processed, and determine two adjacent frequency indices in the preset compensation coefficient table based on the signal frequency; The target compensation coefficient of the data to be processed is determined based on the compensation coefficient corresponding to each frequency index in the preset compensation coefficient table. Data compensation is performed on the data to be processed based on the target compensation coefficient.

2. The method according to claim 1, characterized in that, Determining the target compensation coefficient of the data to be processed based on the compensation coefficient corresponding to each frequency index in the preset compensation coefficient table includes: Extract the standard compensation coefficient corresponding to the frequency index within the preset compensation coefficient; The target compensation coefficient is obtained by linear interpolation based on the signal frequency and the two standard compensation coefficients.

3. The method according to claim 1 or 2, characterized in that, The preset compensation coefficient table includes at least: an IQ mismatch compensation coefficient table and a radio frequency response compensation coefficient table. The preset compensation coefficient table includes at least two frequency indices and standard compensation coefficients corresponding to each frequency index.

4. The method according to claim 1, characterized in that, Also includes: The data to be processed is acquired, and error correction is performed on the data to be processed. The error correction includes at least one of high and low storage position correction, signal storage format correction, and positive and negative storage position correction.

5. The method according to claim 1, characterized in that, Before performing data compensation on the data to be processed based on the target compensation coefficient, the method further includes: The enable indicator parameter for the data compensation is set to the enabled state.

6. The method according to claim 1, characterized in that, Also includes: The equiripple filter is invoked to downsample the data to be processed according to a preset downsampling factor.

7. The method according to claim 1, characterized in that, The signal frequency for acquiring the data to be processed includes: Read the initialization frequency parameters and frequency step increment parameters of the register parameter configuration unit; The signal frequency of the data to be processed is determined according to the initialization frequency parameters and the frequency step increment parameters.

8. The method according to claim 1, characterized in that, Also includes: The resampling interval is determined based on the initial reference parameters configured by the register parameter configuration unit and the adjustment step size parameters. The corresponding fractional delay filter coefficient is found in the fractional delay filter coefficient table according to the resampling interval, and the data to be processed is resampled according to the fractional delay filter coefficient.

9. A digital front-end device, characterized in that, The device includes: A digital front-end processing unit, configured to perform the method according to any one of claims 1-8; A register parameter configuration unit is used to provide parameter configuration for the digital front-end processing unit; The state machine transition unit is used to manage the timing logic and behavior control of the digital front-end processing unit and the register parameter configuration unit.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause a processor to execute the signal preprocessing method according to any one of claims 1-8.

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