Frequency scaling in multi-tenant environment

Abstract

The invention relates to frequency scaling in a multi-tenant environment. Examples described herein relate to circuitry to: monitor availability data for a plurality of processes; determining one or more priority levels associated with at least one of the plurality of processes based on the policy parameters; and adjusting an operating frequency of the interface circuit based on the monitored availability data and the determined priority level of the process. In some examples, an operating frequency of an interface circuit is adjusted to prioritize an operating frequency requested by a high priority workload relative to an operating frequency requested by a low priority workload.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority benefit of U.S. provisional application no. 63 / 643,120 filed May 6, 2024; Indian patent application serial no. 202441035889 filed May 6, 2024; and Indian patent application serial no. 202441035994 filed May 7, 2024. The entire contents of these applications are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates to frequency scaling in a multi-tenant environment. BACKGROUND

[0004] A system on chip (SoC) is a building block for data center and edge computing platforms. A SoC can include general purpose hardware with compute cores, as well as task-specific circuitry, such as, for example, encryption and artificial intelligence (AI) or machine learning (ML) accelerators, data replication technology, circuitry and systems that provide secure domains, network connectivity, and packet processing.

[0005] A processor can utilize circuitry to interface with other components of a SoC, such as, for example, memory and peripherals. Examples of circuitry include uncore from Intel Corporation, system agent, or Infinity Fabric (IF) from Advanced Micro Devices (AMD). For example, the circuitry includes an interface to input output (IO) circuitry, an interface to a network interface controller, and a memory controller. The circuitry operates at a particular frequency, and the operating frequency of the circuitry impacts the performance of the system. Setting the operating frequency of the circuitry to the highest level can avoid reducing the performance of the system, but can increase power consumption. SUMMARY

[0006] According to one embodiment of the present disclosure, an apparatus is provided comprising: a system-in-a-package (SiP) comprising: interface circuitry, and first circuitry to: monitor utilization data for a plurality of processes; determine one or more priority levels associated with at least one of the plurality of processes based on policy parameters; and adjust an operating frequency of the interface circuitry based on the monitored utilization data and the determined one or more priority levels associated with at least one of the plurality of processes, wherein: adjusting the operating frequency of the interface circuitry is to prioritize an operating frequency requested by a high-priority workload over an operating frequency requested by a low-priority workload, and the interface circuitry comprises one or more of: a memory controller, a direct memory access (DMA) circuitry, a cache, a processor-to-processor interconnect, or a bus controller.

[0007] According to one embodiment of the present disclosure, at least one non-transitory computer-readable medium is provided having instructions stored thereon that, when executed by one or more processors, cause the one or more processors to perform the following: execute firmware to: monitor utilization of one or more processors, and selectively modify an operating frequency of interface circuitry of the one or more processors based on the utilization of the one or more processors, wherein the interface circuitry comprises one or more of: a memory controller, a direct memory access (DMA) circuitry, a cache, a processor-to-processor interconnect, or a bus controller.

[0008] According to one embodiment of the present disclosure, a method is provided comprising: a power controller adjusting an operating frequency of interface circuitry based on utilization of one or more processors of a plurality of processors, wherein the interface circuitry comprises one or more of: a memory controller, a direct memory access (DMA) circuitry, a cache, a processor-to-processor interconnect, or a bus controller. BRIEF DESCRIPTION OF DRAWINGS

[0009] FIG. 1 An example system is depicted.

[0010] FIG. 2 An example operation is depicted.

[0011] FIG. 3 An example process is depicted.

[0012] FIG. 4 An example process is depicted.

[0013] FIG. 5 An example process is depicted.

[0014] FIG. 6 An example system is depicted.

[0015] FIG. 7 An example system is depicted.

[0016] FIG. 8 An example system is depicted.

[0017] FIG. 9 An example system is depicted.

[0018] FIG. 10 An example system is depicted. DETAILED DESCRIPTION

[0019] Adjusting the operating frequency of circuitry that provides interfaces to other components can reduce power consumption, but can interfere with the operation of processes executed by the processor. For example, changing the operating frequency of circuitry that provides interfaces to other components can interrupt communication paths to memory, interrupt input / output (I / O), or interrupt core-to-core communication. For certain processes executed by the processor, changing the operating frequency of the circuitry can affect key performance indicators (KPIs), such as latency, packet loss rate, jitter, and overall determinism.

[0020] To reduce the likelihood of impacting the operation of processes that use circuitry that provides interfaces to other components, various examples can adjust the power and / or frequency of circuitry that provides interfaces to other components to one or more processors based on the utilization of the multiple processors, and additionally or alternatively, based on one or more of: a priority level of a requester requesting the adjustment of the frequency of the circuitry, a type of the requester, or a busy level or utilization level of a process executed by the one or more processors. For example, by taking into account the busy or utilization level of a processor or process, it can be possible to avoid interrupting the execution of a process by reducing the operating frequency of circuitry that provides interfaces to other components. For example, by taking into account the priority level of a requester requesting a reduction in the operating frequency of circuitry that provides interfaces to other components, it can be possible to avoid interrupting the operation of a high-priority process.

[0021] Utilization-based control of interface circuitry

[0022] FIG. 1An example system is depicted. The host 100 can be embodied as a server or host system. In some examples, the host 100 can be implemented as a SoC or one or more tiles. The SoC can include an integrated circuit that includes one or more of the following: one or more processors, memory interfaces, input / output (I / O) circuitry, storage interfaces, network interfaces, and other circuitry. The tiles can include one or more processors and I / O circuitry formed in the SoC or connected through a circuit board. At least with respect to FIG. 1 Various examples of circuitry and software that can be used by the host 100 are described.

[0023] The processor 102 can include one or more of the following: a central processing unit (CPU), a processor core, a graphics processing unit (GPU), a neural processing unit (NPU), a general purpose GPU (GPGPU), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a tensor processing unit (TPU), a matrix math unit (MMU), or other circuitry. The processor core can include an execution core or computing unit or engine capable of executing instructions (e.g., an arithmetic logic unit (ALU), a floating point unit (FPU), or other circuitry).

[0024] The cores can be homogeneous devices (e.g., having the same processing capabilities) and / or heterogeneous devices (e.g., having different processing capabilities). The frequency or power usage of the cores can be adjustable. The cores can be sold or designed by a Reduced Instruction Set Computer (RISC) instruction set architecture (ISA) (e.g., RISC-V), and the like. The cores can have access to their own cache and read-only memory (ROM), or multiple cores can share a cache or ROM.

[0025] The interface circuitry 104 can include one or more of the following: a memory controller, a shared cache (e.g., last level cache (LLC)), a cache coherency manager, an arithmetic logic unit, a floating point unit, a core or processor interconnect, a Caching / Home Agent (CHA), fabric interface circuitry, memory interface circuitry, device interface circuitry, and / or a bus or link controller. The interface circuitry 104 can include circuitry that performs one or more of the following: direct memory access (DMA) engine connections, non-cached coherent master connections, core-to-core data cache coherency and arbitrate cache requests, or Advanced Microcontroller Bus Architecture (AMBA) functionality. The interface circuitry 104 can include a non-core, system agent, or infinite fabric (IF).

[0026] Interface circuitry 104 can be used by one or more processor cores or processors 102. For example, an instance of interface circuitry 104 can be used by a core associated with one or more core lists specified in configuration 114, a second instance of interface circuitry 104 can be used by a core associated with a processor socket specified in configuration 114, and / or a third instance of interface circuitry 104 can be used by a core associated with a system with two or more processor sockets specified in configuration 114.

[0027] Various types of inter-processor communication techniques can be used, such as but not limited to messaging, inter-processor interrupts (IPIs), inter-processor communication, and the like. Cores can be connected in any type of way, such as but not limited to a bus, ring, or mesh. Cores can be coupled to a system agent (non-core) via an interconnect. A processor socket can include mechanical components that provide mechanical and electrical connections between a processor and a printed circuit board (PCB).

[0028] Processor 102 can execute a process 120. Process 120 can include one or more of an application, a process, a thread, a virtual machine (VM), a micro-VM, a container, a microservice, or other virtualized execution environment. Various examples of process 120 can perform packet processing based on one or more of a data plane development kit (DPDK), a storage performance development kit (SPDK), open data plane, network function virtualization (NFV), software defined networking (SDN), evolved packet core (EPC), Internet of Things (IoT), 5G radio access network, or 5G network slicing. Some example implementations of NFV are described in ETSI specifications or open source NFV MANO from the open source Mano (OSM) organization from ETSI. A process can include a virtual network function (VNF), such as a service chain or sequence of virtualized tasks that are executed on a general purpose configurable hardware (e.g., firewall, domain name system (DNS), cache, or network address translation (NAT)) and are capable of running in a virtual execution environment. VNFs can be chained together as a service chain. A process can include a cloud native network function (CNF), which can include a network function that is executed inside a container. In some examples, EPC is a core architecture specified by 3GPP for at least long term evolution (LTE) access. 5G network slicing can provide for multiplexing of virtualized and independent logical networks on the same physical network infrastructure. Some processes can perform video processing or media transcoding (e.g., changing the encoding of an audio, image, or video file).

[0029] Host interface 130 can provide communication between host 100 and one or more devices 140-0 through 140-A, where A is an integer. In various examples, host interface 130 can provide communication consistent with Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), Universal Chipset Interconnect Express (UCIe), or other connection technologies. See, e.g., Peripheral Component Interconnect Express (PCIe) Base Specification 1.0 (2002), and earlier versions, later versions, and variations thereof. See, e.g., Compute Express Link (CXL) Specification Revision 1.0, Version 0.7 (2019), and earlier versions, later versions, and variations thereof. See, e.g., Universal Chipset Interconnect Express (UCIe) 1.0 Specification (2022), and earlier versions, later versions, and variations thereof.

[0030] Devices 140-0 through 140-A can include one or more of a network interface device, an accelerator, a storage controller, a storage device, a memory device, another host system, or other component. A network interface device can include one or more of a network interface controller (NIC), a remote direct memory access (RDMA)-capable NIC, a smart NIC, a router, a switch, a forwarding element, an infrastructure processing unit (IPU), a data processing unit (DPU), or a network-attached device.

[0031] In some examples, a process in processes 120 can use utilization monitor 122 to measure a busy level of the process when executed by a processor in processors 102, and store the utilization in utilization data 116. The busy level can indicate a relative busy level of the process (e.g., 0% to 100%, or a numerical value). The busy level can represent a number of cycles consumed by an instruction and software application executing on a particular core, and excluding polling for work to be performed. Other examples of busy level can include a quantized step utilization level from no utilization (e.g., 0) to full utilization (e.g., 5), an average utilization over a certain period of time, and the like. Utilization monitor 122 can collect the utilization of a process, and input the utilization to power manager 106.

[0032] In some examples, an operating system (OS) 124 can use the utilization monitor 122 to collect utilization of the one or more processors 102 and store the utilization in the utilization data 116. For example, the utilization of the one or more processors 102 can indicate a level of utilization of the processor (e.g., 0% to 100% usage and time, or a numerical value). An example of processor utilization includes total CPU usage of a task divided by its runtime, and can be expressed in percentage. Other examples of busy levels can include a quantized step utilization level from never utilized (e.g., 0) to fully utilized (e.g., 5), an average utilization over a certain time period, and the like.

[0033] In some examples, a process can invoke an application programming interface (API) to communicate with the operating system 124 and / or the driver 128 to query or discover capabilities of the power manager 106 to adjust the power and / or frequency of the interface circuit 104 based on the utilization of the one or more processors and additionally or alternatively based on one or more of a priority level of a requester requesting the adjustment of the frequency of the interface circuit, a type of the requester, and / or a busy level or a utilization level of a process executed by the one or more processors. The OS 124 can activate or deactivate the power manager 106 to adjust the power and / or frequency of the interface circuit 104 based on the utilization of the one or more processors and additionally or alternatively based on one or more of a priority level of a requester requesting the adjustment of the frequency of the interface circuit 104, a type of the requester, or a busy level or a utilization level of a process executed by the one or more processors.

[0034] The power manager 106 can select an operating frequency of the interface circuit 104, the selection based on the configuration 114 and a utilization of the one or more processors 102 (e.g., utilization data 116), and additionally or alternatively, based on one or more of a priority level of a requester requesting an adjustment of the frequency of the circuit, a requester type, or a busy level or utilization level of a process executed by the one or more processors 102. The power manager 106 can access the utilization data 116 by a push mode (the utilization data 116 copied to the power manager 106 by the utilization monitor 122 or 126) or a pull mode (e.g., reading the utilization data 116 from the memory 112). The power manager 106 can be implemented in one or more of the following ways: firmware, software executed by the processors, or pcode executed by the power manager 106, for example. The power manager 106 can control an operating frequency of the processors 102 (e.g., increase or decrease the frequency), and control a power and / or operating frequency of the host 100. For example, the power manager 106 can increase or decrease an operating frequency of a processor in the processors 102 based on a utilization level of the processor or a utilization level of a process executed by the processor being below a low level specified in the configuration 114, additionally or alternatively, to decrease an operating frequency of the interface circuit 104.

[0035] In some examples, the operating frequency can include a frequency of a clock signal, or a multiple or fraction thereof.

[0036] In some examples, the adjustment of the operating frequency can refer to clock stretching, where a frequency of a clock signal is decreased based on a voltage level available to the processor being below a certain threshold. An example of clock stretching can be from a device provided by Intel® Corporation.

[0037] A data center administrator, orchestrator, or other software can store the configuration 114 in the memory 112. The configuration 114 can specify one or more of a date or day to apply a policy to manage an operating frequency of the interface circuit 104, a time to apply the policy, a particular core in a core list or group, a particular core in a socket, a high frequency level and a low frequency level of operation of the interface circuit 104, a high utilization level and a low utilization level of the one or more processors and processes, or other information. For example, the configuration 114 can include system level, socket level, and core list based groups with utilization levels that trigger an adjustment of an operating frequency of the interface circuit 104.

[0038] For example, based on one or more processor core utilization levels being below a low utilization level for a configured time or number of samples, the power manager 106 can reduce the operating frequency of the interface circuit 104 to reduce power consumption of the interface circuit 104. In some examples, the power manager 106 can apply the following pseudocode to determine whether to increase or decrease the operating frequency of the interface circuit 104 based on core group utilization levels, socket utilization levels, system utilization levels, and / or application utilization levels.

[0039] if ((corelistO_av < corelistO_low_level) AND (socketO_av < socketO_low_level) AND

[0040] (system_av < system_low_level)) AND (inst_busyness < inst_low_level)

[0041] / / If the average utilization of cores in the core list, cores in the socket, cores in the system, and the busy level of one or more processes is below the low level, then decrease the interface circuit frequency by one

[0042] increment or scaling factor

[0043] if ((corelistO_av > corelistO_high_level) OR (socketO_av > socketO_high_level)

[0044] OR (system_av > system_high_level)) OR (inst_busyness > inst_high_level)

[0045] / / If the average utilization of cores in the core list, cores in the socket, cores in the system, or the busy level of one or more processes is above the high level, then increase the interface circuit frequency by one

[0046] increment or scaling factor

[0047] where:

[0048] corelistO_av can represent the average measured utilization of cores in corelistO;

[0049] socketO_av can represent the average measured utilization of cores in socketO;

[0050] system_av can represent the average measured utilization of cores in the system;

[0051] inst_busyness can represent the reported application utilization on one or more cores indicated by an application or process. The value of inst_busyness can indicate the busy level of each application and can be provided by a polling workload or a non-polling workload (e.g., kernel network) capable of providing the busy level of an application from the OS 124;

[0052] inst_low_level can be configured by a data center administrator and can represent a low utilization level for a process; and

[0053] inst_high_level can be configured by a data center administrator and can represent a high utilization level for a process.

[0054] Reducing the operating frequency of the interface circuit 104 can take into account the utilization of the cores sharing the interface circuit 104 to avoid violating the appropriate service level agreement (SLA) or service level objective (SLO) of a process through the interrupt handler to memory path or interrupt I / O and core to core communication when the operating frequency of the interface circuit 104 is changed.

[0055] In the configuration 114, a data center administrator can assign cores to core lists or groups such that different core lists or groups can be associated with different low and / or high utilization or busy levels. Below are examples of the configuration 114 and example operations of the power manager 106.

[0056] # Category 1

[0057] corelistO [core identifiers 3-10, 47-55]: first (low) level percentage of busy or utilization of the core = 10 regardless of what process is executing, and second (high) level percentage of busy or utilization of the core = 85 regardless of what process is executing

[0058] corelistl [core identifiers 15-32, 69-76]: first (low) level percentage of busy or utilization of the core = 15 regardless of what process is executing, and second (high) level percentage of busy or utilization of the core = 80 regardless of what process is executing

[0059] # Category 2

[0060] socketO: first (low) level average percentage of busy or utilization of the cores in CPU socket 0 = 25, and second (high) level average percentage of busy or utilization of the cores in CPU socket 0 = 75

[0061] socket1: first (low) level average percentage of busy or utilization of cores in CPU socket 0 = 30, second (high) level average percentage of busy or utilization of cores in CPU socket 0 = 70

[0062] # Category 3

[0063] system: first (low) level average percentage of busy or utilization of cores in CPU socket 0 = 40, second (high) level average percentage of busy or utilization of cores in CPU socket 0 = 65. An example of a profile scheme can look as follows:

[0064]

[0065] Power manager 106 can be instantiated as software, hardware IP module in the CPU, microcode in the CPU power controller, firmware, or hardware in the management controller, etc. When instantiated in the management controller, telemetry information can be transmitted to the management controller and an analysis system (not shown) using an out-of-band telemetry method. The management controller can perform management and monitoring functions for a system administrator to monitor the operation of at least the host and its connected devices (e.g., network interface devices and storage devices) using channels, including channels capable of transmitting data (e.g., in-band channels) and out-of-band channels. Out-of-band channels can include packet streams or transmission mediums used to transmit metadata and telemetry information and not used to transmit data. In some examples, the management controller can be implemented as one or more of: a baseboard management controller (BMC), a management or manageability engine (ME), or other device.

[0066] Power manager 106 can be instantiated in software in one or more of: the host operating system, the hypervisor layer, the container layer, microservices, sidecars in Kubernetes deployments, daemon sets in Kubernetes deployments, etc.

[0067] FIG. 2An example process for setting an operating frequency of an interface circuit is depicted. Processes 200 executing on a processor or accelerator can have an associated level of utilization or busyness. An operating system 202 executing on the processor can monitor and collect the utilization or busyness of the processes 200 and provide the utilization to a power manager 204. In some examples, the OS 202 can write the utilization of the processes 200 to a register and the power manager 204 can read the utilization of the processes 200 from the register written by the OS 202. Based on the utilization data, the power manager 204 can determine whether to adjust the operating frequency of the interface circuit based on a comparison to low and high utilization levels of a group of processor cores, low and high utilization levels of a CPU socket, low and high utilization levels of a system, low and high utilization levels of a process, and / or a priority level of a requester requesting a change to the operating frequency of the interface circuit.

[0068] FIG. 3 An example process is depicted. In some examples, the process can be performed by a power manager. At 302, initialization can be performed. For example, system initialization can include reading a configuration file that specifies one or more of the following: a time to apply a policy, a core(s) allocated to a group, high and low level ranges of average utilization of a particular processor core, high and low level ranges of average utilization of a particular processor socket, high and low level ranges of average utilization of a system, high and low level ranges of utilization of a process, and so forth. The configuration file can apply to a particular group of one or more cores to evaluate whether to adjust an operating frequency of an interface circuit. In cases where the interface circuit is allocated to a particular group of cores, whether to adjust the operating frequency of the interface circuit can be evaluated based on the configuration of that particular group of cores.

[0069] At 304, a core to be monitored for utilization can be identified. For example, a core to be monitored for utilization can be identified based on a configuration file or a telemetry endpoint.

[0070] At 306, utilization data for the core identified to be monitored can be collected. For example, utilization data can be collected from a data plane, a 5G user plane function (UPF) telemetry endpoint, an OS telemetry endpoint, or other sources.

[0071] At 308, a determination can be made as to whether a trigger rule for adjusting a frequency of an interface circuit based on a configuration is satisfied. For example, as described herein, an operating frequency of an interface circuit can be adjusted based on high and low level parameters in a configuration and based on a utilization of a core, an average utilization of a group of one or more cores, an average utilization of a CPU socket, an average utilization of a system, and / or a utilization of an application.

[0072] At 310, the operating frequency of the interface circuit can be adjusted based on the determined increase or decrease in frequency. For example, based on the utilization being below the low level for a number of measurements specified in the configuration file or endpoint, the operating frequency of the interface circuit can be decreased by an increment specified in the configuration file. The decrease in operating frequency can be scaled according to the rate of decrease in utilization in successive measurements, such that a higher rate of decrease in utilization can result in a higher rate of decrease in the operating frequency of the interface circuit.

[0073] For example, based on the utilization being above the high level specified in the configuration file or endpoint, the operating frequency of the interface circuit can be increased by an increment specified in the configuration file. Based on the utilization increasing in successive measurements, the decrease in operating frequency can be scaled up to the high level specified in the configuration file. The increase in operating frequency can be scaled according to the rate of increase in utilization in successive measurements, such that a higher rate of increase in utilization can result in a higher rate of increase in the operating frequency of the interface circuit.

[0074] FIG. 4 An example process is depicted. In some examples, the process can be performed by a power manager. At 402, processor utilization can be read. For example, an API call or register read can access the utilization of one or more processor cores. At 404, it can be determined whether the processor utilization is above a configured high utilization level. Based on the processor utilization being above the configured high utilization level, the process can proceed to 406 to increase the operating frequency of the interface circuit based on the configuration, as described herein. At 408, the process can reset a counter of low level utilization.

[0075] At 410, based on the processor utilization not being above the configured high utilization level and the detected processor utilization being below the configured low utilization level, the process can proceed to 412 to count the number of times the detected processor utilization is below the configured low utilization level. At 414, based on the number of times the processor utilization is detected to be below the configured low utilization level exceeding a configured number of times, the process can proceed to 416 to decrease the operating frequency of the interface circuit based on the configuration.

[0076] At 414, based on the number of times the processor utilization is detected to be below the configured low utilization level not exceeding the configured number of times, the process can proceed to 402.

[0077] FIG. 5An example process for setting the frequency of an interface circuit is depicted. In some examples, the process can be performed by a power manager circuit. At 502, a policy configuration to be applied to one or more cores can be set, and a corresponding high utilization level and low utilization level that trigger a corresponding increase or decrease in frequency applied to the interface circuit are set. For example, the one or more cores can be associated with a core group, a processor socket, or a system having two or more processor sockets. The high utilization level can indicate a utilization level of the core group, the processor socket, and / or the system having two or more processor sockets that triggers an increase in the operating frequency of the interface circuit(s) used by the core(s) in the core group, the processor socket, and / or the system having two or more processor sockets. The configuration can also specify other parameters, as described herein.

[0078] At 504, a determination can be made as to whether one or more resources (e.g., processor cores) have been identified whose associated interface circuit needs to decrease an operating frequency. Based on the one or more resources whose associated interface circuit needs to decrease an operating frequency having been identified, the process can proceed to 520. Based on the one or more resources whose associated interface circuit needs to decrease an operating frequency not having been identified, the process can proceed to 506.

[0079] At 506, an average of the utilization measured on the cores identified in the configuration can be determined. For example, the configuration can specify a number of utilization measurements to average, or a time window of utilization measurements to average.

[0080] At 508, a determination can be made as to whether the utilization reaches or exceeds the high utilization level specified in the configuration. For example, the configuration can specify a high utilization level for one or more of a core list, a processor socket, or a system. Based on the utilization reaching or exceeding the high utilization level for one or more of the core list, the processor socket, or the system, the process can proceed to 530. Based on the utilization not reaching and being below the high utilization level for one or more of the core list, the processor socket, or the system, the process can proceed to 510.

[0081] At 510, a determination can be made as to whether the utilization reaches or is below the low utilization level specified in the configuration. For example, the configuration can specify a low utilization level for a core list, a processor socket, and a system. Based on the utilization reaching or being below the low utilization level for the core list, the processor socket, and the system, the process can proceed to 512. Based on the utilization not reaching and being above the low utilization level for the core list, the processor socket, and the system, the process can proceed to 514.

[0082] In some examples, to reduce the operating frequency of the interface circuit, the utilization reaches or falls below a low utilization level for all core lists, processor sockets, and systems. In some examples, to reduce the operating frequency of the interface circuit associated with a particular core list, the utilization reaches or falls below a low utilization level for only that core list, and so on. In some examples, to reduce the operating frequency of the interface circuit associated with a particular processor socket, the utilization reaches or falls below a low utilization level for only that processor socket, and so on. In some examples, to reduce the operating frequency of the interface circuit associated with a system having two or more processor sockets, the utilization reaches or falls below a low utilization level for only that system having two or more processor sockets, and so on. For example, if cores 0-20 share use of the interface circuit, and if core 0 has a utilization of 100% and cores 1-20 have a utilization of 0%, reducing the frequency of the interface circuit can negatively impact the operation of core 0. Various examples avoid reducing the operating frequency of the interface circuit used by cores operating at a utilization level above the low utilization level threshold to avoid reducing the performance of these cores.

[0083] At 512, resources associated with the interface circuit for which the operating frequency is to be reduced are identified. For example, these resources can be associated with a core list, a processor socket, or a system having two or more processor sockets. The process can return to 504.

[0084] However, at 514, no resources associated with the interface circuit for which the operating frequency is to be reduced are identified. The process can return to 504.

[0085] At 520, the operating frequency of one or more interface circuits can be reduced based on the configuration. In some examples, the operating frequency of the interface circuit associated with a particular core list that has been identified can be reduced. In some examples, the operating frequency of the interface circuit associated with a particular processor socket that has been identified can be reduced. In some examples, the operating frequency of the interface circuit associated with a particular system having two or more processor sockets that has been identified can be reduced. The level of frequency reduction of the interface circuit can come in the form of a scaling factor. The scaling factor can be based on the rate of change of the utilization.

[0086] At 530, the operating frequency of one or more interface circuits can be increased based on the configuration. In some examples, the operating frequency of interface circuits associated with the identified particular core list (that is associated with a utilization above the high level) can be increased. In some examples, the operating frequency of interface circuits associated with the identified particular processor socket (that is associated with a utilization above the high level) can be increased. In some examples, the operating frequency of interface circuits associated with the identified system (that is associated with a utilization above the high level) can be increased. The level of frequency increase of the interface circuits can come in the form of a scaling factor. The scaling factor can be based on the rate of change of the utilization.

[0087] Priority-based control of interface circuits

[0088] The performance of the process can be compute-bound, cache / memory-bound, and / or I / O-bound. For a memory-bound process whose performance is based on the rate of accessing data from memory (e.g., cache or volatile memory), reducing the operating frequency of the interface circuits can degrade the performance (e.g., latency, throughput, jitter, etc.) of the process.

[0089] In some examples, a basic input / output system (BIOS), a boot firmware (e.g., a universal extensible firmware interface (UEFI) or a bootloader), and / or software executed by a processor can: (1) determine cache miss and memory bandwidth and input output (IO) traffic levels to determine whether to trigger a modification of the frequency of the interface circuits to a lower value; (2) reduce the frequency of the interface circuits for memory-bound and multi-socket applications based on requests from multiple tenants. However, in a single-tenant or multi-tenant environment, lower priority level workloads can reduce the frequency of the interface circuits and can impact latency and jitter key performance indicators (KPIs) of higher priority workloads.

[0090] Various examples described herein can prioritize frequency adjustment of interface circuitry based on a service class of a requester to provide frequency scaling and power savings, potentially preventing low-priority workloads from interfering with performance of high-priority workloads. In some examples, a service class allows a power manager of the interface circuitry to prioritize setting frequencies based on priority of a requester, such that a high-priority workload requesting to change a frequency of the interface circuitry can override a request to change the frequency of the interface circuitry from a low-priority requester. Thus, a high-priority workload can control a frequency of the interface circuitry and prevent a low-priority workload from controlling the frequency of the interface circuitry. Workloads can be grouped into service classes that serve a group of requesters and execute on a particular core(s) such that the particular core(s) execute processes associated with a particular service class. A priority level can be based on a priority of a workload requester.

[0091] Various examples can trigger a reduction in frequency of an interface circuit and trigger power savings without impacting performance of deterministic workloads. Some examples can reduce an operating frequency of an interface circuit based on telemetry information, workload burden (e.g., workload busy or workload available cores), priority of a workload or process (service class (CoS)), priority of a workload (relative to other workloads), and / or an admission controller for arbitrating priority. A workload or process can be identified by a resource monitor ID (RMID) of a core or a process address space ID (PASID) of a requester process. An identifier can be assigned to a requester process before the workload or process begins. The identifier can be associated with a priority level.

[0092] Various examples can focus on prioritizing frequency settings for a subset of processes running on a given CPU. For example, a CPU can use a single clock or multiple non-core clocks to control an operating frequency of one or more interface circuits.

[0093] FIG. 6 An example system is depicted. A power manager 602 can receive a request from a workload (e.g., process or circuit) to change an operating frequency of an interface circuit. For example, a high-priority workload (e.g., process or circuit) can request to change an operating frequency of an interface circuit to a first frequency. For example, a medium-priority workload (e.g., process or circuit) can request to change an operating frequency of an interface circuit to a second frequency. For example, a low-priority workload (e.g., process or circuit) can request to change an operating frequency of an interface circuit to a third frequency.

[0094] The power manager 602 can resolve and determine the operating frequency of the interface circuit (not shown) based on programmable policies that take into account the requester priority, application type, application utilization, or other factors, such as the utilization of one or more cores, the utilization of one or more CPU sockets, the utilization of the system, and / or the utilization of a process or workload, as described herein. In some examples, the policies can specify user-configured settings of whether a workload, or firmware, or pcode specifies the frequency level of the interface circuit. In some examples, the power manager 602 can apply the frequency requested by the highest priority workload to the interface circuit, if the settings allow. In some examples, the power manager 602 can reduce the operating frequency of the interface circuit based on the priority of the requester, and also based on the utilization of the core executing the requester and the utilization of at least one other core in the core group, CPU socket, and / or system. For example, if a high priority requester requests a reduction in the operating frequency of the interface circuit, but the utilization of at least one other core in the core group, CPU socket, and / or system is above a level set in the configuration, the power manager 602 can not reduce the operating frequency of the interface circuit to prevent a performance degradation of processes executed by the at least one other core, or can reduce the operating frequency less (relative to the requested). For example, if a high priority requester requests a reduction in the operating frequency of the interface circuit, but the utilization of at least one other core in the core group, CPU socket, and / or system is at or below a second level set in the configuration, the power manager 602 can reduce the operating frequency of the interface circuit to the requested level, as reducing the operating frequency of the interface circuit will not affect the performance of processes executed by the at least one other core.

[0095] FIG. 7 An example system is depicted. Example operations are as follows. At (1), an orchestrator and / or power and workload analysis system can configure a power controller to apply policy parameters. The policy parameters can apply to tiles and specify one or more of: maximum burst power or frequency; average power or frequency; shared power usage (e.g., ratio of interface circuit operating frequency to core operating frequency); behavior when exceeding power thresholds; whether capping or sharing can be implemented under the overall power budget of the CPU; overall power budget for the combination of CPU, memory, and storage cooling; workload locality to local interface circuit clock on CPU tiles; power consumption profile representing workload power / load curve for a particular workload over X hours / week; workload KPIs (e.g., latency, throughput, etc.); workload sensitivity to interface circuit frequency; or other.

[0096] In (2), the power controller can configure the frequency of each tile according to a policy description or default values. For example, the power controller can configure parameters for each tile, including a minimum base frequency and / or a starting frequency.

[0097] At (3), the power controller can monitor requests for frequency changes and arbitrate based on the priority of the requester and power usage information. For example, the power controller can receive power usage information including one or more of: each core frequency of each tile, power state residency of each core, interface circuit frequency of each tile, and / or overall power consumption (e.g., CPU, memory, storage, cooling). At (4), the power controller can receive workload execution or idle indications. At (5), the power controller can receive CPU telemetry information (e.g., core stalls, memory bandwidth utilization, inter-socket interface bandwidth utilization, etc.).

[0098] At (6), the power controller can adjust the operating frequency of the interface circuit based on the power consumption profile of the process and the SLA / SLO. The power controller can prioritize the frequency adjustment of the interface circuit based on the service class of the requester to provide frequency scaling and power savings, attempting to prevent low-priority workloads from interfering with the performance of high-priority workloads. However, in some examples, the power controller can adjust the frequency of the interface circuit based on commands from firmware or pcode.

[0099] When the priority of the requesters is the same, one or more of the following approaches can be applied. For example, multiple requesters with the same priority can be grouped and one or more actions performed on the requesters according to a policy. Thus, multiple tenants can agree to reduce the frequency of the interface circuit. Thus, the same frequency reduction of the interface circuit can be applied to a set of multiple requesters with the same priority level. In some examples, requests from multiple requesters with the same priority can be prioritized based on application type, the requester with the longest or shortest duration, round robin, or other scheme.

[0100] FIG. 8An example system is depicted. Example operations are as follows. At (1), a controller (e.g., a software defined network (SDN) orchestrator, a management and orchestration (MANO) stack, or a Kubernetes orchestrator) can configure policies to manage operating frequencies of interface circuits, and configure workloads (e.g., processes or bare metal operations) to execute on specific processors and interface circuits. Policy parameters can be applied to tiles, and specify one or more of: maximum burst power or frequency; average power or frequency; shared power usage (e.g., ratio of interface circuit operating frequency to core operating frequency); behavior when exceeding power thresholds; whether able to achieve upper bounds or sharing under overall power budget of CPU; overall power budget of combination of CPU, memory, and storage cooling; workload locality to local interface circuit clock on CPU tiles; power consumption profile representing workload power / load curve for a specific workload over X hours / week; workload KPIs (e.g., latency, throughput, etc.); workload sensitivity to interface circuit frequency; or other. Example policies can specify one or more of: priority or service class of requester, maximum burst power or frequency (e.g., maximum frequency), minimum burst power or frequency (e.g., minimum frequency), utilization threshold, application type, control rate (e.g., hysteresis timer), or duration of application of policy (e.g., time or number of days).

[0101] In (2), a power controller can configure frequency management of interface circuits of each tile according to policy descriptions or default configurations that allow for management of frequencies of interface circuits regardless of priority of requester. For example, each tile parameter can include one or more of: minimum base operating frequency and / or starting operating frequency.

[0102] At (3), a power controller can monitor requests for frequency changes, and arbitrate requests based on policies. For example, the power controller can receive power usage data including one or more of: operating frequency of each core, operating frequency of each tile, power state residency of each core, interface circuit frequency of each tile, and / or overall power consumption (e.g., CPU, memory, storage, cooling).

[0103] For example, Table 1 depicts an example of a policy for arbitrating requests from applications based on the requestor service class. In this example, a low priority tenant request to set the interface circuit’s frequency to 1.0 GHz is resolved to 1.4 GHz because 1.4 GHz is the lowest or low level operating frequency of the interface circuit for high priority applications or tenants. In other words, the policy can prevent the operating frequency of the interface circuit from being lower than the low level for higher or highest priority tenants or applications, despite other requestors requesting to lower the frequency below that low level.

[0104] High priority application / tenant Low priority application / tenant Mandatory: Priority 1 Mandatory: Priority 2 Mandatory maximum interface circuit frequency: 1.8 GHz Mandatory maximum interface circuit frequency: 1.0 GHz Mandatory minimum interface circuit frequency: 1.4 GHz Mandatory minimum interface circuit frequency: 0.7 GHz

[0105] Table 1

[0106] FIG. 9 An example of workload placement is depicted such that workloads (e.g., processes) with similar policies regarding interface circuit frequency settings are executed by the same core or cores. At (1), a controller can configure a policy defining the management of operating frequencies of interface circuits, and the controller can configure workloads (e.g., processes) to be executed on particular processors and interface circuits to avoid runtime impact of running on the same tile sharing usage of the interface circuit, such that the policy can be applied per tile or core group connected to a single interface circuit through an architecture or other interconnect.

[0107] At (2), the controller can consider the power profile of the workloads such that the tile is selected to execute the workload to meet the core frequency and interface circuit power policy of the workload. In other words, the orchestrator can cause workloads with similar power profiles (e.g., similar KPIs) to be grouped to be executed on cores of a common tile or CPU. The placement of workloads on tiles can be such that, for workloads with similar policies, the interface circuit frequency is likely to shrink during quiet periods, or scale up at the same time.

[0108] At (3), the power controller associated with the tile (e.g., tile 0 and tile 1) can monitor CPU telemetry information, including executed CPU cycles, stalls, memory bandwidth. At (4), the power controller can provide the CPU characteristics of each workload to the controller, such as one or more of the following: core frequency of each tile, interface circuit (e.g., non-core) frequency of each tile, executed CPU cycles, stalls, memory bandwidth, workload status (e.g., completed or in progress). At (5), the controller can potentially adjust the placement of workloads to different tiles based on unmet KPIs, SLAs, or SLOs of the workloads.

[0109] At (6), the controller can adjust the operating frequency of the interface circuit of a particular CPU tile based on the utilization of one or more cores, the utilization of the process, and / or the priority of the requester requesting the change in operating frequency of the interface circuit. At (7), the power control circuit can adjust the operating frequency of the associated interface circuit as determined in (6).

[0110] FIG. 10 A system is depicted. In some examples, circuitry of a processor 1010 or other device can adjust a frequency of an interface circuit 1011 as described herein. The interface circuit 1011 can provide an interface connection for the processor 1010 to an interface 1012 and other circuitry. The system 1000 includes a processor 1010 that provides processing, operation management, and execution of instructions for the system 1000. The processor 1010 can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), XPU, processing core, or other processing hardware or combination of processors that provide processing for the system 1000. An XPU can include one or more of a CPU, a graphics processing unit (GPU), a general purpose GPU (GPGPU), and / or other processing unit (e.g., an accelerator or programmable or fixed function FPGA). The processor 1010 controls the overall operation of the system 1000, and can be or include one or more programmable general purpose or special purpose microprocessors, digital signal processors (DSPs), programmable controllers, application specific integrated circuits (ASICs), programmable logic devices (PLDs), or the like, or a combination of such devices.

[0111] In one example, system 1000 includes an interface 1012 coupled to the processor 1010, which can represent a higher speed interface or high throughput interface used for communicating data between system components, such as the memory subsystem 1020 or the graphics interface component 1040, or accelerator 1042, which require higher bandwidth than provided by the bus 1014. The interface 1012 represents an interface circuit, which can be separate from the processor die or integrated thereon. The graphics interface 1040, if present, interfaces to a graphics component, for providing a visual display to a user of the system 1000. In one example, the graphics interface 1040 can drive a display that provides output to a user. In one example, the display can include a touchscreen display. In one example, the graphics interface 1040 generates a display based on data stored in the memory 1030 or based on operations performed by the processor 1010 or both. In one example, the graphics interface 1040 generates a display based on data stored in the memory 1030 or based on operations performed by the processor 1010 or both.

[0112] The accelerator(s) 1042 can be programmable or fixed-function load transfer engines accessible or usable by the processor(s) 1010. For example, one of the accelerator(s) 1042 can provide data compression (DC) capabilities, cryptographic services (e.g., public key encryption (PKE)), ciphering, hashing / authentication capabilities, deciphering, or other capabilities or services. In some cases, the accelerator(s) 1042 can be integrated into a CPU socket (e.g., a connector of a motherboard or circuit board that includes a CPU and provides an electrical interface with the CPU). For example, the accelerator(s) 1042 can include a single-core or multi-core processor, a graphics processing unit, a logic execution unit, a single-level or multi-level cache, a functional unit usable to independently execute programs or threads, an application specific integrated circuit (ASIC), a neural network processor (NNP), programmable control logic, and programmable processing elements such as field programmable gate arrays (FPGAs). The accelerator(s) 1042 can provide multiple neural networks, CPU, processor cores, general purpose graphics processing units, or graphics processing units for use by an artificial intelligence (AI) or machine learning (ML) model. For example, the AI model can use or include any or a combination of the following: a reinforcement learning scheme, a Q-learning scheme, deep Q-learning, or Asynchronous Advantage Actor-Critic (A3C), a combined neural network, a recurrent combined neural network, or other AI or ML model. Multiple neural networks, processor cores, or graphics processing units can be used by the AI or ML model to perform learning and / or inference operations.

[0113] Memory subsystem 1020 represents the main memory of system 1000, and provides storage for code and data values that will be used in the execution of code by processor 1010 or when executing routines. Memory subsystem 1020 can include one or more memory devices 1030, such as read-only memory (ROM), flash memory, one or more varieties of random access memory (RAM) such as DRAM, or other memory devices, or combinations of such devices. Memory 1030 stores and hosts, among other things, an operating system (OS) 1032 to provide a software platform for the execution of instructions in system 1000. In addition, applications 1034 can execute from memory 1030 on the software platform of OS 1032. Applications 1034 represent programs with their own operational logic to perform the execution of one or more functions. Processes 1036 represent agents or routines that provide auxiliary functions to OS 1032 or one or more applications 1034, or a combination thereof. OS 1032, applications 1034, and processes 1036 provide software logic to provide functionality for system 1000. In one example, memory subsystem 1020 includes a memory controller 1022, which is a memory controller to generate and issue commands to memory 1030. It will be understood that memory controller 1022 can be a physical part of processor 1010 or a physical part of interface 1012. For example, memory controller 1022 can be an integrated memory controller, integrated onto a circuit with processor 1010.

[0114] The applications 1034 and / or processes 1036 can alternatively or additionally refer to virtual machines (VMs), containers, microservices, processors, or other software. The various examples described herein can execute an application composed of microservices, where the microservices run in their own processes and communicate using protocols (e.g., application programming interfaces (APIs), Hypertext Transfer Protocol (HTTP) resource APIs, messaging services, remote procedure calls (RPCs), or Google RPCs (gRPCs)). The microservices can communicate with each other using a service mesh and be executed in one or more data centers or edge networks. The microservices can be deployed independently using centralized management of these services. The management system can be written in different programming languages and use different data storage technologies. The microservices can be characterized by one or more of the following: polyglot programming (e.g., code written in multiple languages to capture additional functionality and efficiency that a single language cannot provide), or lightweight container or virtual machine deployment, and decentralized continuous microservice delivery.

[0115] In some examples, the OS 1032 can be FreeBSD, a server or personal computer, VMware vSphere, openSUSE, RHEL, CentOS, Debian, Ubuntu, or any other operating system. The OS and drivers can execute on processors sold or designed by Texas Instruments, among other companies. The OS 1032 can activate or deactivate the power manager circuit 1090 to adjust the power and / or frequency of the interface circuit 1011 based on the utilization of the one or more processors and, additionally or alternatively, adjust the power and / or frequency of the interface circuit 1011 based on one or more of the following: a priority of a requester that requests the adjustment of the frequency of the interface circuit 1011, a type of the requester, or a busy level or utilization level of a process executed by the one or more processors.

[0116] While not specifically illustrated, it will be understood that the system 1000 can include one or more buses or bus systems between the devices, such as a memory bus, graphics bus, interface bus, or others. The buses or other signal lines can communicatively or electrically couple the components together, or both. The buses can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuitry, or combinations of these. The buses can include one or more of, for example, a system bus, a Peripheral Component Interconnect (PCI) bus, a Hyper Transport or industry standard architecture (ISA) bus, a small computer system interface (SCSI) bus, a universal serial bus (USB), or an Institute of Electrical and Electronics Engineers (IEEE) standard 1394 bus (Firewire).

[0117] In one example, system 1000 includes an interface 1014, which can be coupled to interface 1012. In one example, interface 1014 represents an interface circuit (i.e., interface circuitry) that can include standalone components and integrated circuits. In one example, a number of user interface components or peripheral components, or both, are coupled to interface 1014. Network interface 1050 provides the system 1000 with the ability to communicate with remote devices, such as servers or other computing devices, over one or more networks. Network interface 1050 can include an Ethernet adapter, a wireless interconnection component, a cellular network interconnection component, a USB (universal serial bus), or an interface based on other wired or wireless standards or proprietary. Network interface 1050 can transmit data to devices in the same data center or rack or remote devices, which can include sending data stored in memory. Network interface 1050 can receive data from remote devices, which can include storing received data into memory. In some examples, a packet processing device or network interface device 1050 can refer to one or more of a network interface controller (NIC), a remote direct memory access (RDMA)-enabled NIC, a SmartNIC, a SuperNIC with an accelerator, a router, a switch, a forwarding element, an infrastructure processing unit (IPU), an EPU, or a data processing unit (DPU).

[0118] In one example, system 1000 includes one or more input / output (I / O) interfaces 1060. I / O interface 1060 can include one or more interface components through which a user interacts with system 1000. Peripheral interface 1070 can include any hardware interface not specifically mentioned above. Peripherals generally refer to devices that are dependently connected to system 1000.

[0119] In one example, system 1000 includes a storage subsystem 1080 to store data in a non-volatile manner. In one example, at least some components of storage 1080 can overlap with components of memory subsystem 1020 in certain system implementations. Storage subsystem 1080 includes storage device(s) 1084, which can be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic, solid-state, or optical-based disks, or a combination of these. Storage 1084 holds code or instructions and data 1086 in a persistent state (e.g., the values are retained despite interruption of power to system 1000). Storage 1084 can be considered generally as a "memory," although memory 1030 is typically an executing or operating memory to provide instructions to processor 1010. Storage 1084 is non-volatile, whereas memory 1030 can include volatile memory (e.g., the values or state of the data are indeterminate if power to system 1000 is interrupted). In one example, storage subsystem 1080 includes a controller 1082 to interface with storage 1084. In one example, controller 1082 is a physical part of interface 1014 or processor 1010, or can include circuitry or logic in both processor 1010 and interface 1014.

[0120] Volatile memory is memory whose state is indeterminate (and thus the data stored therein is indeterminate) if power to the device is interrupted. A non-volatile memory (NVM) device is a memory whose state is determinate even if power to the device is interrupted.

[0121] In examples, the system 1000 can be implemented using an interconnected computing platform of processors, memory, storage, network interfaces, and other components. High speed interconnects can be used, such as: Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Peripheral Component Interconnect express (PCIe), Intel QuickPath Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Omni-Path, Compute Express Link (CXL), HyperTransport, High-Speed Fabric, AMBA interconnect, OpenCAPI, Gen-Z, Infinity Fabric (IF), Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variants of these. Data can be copied or stored to virtualized storage nodes, or accessed using protocols such as NVMe over Fabrics (NVMe-oF) or NVMe (e.g., a Non-Volatile Memory Express (NVMe) device can operate in compliance with the Non-Volatile Memory Express (NVMe) Specification Revision 1.3c published May 24, 2018, or derivatives or variants thereof).

[0122] Communications between devices can occur using a network that provides die-to-die communications; chip-to-chip communications; board-to-board communications; and / or package-to-package communications. Die-to-die communications can utilize an Embedded Multi-Die Interconnect Bridge (EMIB) or a middle layer. Components of examples described herein can be packaged in one or more semiconductor packages. A semiconductor package can include a metal, plastic, glass, and / or ceramic housing that contains and provides communication among one or more semiconductor devices or integrated circuits internally or between packages. Various examples can be implemented in a die, in a package, or between multiple packages, in a server, or between multiple servers. A SiP can include a package that packages one or more of a SoC, one or more tiles, or other circuitry.

[0123] In examples, system 1000 can be implemented using an interconnected computing platform of processors, memory, storage, network interfaces, and other components. High speed interconnects can be used, such as PCIe, Ethernet, or optical interconnects (or a combination of these).

[0124] Examples herein can be implemented in various types of computing and networking devices, such as switches, routers, racks, and blade servers, such as those employed in data center and / or server farm environments. Servers used in data centers and server farms include arrayed server configurations, such as rack-based servers or blade servers. These servers are interconnected in communication via various network arrangements, such as dividing groups of servers into Local Area Networks (LANs) with appropriate switching and routing facilities between the LANs to form a private intranet. For example, cloud hosting facilities can typically employ large data centers with numerous servers. A blade includes a separate computing platform configured to perform server-type functions, i.e., a "server on a card." Thus, a blade includes components common to traditional servers, including a main printed circuit board (motherboard) that provides internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs) and other components mounted to the board.

[0125] Various examples can be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements can include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, and so forth), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor device, chips, microchips, chip sets, and so forth. In some examples, software elements can include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and / or software elements can vary in accordance with any number of factors, such as desired computational rate, power levels, heat tolerances, processing cycle budget, input data rates, output data rates, memory resources, data bus speeds and other design or performance constraints. A processor can be a hardware state machine, a digital control logic, a central processing unit, or any combination of one or more of hardware, firmware, and / or software elements.

[0126] Some examples can be implemented using or as articles of manufacture or at least one computer-readable medium. A computer-readable medium can include a non-transitory storage medium to store or record at least one computer-readable instruction. In some examples, a non-transitory storage medium can include one or more types of computer-readable storage media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. In some examples, the logic can include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0127] According to some examples, a computer-readable medium can include a non-transitory storage medium to store or maintain instructions that, when executed by a machine, computing device or system, cause the machine, computing device or system to perform methods and / or operations in accordance with the described examples. The instructions can include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, and the like. The instructions can be implemented according to a predefined computer language, manner or syntax, for instructing the machine, computing device or system to perform a certain function. The instructions can be implemented using any

[0128] One or more aspects of at least one example can be implemented by representative instructions stored on at least one machine-readable medium which represents various logic within the processor, which when read by a machine, such as a computer, cause the machine to create means to perform the techniques described herein. Such representations, known as "IP cores" can be stored on a tangible, machine readable medium and supplied to various customers or manufacturing facilities to load into the fabrication machines that actually make the logic or processor.

[0129] The occurrence of the phrase "one example" or "an example" within the specification is not necessarily referring to the same example or embodiment. Any aspect described herein can be combined with any other aspect or similar aspect, whether or not they are described together herein. The division, omission or inclusion of a block function in the division of functionality between the blocks depicted in the drawings does not infer that the hardware components, circuits, software or entities that support that function must be or be included in that block.

[0130] Coupled" and "connection" along with their derivatives can be used. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms "connected" and / or "coupled" can indicate that two or more elements are in direct physical or electrical contact with each other. On the other hand, the term "coupled" can also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.

[0131] The terms "first," "second," and the like, herein do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The term "a" or "an" herein does not denote a limitation of quantity, but rather denotes the presence of at least one of the referenced item. The term "asserted" as used herein with respect to a signal refers to a state of the signal in which the signal is active and which state can be achieved by asserting any logic level to the signal, whether a logic 0 or a logic 1. The terms "subsequently" or "after" can refer to immediately after or following some other event or events. Other sequences of operations can be performed according to alternative embodiments. Moreover, additional operations can be added or existing operations can be removed depending upon the particular applications. Any combination of variations can be used and one of ordinary skill in the art having the benefit of the present disclosure would understand many variations, modifications, and alternative embodiments.

[0132] Unless specifically stated otherwise, as apparent from the preceding discussions, it is appreciated that throughout the specification, discussions utilizing terms such as "at least one of," "comprising," "including," or "comprising," "containing," or "including," "having," and / or "including" are to be interpreted open rather than excluding possession of other

[0133] Illustrative examples of the devices, systems, and methods disclosed herein are provided below. An embodiment of the devices, systems, and methods can include any one or more, and any combination of, the examples described below.

[0134] Example 1 includes one or more examples and includes an apparatus comprising: a system-in-a-package (SiP) comprising: an interface circuit, and a first circuit to: monitor utilization data for a plurality of processes; determine one or more priority levels associated with at least one of the plurality of processes based on a policy parameter; and adjust an operating frequency of the interface circuit based on the monitored utilization data and the determined one or more priority levels associated with at least one of the plurality of processes, wherein: adjusting the operating frequency of the interface circuit is to prioritize an operating frequency requested by a high-priority workload over an operating frequency requested by a low-priority workload, and the interface circuit comprises one or more of: a memory controller, a direct memory access (DMA) circuit, a cache, a processor-to-processor interconnect, or a bus controller.

[0135] Example 2 includes one or more examples where the first circuit includes one of: software executed by a processor, hardware, microcode executed by a processor, firmware, or a management controller.

[0136] Example 3 includes one or more examples where the policy parameter includes a service level objective (SLO) for the process, and where adjusting the operating frequency of the interface circuit is to satisfy the SLO and adjust power consumption.

[0137] Example 4 includes one or more examples and includes a second circuit to collect telemetry data, where the first circuit is to monitor the power consumption level of the interface circuit based on the telemetry data.

[0138] Example 5 includes one or more examples where the first circuit is to decrease the operating frequency of the interface circuit based on a utilization level of a plurality of cores and a process utilization on at least one core of the plurality of cores, and increase the operating frequency of the interface circuit based on a utilization level of one or more cores of the plurality of cores or a process utilization on at least one core of the plurality of cores.

[0139] Example 6 includes one or more examples where at least one core of the plurality of cores includes a first core, and the first core is to request adjustment of the operating frequency of the interface circuit based on a utilization of the first core by a process executed by the first core and / or a level of that utilization of the first core.

[0140] Example 7 includes one or more examples where the process includes a Kubernetes pod.

[0141] Example 8 includes one or more examples where the first circuit is to adjust the operating frequency of the interface circuit based on one or more of: a priority level of a requester requesting adjustment of the frequency of the interface circuit, a type of the requester, or a level of utilization of the first core by the requester.

[0142] Example 9 includes one or more examples where the SiP includes one or more processors, and the one or more processors are coupled to the interface circuit.

[0143] Example 10 includes one or more examples and includes at least one non-transitory computer-readable medium having instructions stored thereon that, if executed by one or more processors, cause the one or more processors to perform operations including: executing firmware to monitor utilization of one or more processors and to selectively modify an operating frequency of an interface circuit for the one or more processors based on the utilization of the one or more processors, wherein the interface circuit includes one or more of a memory controller, a direct memory access (DMA) circuit, a cache, a processor-to-processor interconnect, or a bus controller.

[0144] Example 11 includes one or more examples, wherein the firmware is to cause the operating frequency of the interface circuit to be decreased based on a level of utilization of the one or more processors and a process utilization on at least one of the one or more processors.

[0145] Example 12 includes one or more examples, wherein the firmware is to cause the operating frequency of the interface circuit to be decreased based on a number of processors of the one or more processors sharing use of the interface circuit allowing the operating frequency to be decreased or a level of utilization of the number of processors of the one or more processors being below a configured low level.

[0146] Example 13 includes one or more examples, wherein the firmware is to cause the operating frequency of the interface circuit to be increased based on at least one level of utilization of the one or more processors or a process utilization on at least one of the one or more processors.

[0147] Example 14 includes one or more examples, wherein the firmware is to cause the operating frequency of the interface circuit to be increased based on a priority level of a requester requesting the operating frequency of the interface circuit to be increased.

[0148] Example 15 includes one or more examples and includes a method of manufacturing a processor, including coupling a plurality of processors to an interface circuit and coupling the interface circuit to a power controller, wherein the power controller adjusts an operating frequency of the interface circuit based on a utilization of one or more of the plurality of processors, and wherein the interface circuit includes one or more of a memory controller, a direct memory access (DMA) circuit, a cache, a processor-to-processor interconnect, or a bus controller.

[0149] Example 16 includes one or more examples, wherein the power controller compares a processor utilization to a level of utilization to determine whether to increase a frequency or decrease a frequency.

[0150] Example 17 includes one or more examples wherein the power controller decreases the frequency of the interface circuit based on a number of consecutive times processor utilization is below a level.

[0151] Example 18 includes one or more examples wherein the power controller decreases the frequency based on a level of utilization of a processor utilizing the interface circuit, and wherein the power controller increases the frequency based on a priority level of a requester requesting the increase in frequency.

[0152] Example 19 includes one or more examples wherein the power controller resets a count of measurements of processor utilization below a level based on increasing the frequency of the interface circuit.

[0153] Example 20 includes one or more examples wherein the power controller comprises one or more of: software executed by the processor, hardware, microcode executed by the processor, firmware, or a management controller.

Claims

1. An apparatus comprising: a system-in-a-package (SiP) comprising: an interface circuit, and a first circuit to: monitor utilization data for a plurality of processes; determine one or more priority levels associated with at least one of the plurality of processes based on policy parameters; and adjust an operating frequency of the interface circuit based on the monitored utilization data and the determined one or more priority levels associated with at least one of the plurality of processes, wherein: adjusting the operating frequency of the interface circuit is to prioritize an operating frequency requested by a high-priority workload over an operating frequency requested by a low-priority workload, and the interface circuit comprises one or more of: a memory controller, a direct memory access (DMA) circuit, a cache, a processor-to-processor interconnect, or a bus controller.

2. The apparatus of claim 1, wherein, the first circuit comprises one of: software executed by a processor, hardware, microcode executed by a processor, firmware, or a management controller.

3. The apparatus of claim 1, wherein, the policy parameters comprise a service level objective (SLO) for the processes, and wherein adjusting the operating frequency of the interface circuit is to meet the SLO and adjust power consumption.

4. The apparatus of claim 1, comprising: a second circuit to collect telemetry data, wherein the first circuit is to monitor a power consumption level of the interface circuit based on the telemetry data.

5. The apparatus of claim 1, wherein, the first circuit is to: decrease the operating frequency of the interface circuit based on a utilization level of a plurality of cores and a process utilization on at least one of the plurality of cores, and increase the operating frequency of the interface circuit based on a utilization level of one or more of the plurality of cores or a process utilization on at least one of the plurality of cores.

6. The apparatus of any one of claims 1-5, wherein: at least one of the plurality of cores comprises a first core, and the first core is to request adjustment of the operating frequency of the interface circuit based on a utilization of the first core by a process executed by the first core and / or a level of that utilization of the first core.

7. The apparatus of claim 6, wherein, the process comprises a Kubernetes pod.

8. The apparatus of claim 6, wherein: the first circuit is to adjust the operating frequency of the interface circuit based on one or more of: a priority level of a requester requesting adjustment of the frequency of the interface circuit, a type of the requester, or a level of utilization of the first core by the requester.

9. The apparatus of claim 1, wherein, the SiP comprises one or more processors, and the one or more processors are coupled to the interface circuit.

10. At least one non-transitory computer-readable medium having instructions stored thereon that, if executed by one or more processors, cause the one or more processors to perform operations comprising: executing firmware to: monitor utilization of one or more processors; and selectively modifying an operating frequency of interface circuitry for the one or more processors based on the utilization of the one or more processors, wherein, The interface circuit includes one or more of a memory controller, a direct memory access (DMA) circuit, a cache, a processor-to-processor interconnect, or a bus controller.

11. The computer-readable medium of claim 10, wherein: The firmware is to cause the operating frequency of the interface circuit to be reduced based on at least one of a level of utilization of the one or more processors or a level of process utilization on at least one of the one or more processors.

12. The computer-readable medium of claim 10, wherein: The firmware is to cause the operating frequency of the interface circuit to be increased based on at least one of a level of utilization of the one or more processors or a level of process utilization on at least one of the one or more processors.

13. The computer-readable medium of claim 10, wherein: The firmware is to cause the operating frequency of the interface circuit to be increased based on a priority level of a requester requesting an increase in the operating frequency of the interface circuit.

14. The computer-readable medium of any of claims 10 to 13, wherein: The firmware is to cause the operating frequency of the interface circuit to be reduced based on at least one of a number of processors of the one or more processors sharing use of the interface circuit allowing the operating frequency to be reduced or a level of utilization of the number of processors of the one or more processors being below a configured low level.

15. A method comprising: A power controller adjusting an operating frequency of an interface circuit based on a level of utilization of one or more processors of a plurality of processors, wherein the interface circuit includes one or more of a memory controller, a direct memory access (DMA) circuit, a cache, a processor-to-processor interconnect, or a bus controller.

16. The method of claim 15, comprising: The power controller comparing a processor utilization to a level of utilization to determine whether to increase the frequency or decrease the frequency.

17. The method of claim 15, comprising: The power controller decreasing the frequency of the interface circuit based on a number of consecutive times a processor utilization is below a level.

18. The method of claim 15, comprising: The power controller decreasing the frequency based on a level of utilization of a processor utilizing the interface circuit, wherein the power controller increases the frequency based on a priority level of a requester requesting an increase in the frequency.

19. The method of claim 15, comprising: The power controller resetting a count of a number of measurements of a processor utilization being below a level based on increasing the frequency of the interface circuit.

20. The method of claim 15, wherein, The power controller includes one or more of software executed by a processor, hardware, microcode executed by a processor, firmware, or a management controller.

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