Resistive random access memory based on ferroelectric domain wall current leading and preparation method thereof

Abstract

The invention relates to a resistive random access memory based on ferroelectric domain wall current leading and a preparation method thereof. The method comprises the following steps: epitaxially growing a BiFeOfilm on a [001] SrTiO single crystal substrate which is beveled at 2 degrees in a [100] direction, and inducing to form a periodic stripe domain structure of which a 71-degree domain wall is parallel to a (101) plane by utilizing the limiting characteristic of the beveled substrate; preparing a top electrode by adopting pulse laser deposition or magnetron sputtering; the electron beam lithography technology is used for preparing a nanoscale planar electrode pair structure type device, ultraviolet lithography is used for preparing a capacitance type device with a micron-sized electrode, and good scale dependence and current response characteristics are achieved. By using the electrode deposited by magnetron sputtering, the defect is introduced at the interface, the change of the Schottky barrier in the polarization overturning process is counteracted, the current of the diode can be effectively suppressed, and the real domain wall current is obtained.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor device technology, in particular to a resistive random access memory based on ferroelectric domain wall current and a preparation method thereof. BACKGROUND

[0002] The polarization reversal in ferroelectric thin films can be regulated by external electric field, forming conductive domain walls, and the resistance change characteristics provide a new idea for high-density memory devices. However, in the prior art, the resistive switching behavior of ferroelectric thin films is often disturbed by multiple current mechanisms, including tunneling current, interface Schottky barrier, and diode current induced by polarization reversal modulation, and domain wall current. Among them, the diode current is caused by the random distribution of interface defects, which leads to unstable device performance, and it is difficult to distinguish the dominant mechanism when coexisting with the domain wall current, which seriously restricts the reliability and large-scale application of the memory. In the prior art, few methods can effectively suppress the diode current and clearly determine the contribution of the domain wall current.

[0003] Ferroelectric materials have attracted extensive attention in the application of non-volatile memory devices due to their spontaneous polarization characteristics. Under the action of an external electric field, the local polarization of a ferroelectric thin film will reverse to the other direction, and the interface between the reversed domain and the un-reversed domain forms a 71° or 109° conductive domain wall (CDW). These conductive domain walls, with their nanoscale size, good stability, and controllability, have become one of the key technologies for developing new high-density resistive random access memory (RRAM).

[0004] The core principle of resistive random access memory based on conductive domain walls is to use the presence or absence of unshielded conductive domain walls formed during the polarization reversal process to realize the reversible switching between low and high resistance states, thereby constructing a memory cell. This type of memory device theoretically has excellent characteristics such as high write speed, low energy consumption, high-density integration, and non-volatility, and has the potential to replace traditional flash memory and dynamic random access memory (DRAM). However, to achieve stable resistive switching behavior dominated by domain wall current, there are still several key technical challenges.

[0005] In the prior art, after the polarization reversal in the ferroelectric thin film, the current conduction mechanism is complex, mainly including tunneling current, diode current induced by Schottky barrier modulation, bulk conductivity, and domain wall current. These current mechanisms often coexist in the device, interfering with each other, making it difficult to identify and accurately regulate the contribution of the domain wall current. Especially in the ferroelectric capacitor structure, there are a large number of uncontrollable defects, oxygen vacancies, and bandgap distortions between the upper and lower electrodes and the ferroelectric layer. The change of the Schottky barrier induced during the polarization reversal process will cause significant rectification behavior, showing strong diode current effect.

[0006] The diode current itself also has certain resistance switching capability, but it mainly depends on the change of the interface barrier height, and the process is highly sensitive to the defect state of the material, the deposition process, the heat treatment condition, etc., so it shows obvious randomness and irreproducibility. In addition, since the ferroelectric material may cause interface charge accumulation during polarization reversal, it will further change the distribution of the Schottky barrier, so that the current response of the device is easily affected by temperature drift, electric field pulse width and polarization hysteresis, thereby reducing the stability and controllability of the whole device.

[0007] More seriously, in the case of coexistence of multiple current mechanisms, even if the conductive domain wall has been successfully introduced and stabilized in the ferroelectric film, it is difficult to accurately determine whether the output current is truly dominated by the domain wall. Changes in electrode size, slight fluctuations in preparation process, and even photoetching residual impurities may change the current path, so that the measurement results are mixed with domain wall current and interface current, further blurring the identification of the dominant mechanism, and causing great obstacles to the subsequent establishment of accurate physical models, the development of multi-device array integration and reliability evaluation.

[0008] Meanwhile, the polarization reversal in the ferroelectric film can be regulated by an external electric field to form a conductive domain wall, and the resistance change characteristics of the conductive domain wall provide a new idea for high-density memory devices. The resistance change behavior of the ferroelectric film in the prior art is often disturbed by multiple current mechanisms, including tunneling current, diode current modulated by interface Schottky barrier, and domain wall current. Among them, the diode current is unstable due to the random distribution of interface defects, and it is difficult to distinguish the dominant mechanism when coexisting with the domain wall current, which seriously restricts the reliability and large-scale application of the memory. In the prior art, there are few methods that can effectively suppress the diode current and clearly determine the contribution of the domain wall current. SUMMARY

[0009] In order to improve the technical defects of effectively suppressing the diode current and clearly determining the contribution of the domain wall current, the application provides a resistance change memory based on ferroelectric domain wall current domination and a preparation method thereof.

[0010] In a first aspect, the resistance change memory based on ferroelectric domain wall current domination and the preparation method thereof provided by the application adopt the following technical scheme: A preparation method of a resistance change memory based on ferroelectric domain wall current domination, comprising the following steps: Scheme one: epitaxially grow the bottom electrode (SrRuO3) and ferroelectric film (BiFeO3) on the

[001] direction single crystal substrate SrTiO3 which is 2° off-cut in the

[100] direction, the periodic stripe domain structure with 71° domain wall parallel to (101) plane can be formed by the limiting effect of the off-cut angle and depth of the substrate; island-like SRO top electrode is prepared by ultraviolet lithography and pulsed laser deposition (PLD), or Pt top electrode is prepared by magnetron sputtering, the electrode diameter is 30, 40, 50, 80, 100, 150 μm, and the thickness is 25 nm; Scheme two: planar nano-electrode pair structure devices are prepared by electron beam lithography, which are used to study the domain wall current behavior at small scales, the electrode gap width is 100 nm, and the electrode gap is 40, 100, 150, 200 nm.

[0011] By adopting the above technical scheme, a plurality of key technical functions are realized, and technical problems in the prior art such as interference of the ferroelectric resistive memory by a plurality of current mechanisms, unstable device performance, and difficulty in independently extracting the domain wall current contribution are solved, and specifically include the following aspects: first, the SrRuO3 bottom electrode and the BiFeO3 ferroelectric film are epitaxially grown on the

[001] direction single crystal substrate SrTiO3 which is 2° off-cut in the

[100] direction, the periodic stripe domain structure with two polarizations is effectively induced and stably formed by the limiting effect of the off-cut angle and direction of the substrate on the crystal growth direction, not only the spatial controllability and reproducibility of the conductive domain wall are improved, but also the conductance fluctuation caused by the random distribution of the domain wall is avoided, thereby the stability and recognition degree of the resistance state in the memory device are enhanced, which is helpful to establish the dominant mechanism of the domain wall current; second, the top electrode is prepared in two ways to adapt to different device structure requirements, island-like SRO top electrode is prepared by ultraviolet lithography combined with pulsed laser deposition (PLD) process, which can realize good lattice matching and interface bonding with the lower BiFeO3, and exclude the diode current caused by the asymmetric contact barrier; Pt top electrode prepared by magnetron sputtering can be used as a hetero-contact structure, which is used to introduce defects at the interface to suppress the change of Schottky barrier in the polarization reversal process, by preparing electrodes of different sizes (30-150 μm), the relationship between the electrode area and the domain wall current under different voltages is studied, and the thickness is accurately controlled within 25 nm, which is conducive to avoiding the occurrence of body conductance dominant phenomenon; Third, in the research of small-scale ferroelectric current behavior, high-precision planar nano-electrode pair structure is prepared by electron beam lithography, so that the electrode spacing is accurately controlled between 40-200 nm, which meets the demand for spatial resolution of the domain wall current at the nanoscale, not only improves the localization ability of the spatial electric field distribution, which is conducive to inducing domain wall reconstruction and current concentration effect, but also provides experimental support for analyzing the electrical response behavior of a single domain wall or domain wall cluster, which is helpful to exclude the interference of other current mechanisms.

[0012] Optionally, in the step one, the angle of the SrTiO3 single crystal substrate is 2°, and the direction of the bevel is

[100] , which is used to induce the formation of the 71° domain wall parallel to the (101) plane of the periodic stripe domain structure in the BiFeO3 thin film.

[0013] By using the above technical scheme, the oriented order and periodic distribution stripe domain structure in the BiFeO3 ferroelectric thin film are induced by using the bevel substrate, so that the controllability and repeatability of the domain wall positioning are improved, the stable output of the domain wall current is enhanced, the interference of the non-ideal conduction mechanism such as the interface current is inhibited, the high-reliability resistance change performance dominated by the domain wall current is realized, and technical support is provided for the construction of high-density and low-power ferroelectric memory devices.

[0014] Optionally, the bottom electrode SrRuO3 (SRO) and the ferroelectric thin film BiFeO3 (BFO) are continuously grown by using a pulse laser deposition (PLD) method, the deposition temperature is 580-630 DEG C, the oxygen pressure is 10-15 Pa, and the laser energy is 1.3-1.5 J / cm 2 .

[0015] By using the above technical scheme, the SrRuO3 bottom electrode and the BiFeO3 ferroelectric thin film are continuously grown by using a pulse laser deposition (PLD) method under the conditions of 580-630 DEG C, 10-15 Pa of oxygen pressure, and 1.3-1.5 J / cm 2 , so that high-quality epitaxial growth is realized, the lattice matching and interface stability between the electrode and the thin film are ensured, the defect density is reduced, the order of the domain wall structure and the overall electrical performance of the device are improved, and a reliable foundation is provided for realizing the stable domain wall current conduction behavior and the high-repeatability resistance change effect.

[0016] Optionally, in the ultraviolet lithography process, a positive photoresist is used, the exposure wavelength is 365 nm, the exposure time is 12 seconds, and the development time is 60 seconds.

[0017] By using the above technical scheme, in the ultraviolet lithography process, a positive photoresist is used, the exposure wavelength is 365 nm, the exposure time is 12 seconds, and the development time is 60 seconds, so that high-precision transfer of the micron-level electrode pattern can be realized, the pattern edge is effectively ensured to be clear and the size is stable, an accurate mask structure is provided for the subsequent deposition of the top electrode, the processing precision and consistency of the electrode pattern are improved, and thus the structure control force and the current channel repeatability of the device under the microscale are enhanced.

[0018] Optionally, in the process of preparing the Pt top electrode by using a magnetron sputtering method, the sputtering power is 80 W, the deposition time is 200 seconds, the deposition gas pressure is 5 mTorr, and the temperature is 350 DEG C.

[0019] By adopting the technical scheme, the sputtering power is controlled to be 80 W, the deposition time is 200 seconds, the deposition pressure is 5 mTorr, and the temperature is 350 DEG C during the preparation of the Pt top electrode by the magnetron sputtering, so that the uniform deposition and thickness precision control of the Pt electrode can be realized, the metal electrode layer with the dense surface and good adhesion is obtained, the interface resistance is reduced, the device stability and the conductive consistency are improved, the non-ideal current path caused by process fluctuation is avoided, and it is ensured that the resistance change characteristics are mainly dominated by the domain wall current.

[0020] Optionally, the planar nano electrode prepared by the electron beam lithography adopts a Cr / Au double-layer metal structure, the thickness of the Cr layer is 5 nm, and the thickness of the Au layer is 30 nm.

[0021] By adopting the technical scheme, the Cr / Au double-layer metal planar nano electrode structure is prepared by the electron beam lithography, the thickness of the Cr layer is 5 nm to play a good adhesion role, the thickness of the Au layer is 30 nm to ensure excellent conductivity and chemical stability, high-precision patterning and stable electrical performance of the nano electrode are realized, the mechanical strength and the conductive uniformity of the electrode are effectively improved, a reliable electrode interface is provided for the research and control of the micro-nano scale domain wall current, and the small-size current response and repetition of the device are enhanced.

[0022] The planar nano electrode prepared by the electron beam lithography adopts a Cr / Au double-layer metal structure, the thickness of the Cr layer is 5 nm, and the thickness of the Au layer is 30 nm.

[0023] Optionally, the gap size between the electrodes for researching the domain wall current behavior is precisely controlled by adjusting the electron beam exposure dose, and the gap tolerance is controlled to be within ±10 nm.

[0024] By adopting the technical scheme, the electron beam exposure dose is precisely adjusted, the high-precision control of the gap size between the electrodes is realized, the gap tolerance is kept within ±10 nm, the size consistency and the reproducibility of the electrode gap under the nano scale can be significantly improved, the current behavior of a single or a few domain walls can be accurately detected and analyzed, the current interference caused by the size fluctuation is reduced, and the reliability of the experimental data and the clear verification of the domain wall current dominant mechanism are ensured.

[0025] In a second aspect, the application provides a resistance change memory based on a ferroelectric domain wall current dominant, which adopts the following technical scheme: a resistance change memory based on a ferroelectric domain wall current dominant, the resistance change memory body is determined by a capacitive type and a planar electrode pair type two structure determination methods reliability; The resistance change memory body in the capacitive type structure comprises a bottom electrode 1, a ferroelectric film is arranged on the bottom electrode, and a top electrode is arranged at the upper end of the ferroelectric film. The bottom electrode and the ferroelectric film are epitaxially grown, and the top electrode is deposited by magnetron sputtering; The planar electrode pair type is composed of a ferroelectric film and a planar electrode, and the planar electrode is deposited by magnetron sputtering.

[0026] By adopting the technical scheme, a dual verification system with a capacitor type structure and a planar electrode pair type structure is constructed, the reliability and functional stability of the resistive random access memory dominated by the ferroelectric domain wall current are enhanced, the capacitor type structure realizes a complete three-dimensional current path through high-quality epitaxial growth and deposition of the bottom electrode, the ferroelectric film and the magnetron sputtering top electrode, and effectively reflects the resistive random access memory characteristic of the ferroelectric domain wall current; the planar electrode pair type structure provides a two-dimensional current path, which is convenient for fine regulation and analysis of the domain wall current in a small scale; the combination of the two structures helps to accurately identify and confirm the dominant position of the domain wall current in the resistive random access memory process, and improves the design flexibility and reliability of practical application of the device.

[0027] Optionally, the top electrode includes a positive electrode and a negative electrode, the positive electrode is not less than one, and the negative electrode is several.

[0028] By adopting the technical scheme, the positive electrode not less than one and the multiple negative electrodes are arranged in the top electrode structure, which can realize multi-point sampling and multi-channel current path design, help to comprehensively evaluate the distribution and change characteristics of the domain wall current in different regions of the ferroelectric film, enhance the current detection accuracy of the device in the local region, improve the spatial resolution and electrical signal acquisition efficiency, and provide more abundant data support for analyzing the resistive random access memory behavior dominated by the domain wall current, thereby improving the flexibility of device design and the reliability of experimental results.

[0029] Optionally, the bottom electrode 1 is a SrRuO3 material, the ferroelectric film is a BiFeO3 material, and the two are epitaxially grown along the

[001] direction on a SrTiO3 single crystal substrate to form a periodic stripe domain structure, thereby enhancing the stability and repeatability of the resistive random access memory performance.

[0030] By adopting the technical scheme, SrRuO3 is selected as the bottom electrode, BiFeO3 is selected as the ferroelectric film, and epitaxial growth is performed along the

[001] direction on the SrTiO3 single crystal substrate, which can realize a high-quality heterostructure with good lattice matching, induce the formation of a 71° domain wall parallel to the periodic stripe domain structure of the (101) plane, significantly improve the spatial order and stability of the domain wall, thereby enhance the conduction stability and repeatability of the domain wall current, realize the consistency and reliability of the electrical performance of the resistive random access memory device, and meet the requirement of long-term operation stability for high-density non-volatile memory devices.

[0031] In summary, the present application includes at least one of the following beneficial technical effects: 1. By using magnetron sputtering to deposit the electrode, defects are introduced at the interface, which offsets the change of the Schottky barrier in the polarization reversal process.

[0032] 2. The defects introduced by the interface can effectively suppress diode current and obtain true domain wall current.

[0033] 3. By using a

[001] SrTiO3 single crystal substrate with a 2° bevel angle to induce a periodic striped domain structure with 71° domain walls parallel to the (101) plane, the non-ideal diode current caused by the modulation of the interface Schottky barrier is avoided, which effectively improves the purity and dominance of the domain wall current and significantly enhances the controllability of the device's conductivity mechanism.

[0034] 4. Two structures, capacitive and planar electrode pair, were constructed. By comparing and analyzing the domain wall current behavior with different structural scales and electrode configurations, the contribution of the domain wall current to the resistive switching effect of the device was clarified, thus solving the problem of mixed and difficult-to-distinguish current mechanisms under traditional structures.

[0035] 5. By utilizing the high-quality epitaxial growth of SrRuO3 and BiFeO3 on SrTiO3 substrates, a stable and ordered domain structure is achieved, ensuring consistent resistance states after each polarization reversal, thereby enhancing the electrical reliability and data retention capability of the device under long-term operation.

[0036] 6. High-resolution planar electrode patterns with a spacing of 40–200 nm were fabricated using electron beam lithography and Cr / Au bilayer nanoelectrode structures. This provides a powerful experimental platform for studying the behavior of single domain walls and their correlation with microstructures, and is suitable for the development of next-generation high-density memory chips.

[0037] 7. Electrode types include SRO and Pt heterometallic island structures, with a size range of 30–150 μm and thickness control accuracy up to 25 nm. They can adapt to the requirements of different test environments for parameters such as interface, area, and electric field distribution, improving test flexibility and experimental efficiency.

[0038] 8. By introducing positive photoresist technology, controlling exposure and development parameters, and precisely controlling the gap tolerance to within ±10nm by electron beam exposure dose, the electrode spacing can be controlled more accurately, which helps to refine the domain wall current path and improve repeatability. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the structure and testing principle of the capacitive resistive random access memory according to an embodiment of this application; Figure 2 yes Figure 1 A schematic diagram of the device under a microscope; Figure 3 yes Figure 1 A schematic diagram of the planar electrode structure and its testing principle; Figure 4 The regulation mechanism of the embodiments of this application Figure 1 ; Figure 5 The regulation mechanism of the embodiment of the present application Figure 2 ; Figure 6 The regulation mechanism of the embodiment of the present application Figure 3 ; Figure 7 The total test schematic diagram of the resistive random access memory of the embodiment of the present application.

[0040] Mark explanation: 10, resistive random access memory; 1, bottom electrode; 2, ferroelectric film; 3, top electrode; 31, positive electrode; 32, negative electrode. DETAILED DESCRIPTION

[0041] The following will be combined with the attached Figures 1-7 The present application is further described in detail.

[0042] The embodiment of the present application discloses a preparation method of resistive random access memory based on ferroelectric domain wall current. Referring to Figure 1 , Figure 3 , comprising the following steps: Scheme one: the bottom electrode (SrRuO3) and the ferroelectric film (BiFeO3) are epitaxially grown on the single crystal substrate SrTiO3 which is 2° inclined in the

[100] direction, and the periodic stripe domain structure with 71° domain wall parallel to the (101) plane can be formed by the limiting effect of the inclined angle and the inclined direction of the substrate; the island-shaped SRO top electrode is prepared by ultraviolet lithography and pulsed laser deposition (PLD), or the Pt top electrode is prepared by magnetron sputtering, the electrode diameter is 30, 40, 50, 80, 100, 150 μm, and the thickness is 25 nm; Scheme two: the planar nano electrode pair is prepared by electron beam lithography, which is used to study the domain wall current behavior under small scale, the electrode gap width is 100 nm, and the electrode gap is 40, 100, 150, 200 nm.

[0043] The interface regulation of the embodiment is that the increased interface defect concentration through the high-energy deposition process of the Pt electrode dominates the charge injection and capture at the interface, shields the reversed polarization, makes the interface Schottky barrier height not affected, weakens the diode current, and makes the domain wall current dominant.

[0044] The regulation mechanism of the embodiment is: 1. For the capacitor device of the SRO top electrode, the on-state current and the electrode diameter meet the relationship, d is the electrode size. When the voltage is higher than 2.4 V, the n value of the curve fitting is close to 2, indicating that the polarization flip modulated Schottky barrier dominates the entire conduction process. With the decrease of the voltage, the n value decreases from 1.99 to 1.35. Since the equation of Schottky emission, the current size is exponentially proportional to the applied voltage, indicating that the diode current decreases rapidly in the low voltage region, and the domain wall begins to dominate the conduction process. Therefore, when the n value is between 1-2, the measured macroscopic current is the result of the joint action of the diode current caused by the polarization flip modulated Schottky barrier and the conduction of the conduction domain wall.

[0045] Referring to Figure 4 , SRO top electrode capacitor device: (a) is the I-V curve of the device with different electrode diameters, and the insert is the curve of the electrode size and the corresponding coercive pressure; (b) is the relationship curve of the electrode diameter and the on-state current under different bias voltages, and the short dashed line represents the fitting curve.

[0046] 2. For the capacitor device of the Pt top electrode, the on-state current value related to the size is extracted. Under different voltages, with the increase of the size of the device, the on-state current increases linearly, and the linear fitting result of the data points shows that the resistance change process of the Pt / BFO / SRO capacitor is no longer dominated by the diode current. The on-state current is more likely to be dominated by the conduction domain wall that penetrates the entire BFO film connecting the SRO bottom electrode and the Pt top electrode.

[0047] Referring to Figure 5 , Pt top electrode capacitor device: (a) is the I-V curve of the device with different electrode diameters, and the insert is the corresponding coercive pressure of the device with different electrode sizes; (b) is the relationship curve of the electrode diameter and the current under different bias voltages, and the short dashed line represents the fitting curve.

[0048] 3. Since the data obtained from a limited range of electrode diameters may not be direct evidence of the conduction of the domain wall dominating the resistance change behavior in the BFO device, we prepared Pt electrodes on the surface of the BFO film without using the SRO bottom electrode to study the resistance change behavior in a smaller scale. As can be seen from the following figure, under different voltages, the current and the electrode size show a linear relationship, that is, the current is still dominated by the conduction domain wall.

[0049] Referring to Figure 6 , planar electrode device: (a) is the I-V curve of the nanometer ferroelectric device with different electrode widths, and the insert is the coercive pressure curve with the change of the electrode width; (b) is the fitting curve of the change of the electrode width with the on-state current.

[0050] The implementation principle of the preparation method of the ferroelectric domain wall current dominated resistive random access memory according to the embodiment of the application is as follows: based on the dominant role of the controllably formed conductive domain wall structure in the ferroelectric film in the current transmission behavior, combining interface engineering, electrode structure design and scale effect regulation and other key means, a high-stability resistive random access memory mechanism with the domain wall current as the main conduction current is clearly established. The method is developed around the regulation of the domain wall conductivity, and through experimental structure design and parameter analysis, the transformation from the diode current to the domain wall current dominated mechanism is successfully realized, and the recognition and stability of the device are improved. First, at the material growth level, a

[001] direction SrTiO3 single crystal substrate with a

[100] direction oblique cut of 2° is used, and a SrRuO3 bottom electrode and a BiFeO3 ferroelectric film are epitaxially grown. Through the substrate oblique cut angle induced stress field and lattice orientation, a periodic stripe domain structure with spatial order and 71° domain wall parallel to the (101) plane is realized in BiFeO3, which significantly improves the uniformity, direction consistency and formation probability of the conductive domain wall in the device, and enhances the existence stability and spatial controllability of the domain wall current channel from the source. Secondly, the electrode design aspect respectively constructs a capacitor type device structure (vertical current path) and a planar electrode pair type device structure (horizontal current path) for systematic study of the conductive behavior under different scales and different structures. In the capacitor type structure, island-shaped SrRuO3 top electrode and Pt metal top electrode are selected, wherein the SRO top electrode and the BiFeO3 belong to the same perovskite material, have good lattice matching and interface bonding performance, and are conducive to the formation of a symmetrical interface barrier structure. The Pt metal top electrode has higher chemical activity and larger work function difference. Defects are induced at the interface through the magnetron sputtering plasma enhancement process, which dominates the subsequent charge injection and capture, reduces the Schottky barrier height, and thus weakens the dominant role of the diode current and enhances the current proportion of the conductive domain wall.This interface regulation strategy becomes the key to realize the mechanism conversion in this embodiment; again in the conductive behavior of the capacitor device based on the SRO top electrode, through the analysis of the I-V curve and the current-size relationship under different electrode diameter sizes, it is shown that in the high voltage region, the device shows typical nonlinear Schottky behavior, and the current and voltage satisfy the exponential relationship; while in the low voltage region, the n value decreases significantly to 1.3-1.5, indicating that the diode current decays rapidly, at this time the domain wall current begins to play a dominant role, forming the main contribution of the macroscopic conductance of the device; In contrast, the on-state current of the Pt top electrode device linearly increases with the electrode area in the same voltage interval, showing a different carrier mechanism from the Schottky behavior, indicating that the Pt top electrode induces interface defects and enhances carrier injection, effectively inhibits the diode current caused by the change of Schottky barrier due to polarization reversal, so that the conductive domain wall builds a penetrating path in the BFO film, and dominates the whole resistance change process; Finally, in order to further strip the influence of the bottom electrode structure on the current behavior, a Pt planar electrode opposite type device is prepared on the surface of the BFO thin film without a bottom electrode, and an electron beam lithography is used to accurately control the electrode spacing (40-200nm). In the planar device, through the I-V test under different electrode widths, it is found that the current and the electrode width keep good linear relationship, further confirming that the device current comes from the conductive domain wall of the planar direction connected electrode pair, rather than the diode effect modulated by the interface barrier. Figures 4-5 The change of coercive pressure also supports that the polarization reversal process and the domain wall behavior under different sizes are highly related, which shows that the device behavior is dominated by the domain wall structure.

[0051] The embodiment of the present application discloses a resistance change memory based on ferroelectric domain wall current dominance, referring to Figure 1 , including a resistance change memory body 10, which is determined by a reliable method of capacitor type and planar electrode pair type structure; the resistance change memory body 10 of the capacitor type structure includes a bottom electrode 1, an ferroelectric thin film 2 arranged on the bottom electrode 1, a top electrode 3 arranged on the upper end of the ferroelectric thin film 2, the top electrode 3 includes a positive electrode 31 and a negative electrode 32, the positive electrode 31 is not less than one, and the negative electrode 32 is several; the bottom electrode and the ferroelectric thin film are epitaxially grown, and the top electrode is deposited by magnetron sputtering; the planar electrode pair type is composed of the ferroelectric thin film 2 and a planar electrode, and the planar electrode is deposited by magnetron sputtering; the bottom electrode 1 is a SrRuO3 material, the ferroelectric thin film 2 is a BiFeO3 material, and both are epitaxially grown along the

[001] direction on a SrTiO3 single crystal substrate to form a periodic stripe domain structure with 71° domain wall parallel to the (101) plane, thereby enhancing the stability and repeatability of the resistance change performance.

[0052] The resistive memory body 10 firstly realizes the dual verification of the resistive change mechanism by constructing two device structures of the capacitor type and the planar electrode pair type, improves the credibility of the device working principle and the repeatability of the experimental results, wherein the capacitor type structure adopts a "bottom electrode-ferroelectric film-top electrode" vertical structure, has a clear polarization direction and electric field control ability, and is helpful to macroscopically characterize the modulation effect of ferroelectric polarization on current behavior; the planar electrode pair type structure adopts a horizontal electrode distribution, is suitable for precise detection of domain wall current and local conductance distribution in micro-nano scale, and the two structures complement each other, providing a structural basis for systematically analyzing the dominant position of the domain wall current in the ferroelectric resistive memory. The material system selects SrRuO3(SRO) as the bottom electrode and BiFeO3(BFO) as the ferroelectric film material, and is epitaxially grown on a

[100] direction SrTiO3 single crystal substrate with a 2° tilt, forming a heterostructure along the

[001] direction. This configuration realizes the ordered construction of the periodic 71° conductive domain wall in the BiFeO3 film by using the strain field induced by the tilted substrate, significantly improves the controllability and spatial consistency of the domain wall, effectively avoids the problem of device conductance fluctuation caused by the randomness of the domain wall distribution, thereby enhancing the repeatability and recognition of the resistive change behavior, and providing structural guarantee for constructing high-reliability ferroelectric memory cells. The top electrode structure adopts a multi-electrode configuration design, not less than one positive electrode and a plurality of negative electrodes. Through this multi-point electrode system, multi-channel read-write test can be realized, and the domain wall current behavior of different regions of the ferroelectric film can be spatially resolved and compared, which is beneficial to statistical analysis of the consistency and local conductive difference of the current channel. The top electrode is prepared by a high-consistency deposition process of magnetron sputtering, which ensures the uniform thickness, good surface density and stable interface adhesion of the metal electrode layer, effectively reduces the interface resistance and carrier scattering, and improves the contact reliability and current transmission efficiency between the electrode and the ferroelectric material.

[0053] The implementation principle of the embodiment of the application is as follows: the periodically 71° conductive domain wall controlled and constructed in the BiFeO3 ferroelectric film is used as the main conduction channel, the repeatable manipulation of the resistive switching behavior is realized by adjusting the electrode structure and external bias, the capacitor type and planar electrode pair type are introduced into the structure of the resistive switching memory body 10, and are respectively used for the polarization adjustment in the macro scale and the fine study of the domain wall current in the micro-nano scale, so that the dominant position of the domain wall current in the overall conduction process is verified, the SrRuO3 bottom electrode and the BiFeO3 film are epitaxially grown on the obliquely cut SrTiO3 single crystal substrate, the lattice strain regulation is realized to induce the periodic and orderly distribution of the conductive domain wall, the consistency and stability of the domain wall conduction are significantly improved, the stable electrode interface is constructed by the multi-point electrode arrangement and the high-consistency magnetron sputtering deposition process, the current response is ensured to come from the domain wall channel rather than the interface effect or the bulk conduction, and the high-stability and high-repeatability ferroelectric resistive switching memory device with the conductive domain wall as the dominant mechanism is realized.

[0054] The main key points of the technical solution of the application are as follows: Pt film is deposited on the surface of the film by magnetron sputtering, the barrier change in the polarization reversal process is inhibited by the interface defects, the diode current is inhibited, and the domain wall current is obtained. The material is irrelevant to the work function of the metal material, and is related to the preparation method of the electrode material.

[0055] The main technical protection points of the technical solution of the application are as follows: the device structure and the planar Pt nano electrode pair structure, the device structure is the vertical capacitor structure of the Pt top electrode / BFO ferroelectric layer / SRO bottom electrode; the electrode material of the planar Pt nano electrode pair structure is the Pt electrode, the deposition process of the top electrode material is the magnetron sputtering, and the domain wall current dominant mechanism adopts the linear relationship between the domain wall current and the electrode size.

[0056] The alternative solution of the technical solution of the application is as follows: the Cu electrode is also deposited by the magnetron sputtering scheme, and the defects introduced at the interface can also inhibit the diode current.

[0057] The above are the preferred embodiments of the application, and do not limit the protection scope of the application, so: all equivalent changes made according to the structure, shape and principle of the application should be covered in the protection scope of the application.

Claims

1. A method for preparing a ferroelectric domain wall current dominated resistive switching memory, characterized in that: The method comprises the following steps: Scheme 1: A bottom electrode (SrRuO3) and a ferroelectric film (BiFeO3) are epitaxially grown on a single crystal substrate SrTiO3 with a [001] direction 2° bevelled in a [100] direction, and a periodic stripe domain structure with 71° domain walls parallel to the (101) plane is formed by the limiting effect of the bevel angle and the bevel direction of the substrate; an island-shaped SRO top electrode is prepared by ultraviolet lithography combined with pulsed laser deposition (PLD), or a Pt top electrode is prepared by magnetron sputtering deposition, and the electrode diameter is 30, 40, 50, 80, 100, 150 μm, and the thickness is 25 nm; Scheme 2: A ferroelectric film (BiFeO3) is directly epitaxially grown on a single crystal substrate SrTiO3 with a [001] direction 2° bevelled in a [100] direction, and a planar nano electrode pair is prepared by electron beam lithography and magnetron sputtering deposition, and the electrode gap width is 100 nm, and the electrode gap width is 40, 100, 150, 200 nm.

2. The method of claim 1, wherein: In the two schemes, the bevel angle of the SrTiO3 single crystal substrate is 2°, and the bevel direction is [100], which is used to induce the formation of a periodic stripe domain structure with 71° domain walls parallel to the (101) plane in the BiFeO3 film.

3. The method of claim 1, wherein: The bottom electrode SrRuO3 (SRO) and the ferroelectric film BiFeO3 (BFO) are continuously grown by a pulse laser deposition (PLD) method, the deposition temperature is 580-630 ℃, the oxygen pressure is 10-15 Pa, and the laser energy is 1.3-1.5 J / cm 2 .

4. The method of claim 1, wherein: In the ultraviolet lithography process, a positive photoresist is used, the exposure wavelength is 365 nm, the exposure time is 12 seconds, and the development time is 60 seconds.

5. The method of claim 1, wherein: In the process of preparing the Pt top electrode by magnetron sputtering, the sputtering power is 80 W, the deposition time is 200 seconds, the deposition pressure is 5 mTorr, and the growth temperature is 350 °C.

6. The method of claim 1, wherein: The planar nano electrode prepared by electron beam lithography adopts a Cr / Au double-layer metal structure, the thickness of the Cr layer is 5 nm, and the thickness of the Au layer is 30 nm.

7. The method of claim 1, wherein: The electrode gap size for studying the domain wall current behavior is precisely controlled by adjusting the electron beam exposure dose, and the gap tolerance is controlled within ±10 nm.

8. Resistive switching memory based on ferroelectric domain wall current dominance, comprising a resistive switching memory body (10), characterized in that: The resistive random access memory body (10) is determined by two structure methods of capacitive type and planar electrode pair type; The resistive random access memory body (10) of the capacitive type structure comprises a bottom electrode (1), a ferroelectric film (2) arranged on the bottom electrode (1), and a top electrode (3) arranged at the upper end of the ferroelectric film (2); The bottom electrode and the ferroelectric film are epitaxially grown, and the top electrode is deposited by magnetron sputtering; The planar electrode pair type is composed of a ferroelectric film (2) and a planar electrode, and the planar electrode is deposited by magnetron sputtering.

9. The resistive random access memory based on ferroelectric domain wall current domination as claimed in claim 2, wherein: The top electrode (3) comprises a positive electrode (31) and a negative electrode (32), the positive electrode (31) is not less than one, and the negative electrode (32) is several.

10. The resistive random access memory based on ferroelectric domain wall current domination according to claim 8 or 9, characterized in that the bottom electrode (1) is a SrRuO3 material, and the ferroelectric film (2) is a BiFeO3 material, both of which are epitaxially grown along a [001] direction on a SrTiO3 single crystal substrate to form a periodic stripe domain structure with 71° domain walls parallel to the (101) plane, thereby enhancing the stability and repeatability of the resistive random access memory performance.

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