MOSFET capable of reducing dynamic parameters of device and preparation method

Abstract

The invention discloses an MOSFET capable of reducing dynamic parameters of a device and a preparation method, and relates to the technical field of semiconductors. The epitaxial layer is provided with an active region groove, and the active region groove is internally provided with grid polycrystalline silicon and first source polycrystalline silicon which are arranged at intervals up and down and is filled with a first dielectric layer; compared with a traditional SGT device structure formed in one step, the IPO thickness is greatly increased, the dynamic parameters of the device are reduced, the reliability is improved, and meanwhile, the additional photomask cost is not increased. The problem of electric field concentration caused by a too thin oxide layer at a grid corner position during the design of a low VTH device under a relatively thin gate oxide due to a relatively thin IPO formed in one step is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a MOSFET for reducing dynamic parameters of a device and a preparation method. BACKGROUND

[0002] Discrete power devices are an important category of semiconductor discrete devices, mainly used for converting, controlling and regulating electric energy in power electronic systems. In discrete power devices, Split-Gate Trench (SGT) MOSFET has become the mainstream choice for medium and low voltage (30V-250V) applications due to low gate charge (Qg), high switching speed and figure of merit (FOM). The core structure of SGT MOSFET reduces the on-resistance (Rds_on) and switching loss by splitting the gate trench, i.e., separating the gate (Gate poly) and the source (Source poly) by inter-poly oxide. There are two main processes for forming the inter-poly oxide: 1. Through HDP (High Density Plasma) combined with CMP (Chemical Mechanical Polishing) technology, which has certain requirements for the filling aspect ratio and is relatively high in cost; 2. Through one-step forming (thermal) process, which is simple and low in cost, but the IPO formed by one-step forming is relatively thin (1.5-2 times the thickness of the gate oxide layer), and when the product needs a low threshold voltage (VTH), a thin gate oxide layer (300A-500A) is needed, and the inter-poly oxide formed is also relatively thin, which will increase the gate-source reverse leakage current of the product; at the same time, it will also increase the dynamic parameters (such as input capacitance ciss) of the product, and in extreme cases, it can cause reliability failure. SUMMARY

[0003] The present application provides a MOSFET for reducing dynamic parameters of a device and a preparation method, which can reduce the dynamic parameters of the device, improve the reliability, and does not increase the cost of additional masks.

[0004] The technical solution of the present application is: A preparation method of a MOSFET for reducing dynamic parameters of a device, comprising the following steps: Step 1: growing an epitaxial layer on a substrate wafer, and depositing silicon dioxide on the epitaxial layer to form a hard mask; Step 2: forming a plurality of trenches by etching process; Step three: after the formation of the field dielectric layer by growing on the trench and the epitaxial layer, the source polysilicon is filled in the trench, and is etched back to the surface of the trench; Step four: the area to be etched is defined by a source polysilicon photoetching mask, and the source polysilicon is etched back; after the etching is completed, the source polysilicon is re-doped by using the mask again; Step five: the field dielectric layer in the active area trench region is removed by 1 / 3-2 / 3 of the thickness by using a wet process, and the source polysilicon is etched back again; Step six: the remaining field oxide layer on the sidewall of the active area trench is removed by using a wet process; Step seven: an oxide layer with a thickness of 500-1500A is grown on the active area trench to form an inter-gate oxide; Step eight: the deposition of gate polysilicon is performed on the active area trench, and is etched back to the silicon surface level; Step nine: the gate polysilicon is etched back to a position below the designed channel; and the remaining sidewall gate oxide layer is continuously etched by using a wet process to serve as the required gate oxide layer thickness of the device, and to form a cell trench with different thicknesses of gate oxide layers; Step ten: the deposition and annealing of gate polysilicon is performed in the source area trench; Step eleven: the ion implantation process of the body region P-body and the source forms the channel region of the device; Step twelve: the deposition of an ILD dielectric layer and the definition of the contact source of the device by a mask are performed; Step thirteen: the sputtering of the front metal and the deposition of the passivation layer are performed.

[0005] Specifically, the trench includes an active area trench and a terminal area trench.

[0006] Specifically, the etching back of the source polysilicon in step four has a depth of 0.8-2um.

[0007] Specifically, the re-doping in step four has a doping concentration greater than 1e 21 , and the doping ion is arsenic As.

[0008] Specifically, the etching back of the source polysilicon in step five has a depth of 1-2um.

[0009] Specifically, the remaining sidewall gate oxide layer is continuously etched by using a wet process to a thickness of 300-1000A in step nine.

[0010] Specifically, the body region P-body in step eleven includes a first body region P-body and a second body region P-body which are arranged by a trench.

[0011] A MOSFET for reducing device dynamic parameters, comprising, from bottom to top, a substrate, an epitaxial layer, an ILD dielectric layer, a metal layer and a passivation layer; The epitaxial layer is provided with: An active region trench, the active region trench is provided with a gate polysilicon and a first source polysilicon arranged in an upper and lower interval, and filled by a first dielectric layer; A terminal region trench, the terminal region trench is provided with a second source polysilicon, and filled by a second dielectric layer; the second dielectric layer extends upward to between the ILD dielectric layer and the epitaxial layer; A first body region P-body, located at a side of the active region trench, and extending downward from a top of the epitaxial layer; A first source region, arranged at a top of the first body region P-body; A second body region P-body, located between the terminal region trench and the active region trench, and extending downward from a top of the epitaxial layer; The ILD dielectric layer is provided with a first metal connection region extending to the first body region P-body, a second metal connection region extending to the second body region P-body and a third metal connection region extending to the second source polysilicon.

[0012] Specifically, the first source region has a depth range of 0.2-0.5 um.

[0013] Specifically, the first body region P-body and the second body region P-body each have a depth range of 0.5-1.5 um.

[0014] The IPO thickness is improved by process design of ladder type gate oxide layer combined with heavy doping of polysilicon to improve oxidation effect, compared with the traditional one-step forming SGT device structure, the IPO thickness is greatly increased, the device dynamic parameters are reduced, the reliability is improved, and the additional mask cost is not increased. The problem of electric field concentration caused by too thin oxide layer at the gate corner position in the design of low VTH device under the condition of thin IPO in one-step forming is solved. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a structural schematic diagram of step one of the present application, Figure 2 is a structural schematic diagram of step two of the present application, Figure 3 is a structural schematic diagram of step three of the present application, Figure 4 is a structural schematic diagram of step four of the present application, Figure 5 is a structural schematic diagram of step five of the present application, Figure 6is a structural schematic diagram of step six of the present application, Figure 7 is a structural schematic diagram of step seven of the present application, Figure 8 is a structural schematic diagram of step eight of the present application, Figure 9 is a structural schematic diagram of step nine of the present application, Figure 10 is a structural schematic diagram of step ten of the present application, Figure 11 is a structural schematic diagram of step eleven of the present application, Figure 12 is a structural schematic diagram of step twelve of the present application, Figure 13 is a structural schematic diagram of step thirteen of the present application, Figure 14 is an Inter-Poly Oxide thickness and input capacitance ciss simulation diagram; In the figure, 100 is a substrate, 200 is an epitaxial layer, 300 is an ILD dielectric layer, 400 is a metal layer, 500 is a passivation layer, 600 is an active region trench, 610 is a gate polysilicon, 620 is a first source polysilicon, 630 is a first dielectric layer, 700 is a terminal region trench, 710 is a second source polysilicon, 720 is a second dielectric layer, 810 is a first body region P-body, 820 is a second body region P-body, 900 is a first source region, A10 is a first metal connection region, A20 is a second metal connection region, A30 is a third metal connection region. DETAILED DESCRIPTION

[0016] Embodiments of the present application are described in detail below with reference to the accompanying drawings, examples of which are shown in the drawings, wherein the same or similar notations represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application and cannot be understood as a limitation of the present application.

[0017] In the description of the present application, it should be understood that the terms "upper", "lower", "left", "right", "vertical", "horizontal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0018] In the description of the present application, it is to be noted that unless specifically stated and limited otherwise, the terms "mounting", "connected", "connection" should be understood broadly, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through intermediate medium, can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0019] A preparation method of a MOSFET for reducing device dynamic parameters, comprising the following steps: Step one: grow an epitaxial layer on the substrate 100, deposit silicon dioxide on the epitaxial layer to form a hard mask, and coat photoresist, as shown in Figure 1 ; Step two: define a trench area on the hard mask by using a trench mask, form a plurality of trenches by etching process, and then remove the hard mask and photoresist; The trench includes a cell trench and a terminal trench, as shown in Figure 2 ; Step three: after growing a field dielectric layer on the trench and the epitaxial layer, fill the source poly in the trench, and etch back to the surface of the trench, as shown in Figure 3 ; Step four: as shown in Figure 4 , define the area to be etched by the source poly photoresist mask and etch back the source poly, the etch back depth is determined according to different voltage products, generally between 0.8~2um; after etching, the source poly is re-doped again using the mask, which improves the oxidation effect of subsequent IPO growth. After a large number of phosphorus atoms enter the silicon lattice, a large number of electrons will be generated. In order to maintain electrical neutrality, more vacancies will be generated in the silicon lattice, which provides more channels and reaction sites for the diffusion of oxygen atoms in silicon, thereby accelerating the oxidation reaction. The thick (usually 1500A~7000A; and the thickness increases with the increase of the breakdown voltage BV of the product, such as 100V product usually in 5000A~6000A) field dielectric (liner oxide) becomes a barrier layer of the hard mask; the re-doped doping concentration is greater than 1e 21 , the doping ion is arsenic As.

[0020] Step five: without removing the photoresist, remove 1 / 3~2 / 3 thickness of the field dielectric layer in the cell trench area by using wet process, as shown in Figure 5 , etch back the source poly again, and the etch back depth is 1~2um; Step six: remove the photoetching plate, and remove the remaining field oxide layer on the active area trench side wall by using a wet process, as shown in Figure 6 ; Step seven: grow an oxide layer with a thickness of 500-1500A on the active area trench to form a relatively thick inter-poly oxide, as shown in Figure 7 , the oxide layer grown at the IPO position is 1.5-2 times thicker than the trench side wall; Step eight: deposit gate polysilicon on the active area trench and etch back to the silicon surface level, as shown in Figure 8 ; Step nine: etch back the gate polysilicon to a position below the designed channel, generally set at 0.6-2um; and continue to etch the remaining side wall gate oxide layer to 300-1000A by using a wet process, as the required gate oxide layer thickness of the device, and form a cell trench with different thickness gate oxide layers, as shown in Figure 9 ; Step ten: deposit and anneal the gate polysilicon in the source area trench, as shown in Figure 10 ; Step eleven: P-body and source ion implantation process to form the channel region of the device, as shown in Figure 11 ; Step twelve: deposit the ILD dielectric layer and define the contact source of the device by using a photo mask, as shown in Figure 12 ; Step thirteen: sputter the front metal and deposit the passivation layer to form the complete device structure, as shown in Figure 13 .

[0021] A MOSFET for reducing the dynamic parameters of the device, comprising, from bottom to top, a substrate 100, an epitaxial layer 200, an ILD dielectric layer 300, a metal layer 400, and a passivation layer 500; The epitaxial layer 200 is provided with: An active area trench 600, the active area trench 600 is provided with a gate polysilicon 610 and a first source polysilicon 620 arranged in an upper and lower spaced manner in the active area trench 600, and filled by a first dielectric layer 630; The gate polysilicon 610 of the case includes an upper gate polysilicon and a lower gate polysilicon connected in sequence, the lateral length of the upper gate polysilicon is greater than the lateral length of the lower gate polysilicon; the bottom of the lower gate polysilicon is provided with a downwardly extending boss.

[0022] The first dielectric layer 630 comprises a gate oxide layer one 631, a gate oxide layer two 632 and an insulating polysilicon oxide (IPO) 633 connected in sequence; the gate oxide layer one 631 and the gate oxide layer two 632 form a stepped structure in thickness difference, that is, the lateral width of the gate oxide layer two 632 is greater than the lateral width of the gate oxide layer one 631.

[0023] The stepped structure design improves the IPO thickness under the condition of ensuring the same gate oxide layer one 631, and the IPO thickness can be adjusted according to the product voltage, that is, the defined product voltage is 30V to 150V, the distance h1 from the silicon surface to the bottom of the trench is 1.5um~6um, the distance h2 from the bottom surface of the IPO to the silicon surface is 0.5um-1.5um, and the distance from the bottom surface of the IPO to the top surface is 0.1um-0.4um. Taking an 80V product as an example, the distance from the silicon surface to the bottom of the trench is 4.5um, and the distance from the bottom surface of the IPO to the silicon surface is 1um.

[0024] The terminal area trench 700 is provided with a second source polysilicon 710 and filled by a second dielectric layer 720; the second dielectric layer 720 extends upward to between the ILD dielectric layer 300 and the epitaxial layer 200; The first body region P-body 810 is located at the side of the active area trench 600 and extends downward from the top of the epitaxial layer 200 with a spacing from the bottom surface of the epitaxial layer 200; The first source region 900 is arranged at the top of the first body region P-body 810; The second body region P-body 820 is located between the terminal area trench 700 and the active area trench 600 and extends downward from the top of the epitaxial layer 200; The ILD dielectric layer 300 is provided with a first metal connection area A10 extending to the first body region P-body 810, a second metal connection area A20 extending to the second body region P-body 820 and a third metal connection area A30 extending to the second source polysilicon 710.

[0025] The second field dielectric layer 720 extends to the top surface of the epitaxial layer 200 and is used for separating the ILD dielectric layer 300 from the passivation layer 200, the gate polysilicon 610, the first source region 900 and the second body region P-body 820, respectively. In the case, the first metal connection area A10, the second metal connection area A20 and the third metal connection area A30 all adopt tungsten metal.

[0026] The depth range of the first source region 900 is 0.2~0.5um.

[0027] The depth range of the first body region P-body 810 and the second body region P-body 820 is 0.5~1.5um.

[0028] The present case solves the pain point of thin Inter-Poly Oxide of SGT MOSFET of one-step forming in the industry through process flow improvement, and the process is simple and low in cost; the thickness of Inter-Poly Oxide under high and low threshold voltage (VTH) can be controlled independently, and the corresponding thickness can be adjusted according to the product dynamic parameter input capacitance CISS requirement; for example Figure 14 According to the simulation of the thickness of Inter-Poly Oxide and the input capacitance ciss, as the IPO thickness increases, the input capacitance ciss decreases.

[0029] For the content disclosed in the present case, the following points need to be explained: (1) The embodiment disclosed in the present case only involves the structure involved in the disclosed embodiment, and other structures can refer to the usual design; (2) In the case of no conflict, the embodiments disclosed in the present case and the features in the embodiments can be combined to obtain new embodiments; The above is only a specific implementation of the present case, but the protection scope of the present disclosure is not limited to this. The protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for fabricating a MOSFET that reduces device dynamic parameters, characterized in that, The method comprises the following steps: Step 1: growing an epitaxial layer on a substrate, and depositing silicon dioxide on the epitaxial layer to form a hard mask; Step 2: forming a plurality of trenches by an etching process; Step 3: after growing a field dielectric layer on the trenches and the epitaxial layer, filling the trenches with source polysilicon and etching back to the surface of the trenches; Step 4: defining the area to be etched by a source polysilicon photomask and etching back the source polysilicon; After etching, the source polysilicon is re-doped using the photomask again; Step 5: using a wet process to remove 1 / 3-2 / 3 of the thickness of the field dielectric layer in the active area trench region, and etching back the source polysilicon again; Step 6: using a wet process to remove the remaining field oxide layer on the sidewall of the active area trench; Step 7: growing an oxide layer with a thickness of 500-1500A on the active area trench to form an inter-gate oxide; Step 8: depositing gate polysilicon in the active area trench and etching back to the silicon surface level; Step 9: etching back the gate polysilicon to a position below the designed channel, and using a wet process to continue etching the remaining sidewall gate oxide layer as the required gate oxide layer thickness, and forming a cell trench with different thicknesses of gate oxide layers; Step 10: depositing and annealing the gate polysilicon in the source area trench; Step 11: ion implantation process of the body region P-body and the source to form the channel region of the device; Step 12: depositing an ILD dielectric layer and defining the contact source of the device by a photomask; Step 13: sputtering of the front metal and deposition of the passivation layer.

2. The method of claim 1, wherein the MOSFET is a device with reduced dynamic parameters, characterized in that, The trenches include active area trenches and terminal area trenches.

3. The method of claim 1, wherein the step of forming the MOSFET is performed by a method comprising: In step 4, the etching depth of the source polysilicon is between 0.8-2um. ​ 4. The method of claim 1, wherein the step of forming the MOSFET device is performed by a method comprising: The heavily doped doping concentration is greater than 1e 21 in step four, and the doping ion is arsenic As. ​ 5. The method of claim 1, wherein the MOSFET is a device with reduced dynamic parameters, and wherein the step of forming the gate oxide layer is performed by a method selected from the group consisting of: a thermal oxidation method, a chemical vapor deposition method, a plasma oxidation method, and a combination thereof. In step 5, the etching depth of the source polysilicon is between 1-2um.

6. The method of claim 1, wherein the MOSFET is a device with reduced dynamic parameters, and wherein the method further comprises: In step 9, the wet process is used to continue etching the remaining sidewall gate oxide layer to a thickness of 300-1000A.

7. The method of claim 1, wherein the MOSFET is a device with reduced dynamic parameters, and wherein the method further comprises: forming a gate oxide layer on the substrate; forming a gate electrode on the gate oxide layer; forming a gate dielectric layer on the gate electrode; and forming a gate electrode on the gate dielectric layer. In step 11, the body region P-body includes a first body region P-body and a second body region P-body arranged by a trench.

8. A MOSFET with reduced dynamic parameter of a device, prepared by the preparation method of the MOSFET with reduced dynamic parameter of a device according to claim 1, characterized in that, The device comprises, from bottom to top, a substrate (100), an epitaxial layer (200), an ILD dielectric layer (300), a metal layer (400), and a passivation layer (500); The epitaxial layer (200) is provided with: An active area trench (600) in which a gate polysilicon (610) and a first source polysilicon (620) are arranged in a top-to-bottom manner and filled by a first dielectric layer (630); A terminal area trench (700) in which a second source polysilicon (710) is arranged and filled by a second dielectric layer (720), and the second dielectric layer (720) extends upward between the ILD dielectric layer (300) and the epitaxial layer (200); A first body region P-body (810) located on the side of the active area trench (600) and extending downward from the top of the epitaxial layer (200); A first source region (900) arranged on the top of the first body region P-body (810). A second body region P-body (820) is located between the terminal region trench (700) and the active region trench (600) and extends downward from the top of the epitaxial layer (200); The ILD dielectric layer (300) is provided with a first metal connection region (A10) extending to the first body region P-body (810), a second metal connection region (A20) extending to the second body region P-body (820), and a third metal connection region (A30) extending to the second source polysilicon (710).

9. The MOSFET of claim 8, wherein, The first source region (900) has a depth range of 0.2-0.5 um.

10. The MOSFET of claim 8, wherein, The first body region P-body (810) and the second body region P-body (820) each have a depth range of 0.5-1.5 um.

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