Power amplifier circuit

Abstract

The power mode is switched without providing a switch for switching the power mode. The power amplifier circuit includes: a first differential power amplifier including a first power amplifier and a second power amplifier; a first balun provided on the input side of the first differential power amplifier; a second balun provided on the output side of the first differential power amplifier; and a bias circuit that supplies a bias to the first differential power amplifier, the first balun includes a primary winding and a secondary winding that are electromagnetically coupled to each other, and a midpoint of the primary winding and the secondary winding of the first balun that is close to the secondary winding of the first differential power amplifier is connected to a reference potential. The bias circuit supplies bias to both the first power amplifier and the second power amplifier in a high-power mode, and supplies bias to one of the first power amplifier and the second power amplifier and does not supply bias to the other in a low-power mode.

Description

TECHNICAL FIELD

[0001] The present application relates to a power amplification circuit. BACKGROUND

[0002] A power amplification circuit for wireless communication and the like is known (for example, Patent Literature 1). The power amplification circuit disclosed in Patent Literature 1 has a high power mode (hereinafter referred to as HPM) and a low power mode (hereinafter referred to as LPM) as operation modes. The power amplification circuit disclosed in Patent Literature 1 has, in order to realize the two power modes, a power amplifier for LPM in addition to a differential power amplifier for HPM. Also, at the time of switching the power mode, the power amplifier is bypassed by a switch. That is, in the case of using the power amplifier for HPM, the power amplifier for LPM is bypassed by the switch. Further, in the case of using the power amplifier for LPM, the power amplifier for HPM is bypassed by the switch.

[0003] PRIOR ART LITERATURE

[0004] PATENT LITERATURE

[0005] Patent Literature 1: U.S. Patent No. 9160377 Specification SUMMARY OF THE INVENTION

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] However, in the power amplification circuit disclosed in Patent Literature 1, a switch for switching the power mode is required. Further, in addition to the power amplifier for HPM, a power amplifier for LPM needs to be provided. Therefore, for the power amplification circuit disclosed in Patent Literature 1, there is a problem that the mounting area becomes large.

[0008] The present application has been achieved in view of the above circumstances, and aims to provide a power amplification circuit capable of switching the power mode while suppressing an increase in mounting area.

[0009] TECHNICAL SOLUTION FOR SOLVING THE PROBLEM

[0010] The power amplification circuit of one aspect of the present invention includes a first differential power amplifier having a first power amplifier and a second power amplifier, a first balun provided on an input side of the first differential power amplifier, a second balun provided on an output side of the first differential power amplifier, and a bias circuit that supplies bias to the first differential power amplifier, the first balun includes a primary winding and a secondary winding electromagnetically coupled to each other, a midpoint of the secondary winding of the first balun that is closer to the first differential power amplifier is connected to a reference potential, the bias circuit supplies bias to both the first power amplifier and the second power amplifier in a high power mode, the bias circuit supplies bias to one of the first power amplifier and the second power amplifier and does not supply bias to the other in a low power mode.

[0011] The power amplification circuit of another aspect of the present invention includes a first differential power amplifier having a first power amplifier and a second power amplifier, a first balun provided on an input side of the first differential power amplifier, a second balun provided on an output side of the first differential power amplifier, a bias circuit that supplies bias to the first differential power amplifier, and a tenth capacitor, the first balun includes a primary winding and a secondary winding electromagnetically coupled to each other, a midpoint of the secondary winding of the first balun that is closer to the first differential power amplifier is connected to one end of the tenth capacitor, the other end of the tenth capacitor is connected to a reference potential, the bias circuit supplies bias to both the first power amplifier and the second power amplifier in a high power mode, the bias circuit supplies bias to one of the first power amplifier and the second power amplifier and does not supply bias to the other in a low power mode.

[0012] Effects of the Invention

[0013] The power amplification circuit according to the present invention can switch the power mode while suppressing an increase in mounting area. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 FIG. 1 is a diagram showing an example of a power amplification circuit according to a first embodiment of the present disclosure.

[0015] Figure 2 FIG. 2 is a diagram showing an example of a power amplification circuit according to a second embodiment of the present disclosure.

[0016] Figure 3 FIG. 3 is a diagram showing an example of a power amplification circuit according to a third embodiment of the present disclosure.

[0017] Figure 4 is a diagram illustrating Figure 3 the operation of the power amplification circuit of the third embodiment.

[0018] Figure 5 is a diagram showing an example of the total gain of the output signal under the HPM of the power amplification circuit.

[0019] Figure 6 is a diagram showing an example of the voltage standing wave ratio characteristic from the input terminal side under the HPM of the power amplification circuit.

[0020] Figure 7 is a diagram showing an example of the total gain of the output signal under the LPM of the power amplification circuit.

[0021] Figure 8 is a Smith chart showing the characteristics of the power amplification circuit.

[0022] Figure 9 is a diagram showing an example of the voltage standing wave ratio characteristic from the input terminal side under the LPM of the power amplification circuit.

[0023] Figure 10 is a diagram showing an example of the power amplification circuit of the fourth embodiment to which the present disclosure relates.

[0024] Figure 11 is a diagram showing an example of the power amplification circuit of the fifth embodiment to which the present disclosure relates.

[0025] Figure 12 is a diagram showing an example of the power amplification circuit of the sixth embodiment to which the present disclosure relates.

[0026] Figure 13 is a diagram showing Figure 12 the operation state under the LPM of the power amplification circuit shown in

[0027] Figure 14 is a diagram showing an example of the power amplification circuit of the seventh embodiment to which the present disclosure relates.

[0028] Figure 15 is a diagram showing an example of the power amplification circuit of the eighth embodiment to which the present disclosure relates.

[0029] Figure 16 is a diagram showing Figure 15 the operation state under the LPM of the power amplification circuit shown in

[0030] Figure 17 is a diagram showing an example of the power amplification circuit of the ninth embodiment to which the present disclosure relates.

[0031] Figure 18 is a graph showing an operation state of the power amplification circuit under LPM. Figure 17

[0032] Figure 19 is a graph showing an example of the power amplification circuit according to the 10th embodiment.

[0033] Figure 20 is a graph showing an example of the power amplification circuit according to the 11th embodiment.

[0034] Figure 21 is a graph showing an example of the power amplification circuit according to the 12th embodiment.

[0035] Figure 22 is a graph showing an example of the power amplification circuit according to the 13th embodiment.

[0036] Figure 23 is a graph showing an operation state of the power amplification circuit under LPM. Figure 22 DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present application will be explained in detail based on the accompanying drawings. In the explanation of each of the embodiments below, the same reference numerals are assigned to the same or equivalent constituent parts as those of other embodiments, and the explanation thereof is simplified or omitted. The present application is not limited by each of the embodiments. Furthermore, in the constituent elements of each of the embodiments, there are included constituent elements which can be substituted by those skilled in the art and are easily substituted, or substantially equivalent constituent elements. The structures described below can be combined as appropriate. Omission, substitution, or alteration of the structures can be made within a scope not departing from the gist of the present application. In addition, in the embodiments after the 2nd embodiment, the description about matters common to the 1st embodiment is appropriately omitted, and the differences are explained. In particular, for the same effects brought by the same structures, the same effects are not mentioned in each of the embodiments successively.

[0038] (1st Embodiment)

[0039] (Structure)

[0040] Figure 1 is a graph showing an example of the power amplification circuit according to the 1st embodiment. Figure 1 The power amplification circuit 1 shown in FIG. 1 includes an input terminal 201, a capacitor 40, a matching circuit MN1, a balun 110, a differential power amplifier 20, a balun 120, an output terminal 202, a bias circuit 21, and an inductor L1.

[0041] ​​The differential power amplifier 20 includes the first power amplifier 11 and the second power amplifier 12. The first power amplifier 11 and the second power amplifier 12 constitute a differential pair. The differential power amplifier 20 corresponds to the "first differential power amplifier" of the present disclosure.

[0042] The balun 110 performs unbalanced-to-balanced conversion. The balun 110 includes a primary winding 111 and a secondary winding 112. The balun 110 corresponds to the "first balun" of the present disclosure. The primary winding 111 and the secondary winding 112 are electromagnetically coupled to each other. By the term "electromagnetically coupled", either one of magnetic field coupling, electric field coupling, or both are meant.

[0043] One end of the primary winding 111 is connected to the matching circuit MN1. The other end of the primary winding 111 is electrically connected to the reference potential. The midpoint P21 of the secondary winding 112 is electrically connected to the reference potential. That is, the midpoint P21 of the secondary winding 112 of the balun 110, which is closer to the differential power amplifier 20 among the primary winding and the secondary winding of the balun 110, is connected to the reference potential. The midpoint P21 is an imaginary ground point for high frequency signals. The midpoint in the present disclosure does not mean a position which becomes half of an inductance value of the secondary winding of a transformer, but is defined as half of the winding within a range of manufacturing variation of the secondary winding of the transformer.

[0044] Also, the reference potential exemplifies a ground potential, but the present disclosure is not limited thereto. The same applies to the following description.

[0045] The balun 120 performs balanced-to-unbalanced conversion. The balun 120 includes a primary winding 121 and a secondary winding 122. The balun 120 corresponds to the "second balun" of the present disclosure. The primary winding 121 and the secondary winding 122 are electromagnetically coupled to each other. The midpoint P22 of the primary winding 121 is electrically connected to the power supply Vcc1 via the inductor LI. That is, the midpoint P22 of the primary winding 121 of the balun 120, which is closer to the differential power amplifier 20 among the primary winding and the secondary winding of the balun 120, is connected to the power supply Vcc1. The midpoint P22 is an imaginary ground point for high frequency signals. Also, the midpoint P22 of the primary winding 121 of the balun 120 can be connected to the reference potential instead of being connected to the power supply Vcc1. Further, in this case, for example, the power supply Vcc1 can be supplied to a node between the first power amplifier 11 and the primary winding 121 of the balun 120, and a node between the second power amplifier 12 and the primary winding 121 of the balun 120, respectively, via inductors.

[0046] The bias circuit 21 supplies bias to the differential power amplifier 20. More specifically, the bias circuit 21 supplies bias bl to the transistor in the first power amplifier 11. Further, the bias circuit 21 supplies bias b2 to the transistor in the second power amplifier 12.

[0047] The input terminal 201 inputs an input signal Pin. The capacitor 40 cuts off a direct current component of the input signal Pin. The output terminal 202 outputs an output signal Pout.

[0048] (Action)

[0049] The signal input to the input terminal 201, for example, an input signal Pin of RF (Radio Frequency), is input to the balun 110 via the capacitor 40 and the matching circuit MN1. By the balun 110, the single-ended input signal Pin is converted into a pair of differential signals. The converted differential signals are input to the first power amplifier 11 and the second power amplifier 12 that constitute the differential pair of the differential power amplifier 20. The first power amplifier 11 and the second power amplifier 12 perform power amplification by being input with bias bl, b2. More specifically, the transistors in the first power amplifier 11 and the second power amplifier 12 determine the operating point by the input bias bl, b2, and perform power amplification.

[0050] The differential signals output from the first power amplifier 11 and the second power amplifier 12 are input to the balun 120. The differential signals output from the first power amplifier 11 and the second power amplifier 12 are converted into a single-ended signal by the balun 120, and are output as the output signal Pout from the output terminal 202.

[0051] Here, in the case where the power amplification circuit 1 is HPM, power amplification is performed by both the first power amplifier 11 and the second power amplifier 12 that constitute the differential pair. In order to perform power amplification by both the first power amplifier 11 and the second power amplifier 12, both the first power amplifier 11 and the second power amplifier 12 are set to the on state. In order to set both to the on state, the bias circuit 21 supplies bias bl to the first power amplifier 11 and supplies bias b2 to the second power amplifier 12. Under HPM, both the first power amplifier 11 and the second power amplifier 12 are set to the on state. Therefore, under HPM, the power amplification circuit 1 performs power amplification with a higher gain than LPM in which only either one is set to the on state.

[0052] In the secondary winding 112 of the balun 110, the midpoint P21 is connected to a reference potential. Also, in the primary winding 121 of the balun 120, the midpoint P22 is connected to the power supply Vccl via the inductor LI. Since the connection is made to the midpoints P21, P22, the operation of the first power amplifier 11 and the second power amplifier 12 is not affected. Therefore, the output signals of the first power amplifier 11 and the second power amplifier 12, which are high-frequency signals, are not affected.

[0053] On the other hand, in the case where the power amplifying circuit 1 is LPM, power amplification is performed by only one of the first power amplifier 11 and the second power amplifier 12 constituting a differential pair. In order to perform power amplification by only one of the first power amplifier 11 and the second power amplifier 12, one of the first power amplifier 11 and the second power amplifier 12 is set to the on state, and the other is set to the off state. For example, the first power amplifier 11 is set to the on state, and the second power amplifier 12 is set to the off state. At this time, the bias circuit 21 supplies the bias bl to the first power amplifier 11, and does not output the bias b2. Since the bias b2 is not supplied, the second power amplifier 12 does not operate, and becomes in the off state. Therefore, the power amplifying circuit 1 performs power amplification with a lower gain than HPM in LPM. In addition, in LPM, the second power amplifier 12 can be set to the on state, and the first power amplifier 11 can be set to the off state. In the following description, in LPM, the first power amplifier 11 is set to the on state, and the second power amplifier 12 is set to the off state.

[0054] The midpoint P21 of the secondary winding 112 of the balun 110 is connected to a reference potential. Therefore, in LPM, the midpoint P21 functions as a reference potential, and becomes a virtual ground. At this time, the second power amplifier 12 in the off state becomes invisible from the midpoint P21, and can be regarded as a state where it is not connected to the midpoint P21. Therefore, the impedance is stabilized, and the second power amplifier 12 in the off state does not affect the amplification operation of the power amplifying circuit 1.

[0055] Also, in the midpoint P22 of the primary winding 121 of the balun 120, the power supply Vccl is connected via the inductor LI. Therefore, in LPM, the midpoint P22 functions as the power supply Vccl. The primary winding 121 functions as a DC feed inductor for supplying a direct-current voltage to the transistor of the first power amplifier 11. Thus, it is possible to prevent the output signal of the first power amplifier 11 from leaking to the power supply Vccl side.

[0056] In addition, as described above, the primary winding 121 functions as an inductor for supplying a direct-current voltage. Therefore, the inductor L1 of the first power amplifier 11 can be omitted.

[0057] (EFFECTS)

[0058] According to the power amplification circuit 1 of the first embodiment, one of the first power amplifier 11 and the second power amplifier 12 is set to the ON state and the other is set to the OFF state by the supply of the bias. Therefore, a switch for switching between the HPM and the LPM is not needed, and the circuit structure needed for switching the power mode is not increased. Therefore, the power mode can be switched while suppressing an increase in mounting area.

[0059] (SECOND EMBODIMENT)

[0060] (STRUCTURE)

[0061] Figure 2 is a view showing an example of the power amplification circuit according to the second embodiment of the present disclosure. Figure 2 The power amplification circuit 1a shown becomes a power amplification circuit in which the power amplifier 10 is added to the power amplification circuit 1 shown in Figure 1 The power amplification circuit 1a shown becomes a power amplification circuit in which the power amplifier 10 is added to the power amplification circuit 1 shown in Figure 1 The other structures of the power amplification circuit 1a are the same as those of the power amplification circuit 1 shown in

[0062] (OPERATION)

[0063] Next, the operation of the power amplification circuit 1a will be described. In the power amplification circuit 1a, the power amplifier 10 operates as a driver stage, and the differential power amplifier 20 operates as a power stage. The power amplifier 10 inputs the output signal of the matching circuit MN1. The output of the power amplifier 10 is input to the primary winding of the balun 110. The output of the power amplifier 10 is a single-ended signal, which is converted into a pair of differential signals by the balun 110. The other operation of the power amplification circuit 1a is the same as that of the power amplification circuit 1 shown in Figure 1 The other operation of the power amplification circuit 1a is the same as that of the power amplification circuit 1 shown in

[0064] (EFFECTS)

[0065] According to the power amplification circuit 1a of the second embodiment, as with the power amplification circuit 1 of the first embodiment, a switch for switching between the HPM and the LPM is not needed, and the circuit structure needed for switching the power mode is not increased. Therefore, the power mode can be switched while suppressing an increase in mounting area.

[0066] (3rd Embodiment)

[0067] (Structure)

[0068] Figure 3 is a diagram showing an example of the power amplification circuit according to the 3rd embodiment of the present disclosure. Figure 3 The power amplification circuit 1b shown includes differential power amplifiers 20 and 30 of a two-stage structure. That is, Figure 3 The power amplification circuit 1b shown includes a differential power amplifier 30, a balun 130, an output matching circuit MN2, and a bias circuit 22. In addition, the secondary winding of the balun 120 is not connected in a single-ended manner but in a differential manner. Figure 1 The power amplification circuit 1b shown includes a differential power amplifier 30, a balun 130, an output matching circuit MN2, and a bias circuit 22. In addition, the secondary winding of the balun 120 is not connected in a single-ended manner but in a differential manner.

[0069] The differential power amplifier 30 takes as input the output from the secondary winding of the balun 120. The differential power amplifier 30 includes a 1st power amplifier 11a and a 2nd power amplifier 12a. The 1st power amplifier 11a and the 2nd power amplifier 12a constitute a differential pair. The differential power amplifier 30 corresponds to the "2nd differential power amplifier" of the present disclosure.

[0070] The balun 130 is provided on the output side of the differential power amplifier 30. The balun 130 has a primary winding 131 and a secondary winding 132 electromagnetically coupled to each other. The midpoint P23 of the primary winding 131 of the balun 130 is connected to the power supply Vcc2 via the inductor L2. The balun 130 corresponds to the "3rd balun" of the present disclosure.

[0071] The bias circuit 22 supplies bias to the differential power amplifier 30. More specifically, the bias circuit 22 supplies bias b3 to the transistor within the 1st power amplifier 11a. In addition, the bias circuit 22 supplies bias b4 to the transistor within the 2nd power amplifier 12a.

[0072] The differential power amplifier 20 functions as a driver stage, and the differential power amplifier 30 functions as a power stage.

[0073] (Action)

[0074] Next, the action of the power amplification circuit 1b will be described. Under HPM, bias b1 and b2 are supplied from the bias circuit 21 to the 1st power amplifier 11 and the 2nd power amplifier 12 constituting a differential pair. That is, bias is supplied to both the 1st power amplifier 11a and the 2nd power amplifier 12a constituting a differential pair. In addition, bias b3 and b4 are supplied from the bias circuit 22 to the 1st power amplifier 11a and the 2nd power amplifier 12a constituting a differential pair.

[0075] Therefore, under HPM, the first power amplifier 11 and the second power amplifier 12 of the differential power amplifier 20 operate, and both the first power amplifier 11a and the second power amplifier 12a of the differential power amplifier 30 operate. If we are interested in the differential power amplifier 20, by operating the first power amplifier 11 and the second power amplifier 12 that constitute the differential pair, an output signal Pout with a gain higher than LPM is obtained.

[0076] Next, the operation under LPM will be explained. Under LPM, bias b1 is supplied from bias circuit 21 to the first power amplifier 11, which constitutes the differential pair (first power amplifier 11 and second power amplifier 12), while no bias is supplied to the second power amplifier 12. Therefore, the first power amplifier 11 is in the ON state, and the second power amplifier 12 is in the OFF state. If we are interested in the differential power amplifier 20, by operating only one of the first power amplifier 11 and the second power amplifier 12 constituting the differential pair, an output signal Pout with a lower gain than HPM is obtained.

[0077] here, Figure 4 This is an explanation Figure 3 A diagram showing the operation of the power amplifier circuit 1b under LPM according to the third embodiment. Figure 4 The equivalent circuit of power amplifier circuit 1b under LPM is shown. Figure 4 As shown, in the differential power amplifier 20, a bias b1 is supplied from the bias circuit 21 to the first power amplifier 11. Therefore, the first power amplifier 11 performs power amplification. Conversely, no bias is supplied to the second power amplifier 12. Therefore, the second power amplifier 12 does not perform power amplification. Figure 4 In the diagram, the second power amplifier 12, which does not perform power amplification, is shown by a dashed line.

[0078] At this time, the input side of the first power amplifier 11 is in the following state, i.e., connected... Figure 3 The secondary winding 112a is half of the secondary winding 112 shown, and its midpoint P21 is connected to the reference potential. Furthermore, on the output side of the first power amplifier 11, it is in the following state: connected... Figure 3 The primary winding 121a is shown as half of the primary winding 121, and a power supply Vcc1 is connected at the midpoint P22.

[0079] exist Figure 4In the illustrated state, in the differential power amplifier 20, the first power amplifier 11 is in operation, and the second power amplifier 12 is not in operation. By causing only one of the first power amplifier 11 and the second power amplifier 12, which constitute a differential pair, to operate, an output signal Pout having a gain lower than that of the HPM is obtained.

[0080] (Characteristics under HPM)

[0081] Here, Figure 5 is a graph showing an example of the total gain of the output signal Pout of the power amplification circuit lb under the HPM. In Figure 5 , the horizontal axis is the frequency (GHz), and the vertical axis is the gain (dB).

[0082] In Figure 5 , the characteristic gH1 shown by the broken line is a characteristic in a case where the midpoint P21 of the secondary winding 112 of the balun 110 is not connected to the reference potential. Further, the characteristic gH2 shown by the solid line is a characteristic in a case where the midpoint P21 is connected to the reference potential. The characteristics gH1 and gH2 depict substantially the same curve, and both become the maximum gain between 4.2 GHz and 4.6 GHz. Thus, it can be understood that whether or not the midpoint P21 is connected to the reference potential does not have an influence on the operation of the HPM.

[0083] Figure 6 is a graph showing an example of the voltage standing wave ratio characteristic, i.e., the VSWR (Voltage Standing Wave Ratio) characteristic, of the power amplification circuit lb under the HPM, as viewed from the input terminal 201 side. In Figure 6 , the horizontal axis is the frequency (GHz), and the vertical axis is the VSWR. The VSWR is maximized at "1.0", and the closer to "1.0", the more preferable.

[0084] In Figure 6 , the characteristic VH1 shown by the broken line is a characteristic in a case where the midpoint P21 of the secondary winding 112 of the balun 110 is not connected to the reference potential. Further, the characteristic VH2 shown by the solid line is a characteristic in a case where the midpoint P21 is connected to the reference potential. The characteristics VH1 and VH2 depict substantially the same curve, and both become "1.0" at about 4.7 GHz. Thus, it can be understood that whether or not the midpoint P21 is connected to the reference potential does not have an influence on the operation of the HPM.

[0085] (Characteristics under LPM)

[0086] Figure 7 is a graph showing an example of the total gain of the output signal Pout of the power amplification circuit lb under the LPM. In Figure 7In FIG. 8, the horizontal axis is frequency (GHz), and the vertical axis is gain (dB). Figure 7 The characteristic gL1 shown in FIG. 8 is a characteristic in a case where the midpoint P21 of the secondary winding 112 of the balun 110 is not connected to the reference potential. The characteristic gL2 is a characteristic in a case where the midpoint P21 of the secondary winding 112 of the balun 110 is connected to the reference potential.

[0087] The characteristic gL1 becomes a characteristic in which gain varies greatly and impedance is unstable. In contrast, the characteristic gL2 obtains a higher gain than the characteristic gL1 in the range of 3.4 GHz to 5.0 GHz. Further, the characteristic gL2 becomes a characteristic in which variation is less and impedance is stable compared to the characteristic gL1.

[0088] Figure 8 is a Smith chart showing a characteristic of the power amplification circuit lb. Figure 8 An example of a change in input reflection coefficient S11 with respect to a change in frequency of an input signal is shown in FIG. 9. In FIG. 9, the horizontal axis is frequency (GHz), and the vertical axis is input reflection coefficient S11 (dB). Figure 8 In FIG. 9, the characteristic S1 shown by a dashed line is a characteristic in a case where the midpoint P21 of the secondary winding 112 of the balun 110 is not connected to the reference potential. The characteristic S2 shown by a solid line is a characteristic in a case where the midpoint P21 is connected to the reference potential. In Figure 8 In FIG. 9, the characteristic S2 has less variation than the characteristic S1 that varies greatly. Thus, it can be understood that by connecting the midpoint P21 to the reference potential, a stable characteristic is obtained by matching.

[0089] Figure 9 is a graph showing an example of a VSWR characteristic observed from the input terminal 201 side of the power amplification circuit lbunder LPM. In Figure 9 In FIG. 10, the horizontal axis is frequency (GHz), and the vertical axis is VSWR. The VSWR is preferably closer to "1" as it is closer to "1" with a maximum of "1".

[0090] In Figure 9 In FIG. 11, the characteristic VL1 is a characteristic in a case where the midpoint P21 of the secondary winding 112 of the balun 110 is not connected to the reference potential. Further, the characteristic VL2 is a characteristic in a case where the midpoint P21 is connected to the reference potential. In Figure 9 In FIG. 11, it can be understood that the characteristic VL1 varies greatly and matching is not obtained. In contrast, it can be understood that the characteristic VL2 becomes a VSWR close to "1" in the range of about 4.2 GHz to 6.2 GHz, and matching is obtained.

[0091] (EFFECTS)

[0092] According to the power amplification circuit 1b of the third embodiment, one of the first power amplifier 11 and the second power amplifier 12 is set to the on state and the other is set to the off state by the supply of the bias. Therefore, a switch for switching the HPM and the LPM is not needed, and the circuit structure needed for switching the power mode is not increased. Therefore, it is possible to switch the power mode while suppressing an increase in mounting area.

[0093] (4th Embodiment)

[0094] (Configuration)

[0095] Figure 10 is a view showing an example of the power amplification circuit of the fourth embodiment to which the present disclosure relates. Figure 3 The power amplification circuit 1b of the third embodiment shown above includes two-stage differential power amplifiers 20 and 30, and with respect to this, Figure 10 The power amplification circuit 1c shown above sets the differential power amplifier to n stages (n is a natural number, the same hereinafter).

[0096] In the power amplification circuit 1c shown in Figure 10 , the power amplification circuit 1c includes differential power amplifiers 20-1, 20-2,..., 20-n, and bias circuits 21-1, 21-2,..., 21-n provided in correspondence with them. That is, the first-stage differential power amplifier 20-1 includes the first power amplifier 11-1 and the second power amplifier 12-1. The bias circuit 21-1 supplies the bias b1-1 to the first power amplifier 11-1 and the bias b2-1 to the second power amplifier 12-1, respectively. The second-stage differential power amplifier 20-2 includes the first power amplifier 11-2 and the second power amplifier 12-2. The bias circuit 21-2 supplies the bias b1-2 to the first power amplifier 11-2 and the bias b2-2 to the second power amplifier 12-2, respectively. Hereinafter, in the same manner, the first power amplifier and the second power amplifier of each differential power amplifier are supplied with the bias from the corresponding bias circuit. The n-stage differential power amplifier 20-n includes the first power amplifier 11-n and the second power amplifier 12-n. The bias circuit 21-n supplies the bias b1-n to the first power amplifier 11-n and the bias b2-n to the second power amplifier 12-n, respectively.

[0097] The midpoint P21-1 of the secondary winding 112 of the balun 110 on the input side of the 1st stage is connected to a reference potential. The midpoint P22-1 of the primary winding 121-1 of the balun 120-1 of the 2nd stage is connected to the power supply Vcc1 via the inductor LI. The midpoint P21-2 of the secondary winding 122-1 of the balun 120-1 of the 2nd stage is connected to a reference potential. Further, the midpoint P22-2 of the primary winding 121-2 of the balun of the next stage is connected to the power supply Vcc2 via the inductor L2. The midpoint Pn of the primary winding 121-n of the balun 120-n of the n-th stage is connected to the power supply Vccn via the inductor Ln. One end of the secondary winding 122-n of the balun 120-n of the n-th stage is connected to a reference potential. The other end of the secondary winding 122-n is connected to the output matching circuit MN2.

[0098] Here, regarding the differential power amplifier 20-1 of the 1st stage, under the HPM, the 1st power amplifier 11-1 and the 2nd power amplifier 12-1 are set to the ON state. On the other hand, under the LPM, the 1st power amplifier 11-1 is set to the ON state, and the 2nd power amplifier 12-1 is set to the OFF state. At this time, the midpoint P21-1 of the secondary winding 112 of the balun 110 immediately before the 2nd power amplifier 12-1 to be set to the OFF state under the LPM is connected to a reference potential. That is, the midpoint P21-1 of the secondary winding 112 close to the differential power amplifier 20-1 is connected to a reference potential.

[0099] Further, regarding the differential power amplifier 20-2 of the 2nd stage, under the HPM, the 1st power amplifier 11-2 and the 2nd power amplifier 12-2 are set to the ON state. On the other hand, under the LPM, the 1st power amplifier 11-2 is set to the ON state, and the 2nd power amplifier 12-2 is set to the OFF state. At this time, the midpoint P21-2 of the secondary winding 122-1 of the balun 120-1 immediately before the 2nd power amplifier 12-2 to be set to the OFF state under the LPM is connected to a reference potential. That is, the midpoint P21-2 of the secondary winding 112 close to the differential power amplifier 20-2 is connected to a reference potential.

[0100] On the other hand, regarding the differential power amplifier 20-n of the n-th stage, the 1st power amplifier 11-n and the 2nd power amplifier 12-n are set to the ON state under the HPM and the LPM. Therefore, the secondary winding of the balun immediately before the differential power amplifier 20-n is not connected to a reference potential. As described above, in the power amplifying circuit 1c, the midpoint of the secondary winding of the balun immediately before the power amplifier to be set to the OFF state under the LPM is connected to a reference potential.

[0101] (Action)

[0102] The power amplification circuit 1c supplies each bias b1-1, b2-1, b1-2, b2-2,..., b1-n, b2-n from the bias circuit 21-1, 21-2,..., 21-n under the HPM. Thereby, the first power amplifier and the second power amplifier of all the differential power amplifiers 20-1, 20-2,..., 20-n are set to the on state. Therefore, it is possible to realize the amplification operation based on the high gain.

[0103] Further, under the LPM, regarding the differential power amplifier 20-1, the first power amplifier 11-1 is set to the on state and the second power amplifier 12-1 is set to the off state. Further, regarding the differential power amplifier 20-2, the first power amplifier 11-2 is set to the on state and the second power amplifier 12-2 is set to the off state. Thereby, it is possible to realize the amplification operation based on the gain lower than the HPM.

[0104] (Effects)

[0105] According to the power amplification circuit 1c of the fourth embodiment, even in a case where the differential power amplifier is set to n stages, one of the first power amplifier and the second power amplifier is set to the on state and the other is set to the off state by the supply of the bias or not. Therefore, it is not necessary to provide a switch for switching the HPM and the LPM, and the circuit structure necessary for switching the power mode is not increased. Therefore, it is possible to switch the power mode while suppressing the increase of the mounting area.

[0106] (Fifth Embodiment)

[0107] (Configuration)

[0108] Figure 11 is a view illustrating an example of the power amplification circuit according to the fifth embodiment of the present disclosure. Figure 11 The power amplification circuit 1d illustrated in the drawing becomes a structure in which the matching element for the matching adjustment is added to the power amplification circuit 1b of the third embodiment. Specifically, the power amplification circuit 1d becomes a structure in which the capacitor 41 and the switch SW1 are added to the power amplification circuit 1b of the third embodiment.

[0109] The capacitor 41 is a matching element for matching adjustment. By turning on the switch SW1, the capacitor 41 is electrically connected between the capacitor 40 and the primary winding 111. By turning off the switch SW1, the capacitor 41 is not connected. In a case where input matching cannot be achieved at the time of switching between the HPM and the LPM, by turning on or off the switch SW1, matching can be achieved. The switch SW1 can be implemented by a transistor that is turned on or off at the time of switching the power mode, for example. That is, the power amplification circuit Id further includes a matching element for matching adjustment, and a switch that electrically connects the matching element at the time of the high power mode or the low power mode.

[0110] In a case where input matching needs to be adjusted, the capacitor 41 is connected between the capacitor 40 and the primary winding 111, but they can be disposed at other positions. That is, a matching element for matching adjustment and a switch can be disposed in advance at a position where matching needs to be adjusted, and the switch is turned on or off at the time of switching the power mode.

[0111] In addition, an inductor can be disposed instead of the capacitor 41 as a matching element for matching adjustment. Further, an inductor can be disposed together with the capacitor 41 as a matching element for matching adjustment.

[0112] (Action)

[0113] At the time of switching the HPM and the LPM, the switch SW1 is turned on or off. Thereby, impedance can be appropriately set.

[0114] (Effect)

[0115] According to the power amplification circuit Id of the 5th embodiment, by the presence or absence of supply of bias, one of the 1st power amplifier 11 and the 2nd power amplifier 12 is set to an on state, and the other is set to an off state. Therefore, a switch for switching the HPM and the LPM is not needed, and the circuit structure needed for switching the power mode is not increased. Therefore, the power mode can be switched while suppressing an increase in mounting area.

[0116] (6th Embodiment)

[0117] (Configuration)

[0118] Figure 12 is a diagram showing an example of the power amplification circuit of the 6th embodiment to which the present disclosure relates. Figure 12 The power amplification circuit 1e shown is a structure in which capacitors 42a and 42b and an inductor LL are added to the power amplification circuit 1b of the 3rd embodiment.

[0119] One end of the capacitor 42a is connected to the output end of the first power amplifier 11. One end of the capacitor 42b is connected to the output end of the second power amplifier 12. The other end of the capacitor 42a and the other end of the capacitor 42b are connected. One end of the inductor LL is connected to the connection point of the other end of the capacitor 42a and the other end of the capacitor 42b. The other end of the inductor LL is connected to the reference potential via the inductor LI and to the midpoint P22 of the primary winding 121 of the balun 120. The capacitor 42a corresponds to the first capacitor of the present disclosure. The capacitor 42b corresponds to the second capacitor of the present disclosure. The inductor LL corresponds to the first inductor of the present disclosure.

[0120] If viewed from the output end of the first power amplifier 11, the capacitor 42a, the inductor LL, and the inductor LI are connected between the output end and the reference potential. If viewed from the output end of the second power amplifier 12, the capacitor 42b, the inductor LL, and the inductor LI are connected between the output end and the reference potential.

[0121] (Action)

[0122] The operation of the power amplification circuit le in the HPM is described. In the HPM, the bias circuit 21 supplies the bias bl to the transistor in the first power amplifier 11. In addition, the bias circuit 21 supplies the bias b2 to the transistor in the second power amplifier 12.

[0123] Here, the capacitance values of the capacitors 42a and 42b and the inductance values of the inductors LL and LI are appropriately selected in advance. Thus, by series resonance based on these capacitors and inductors, it is possible to attenuate harmonics contained in the outputs of the first power amplifier 11 and the second power amplifier 12.

[0124] Next, the operation of the power amplification circuit le in the LPM is described. Figure 13 is a view showing Figure 12 the operation state of the power amplification circuit le in the LPM. In the LPM, the bias circuit 21 supplies the bias bl to the transistor in the first power amplifier 11, but does not supply the bias to the transistor in the second power amplifier 12. Thus, as shown by the broken line in Figure 13 the second power amplifier 12 becomes a state of being turned off. At this time, at the output end of the first power amplifier 11, the capacitor 42a is connected to the reference potential via the inductors LL and LI. By appropriately selecting the capacitance value of the capacitor 42a in advance, it is possible to set the capacitor 42a as a matching element for matching adjustment.

[0125] Further, the above describes a case where, in the LPM, the bias is supplied from the bias circuit 21 to the transistor in the first power amplifier 11, and the bias bl is not supplied to the transistor in the second power amplifier 12. Not limited to this case, in the LPM, the bias bl can be supplied from the bias circuit 21 to the transistor in the second power amplifier 12, and the bias can not be supplied to the transistor in the first power amplifier 11. That is, in the LPM, by the presence or absence of the supply of the bias, one of the first power amplifier 11 and the second power amplifier 12 is set to the on state, and the other is set to the off state.

[0126] (EFFECTS)

[0127] The power amplification circuit le according to the sixth embodiment, by the presence or absence of the supply of the bias, one of the first power amplifier 11 and the second power amplifier 12 is set to the on state, and the other is set to the off state. Therefore, a switch for switching the HPM and the LPM is not needed, and the circuit structure needed for switching the power mode is not increased. Therefore, it is possible to switch the power mode while suppressing an increase in mounting area.

[0128] Further, in the HPM (corresponding to Figure 12 ), by the series resonance based on the added capacitors 42a and 42b and the inductor LL, it is possible to attenuate harmonics contained in the outputs of the first power amplifier 11 and the second power amplifier 12. Further, in the LPM (corresponding to Figure 13 ), by the capacitor 42a (or the capacitor 42b), it is possible to achieve matching.

[0129] (SEVENTH EMBODIMENT)

[0130] (STRUCTURE)

[0131] Figure 14 is a view showing an example of the power amplification circuit according to the seventh embodiment of the present disclosure. Figure 14 The power amplification circuit lf shown becomes a structure in which the capacitors 43a and 43b are added to the power amplification circuit lb of the third embodiment.

[0132] As described above, the first power amplifier 11 and the second power amplifier 12 constitute a differential pair. One end of the capacitor 43a is connected to the output terminal of the second power amplifier 12. The other end of the capacitor 43a is connected to the input terminal of the first power amplifier 11. One end of the capacitor 43b is connected to the output terminal of the first power amplifier 11. The other end of the capacitor 43b is connected to the input terminal of the second power amplifier 12. That is, it becomes a structure of a cross-coupling capacitor that feeds back from the output of the differential pair to the input of the opposite polarity to each other. The capacitor 43a corresponds to the third capacitor of the present disclosure. The capacitor 43b corresponds to the fourth capacitor of the present disclosure.

[0133] (Action)

[0134] According to the power amplification circuit 1f, feedback is performed from the output of the differential pair to the input of the opposite polarity to each other via the capacitors 43a, 43b. Thereby, the capacitance generated from the input to the output of each transistor of the 1st power amplifier 11 and the 2nd power amplifier 12 can be eliminated.

[0135] (Effect)

[0136] According to the power amplification circuit 1f of the 7th embodiment, by the presence or absence of the supply of the bias, one of the 1st power amplifier 11 and the 2nd power amplifier 12 is set to the ON state, and the other is set to the OFF state. Therefore, a switch for switching the HPM and the LPM is not needed, and the circuit structure needed for switching the power mode is not increased. Therefore, it is possible to switch the power mode while suppressing the increase in mounting area. Moreover, by performing feedback from the output of the differential pair to the input of the opposite polarity to each other, it is possible to obtain the gain based on the 1st power amplifier 11 and the 2nd power amplifier 12.

[0137] (8th Embodiment)

[0138] (Configuration)

[0139] Figure 15 is a view illustrating an example of the power amplification circuit of the 8th embodiment to which the present disclosure relates. Figure 15 The power amplification circuit 1g illustrated is a structure in which the capacitor 44 is added to the power amplification circuit 1b of the 3rd embodiment. One end of the capacitor 44 is connected to the midpoint P24 of the secondary winding 122 of the balun 120. The other end of the capacitor 44 is connected to the reference potential. The capacitor 44 corresponds to the 5th capacitor of the present disclosure.

[0140] (Action)

[0141] The operation under the HPM of the power amplification circuit 1g will be described. Under the HPM, the bias circuit 21 supplies the bias b1 to the transistor within the 1st power amplifier 11. In addition, the bias circuit 21 supplies the bias b2 to the transistor within the 2nd power amplifier 12.

[0142] Under the HPM of the power amplification circuit 1g, for the even-order harmonics of the fundamental frequency, the midpoint P24 of the balun 120 does not become the virtual ground, but the capacitance of the capacitor 44 can be seen. Therefore, it is possible to attenuate the even-order harmonics.

[0143] Next, the operation under the LPM of the power amplification circuit 1g will be described. Figure 16 is a view illustrating an example of the power amplification circuit of the 8th embodiment to which the present disclosure relates. Figure 15The diagram shows the operating state of the power amplifier circuit 1g under LPM (Limited Power Mode). Under LPM, the bias circuit 21 supplies bias b1 to the transistors in the first power amplifier 11, but does not supply bias to the transistors in the second power amplifier 12. Therefore, as... Figure 16 As shown by the dashed line, the second power amplifier 12 is in the off state. At this time, the output terminal of the first power amplifier 11 is electrically connected to the power supply Vcc1 via half of the primary winding 121 of the balancing converter 120 and the inductor L1. Furthermore, the midpoint P24 of the secondary winding 122 of the balancing converter 120, which constitutes the input side of the first power amplifier 11a and the second power amplifier 12a of the differential power amplifier 30, is connected to the reference potential via the capacitor 44.

[0144] (Effect)

[0145] In the LPM of the power amplifier circuit 1g in the eighth embodiment, the midpoint P24 of the balun 120 is not considered as grounded for even harmonics of the fundamental frequency, and the capacitance of capacitor 44 can be seen. Therefore, even harmonics can be attenuated.

[0146] (9th implementation)

[0147] (structure)

[0148] Figure 17 This is a diagram illustrating an example of a power amplifier circuit according to the ninth embodiment of this disclosure. Figure 17 The power amplifier circuit 1h shown is a structure in which a capacitor 45 is added to the power amplifier circuit 1b of the third embodiment. One end of the capacitor 45 is connected to the midpoint P21 of the secondary winding 112 of the balun 110. The other end of the capacitor 45 is connected to a reference potential. Figure 17 In the power amplifier circuit shown in step 1h, it becomes the replacement Figure 15 The power amplifier circuit 1g shown uses capacitor 45 instead of capacitor 44. Capacitor 45 is equivalent to the 10th capacitor of this disclosure.

[0149] (action)

[0150] The operation of the power amplifier circuit 1h under HPM (High-Performance Mode) will be explained. Under HPM, the bias circuit 21 supplies bias b1 to the transistors in the first power amplifier 11. In addition, the bias circuit 21 supplies bias b2 to the transistors in the second power amplifier 12.

[0151] Under HPM conditions of power amplifier circuit 1h, for even harmonics of the fundamental frequency, the midpoint P21 of the secondary winding 112 of the balun 110 is not considered grounded, and the capacitance of capacitor 45 can be observed. Therefore, even harmonics can be attenuated.

[0152] Next, the operation in the LPM of the power amplification circuit 1h will be described. Figure 18 is a view showing Figure 17 the operation state of the power amplification circuit 1h in the LPM. In the LPM, the bias circuit 21 supplies the bias b1 to the transistor in the 1st power amplifier 11, but does not supply the bias to the transistor in the 2nd power amplifier 12. Therefore, as shown by a broken line in Figure 18 the 2nd power amplifier 12 becomes the off state. At this time, the output terminal of the 1st power amplifier 11 is electrically connected to the power supply Vcc1 via one half of the primary winding 121 of the balun 120 and the inductor L1. Further, the midpoint P21 of the secondary winding 112 of the balun 110 on the input side of the 1st power amplifier 11 is connected to the reference potential via the capacitor 45.

[0153] (EFFECTS)

[0154] In the LPM of the power amplification circuit 1h of the 9th embodiment, the capacitor 45 can be utilized as a matching element. Further, a switch for switching the HPM and the LPM is not required, and the circuit structure required for switching the power mode is not increased. Therefore, it is possible to switch the power mode while suppressing an increase in mounting area.

[0155] (10th Embodiment)

[0156] (Structure)

[0157] Figure 19 is a view showing an example of the power amplification circuit according to the 10th embodiment of the present disclosure. In Figure 19 , the structure of the power amplification circuit 1i is the same as that of the power amplification circuit 1g described with reference to Figure 15 . That is, Figure 19 the power amplification circuit 1i shown in

[0158] (Operation)

[0159] the operation in the HPM of the power amplification circuit 1i is the same as that of the power amplification circuit 1g described with reference to Figure 15 . Figure 19 is a view showing the operation state of the power amplification circuit 1i in the LPM. The operation of the power amplification circuit 1i in the LPM is different from that of the power amplification circuit 1g described with reference to Figure 15 . Specifically, the operation of the bias circuit 22 is different from that of the power amplification circuit 1g.

[0160] That is, under the LPM of the power amplification circuit 1i, the bias circuit 22 supplies the bias b3 to the transistor in the 1st power amplifier 11a, but does not supply the bias to the transistor in the 2nd power amplifier 12a. Therefore, as shown by a solid line in FIG. 6, the 2nd power amplifier 12a becomes the off state. Figure 19

[0161] By the 2nd power amplifier 12a becoming the off state, the midpoint P24 of the secondary winding 122 of the balun 120 on the input side of the 1st power amplifier 11a is connected to the reference potential via the capacitor 44. That is, the input side of the 1st power amplifier 11a is connected to the reference potential via one half of the secondary winding 122 and the capacitor 44.

[0162] In addition, the midpoint P23 of the primary winding 131 of the balun 130 on the output side of the 1st power amplifier 11a is connected to the reference potential via the inductor L2. That is, the output side of the 1st power amplifier 11a is connected to the reference potential via one half of the primary winding 131 and the inductor L2.

[0163] (EFFECTS)

[0164] As described above, the input side of the 1st power amplifier 11a of the 10th embodiment is connected to the reference potential via one half of the secondary winding 122 and the capacitor 44. Thereby, the capacitor 44 can be used as a matching element for matching adjustment. Further, a switch for switching the HPM and the LPM is not needed, and the circuit structure needed for switching the power mode is not increased. Therefore, it is possible to switch the power mode while suppressing an increase in mounting area.

[0165] (11th Embodiment)

[0166] (STRUCTURE)

[0167] Figure 20 is a view showing an example of the power amplification circuit according to the 11th embodiment of the present disclosure. Figure 20 The power amplification circuit 1j shown in the drawing is a structure in which the capacitors 46a and 46b are added to the power amplification circuit 1b of the 3rd embodiment.

[0168] ​One end of the capacitor 46a is connected to the input of the first power amplifier 11. The other end of the capacitor 46a is connected to the output of the bias b1 of the bias circuit 21. That is, the input path of the RF signal to the first power amplifier 11 and the output of the bias circuit 21 are connected via the capacitor 46a. One end of the capacitor 46b is connected to the input of the second power amplifier 12. The other end of the capacitor 46b is connected to the output of the bias b2 of the bias circuit 21. That is, the input path of the RF signal to the second power amplifier 12 and the output of the bias circuit 21 are connected via the capacitor 46b. The capacitor 46a corresponds to the sixth capacitor of the present disclosure. The capacitor 46b corresponds to the seventh capacitor of the present disclosure.

[0169] (Action)

[0170] In the power amplification circuit 1j of the present embodiment, a part of the RF signal input to the first power amplifier 11 is supplied to the bias circuit 21 via the capacitor 46a. Further, a part of the RF signal input to the second power amplifier 12 is supplied to the bias circuit 21 via the capacitor 46b.

[0171] (Effect)

[0172] In the power amplification circuit 1j of the eleventh embodiment, by adding the capacitors 46a and 46b, it is possible to suppress the voltage drop of the bias circuit and suppress the gain compression of the RF output signal. Further, a switch for switching the HPM and the LPM is not needed, and the circuit structure needed for switching the power mode is not increased. Therefore, it is possible to switch the power mode while suppressing the increase of the mounting area.

[0173] (Twelfth Embodiment)

[0174] (Structure)

[0175] Figure 21 is a view showing an example of the power amplification circuit of the twelfth embodiment to which the present disclosure relates. Figure 21 The power amplification circuit 1k shown becomes a structure in which the capacitors 47 and 48 are added to the power amplification circuit 1b of the third embodiment.

[0176] The capacitor 47 is connected between the primary winding 111 of the balun 110 and the reference potential. The balun 110 is a balun that converts a balanced signal into a differential signal. The capacitor 47 is inserted between the winding (i.e., the primary winding 111) on the balanced signal side of the balun 110 and the reference potential. The capacitor 47 corresponds to the eighth capacitor of the present disclosure.

[0177] The capacitor 48 is connected between the secondary winding 132 of the balun 130 and the reference potential. The balun 130 is a balun that converts a differential signal into a single-ended signal. The capacitor 48 is inserted between the winding (i.e., the secondary winding 132) on the single-ended signal side of the balun 130 and the reference potential. The capacitor 48 corresponds to the 9th capacitor of the present disclosure.

[0178] (Action)

[0179] There is a case in which the balun 110 generates a parasitic capacitance, and the phase inversion of the differential does not become 180 degrees, but slightly deviates from 180 degrees. Even in such a case, by providing the capacitor 47, it is possible to eliminate the imbalance of the differential caused by the parasitic capacitance, and perform impedance matching.

[0180] Further, there is a case in which the balun 130 generates a parasitic capacitance, and the phase inversion of the differential does not become 180 degrees, but slightly deviates from 180 degrees. Even in such a case, by providing the capacitor 48, it is possible to eliminate the imbalance of the differential caused by the parasitic capacitance, and perform impedance matching.

[0181] In Figure 21 In the power amplification circuit 1k shown in FIG. 12, both the capacitor 47 and the capacitor 48 are provided. For the capacitor 47 and the capacitor 48, it is also possible that not both of them are provided, but only either one is provided. That is, by providing the capacitor 47, it is possible to eliminate the imbalance of the differential caused by the parasitic capacitance of the balun 110. Further, by providing the capacitor 48, it is possible to eliminate the imbalance of the differential caused by the parasitic capacitance of the balun 130.

[0182] (Effects)

[0183] In the power amplification circuit 1k of the 12th embodiment, a switch for switching the HPM and the LPM is not required, and the circuit structure required for switching the power mode is not increased. Therefore, it is possible to switch the power mode while suppressing an increase in mounting area.

[0184] (13th Embodiment)

[0185] (Configuration)

[0186] Figure 22 is a diagram showing an example of the power amplification circuit of the 13th embodiment to which the present disclosure relates. Figure 22The power amplifier circuit 1m shown is configured in the power amplifier circuit 1b of the third embodiment to connect the midpoint P24 of the secondary winding 122 of the balancing converter 120 to a reference potential. In the power amplifier circuit 1b of the third embodiment described above, while connecting the midpoint P21 of the secondary winding 112 of the balancing converter 110 to a reference potential, the midpoint P24 of the secondary winding 122 of the balancing converter 120 is further connected to a reference potential.

[0187] (action)

[0188] The operation of the power amplifier circuit 1m under HPM (High-Performance Mode) will be explained. Under HPM, bias circuit 21 supplies bias b1 to the transistors in the first power amplifier 11. Furthermore, bias circuit 21 supplies bias b2 to the transistors in the second power amplifier 12. Bias circuit 22 supplies bias b3 to the transistors in the first power amplifier 11a. Furthermore, bias circuit 21 supplies bias b4 to the transistors in the second power amplifier 12a.

[0189] Under HPM conditions of 1m in the power amplifier circuit, the midpoint P21 of the secondary winding 112 of the balun 110 operates as a hypothetical ground. Therefore, compared to the case where the midpoint P21 is not connected to the reference potential, it does not affect the differential power amplifier 20, and the amplification characteristics of the differential power amplifier 20 remain unchanged.

[0190] Furthermore, under HPM conditions of 1m in the power amplifier circuit, the midpoint P24 of the secondary winding 122 of the balun 120 operates as a hypothetical ground. Therefore, compared to the case where the midpoint P24 is not connected to the reference potential, it does not affect the differential power amplifier 30, and the amplification characteristics of the differential power amplifier 30 remain unchanged.

[0191] Next, the operation of the power amplifier circuit at 1m LPM will be explained. Figure 23 It is shown Figure 22 The diagram shows the operating state of the power amplifier circuit 1m under LPM. Under LPM, the bias circuit 21 supplies bias b1 to the transistors in the first power amplifier 11, but does not supply bias to the transistors in the second power amplifier 12. Therefore, as... Figure 23 As shown by the dashed line, the second power amplifier 12 is in the off state. At this time, the output terminal of the first power amplifier 11 is electrically connected to the power supply Vcc1 via half of the primary winding 121 of the balun 120 and the inductor L1. The input terminal of the first power amplifier 11 is connected to the reference potential via half of the secondary winding 112 of the balun 110.

[0192] Further, in the LPM, the bias circuit 22 supplies a bias b3 to the transistor in the first power amplifier 11a, but does not supply a bias to the transistor in the second power amplifier 12a. Therefore, as shown by a broken line in FIG. 6, the second power amplifier 12a becomes in the off state. At this time, the output terminal of the first power amplifier 11a is electrically connected to the power supply Vcc2 via one half of the primary winding 131 of the balun 130 and the inductor L2. The input terminal of the first power amplifier 11a is connected to the reference potential via one half of the secondary winding 122 of the balun 120. Figure 23

[0193] (EFFECTS)

[0194] In the power amplification circuit lm of the 13th embodiment, not only the midpoint of the balun on the input side is connected to the reference potential for the differential power amplifier 20 of the first stage, but also the midpoint of the balun on the input side is connected to the reference potential for the differential power amplifier 30 of the second stage. Further, in the LPM, the single-sided power amplifier of the first stage and the second stage is set to be off. Therefore, compared with the case where the single-sided power amplifier of the first stage is set to be off, the gain can be further reduced.

[0195] In the power amplification circuit lm of the present embodiment, too, a switch for switching between the HPM and the LPM is not needed, and the circuit structure needed for switching the power mode is not increased. Therefore, the power mode can be switched while the increase in the mounting area is suppressed.

[0196] As to the recitation of the claims, the present disclosure can take the following modes. (1)

[0198] A power amplification circuit comprising:

[0199] a first differential power amplifier having a first power amplifier and a second power amplifier;

[0200] a first balun provided on the input side of the first differential power amplifier;

[0201] a second balun provided on the output side of the first differential power amplifier; and

[0202] a bias circuit that supplies a bias to the first differential power amplifier,

[0203] the first balun includes a primary winding and a secondary winding electromagnetically coupled to each other,

[0204] the midpoint of the secondary winding of the first balun is connected to a reference potential,​

[0205] the bias circuit supplies bias to both the first power amplifier and the second power amplifier in a high power mode,

[0206] the bias circuit supplies bias to one of the first power amplifier and the second power amplifier in a low power mode, and does not supply bias to the other. (2)

[0208] In the power amplification circuit described in (1),

[0209] the second balun includes a primary winding and a secondary winding electromagnetically coupled to each other,

[0210] the midpoint of the primary winding of the second balun, which is closer to the first differential power amplifier, is connected to a reference potential or a power supply. (3)

[0212] In the power amplification circuit described in (1) or (2),

[0213] the power amplification circuit further includes another power amplifier provided on the primary winding side of the first balun,

[0214] the output of the other power amplifier is input to the primary winding of the first balun. (4)

[0216] In the power amplification circuit described in (1) or (2),

[0217] the power amplification circuit further includes a second differential power amplifier that inputs the output from the secondary winding of the second balun, and a third balun provided on the output side of the second differential power amplifier and having a primary winding and a secondary winding electromagnetically coupled to each other,

[0218] the midpoint of the primary winding of the third balun is connected to a power supply. (5)

[0220] In the power amplification circuit described in any one of (1) to (4),

[0221] the power amplification circuit further includes a matching element for matching adjustment, and a switch that electrically connects the matching element in a high power mode or a low power mode. (6)

[0223] In the power amplification circuit described in (2),

[0224] The power amplification circuit further includes a first capacitor, a second capacitor, and a first inductor,

[0225] One end of the first capacitor is connected to an output terminal of the first power amplifier,

[0226] One end of the second capacitor is connected to an output terminal of the second power amplifier,

[0227] The other end of the first capacitor and the other end of the second capacitor are connected,

[0228] One end of the first inductor is connected to a connection point of the other end of the first capacitor and the other end of the second capacitor, and the other end of the first inductor is connected to a midpoint of the primary winding of the second balun,

[0229] The midpoint of the primary winding of the second balun is connected to a power supply. (7)

[0231] In the power amplification circuit described in (2),

[0232] The power amplification circuit further includes a third capacitor and a fourth capacitor,

[0233] One end of the third capacitor is connected to an output terminal of the first power amplifier,

[0234] The other end of the third capacitor is connected to an input terminal of the first power amplifier,

[0235] One end of the fourth capacitor is connected to an output terminal of the second power amplifier,

[0236] The other end of the fourth capacitor is connected to an input terminal of the second power amplifier. (8)

[0238] In the power amplification circuit described in (2),

[0239] The power amplification circuit further includes a fifth capacitor,

[0240] One end of the fifth capacitor is connected to a midpoint of the secondary winding of the second balun,

[0241] The other end of the fifth capacitor is connected to a reference potential. (9)

[0243] In the power amplification circuit described in (2),

[0244] The power amplification circuit further includes a sixth capacitor and a seventh capacitor,

[0245] one end of the sixth capacitor is connected to an input terminal of the first power amplifier,

[0246] the other end of the sixth capacitor is connected to an output terminal of biasing from the bias circuit to the first power amplifier,

[0247] one end of the seventh capacitor is connected to an input terminal of the second power amplifier,

[0248] the other end of the seventh capacitor is connected to an output terminal of biasing from the bias circuit to the second power amplifier. (10)

[0250] In the power amplifier circuit described in (4),

[0251] the power amplifier circuit further includes at least one of an eighth capacitor and a ninth capacitor,

[0252] one end of the eighth capacitor is connected to the primary winding of the first balun,

[0253] the other end of the eighth capacitor is connected to a reference potential,

[0254] one end of the ninth capacitor is connected to the secondary winding of the third balun,

[0255] the other end of the ninth capacitor is connected to a reference potential. (11)

[0257] In the power amplifier circuit described in (2) or (4),

[0258] a midpoint of the secondary winding of the second balun is connected to a reference potential. (12)

[0260] A power amplifier circuit includes:

[0261] a first differential power amplifier having a first power amplifier and a second power amplifier;

[0262] a first balun provided on an input side of the first differential power amplifier;

[0263] a second balun provided on an output side of the first differential power amplifier;

[0264] a bias circuit that supplies bias to the first differential power amplifier; and

[0265] a tenth capacitor,

[0266] The first balun includes a primary winding and a secondary winding electromagnetically coupled to each other,

[0267] The midpoint of the secondary winding of the primary winding and the secondary winding of the first differential power amplifier is connected to one end of the tenth capacitor,

[0268] The other end of the tenth capacitor is connected to a reference potential,

[0269] The bias circuit supplies bias to both the first power amplifier and the second power amplifier in a high power mode,

[0270] The bias circuit supplies bias to one of the first power amplifier and the second power amplifier in a low power mode, and does not supply bias to the other.

[0271] Reference numeral explanation

[0272] 1, 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i, 1j, 1k, 1m: power amplification circuit

[0273] 10: power amplifier

[0274] 11, 11a, 11-1, 11-2, 11-n: first power amplifier

[0275] 12, 12a, 12-1, 12-2, 12-n: second power amplifier

[0276] 20, 20-1, 20-2, 20-n, 30: differential power amplifier

[0277] 21, 21-1, 21-2, 21-n, 22: bias circuit

[0278] 40, 41, 42a, 42b, 43a, 43b, 44, 45, 46a, 46b, 47, 48: capacitor

[0279] 110, 120, 130: balun

[0280] 111, 121, 121-1, 121-2, 121-n, 131: primary winding

[0281] 112, 122, 122-1, 122-n, 132: secondary winding

[0282] 201: input terminal

[0283] 202: output terminal

[0284] L1, L2, Ln, LL: inductors;

[0285] MN1: matching circuit;

[0286] MN2: output matching circuit;

[0287] P21, P21-1, P21-2, P22, P22-1, P22-2, P23, P24, Pn: mid-point.

Claims

1. A power amplification circuit comprising: a first differential power amplifier having a first power amplifier and a second power amplifier; a first balun provided on an input side of the first differential power amplifier; a second balun provided on an output side of the first differential power amplifier; and a bias circuit that supplies bias to the first differential power amplifier, wherein the first balun includes a primary winding and a secondary winding that are electromagnetically coupled to each other, wherein the secondary winding of the first balun is connected to a reference potential at a midpoint thereof that is close to the first differential power amplifier, wherein the bias circuit supplies bias to both the first power amplifier and the second power amplifier in a high power mode, and wherein the bias circuit supplies bias to one of the first power amplifier and the second power amplifier and does not supply bias to the other in a low power mode.

2. The power amplification circuit according to claim 1, wherein the second balun includes a primary winding and a secondary winding that are electromagnetically coupled to each other, and wherein the midpoint of the primary winding of the second balun is connected to a reference potential or a power supply at a midpoint thereof that is close to the first differential power amplifier.

3. The power amplification circuit according to claim 1 or 2, further comprising a further power amplifier provided on a primary winding side of the first balun, wherein an output of the further power amplifier is input to the primary winding of the first balun.

4. The power amplification circuit according to claim 1 or 2, further comprising a second differential power amplifier that takes as input an output from a secondary winding of the second balun, and a third balun provided on an output side of the second differential power amplifier and having a primary winding and a secondary winding that are electromagnetically coupled to each other, wherein the midpoint of the primary winding of the third balun is connected to a power supply.

5. The power amplification circuit according to any one of claims 1 to 4, further comprising a matching element for matching adjustment, and a switch that electrically connects the matching element in a high power mode or a low power mode.

6. The power amplification circuit according to claim 2, further comprising a first capacitor, a second capacitor, and a first inductor, wherein one end of the first capacitor is connected to an output terminal of the first power amplifier, wherein one end of the second capacitor is connected to an output terminal of the second power amplifier, wherein the other end of the first capacitor and the other end of the second capacitor are connected, wherein one end of the first inductor is connected to the connection point of the other end of the first capacitor and the other end of the second capacitor, and the other end of the first inductor is connected to the midpoint of the primary winding of the second balun, and wherein the midpoint of the primary winding of the second balun is connected to a power supply. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 7. The power amplification circuit according to claim 2, wherein the power amplification circuit further comprises a third capacitor and a fourth capacitor, one end of the third capacitor is connected to an output terminal of the first power amplifier, the other end of the third capacitor is connected to an input terminal of the first power amplifier, one end of the fourth capacitor is connected to an output terminal of the second power amplifier, the other end of the fourth capacitor is connected to an input terminal of the second power amplifier.

8. The power amplification circuit according to claim 2, wherein the power amplification circuit further comprises a fifth capacitor, one end of the fifth capacitor is connected to a midpoint of the secondary winding of the second balun, the other end of the fifth capacitor is connected to a reference potential.

9. The power amplification circuit according to claim 2, wherein the power amplification circuit further comprises a sixth capacitor and a seventh capacitor, one end of the sixth capacitor is connected to an input terminal of the first power amplifier, the other end of the sixth capacitor is connected to an output terminal of a bias from the bias circuit to the first power amplifier, one end of the seventh capacitor is connected to an input terminal of the second power amplifier, the other end of the seventh capacitor is connected to an output terminal of a bias from the bias circuit to the second power amplifier.

10. The power amplification circuit according to claim 4, wherein the power amplification circuit further comprises at least one of an eighth capacitor and a ninth capacitor, one end of the eighth capacitor is connected to the primary winding of the first balun, the other end of the eighth capacitor is connected to a reference potential, one end of the ninth capacitor is connected to the secondary winding of the third balun, the other end of the ninth capacitor is connected to a reference potential.

11. The power amplification circuit according to claim 2 or 4, wherein a midpoint of the secondary winding of the second balun is connected to a reference potential.

12. A power amplification circuit comprising: a first differential power amplifier having a first power amplifier and a second power amplifier; a first balun provided on an input side of the first differential power amplifier; a second balun provided on an output side of the first differential power amplifier; a bias circuit that supplies a bias to the first differential power amplifier; and a tenth capacitor, the first balun comprises a primary winding and a secondary winding electromagnetically coupled to each other, a midpoint of the secondary winding of the first balun is connected to one end of the tenth capacitor, the other end of the tenth capacitor is connected to a reference potential, the bias circuit supplies a bias to both the first power amplifier and the second power amplifier in a high power mode, the bias circuit supplies a bias to one of the first power amplifier and the second power amplifier and does not supply a bias to the other in a low power mode. ​

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