Skyrmion memory device and cross array circuit using same

Abstract

The present invention relates to a Skyrmion memory device and a cross array circuit using the same, the Skyrmion memory device according to an embodiment of the present invention includes a resistive vertical electrode forming a Skyrmion, a Skyrmion channel layer moving the formed Skyrmion, and a magnetic tunnel junction including the Skyrmion channel layer, and a Skyrmion channel layer including a spin orbit moment channel layer, the free layer, an insertion layer, and a tunnel barrier layer, and sensing the moved Skyrmion to determine either a low resistance state or a high resistance state according to magnetization directions of the free layer and the pinned layer, the Skyrmion channel layer including a spin orbit moment channel layer, the free layer, the insertion layer, and the tunnel barrier layer, the area of the free layer can be controlled by controlling the size and the number of the moved skyrmions on the basis of the thickness of the insertion layer and the type of the forming material.

Description

TECHNICAL FIELD

[0001] The present application relates to a Skyrmion memory device and a crossbar array circuit using the same, and more particularly, to a Skyrmion memory device and a crossbar array circuit using the same, in which a resistive switching vertical electrode for generating a Skyrmion, a Skyrmion channel layer for moving the Skyrmion, and a magnetic tunnel structure for sensing the Skyrmion are formed, and a change in resistance according to a number of Skyrmions is linear. BACKGROUND

[0002] In order to implement an artificial intelligence semiconductor chip, a cross-point synaptic array circuit and a neuron unit having high integration are required.

[0003] A CMOS FET cross-point and a cross-point array based on a new generation memory (RRAM, PCRAM, STT-MRAM, SOT-MRAM) are reported in the prior art, but have a poor linearity in potentiation and depression, and thus have a disadvantage in that an additional compensation circuit is required.

[0004] In 2020, a research team of the Massachusetts Institute of Technology (MIT) published in Marc A Baldo et al., Magnetic Domain Wall Based Synaptic and Activation Function Generator for Neuromorphic Accelerators, Nano Lett., 1033.1040, 2020 that a man-made synaptic device according to spin-orbit torque (SOT) tunnel-based magnetic domain wall displacement was implemented.

[0005] The MIT published artificial synapse device is composed of a structure of Ta SOT tunnel / free layer (information storage layer) / tunnel barrier layer / pinning layer (magnetic layer) / connection layer / lower exchange anti-ferromagnetic multi-layers (SyAF MLs) / separation layer / upper exchange anti-ferromagnetic multi-layers (SyAF MLs) / capping layer / upper electrode.

[0006] The conventional artificial synapse device is a device that switches the spin direction of the free layer of the pSTT-MRAM by the SOT effect generated in the Ta SOT tunnel to displace the domain wall of the free layer, thereby changing the resistance, and implements the enhancement / inhibition operation of the synapse in this way.

[0007] However, the SOT tunnel and the pSTT-MRAM provided in a lateral structure have a minimum feature size of 93F 2 Therefore, there is a fatal shortcoming in the integration level.

[0008] That is, the synapse device structure based on the SOT MRAM as the prior art cannot be highly integrated into a three-terminal structure, and the synapse device based on the SOT MRAM has problems of requiring a lot of energy by the domain wall motion and the pinning being affected by the defect site. SUMMARY

[0009] TECHNICAL PROBLEM

[0010] The object of the present application is to achieve a skyrmion storage device and a crossbar array circuit using the same in which a resistance change with the number of skyrmions is linear, composed of a resistance-change vertical electrode for generating skyrmions, a skyrmion channel layer for moving skyrmions, and a magnetic tunnel structure for sensing skyrmions.

[0011] The present application aims to provide a skyrmion storage device and a crossbar array circuit using the same, in which a skyrmion-stable skyrmion tunnel is formed by adding an insertion layer to the interface of a free layer and a tunnel barrier, a skyrmion is formed by forming an electrochemical metallization memory, a valence change memory, and a resistive vertical electrode of a mixture of ECM and VCM input pulse, and the resistance is changed according to the number of skyrmions by changing the structure of the free layer of the magnetic tunnel junction, so that enhancement and inhibition can be linearly achieved.

[0012] The present application aims to provide a skyrmion storage device and a crossbar array circuit using the same, in which a skyrmion-stable skyrmion tunnel is formed by adding an insertion layer to the interface of a free layer and a tunnel barrier, a skyrmion is formed by forming an electrochemical metallization memory, a valence change memory, and a resistive vertical electrode of a mixture of ECM and VCM input pulse, and the resistance is changed according to the number of skyrmions by changing the structure of the free layer of the magnetic tunnel junction, so that enhancement and inhibition can be linearly achieved.

[0013] The present application aims to provide a skyrmion storage device and a crossbar array circuit using the same, in which a skyrmion-stable skyrmion tunnel is formed by adding an insertion layer to the interface of a free layer and a tunnel barrier, a skyrmion is formed by forming an electrochemical metallization memory, a valence change memory, and a resistive vertical electrode of a mixture of ECM and VCM input pulse, and the resistance is changed according to the number of skyrmions by changing the structure of the free layer of the magnetic tunnel junction, so that enhancement and inhibition can be linearly achieved.

[0014] The present application aims to provide a skyrmion storage device and a crossbar array circuit using the same, in which a skyrmion-stable skyrmion tunnel is formed by adding an insertion layer to the interface of a free layer and a tunnel barrier, a skyrmion is formed by forming an electrochemical metallization memory, a valence change memory, and a resistive vertical electrode of a mixture of ECM and VCM input pulse, and the resistance is changed according to the number of skyrmions by changing the structure of the free layer of the magnetic tunnel junction, so that enhancement and inhibition can be linearly achieved.

[0015] The present application aims to provide a skyrmion storage device and a crossbar array circuit using the same, in which a skyrmion-stable skyrmion tunnel is formed by adding an insertion layer to the interface of a free layer and a tunnel barrier, a skyrmion is formed by forming an electrochemical metallization memory, a valence change memory, and a resistive vertical electrode of a mixture of ECM and VCM input pulse, and the resistance is changed according to the number of skyrmions by changing the structure of the free layer of the magnetic tunnel junction, so that enhancement and inhibition can be linearly achieved.

[0016] Technical solutions

[0017] The skyrmion storage device of an embodiment of the present application includes a resistive vertical electrode forming a skyrmion, a skyrmion channel layer moving the formed skyrmion, and a magnetic tunnel junction including the skyrmion channel layer and determining any one of a low resistance state and a high resistance state according to the magnetization direction of a free layer and a pinned layer by sensing the moved skyrmion, the skyrmion channel layer including a spin orbit torque (SOT) channel layer, the free layer, an insertion layer, and a tunnel barrier layer, the size and the number of the moved skyrmion being controlled based on the thickness and the kind of the formation material of the insertion layer, so that the area of the free layer can be controlled.

[0018] The magnetic tunnel junction can sense a multi-bit skyrmion when the number of skyrmions is plural, and the area of the free layer increases with the multi-bit skyrmion.

[0019] The resistance level of the magnetic tunnel junction can gradually change with the increase of the area of the free layer, thereby ensuring the linearity of the enhancement or suppression achieved in multiple levels.

[0020] The resistive switching vertical electrode can be any one of an electrochemical metallization memory (ECM) vertical electrode, a valence change memory (VCM) vertical electrode, and a vertical electrode combining ECM and VCM.

[0021] The resistive switching vertical electrode includes an electrode and a resistive switching layer, and the resistive switching layer can be formed of any one of SiO x , MgO, HfO x , AlO x , TiO x , TaO x , GeSe, GeS2, GeTe, ZnTe, and the electrode can be formed of any one of Al, TiN, Ti, Ag, Cu, CuTe, W, Pt, and Ru.

[0022] The skyrmion channel layer can be formed in a first structure in which the spin-orbit torque channel layer, the free layer, the insertion layer, and the tunnel barrier layer are sequentially stacked.

[0023] The skyrmion channel layer can be formed in a second structure in which the spin-orbit torque channel layer, an oxide seed layer, the insertion layer, a first free layer, a spacer layer, a second free layer, and the tunnel barrier layer are sequentially stacked.

[0024] In the case of being formed in the second structure, the skyrmion channel layer can cancel skyrmion Hall effect by moving the formed skyrmion to an anti-ferro-coupled skyrmion through the first free layer and the second free layer.

[0025] The skyrmion channel layer can be formed in a third structure in which the tunnel barrier layer, the insertion layer, the free layer, and the spin-orbit torque channel layer are sequentially stacked.

[0026] The insertion layer can be formed of any one of Ta, W, Pt, Mo, and Ti, and the thickness of the insertion layer can be inversely proportional to the size and number of the skyrmions.

[0027] The magnetic tunnel junction can be formed in a structure in which the spin-orbit torque channel layer, the free layer, the insertion layer, the tunnel barrier layer, the pinned layer, a bridge layer, a first synthetic anti-ferromagnetic multi-layer, a spacing layer, a second synthetic anti-ferromagnetic multi-layer, and an upper electrode are sequentially stacked.

[0028] According to an embodiment of the present application, a cross-point array circuit utilizes a skyrmion storage device including a resistive vertical electrode for generating a skyrmion, a skyrmion channel layer for moving the generated skyrmion, and a magnetic tunnel junction including a skyrmion channel layer and determining any one of a low resistance state and a high resistance state according to magnetization directions of a free layer and a pinned layer by sensing the moved skyrmion, the skyrmion channel layer including a spin-orbit torque channel layer, the free layer, an insertion layer, and a tunnel barrier layer, the size and number of the moved skyrmion being controlled based on the thickness and formation material of the insertion layer, thereby controlling the area of the free layer. In the cross-point array circuit, the skyrmion storage device and a switching device constitute one bit cell, and can include an array arranged by a plurality of the bit cells and a driving part for applying a driving signal to the array.

[0029] The bit cell can have a two-terminal structure in which the resistive vertical electrode is connected to a drain terminal of the switching device and an upper electrode of the magnetic tunnel junction is connected to a bit line.

[0030] Effects of the Invention

[0031] According to an embodiment, the present application can implement a skyrmion storage device and a cross-point array circuit using the same in which a resistive vertical electrode for generating a skyrmion, a skyrmion channel layer for moving the skyrmion, and a magnetic tunnel structure for sensing the skyrmion are formed, and the resistance change with the number of skyrmions is linear.

[0032] The present application can provide a skyrmion storage device and a crossbar circuit using the same, in which a skyrmion-stable skyrmion tunnel is formed by adding an insertion layer at the interface of a free layer and a tunnel barrier, a skyrmion is formed by an input pulse of an electrochemical metallization memory, a valence change memory, and a resistive vertical electrode of a mixture of ECM and VCM, and the resistance is changed according to the number of skyrmions by changing the structure of the free layer of the magnetic tunnel junction, so that enhancement and inhibition can be linearly achieved.

[0033] The present application can adjust the number of skyrmions in a single magnetic tunnel junction by controlling the size of skyrmions according to the kind and thickness of the formation material of the insertion layer in a skyrmion channel layer in which skyrmions move, and thus realize bits on multiple levels.

[0034] The present application can realize an ultra-low power synapse device in which the voltage for generating skyrmions is very low, 1V or less, and the voltage for sensing skyrmions moving through a magnetic tunnel junction is very low, about 0.1V, based on a skyrmion storage device in which the resistance changes linearly according to the number of skyrmions.

[0035] The present application can reduce the write energy required for skyrmion movement by controlling the kind and thickness of the formation material of the insertion layer in a skyrmion channel layer in which skyrmions move.

[0036] The present application can control the coercivity of a free layer by controlling the kind and thickness of the formation material of the insertion layer in a skyrmion channel layer in which skyrmions move, and remove residual magnetization by forming a stripe domain. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 A diagram of a skyrmion storage device for explaining an embodiment of the present application.

[0038] Figure 2 A diagram for explaining the structure and working concept of a skyrmion storage device formed in a two-terminal manner according to an embodiment of the present application.

[0039] Figure 3 A diagram for explaining a crossbar circuit using a skyrmion storage device according to an embodiment of the present application.

[0040] Figures 4a to 5b A diagram for explaining a spin-orbit torque channel layer included in a skyrmion channel layer in a skyrmion storage device according to an embodiment of the present application.

[0041] Figures 6a to 10 A diagram for explaining an insertion layer included in a skyrmion channel layer in a skyrmion storage device according to an embodiment of the present application.

[0042] Figure 11 FIG. 1 is a diagram to explain a structure and a working concept of a synapse device using an anti-ferro coupled SGM channel layer according to an embodiment of the present application.

[0043] Figure 12 FIG. 2 is a diagram to explain a SGM Hall effect cancellation using an anti-ferro coupled SGM channel layer according to an embodiment of the present application.

[0044] Figure 13 FIG. 3 is a diagram to explain a structure of a resistance-change vertical electrode for generating SGMs according to an embodiment of the present application.

[0045] Figure 14 FIG. 4 is a diagram to explain an I-V curve in the structure of the resistance-change vertical electrode for generating SGMs according to an embodiment of the present application.

[0046] Figure 15 FIG. 5 is a diagram to explain SGM generation and movement of the resistance-change vertical electrode for generating SGMs according to an embodiment of the present application.

[0047] Figures 16a to 16d FIG. 6 is a diagram to explain a multi-level implementation according to a number of SGMs according to an embodiment of the present application.

[0048] Figure 17 and Figure 18 FIG. 7 is a diagram to explain another structure of a SGM memory device according to an embodiment of the present application. DETAILED DESCRIPTION

[0049] Hereinafter, various embodiments of the present application will be described with reference to the accompanying drawings.

[0050] It should be understood that the embodiments and the terms used therein are not intended to limit the technology described in the specification to particular embodiments, and include various modifications, equivalents, and / or alternatives of the related embodiments.

[0051] In describing various embodiments, detailed description of functions or structures related to related known functions or structures will be omitted when it is determined that such a detailed description can unnecessarily obscure the gist of the present application.

[0052] Also, the terms described later are terms defined after considering the functions in the various embodiments, and can vary according to the intention of a user, an operator, or management, etc. Therefore, these terms should be defined based on the content of the entire specification.

[0053] In the description of the drawings, similar structural elements can use similar reference numerals.

[0054] The singular expression can include the plural expression unless the context clearly dictates otherwise.

[0055] In the present specification, expressions such as "A or B" or "at least one of A and / or B" can include all possible combinations of the listed items.

[0056] Expressions such as "first", "second", "primary" or "secondary" can modify an associated element without relation to order or importance, for distinguishing one element from other elements, rather than to limit the associated element.

[0057] When it is mentioned that a certain (for example, first) element is "connected" or "coupled" (in a functional or communicative manner) to other (for example, second) element, the certain element can be connected to the other element directly or through other element (for example, third element).

[0058] In the present specification, "configured to" can be used interchangeably with, for example, "adapted to", "having the ability", "altered to", "manufactured to", "capable of", or "designed to", according to circumstances.

[0059] In some cases, the expression "device configured to" can mean that the device can be "capable of" other devices or accessories.

[0060] For example, the expression "a processor configured to (or set to) perform A, B, and C" can refer to a dedicated processor (for example, an embedded processor) for performing the associated operations or a general-purpose processor (for example, a central processing unit (CPU) or an application processor) that performs the associated operations by executing one or more software programs stored in a memory.

[0061] Also, the term "or" means the logical or "inclusive or" rather than the logical or "exclusive or".

[0062] That is, unless otherwise specified or the context clearly indicates otherwise, the expression "x utilizes a or b" means any one of the natural inclusive permutations.

[0063] In the above detailed description, the structural elements included in the present application are expressed in singular or plural according to the proposed detailed description.

[0064] However, the singular or plural expression is selected for convenience of explanation in a manner suitable for the situation presented, and the above-described embodiments are not limited by the singular or plural structural elements, and a structural element expressed in the plural can be constituted by the singular, and a structural element expressed in the singular can also be constituted by the plural.

[0065] On the other hand, in the description of the present application, although the contents relating to the specific embodiments are described, it is self-evident that various modifications can be made within the scope of the technical idea including various embodiments.

[0066] Therefore, the scope of the present application should not be limited to the described embodiments, but should be determined by the scope of the claims and equivalents thereto.

[0067] Figure 1 A diagram of a skyrmion memory device for explaining an embodiment of the present application.

[0068] Figure 1 A structure of a skyrmion memory device of an embodiment of the present application is exemplified.

[0069] Reference Figure 1 The skyrmion memory device 100 of an embodiment of the present application can implement a synapse device as a p-MTJ memory device based on skyrmions.

[0070] For example, the skyrmion memory device 100 replaces a 1T1C (1 transistor and 1 capacitor) structure as a basic unit (Cell) unit of a DRAM with a 1T1R (1 transistor 1 magnetic tunneling junction) structure of a skyrmion-based p-MTJ using a transistor and a p-MTJ, maintains a high-speed DRAM characteristic, and adds a nonvolatile characteristic of the p-MTJ, thereby making it possible to replace all existing memory fields (DRAM, SRAM, Flash memory) with a nonvolatile memory capable of high-speed rewriting, and making it possible to implement a multi-level according to the number of skyrmions.

[0071] According to an embodiment of the present application, the skyrmion memory device 100 includes a resistance-change vertical electrode 110 forming a skyrmion, a skyrmion channel layer 120 moving the skyrmion, and a magnetic tunnel junction 130 including the skyrmion channel layer 120 and determining any one of a low resistance state and a high resistance state according to the magnetization directions of a free layer 122 and a pinned layer 131 by sensing the skyrmion.

[0072] The SGM channel layer 120 includes a spin orbit torque channel layer 121, a free layer 122, an insertion layer 123, and a tunnel barrier layer 124.

[0073] The magnetic tunnel junction 130 controls the number of SGMs moving to the SGM channel layer 120 based on the thickness of the insertion layer 123 and the kind of formation material, thereby making it possible to control the area of the free layer 122.

[0074] That is, the SGM memory device 100 can control the size and the number of moving SGMs based on the thickness of the insertion layer 123 and the kind of formation material, thereby controlling the area of the free layer.

[0075] According to an embodiment of the present application, the resistive switching vertical electrode 110 includes an electrode 111 and a resistive switching layer 112. Herein, the electrode 111 can be referred to as a lower electrode.

[0076] For example, the resistive switching layer 112 can be formed of any one of SiO x , MgO, HfO x , AlO x , TiO x , TaO x , GeSe, GeS2, GeTe, ZnTe as a binary oxide, and the electrode 111 can be formed of any one of Al, TiN, Ti, Ag, Cu, CuTe, W, Pt, and Ru as a chalcogenide.

[0077] For example, the resistive switching vertical electrode 110 can be any one of an ECM vertical electrode, a VCM vertical electrode, and an ECM and VCM combined vertical electrode.

[0078] For example, the ECM and VCM combined vertical electrode can be a vertical electrode simultaneously including the characteristics of the ECM vertical electrode and the characteristics of the VCM vertical electrode.

[0079] The ECM vertical electrode can be a vertical electrode using a metal wire-based resistive switching (RS) element, and the VCM vertical electrode can be a vertical electrode using an oxide-based RS element.

[0080] For example, when the resistive switching vertical electrode 110 is a VCM vertical electrode, oxygen vacancies move to the resistive switching layer 112 to form a filament, and simultaneously form a low resistance state vertical electrode.

[0081] For example, when the resistance change vertical electrode 110 is an ECM vertical electrode, a metal substance forming a metal electrode moves to the resistance change layer 112 to form a filament, and a vertical electrode in a low resistance state is formed.

[0082] According to an embodiment of the present application, the skyrmion channel layer 120 can be formed in a first structure in which a spin-orbit torque channel layer 121, a free layer 122, an insertion layer 123, and a tunnel barrier layer 124 are sequentially stacked.

[0083] For example, the insertion layer 123 is formed of a non-magnetic metal selected from Mo, Ta, W, PT, and Ti.

[0084] Also, the skyrmion channel layer 120 controls the coercivity of the free layer 122 and forms a stripe domain when controlling the thickness of the insertion layer 123, and a stripe width related to the formed stripe domain is controlled, and the number and size of skyrmions are proportional to the controlled stripe width.

[0085] If the thickness of the insertion layer 123 increases, the width of the stripe domain decreases.

[0086] That is, the thickness of the insertion layer 123 is inversely proportional to the number and size of skyrmions generated in the free layer 122.

[0087] The skyrmion channel layer 120 moves skyrmions in response to a voltage pulse applied from the vertical electrode 110.

[0088] The magnetic tunnel junction 130 is configured in a bottom free structure of a p-MTJ (perpendicular-Magneto Tunneling Junction) spin-valve, and is formed in a structure in which the spin-orbit torque channel layer 121, the free layer 122, the insertion layer 123, the tunnel barrier layer 124, the pinned layer 131, the bridge layer 132, the first exchange anti-ferromagnetic layer 134, the separation layer 135, the second exchange anti-ferromagnetic layer 136, and the upper electrode 140 are sequentially stacked, and can further include the capping layer 137.

[0089] The first exchange anti-ferromagnetic layer 134, the separation layer 135, and the second exchange anti-ferromagnetic layer 136 configure a synthetic anti-ferromagnetic multi-layer (SyAF) 133.

[0090] As the magnetic tunnel junction 130, the p-MTJ spin-valve includes the skyrmion channel layer 120.

[0091] The vertical electrode 110 applies a write voltage pulse V through the electrode 111 write At this time, a skyrmion is formed.

[0092] A voltage pulse V that moves the skyrmion is injected through the electrode 111 shift At this time, the skyrmion channel layer 120 moves the skyrmion to the lower portion of the magnetic tunnel junction 130.

[0093] When the skyrmion moves to the lower portion of the magnetic tunnel junction 130, if the magnetization directions of the free layer 122 and the pinned layer 131 are parallel, a low resistive state (LRS) is formed due to the easy flow of the current, and thus the low resistive state can be referred to as a parallel state.

[0094] Also, if the magnetization directions of the free layer 122 and the pinned layer 131 are anti-parallel, a high resistive state (HRS) is formed due to the reduction of the current, and thus the high resistive state can be referred to as an anti-parallel state.

[0095] As the number of skyrmions increases, the area of the free layer 122 of the magnetic tunnel junction 130 that is switched increases, and the resistance difference gradually changes, thereby ensuring the linearity of enhancement and inhibition.

[0096] Accordingly, the present application can provide a skyrmion memory device capable of linearly achieving enhancement and inhibition and a crossbar circuit using the same, by forming a skyrmion tunnel in which a skyrmion is stably formed by adding an insertion layer to the interface of a free layer and a tunnel barrier, forming a skyrmion and changing the structure of a free layer of a magnetic tunnel junction using an input pulse of a resistance change vertical electrode formed by ECM, VCM, and a mixture of ECM and VCM, and changing the resistance according to the number of skyrmions.

[0097] The switching method of the magnetic tunnel junction 130 is not a spin-transfer-torque method through the tunnel barrier layer 124, but a resistance change is formed by the movement of a skyrmion formed by applying a voltage pulse to a VCM or ECM vertical electrode, and thus the resistance*area (RA) of the p-MTJ can be increased by increasing the thickness of the tunnel barrier layer 124.

[0098] Also, due to the topological stability of the skyrmion, the pinning effect on defects can be weak.

[0099] The skyrmion memory device 100 can implement multiple levels by controlling the number of skyrmions in a single magnetic tunnel junction 130 by controlling the skyrmion size with the insertion layer 123 thickness.

[0100] For example, the skyrmion memory device 100 can be used in magnetic nonvolatile memories capable of telling rewriting, neuromorphic computing, neuromorphic devices, artificial intelligence hardware.

[0101] Figure 2 A diagram to explain the structure and working concept of a skyrmion memory device formed in a two-terminal according to an embodiment of the present application.

[0102] Figure 2 Structural elements constituting the structure of a skyrmion memory device formed in a two-terminal according to an embodiment of the present application are exemplified, and the operation based on the structural elements is exemplified.

[0103] Reference Figure 2 The skyrmion memory device 200 of an embodiment of the present application includes a spin torque channel layer 201, a free layer 202, an insertion layer 203, and a tunnel barrier layer 204, a pinned layer 205 in a region 200 where a skyrmion channel layer and a magnetic tunnel junction are repeated.

[0104] The lower part of the spin torque channel layer 201 uses ECM as a resistance change vertical electrode.

[0105] The skyrmion memory device 200 is divided into a low resistance state 210 and a high resistance state 220, and when a voltage pulse for a write operation is applied, it can move from the low resistance state 210 to the high resistance state 220, and when a voltage pulse for an erase operation is applied, it moves from the high resistance state 220 to the low resistance state 210.

[0106] The low resistance state 210 of the skyrmion memory device 200 is not located at a position where the skyrmion 211 and the pinned layer 205 are perpendicular in the free layer 202.

[0107] The high resistance state 220 of the skyrmion memory device 200 is located at a position where the skyrmion 221 and the pinned layer 205 are perpendicular in the free layer 202.

[0108] The skyrmion memory device 200 becomes a low resistance state 210 when the magnetization directions of the free layer 202 and the pinned layer 205 are parallel due to the easy flow of current, and becomes a high resistance state 220 when the magnetization directions of the free layer 202 and the pinned layer 205 are anti-parallel due to the reduction of current.

[0109] That is, in the skyrmion memory device 200, the arrow directions of the low resistance state 210 and the lower free layer 202 of the pinning layer 205 are the same, and the arrow directions of the high resistance state 220 and the lower free layer 202 of the pinning layer 205 are different.

[0110] Figure 3 A diagram for explaining a crossbar circuit of a skyrmion memory device according to an embodiment of the present application.

[0111] Figure 3 A crossbar circuit of a skyrmion memory device according to an embodiment of the present application is exemplified.

[0112] Reference Figure 3 The crossbar circuit 300 of the skyrmion memory device according to an embodiment of the present application is composed of a skyrmion memory device 311 and a switching device for one bit cell 310, and includes an array in which a plurality of bit cells 310 are arranged and a driving section 320 for applying a driving signal to the array. The switching device can be, for example, a metal-oxide-semiconductor field effect transistor (MOSFET).

[0113] For example, the bit cell 310 has a two-terminal structure in which the resistive switching vertical electrode of the skyrmion memory device 311 is connected to the drain terminal of the switching device and the upper electrode is connected to the bit line at the magnetic tunnel junction of the skyrmion memory device 311.

[0114] The crossbar circuit 300 can reduce power consumption in the array, and since it uses an existing crossbar as a framework, it is also easy to achieve high integration.

[0115] Therefore, the present application relates to a skyrmion memory device and a crossbar circuit using the same, and can achieve a skyrmion memory device and a crossbar circuit using the same in which the resistance change with the number of skyrmions is linear, composed of a resistive switching vertical electrode for generating a skyrmion, a skyrmion channel layer for moving the skyrmion, and a magnetic tunnel structure for sensing the skyrmion.

[0116] Figures 4a to 5b A diagram for explaining a spin-orbit torque channel layer included in a skyrmion channel layer of a skyrmion memory device according to an embodiment of the present application.

[0117] Figure 4a and Figure 4bAn A15 crystal structure of β-W, which is known as a substance having high spin torque efficiency, is exemplified in a skyrmion storage device of an embodiment of the present application, which is used in order to reduce the writing energy required for moving a skyrmion in a skyrmion channel layer.

[0118] Referring to Figure 4a a graph 400 of FIG. 4 and Figure 4b a graph 410 of FIG. 5, it can be confirmed that when the thickness of tungsten (W) used as a spin-orbit torque channel layer in a skyrmion channel layer is 5 nm or less, peaks of 5.5° 200, 39.8° 210, 43.8° 211 of β-W are present.

[0119] The graph 400 exemplifies a crystal structure according to the thickness of a spin-orbit torque channel layer with respect to a skyrmion channel layer, and the graph 410 exemplifies crystallinity according to a direct current (DC) sputtering power.

[0120] From the thickness of tungsten being 6 nm or more, only an α-W 40.1° 110 peak is present, and thus it can be confirmed that an α-phase (b.c.c.) crystal structure is present.

[0121] Also, when the thickness of a tungsten thin film is 4 nm, it can be confirmed that α-W 5.5° 200, 39.8° 210, 43.8° 211 peaks are present at a DC sputtering power of 150 W or less.

[0122] It can be confirmed that in the case of securing an A15 crystal structure of α-W of a spin-orbit torque channel layer of a skyrmion channel layer, a high spin hall angle of 0.3 as shown in Table 1 can be secured.

[0123] Table 1

[0124]

[0125] Figure 5a Exemplified is surface roughness (Ra) of a skyrmion channel layer in a skyrmion storage device as a DC sputtering power is changed in a process of forming a spin-orbit torque channel layer of the skyrmion channel layer.

[0126] Figure 5b Exemplified is a Magneto-Optical Kerr Effect (MOKE) microscope image of a free layer as a sputtering power of a skyrmion channel layer is changed.

[0127] Referring to Figure 5aFigure 500 confirms that the surface roughness of the skyrmion channel layer increases with increasing W sputtering power.

[0128] refer to Figure 5b As shown in Figures 510, 511 and 512, it can be confirmed that the domain edge roughness increases with the increase of the surface roughness of the skyrmion channel layer.

[0129] Image 510 illustrates the case where the W sputtering power is 20W, image 511 illustrates the case where the W sputtering power is 100W, and image 512 illustrates the case where the W sputtering power is 150W.

[0130] W is the sputtering power used for sputtering tungsten deposition.

[0131] This indicates that the increase in pinning sites caused by the surface roughness of the skyrmion channel layer will hinder the movement of skyrmions. Therefore, the surface roughness of the skyrmion channel layer needs to be below 1 Å.

[0132] Figures 6a to 10 This diagram illustrates the insertion layer included in the skyrmion channel layer of a skyrmion storage device according to an embodiment of the present invention.

[0133] Figure 6a and Figure 6b An illustration is provided of the vertical magnetization curve and MOKE strip domain image in a skyrmion channel layer as the thickness of the insertion layer is shown according to an embodiment of the invention.

[0134] refer to Figure 6a Figure 600 confirms that the coercivity of the free layer decreases with the increase of the thickness of the inserted layer, and the remanence disappears with the formation of strip magnetic domains.

[0135] In particular, such as Figure 6b As shown in Figure 610, when the thickness of the intercalation layer is 0.099 nm, 1 μm-sized strip magnetic domains with both spin-up and spin-down properties are formed in the region where coercivity disappears. Locally, the vertical magnetization characteristics of spin-up and spin-down are retained, but they cancel each other out overall, thus showing the characteristic of no vertical magnetization.

[0136] Figure 7a and Figure 7b The magnetic properties of the material and thickness of the insertion layer formed according to an embodiment of the present invention are illustrated.

[0137] Figure 7aFig. 700 illustrates magnetic moment of the insertion layer with respect to the kind of the material forming the insertion layer and the thickness of the insertion layer, Figure 7b Fig. 710 illustrates anisotropy field (H k ) of the insertion layer with respect to the kind of the material forming the insertion layer and the thickness of the insertion layer.

[0138] According to the graph 700 and the graph 710, in the case of Pt (0.110 ~ 0.209 nm) and Ti (0.300 ~ 0.402 nm), while maintaining the magnetic moment (M s ) of 102 ± 6 μemu, 61 ± 5 μemu, respectively, the anisotropy field of Pt is reduced from +5.10 kOe to -2.98 kOe, and the anisotropy field of Ti is reduced from +5.29 kOe to -1.20 kOe.

[0139] In the case of forming the insertion layer of tungsten, the magnetic moment value continuously decreases from 49 μemu to 5 μemu as the thickness increases, and the anisotropy field also decreases as the thickness of the insertion layer formed of tungsten increases, but compared to other materials, it remains from 8.30 kOe to 3.50 kOe.

[0140] Accordingly, the present application controls the coercivity of the free layer by controlling the kind of the material forming the insertion layer and the thickness in the SGMON channel layer in which the SGMON moves, so that the residual magnetization can be eliminated by forming a stripe domain.

[0141] Figure 8a The magnetic properties with respect to the thickness of the material forming the insertion layer of an embodiment of the present application and the M-H curve using the stripe domain width MOKE are illustrated.

[0142] Figure 8b The anisotropy field (H k ) and the stripe domain width with respect to the thickness of the material forming the insertion layer of an embodiment of the present application are illustrated.

[0143] Referring to Figure 8a , the graph 800 represents Pt, the graph 801 represents W, and the graph 802 represents Ti.

[0144] Referring to Figure 8b , the graph 810 represents Pt, the graph 811 represents W, and the graph 812 represents Ti.

[0145] Figure 9 The MOKE image in the SGMON channel layer of the present application with respect to the material forming the insertion layer and the thickness of the insertion layer is illustrated.

[0146] Referring to Figure 9, the image 900 shows a case where the formation substance of the insertion layer is Pt, the image 910 shows a case where the formation substance of the insertion layer is W, and the image 920 shows a case where the formation substance of the insertion layer is Ti.

[0147] The stripe domain width (λ0) is proportional to , and thus, as Figures 8a to 9 indicated, the stripe domain width decreases as the anisotropy field (H K ) decreases, and thus, it can be confirmed that Pt can secure a stripe domain width of about 1 μm in 0.1670 nm, W can secure a stripe domain width of about 1 μm in 0.0806 nm, and Ti can secure a stripe domain width of about 1 μm in 0.3615 nm.

[0148] That is, according to the images 900 to 920, it can be confirmed that the stripe domain width decreases as the thickness of the insertion layer increases.

[0149] According to the case where the stripe domain width is proportional to the size and number of the skyrmions, it can be confirmed that the thickness of the insertion layer is inversely proportional to the size and number of the skyrmions.

[0150] Figure 10 A skyrmion MOKE image with respect to a magnetic field is illustrated after fixing the thickness of the insertion layer in the skyrmion channel layer of the present application.

[0151] Referring to Figure 10 , the image 1000 shows a case where the formation substance of the insertion layer is Pt, the image 1010 shows a case where the formation substance of the insertion layer is W, and the image 1020 shows a case where the formation substance of the insertion layer is Ti.

[0152] In the images 1000 to 1020, Pt is fixed to a thickness of 0.1670 nm, W is fixed to a thickness of 0.0806 nm, and Ti is fixed to a thickness of 0.3615 nm.

[0153] It can be confirmed in the images 1000 to 1020 that the perpendicular external magnetic field increases as it moves to the right.

[0154] Also, it can be confirmed in the images 1000 to 1020 that, when a change in the external magnetic field is applied in the fixed thickness of the insertion layer, skyrmions of about 1 to 2 μm are generated.

[0155] Thus, the present application can implement an ultra-low power synapse device in which a voltage for generating skyrmions is very low, 1 V or less, based on a skyrmion memory device in which resistance is linear with respect to a change in the number of skyrmions, and a voltage for sensing skyrmions moving through a magnetic tunnel junction is very low, about 0.1 V.

[0156] Also, the present application can reduce the writing energy required for skyrmion movement by controlling the kind and thickness of the formation substance of the insertion layer in the skyrmion channel layer in which the skyrmion moves.

[0157] Figure 11 A diagram for explaining the structure and operation concept of a synapse device of an antiferromagnetically coupled skyrmion channel layer according to an embodiment of the present application.

[0158] Figure 11 A structure of a synapse device for canceling a skyrmion hall effect in a skyrmion channel layer in which a skyrmion moves according to an embodiment of the present application is exemplified

[0159] Reference Figure 11 In the skyrmion storage device according to an embodiment of the present application, the skyrmion channel layer 1100 is formed in a second structure in which a spin orbit torque channel layer, an oxide seed layer 1101, an insertion layer 1102, a first free layer 1103, a spacer layer 1104, a second free layer 1105, and a tunnel barrier layer 1106 are sequentially stacked, and an upper portion is provided with a pinning layer 1107 as a structure of a magnetic tunnel junction.

[0160] The first free layer 1103 and the second free layer 1105 have opposite spin directions in an RKKY coupling manner through the spacer layer 1104.

[0161] For example, the free layer can also be referred to as a magnetic layer.

[0162] The skyrmion storage device is divided into a low resistance state 1110 and a high resistance state 1120, and when a voltage pulse for a write operation is applied, it is movable from the low resistance state 1110 to the high resistance state 1120, and when a voltage pulse for an erase operation is applied, it is movable from the high resistance state 1120 to the low resistance state 1110.

[0163] The low resistance state (1110) of the skyrmion storage device is not located at a position perpendicular to the antiferromagnetically coupled skyrmion 1111 and the pinning layer 1107 in the first free layer 1103 and the second free layer 1105.

[0164] The high resistance state 1120 of the skyrmion storage device is located at a position perpendicular to the antiferromagnetically coupled skyrmion 1121 and the pinning layer 1107 in the first free layer 1103 and the second free layer 1105.

[0165] The skyrmion memory device becomes a low resistance state 1110 when the magnetization directions of the first free layer 1103 and the second free layer 1105 and the pinned layer 1107 are parallel due to the easy flow of current, and becomes a high resistance state 1120 when the magnetization directions of the first free layer 1103 and the second free layer 1105 and the pinned layer 1107 are anti-parallel, in which the current is reduced.

[0166] That is, in the skyrmion memory device, the arrow directions of the lower first free layer 1103 and the second free layer 1105 under the pinned layer 1107 are the same in the low resistance state 1110, and the arrow directions of the lower first free layer 1103 and the second free layer 1105 under the pinned layer 1107 are different in the high resistance state 1120.

[0167] Figure 12 A diagram for explaining a skyrmion channel layer using anti-ferromagnetic coupling to cancel skyrmion Hall effect according to an embodiment of the present application.

[0168] Referring to Figure 12 , the image 1200 illustrates a case where a skyrmion is bent in a moving path by a magnus force due to the skyrmion Hall effect, and the image 1201 illustrates a case where a first free layer and a second free layer are formed in an anti-ferro coupling manner having opposite spin directions by RKKY coupling through a spacer layer, thereby canceling the skyrmion Hall effect.

[0169] That is, as illustrated in the image 1201, when magnus forces act in the first free layer and the second free layer, respectively, the skyrmion Hall effect can be canceled by the magnus forces being canceled.

[0170] That is, in a case where a skyrmion channel layer is formed in a second structure in which a first free layer and a second free layer are formed in RKKY coupling through a spacer layer, the skyrmion Hall effect can be canceled by moving the formed skyrmion to an anti-ferro-coupled skyrmion by the first free layer and the second free layer.

[0171] Figure 13 A diagram for explaining a structure of a resistance variable vertical electrode for generating a skyrmion according to an embodiment of the present application, Figure 14 A diagram for explaining an I-V curve in a structure of a resistance variable vertical electrode for generating a skyrmion according to an embodiment of the present application.

[0172] Figure 13 An example according to an embodiment of the present application illustrates a VCM-based vertical electrode structure for generating a skyrmion, Figure 14Forming, set and reset voltages are exemplified by I-V curves in a VCM-based vertical electrode structure.

[0173] Referring to Figure 13 , a structure 1300 of a resistance-change vertical electrode for generating a skyrmion according to an embodiment of the present application is composed of a lower electrode 1310 formed of Ru, a skyrmion channel layer 1320, and a resistance-change vertical electrode 1330, the skyrmion channel layer 1320 is composed of a spin-orbit torque channel layer 1321, a free layer 1322, an insertion layer 1323, and a tunnel barrier layer 1324, the resistance-change vertical electrode 1330 is composed of a resistance-change layer 1331 formed of HfO x , and an electrode 1332 formed of Pt.

[0174] The free layer 1322 can be formed of CoFeB, the insertion layer 1323 can be formed of Ta, W, Pt, Ti, and the tunnel barrier layer 1324 can be formed of MgO.

[0175] Referring to Figure 14 , a graph 1400 exemplifies Figure 13 a structure having a forming voltage of -3.6 V, a set voltage of -1.56 V, and a reset voltage of +5.4 V when the thickness of the resistance-change layer 1331 in the structure 1300 of the resistance-change vertical electrode explained in

[0176] Figure 15 A graph for explaining skyrmion generation and movement of a skyrmion generated by a resistance-change vertical electrode for generating a skyrmion according to an embodiment of the present application.

[0177] Figure 15 To explain a case of skyrmion generation with an input voltage pulse in a resistance-change vertical electrode for generating a skyrmion according to an embodiment of the present application, a case in which the pulse amplitude is +0.9 V and the pulse width is 200 ms is exemplified in an image 1500, a case in which the pulse amplitude is +0.3 V and the pulse width is 50 ms is exemplified in an image 1510, and a case in which the pulse amplitude is -0.3 V and the pulse width is 50 ms is exemplified in an image 1520.

[0178] Referring to the image 1500, a skyrmion is generated with the application of an input pulse, and the skyrmion moves in the current direction with a successive input pulse.

[0179] Referring to the image 1510, when an input pulse is applied as a voltage pulse, which is decreased from +1 V to +0.3 V, a previously generated skyrmion moves to the right side in the current direction, but no skyrmion is formed any more.

[0180] Referring to the image 1520, in the case where the pulse size is -0.3 V and the pulse width is 50 ms, it can be confirmed that the skyrmion moves to the left side in the current direction.

[0181] Therefore, in Figure 13 In the case where a magnetic tunnel junction as a p-MTJ spin valve is disposed at the lower electrode position, in the free layer of the skyrmion channel layer, the resistance of the MTJ can change to a low resistance (parallel state) and a high resistance (anti-parallel state) according to the position of the skyrmion.

[0182] Figures 16a to 16d An image according to the number of skyrmions in a plurality of levels according to an embodiment of the present application is illustrated.

[0183] Figure 16a Various cases of the number of skyrmions according to an embodiment of the present application are illustrated, Figure 16b Changes in the resistance state according to the number of skyrmions according to an embodiment of the present application are illustrated, Figure 16c A 16-level multi-bit skyrmion according to an embodiment of the present application is illustrated, Figure 16d A 16-level multi-bit enhancement and inhibition according to an embodiment of the present application is illustrated in terms of a resistance level.

[0184] Referring to Figure 16a The image 1601 illustrates the case where the skyrmion is one, the image 1602 illustrates the case where the skyrmion is three, the image 1603 illustrates the case where the skyrmion is five, and the image 1604 illustrates the case where the skyrmion is seven.

[0185] Referring to Figure 16b The graph 1610 of FIG. 16 illustrates that, as the number of skyrmions increases, the low resistance state (LRS) changes to the high resistance state (HRS).

[0186] This indicates that, in the case where the size of the skyrmion is smaller than the magnetic tunnel junction, a multi-level can be implemented according to the number of skyrmions.

[0187] Referring to Figure 16c The image 1620 illustrates a 16-level multi-bit skyrmion, Figure 16d The graph 1630 of FIG. 16 illustrates the enhancement and inhibition of the synapse according to the number of skyrmions.

[0188] It is illustrated that, in the case where the number of skyrmions that the magnetic tunnel junction has is defined as 16 in terms of the size of the skyrmion, it is also possible to implement a synapse device by implementing linear enhancement and inhibition of the synapse.

[0189] In the magnetic tunnel junction of the skyrmion memory device of one embodiment of the present application, in the case where the number of skyrmions is plural, a plurality of skyrmions are sensed, the immunity of the free layer increases with the plurality of skyrmions, and the resistance level gradually changes, so that the linearity of enhancement and suppression to be realized as a plurality of levels can be ensured.

[0190] Therefore, in the skyrmion channel layer in which the skyrmions move, the insertion layer is provided between the free layer and the tunnel barrier layer in the skyrmion memory device of one embodiment of the present application, the size of the skyrmions is controlled depending on the kind and thickness of the formation material of the insertion layer, so that the bit of the level storage can be realized by adjusting the number of skyrmions in a single magnetic tunnel junction.

[0191] Figure 17 and Figure 18 A diagram for explaining another structure of the skyrmion memory device of one embodiment of the present application is shown. Figure 17 and Figure 18 An example of a structure of the skyrmion memory device of one embodiment of the present application is shown. Figure 13 A design structure of the experiment shown is shown.

[0192] Figure 17 A first other structure of the skyrmion memory device of one embodiment of the present application is shown. The first other structure can be a structure different from the skyrmion memory device described in Embodiment 1. Figure 1

[0193] Referring to FIG. 17B, the skyrmion memory device 1700 shows a structure upside down from the skyrmion memory device 100 shown in Embodiment 1. Figure 17 Figure 1

[0194] For example, the skyrmion memory device 1700 can include a magnetic tunnel junction 1730 including a buffer layer 1738, a seed layer 1737, a first exchange antiferromagnetic layer 1736, a separation layer 1735, a second exchange antiferromagnetic layer 1734, a bridge layer 1732, and a pinning layer 1731 over the lower electrode 1740.

[0195] The buffer layer 1738 can be formed of Ta at a thickness of 5 nm, and the seed layer 1737 can be formed of Pt at a thickness of 3 nm.

[0196] The bridge layer 1732 can be formed of W at a thickness of 0.3 nm to 0.5 nm.

[0197] The first exchange antiferromagnetic layer 1736, the separation layer 1735, and the second exchange antiferromagnetic layer 1734 form a synthetic exchange antiferromagnetic layer 1733.

[0198] The magnetic tunnel junction 1730 further includes a tunnel barrier layer 1724, an insertion layer 1723, a free layer 1722, and a spin-orbit torque channel layer 1711.​​​

[0199] According to an embodiment of the present application, the magnetic tunnel junction 1730 can be formed on the lower electrode 1740 in a second structure sequentially stacking the buffer layer 1738, the seed layer 1737, the first exchange antiferromagnetic layer 1736, the separation layer 1735, the second exchange antiferromagnetic layer 1734, the bridge layer 1732 and the pinning layer 1731, the tunnel barrier layer 1724, the insertion layer 1723, the free layer 1722 and the spin-orbit torque channel layer 1711.

[0200] The tunnel barrier layer 1724, the insertion layer 1723, the free layer 1722 and the spin-orbit torque channel layer 1711 form the skyrmion channel layer 1720.

[0201] For example, the skyrmion channel layer 1720 can be formed in a third structure sequentially stacking the tunnel barrier layer 1724, the insertion layer 1723, the free layer 1722 and the spin-orbit torque channel layer 1721.

[0202] For example, the magnetic tunnel junction 1730 includes the skyrmion channel layer 1720.

[0203] The insertion layer 123 is formed of a material formed of any one of Ta, W, PT and Ti.

[0204] The spin-orbit torque channel layer 1711 is provided with a resistive vertical electrode 1710, and the resistive vertical electrode 1710 includes an electrode 1711 and a resistive layer 1712. The electrode 1711 can be referred to as an upper electrode.

[0205] For example, the resistive layer 1712 can be formed of HfO x The electrode 1711 can be formed of any one of Pt and Ru.

[0206] For example, the resistive vertical electrode 1710 can be any one of an ECM vertical electrode, a VCM vertical electrode and a vertical electrode combining ECM and VCM.

[0207] Figure 18 A second other structure of the skyrmion memory device of an embodiment of the present application is illustrated. The second other structure can be a structure different from the skyrmion memory device illustrated in Figure 1 and Figure 17 .

[0208] Referring to Figure 18 , the resistive vertical electrode of the skyrmion memory device 1800 of an embodiment of the present application is different from the position of the resistive vertical electrode of the skyrmion memory device 100 illustrated. Figure 1

[0209] ​The resistance change vertical electrode 1810 of the skyrmion storage device 1800 is provided on the tunnel barrier layer 1824 of the skyrmion channel layer 1820 and the magnetic tunnel junction 1830.

[0210] The skyrmion channel layer 1820 can be formed in a first structure in which a spin orbit torque channel layer 1821, a free layer 1822, an insertion layer 1823, and a tunnel barrier layer 1824 are sequentially stacked.

[0211] The magnetic tunnel junction 1830 is formed in a structure in which the spin orbit torque channel layer 1821, the free layer 1822, the insertion layer 1823, the tunnel barrier layer 1824, the pinned layer 1831, the bridge layer 1832, the first exchange antiferromagnetic layer 1834, the separation layer 1835, the second exchange antiferromagnetic layer 1836, and the upper electrode 1840 are sequentially stacked, and can further include a capping layer 1837.

[0212] That is, the magnetic tunnel junction 1830 includes the skyrmion channel layer 1820.

[0213] The first exchange antiferromagnetic layer 1834, the separation layer 1835, and the second exchange antiferromagnetic layer 1836 constitute a synthetic exchange antiferromagnetic layer 1833.

[0214] That is, the skyrmion storage device 1800 can form a new structure by changing the position of the resistance change vertical electrode 1810.

[0215] Accordingly, the present application relates to a skyrmion storage device and a crossbar circuit using the same, and can implement a skyrmion storage device and a crossbar circuit using the same in which a resistance change vertical electrode for generating a skyrmion, a skyrmion channel layer for moving the skyrmion, and a magnetic tunnel structure for sensing the skyrmion are formed to be linear with respect to a resistance change in the number of skyrmions.

[0216] The above-described embodiments have been described with reference to the accompanying drawings, but a person of ordinary skill in the art to which the present application pertains can derive various modifications and changes from the above-described description. For example, the described technology can be implemented by performing the described methods in different orders and / or combining or combining the described system, structure, device, circuit, and the like in a form different from the described method, or by achieving a proper result through the substitution or replacement of other structural elements or equivalents.

[0217] Accordingly, other examples, other embodiments, and equivalents of the claimed scope should also be included in the claimed scope.

Claims

1. A skyrmion storage device, comprising: a resistance change vertical electrode forming a skyrmion; a skyrmion channel layer moving the formed skyrmion; and a magnetic tunnel junction including the skyrmion channel layer and determining either one of a low resistance state and a high resistance state according to magnetization directions of a free layer and a pinned layer by sensing the moved skyrmion, the skyrmion channel layer including a spin orbit torque channel layer, a free layer, an insertion layer, and a tunnel barrier layer, a size and a number of the moved skyrmion being controlled based on a thickness of the insertion layer and a kind of a forming material, thereby controlling an area of the free layer. the magnetic tunnel junction sensing a multi-bit skyrmion in a case where the number of the skyrmions is plural, the area of the free layer being increased with the multi-bit skyrmion.

2. The skyrmion memory device of claim 1, wherein, a resistance level of the magnetic tunnel junction being gradually changed with the increase of the area of the free layer, thereby securing linearity of enhancement or suppression implemented on a plurality of levels.

3. The skyrmion memory device of claim 2, wherein, the resistance change vertical electrode being any one of an electrochemical metallization memory vertical electrode, a valence change memory vertical electrode, and a vertical electrode combined with an electrochemical metallization memory and a valence change memory.

4. The skyrmion memory device of claim 1, wherein, 5.The skyrmion storage device of claim 4, wherein the resistance change vertical electrode includes an electrode and a resistance change layer, the electrode is formed of any one of Al, TiN, Ti, Ag, Cu, CuTe, W, Pt, and Ru. The resistance change layer is formed of any one of SiO x , MgO, HfO x , AlO x , TiO x , TaO x , GeSe, GeS2, GeTe, ZnTe, the skyrmion channel layer is formed in a first structure in which the spin orbit torque channel layer, the free layer, the insertion layer, and the tunnel barrier layer are sequentially stacked.

6. The skyrmion memory device of claim 1, wherein, the skyrmion channel layer is formed in a second structure in which the spin orbit torque channel layer, an oxide seed layer, the insertion layer, a first free layer, a spacer layer, a second free layer, and the tunnel barrier layer are sequentially stacked.

7. The skyrmion memory device of claim 1, wherein, in a case where it is formed in the second structure, the skyrmion channel layer cancels a skyrmion Hall effect by causing the first free layer and the second free layer to move the formed skyrmion to an anti-ferromagnetic coupled skyrmion movement.

8. The skyrmion memory device of claim 7, wherein, the skyrmion channel layer is formed in a third structure in which the tunnel barrier layer, the insertion layer, the free layer, and the spin orbit torque channel layer are sequentially stacked.

9. The skyrmion memory device of claim 1, wherein, 10.The skyrmion storage device of claim 1, wherein the insertion layer is formed of any one of Ta, W, Pt, Mo, and Ti, a thickness of the insertion layer is inversely proportional to a size and a number of the skyrmion. the magnetic tunnel junction is formed in a structure in which the spin orbit torque channel layer, the free layer, the insertion layer, the tunnel barrier layer, the pinned layer, a bridge layer, a first exchange anti-ferromagnetic layer, a separation layer, a second exchange anti-ferromagnetic layer, and an upper electrode are sequentially stacked.

11. The skyrmion memory device of claim 1, wherein, ​ 12. A cross-point array circuit using a skyrmion storage device including a resistance change vertical electrode forming a skyrmion, a skyrmion channel layer moving the formed skyrmion, and a magnetic tunnel junction including the skyrmion channel layer and determining either one of a low resistance state and a high resistance state by sensing the moved skyrmion according to magnetization directions of a free layer and a pinned layer, the skyrmion channel layer including a spin orbit torque channel layer, the free layer, an insertion layer, and a tunnel barrier layer, a size and a number of the moved skyrmion being controlled based on a thickness and a kind of a formation material of the insertion layer, thereby controlling an area of the free layer, the cross-point array circuit characterized in that, the skyrmion storage device and a switching device constitute a bit cell, an array including a plurality of the bit cells arranged and a driving section applying a driving signal to the array.

13. The cross-point array circuit of claim 12, wherein, the bit cell has a two-terminal structure connected by the resistance change vertical electrode and a drain terminal of the switching device and an upper electrode of the magnetic tunnel junction and a bit line.

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