Modern global navigation satellite system receiver

Abstract

The invention relates to a modernized global navigation satellite system receiver. GNSS receivers and systems within such receivers use improvements to reduce memory usage while providing sufficient processing resources to directly receive, capture and track E5 band GNSS signals (in one embodiment, not attempting to receive L1 GNSS signals). Other aspects are also described.

Description

[0001] This application is a divisional application of invention patent application 202080071834.5 entitled "Modern Global Navigation Satellite System Receiver" filed on October 13, 2020. Background Technology

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 915,510, filed October 15, 2019, and U.S. Non-Provisional Patent Application No. 17 / 068,659, filed October 12, 2020, both of which are incorporated herein by reference.

[0003] This disclosure relates to the field of Global Navigation Satellite Systems (GNSS), and specifically, in one embodiment, to a GNSS receiver using modern L5 signals in the L5 band. Many GNSS systems are available, including the U.S. GPS (Global Positioning System), GLONASS, Galileo, BeiDou, and regional systems that are already in place or may be deployed in the future. The U.S. GPS system was initially available only in the L1 band. Currently, the U.S. GPS system includes GNSS signals in the L5 band, and the Galileo system includes modernized GNSS signals (such as E5A and E5B) in the L5 band centered at 1191.79 MHz. Modernized GNSS signals in the L5 band offer certain advantages over GNSS signals in the L1 band, some of which are discussed below. However, without prior acquisition of the L1 GNSS signal in the GNSS receiver, direct acquisition of the L5 band GNSS signal is considered too difficult. Therefore, conventional GNSS receivers employ a technique of first acquiring the L1 GNSS signal, and this acquisition provides information for acquiring the GNSS signal in the E5 band, such as timing information and Doppler estimation. Consequently, conventional GNSS receivers supporting GNSS L5 signals use RF front-ends that receive both L5 and L1 signals; this means that there are duplicate RF components in these GNSS receivers. Furthermore, conventional receivers must store and use pseudo-random noise (PRN) codes for both L1 and L5 GNSS signals. Summary of the Invention

[0004] The various aspects described herein provide improvements that allow GNSS receivers to directly receive, capture, process, and use L5-band GNSS signals with greater sensitivity and reliability than by capturing them in the narrow L1 band. However, in some embodiments, these improvements can be used with conventional receivers that receive and process L5-band GNSS signals as well as one or more additional GNSS bands (such as the L1 GPS band). These aspects can be implemented in various embodiments that may include a GNSS receiver or a portion thereof, or a data processing system (such as a smartphone) containing such a receiver or a portion thereof, and may include methods performed by such a device (e.g., a GNSS receiver, etc.), and may include a non-transitory machine-readable medium storing computer program instructions that, when executed by the data processing system, cause the data processing system to perform one or more of the methods described herein.

[0005] One aspect of this disclosure relates to the direct acquisition of L5-band GNSS signals. In other words, in this aspect, a GNSS receiver directly acquires L5-band GNSS signals without attempting to obtain time and frequency information from L1-band GNSS signals. The terms "direct acquisition" and "directly acquiring" are intended to mean that the GNSS receiver receives L5-band GNSS signals and acquires these L5-band GNSS signals to obtain time and frequency information derived from them without obtaining time and frequency information from L1-band GNSS signals. While cellular phone auxiliary data (such as time or phase locking for frequency as described in the previous Snaptrack patent) is available in the GNSS receiver, L1-band GNSS signals are not acquired and are not used by GNSS receivers that directly acquire L5-band GNSS signals. Therefore, when a GNSS receiver directly acquires L5-band GNSS signals, it acquires the L5-band GNSS signals to obtain time and frequency information from them without the advantages of previously acquiring L1-band GNSS signals or obtaining time or frequency information from L1-band GNSS signals.

[0006] Another aspect of this disclosure relates to sharing cache memory (or other memory) between a group of one or more application processors (APs) and a GNSS processing system. This aspect provides a solution to the often excessive memory requirements for capturing L5 GNSS signals, especially for methods using Discrete Fourier Transform (DFT) calculations. One or more application processors (or other processors) and the GNSS processing system can be implemented together in a single monolithic integrated circuit (IC) on a single semiconductor substrate, which may be referred to as a system-on-a-chip (SOC), and the cache memory may also be on the same IC. In this aspect, the application processor (or other processor) shares the cache memory (or other memory) of the application processor (or other processor) with at least the capture engine (AE) of the GNSS processing system. In one embodiment, this sharing may be limited to those cases where the capture engine initially captures GNSS signals (e.g., startup with or without auxiliary data from a cellular telephone network). In response to a request for location data (such as latitude and longitude) from an application (such as a map application or other applications), a portion of cache memory (which may be an L1 (Level 1) or L2 (Level 2) SRAM cache of one or more application processors, or other memory used by other processing systems) may be allocated to the capture engine for the capture phase. Depending on the location request, this allocation may be prioritized or not prioritized by the system's operating system (OS) or firmware on the IC; if the location request comes from a low-priority background daemon application, the allocation may be temporarily deferred until sufficient free memory is available in the cache. On the other hand, if the location request comes from a map application acting as a foreground application (and therefore the device's display shows the map application's user interface to the user), the allocation is prioritized. In one embodiment, the portion to be allocated can be identified by determining which pages in the cache memory are not dirty and are stored in backup storage such as main DRAM or better, non-volatile memory such as flash memory. Such pages (e.g., not dirty and stored in backup storage) can be immediately refreshed / deleted from the cache (or other storage) and then allocated to the AE for storing, for example, one or more of the following: hypothesis data or generated GNSS PRN codes and / or their codespectrum derived from the DFT.

[0007] According to its shared aspect method, the following operations implemented in a GNSS receiver may be included: receiving from one or more application processors on an integrated circuit a request to generate location data using a GNSS processing system on the integrated circuit, the GNSS processing system including an acquisition engine (AE) configured to acquire a plurality of GNSS signals, each of which is transmitted from one of a GNSS space carrier (SV) constellation; identifying a portion of cache memory (or other memory) on the integrated circuit and, in response to the request to generate location data, allocating that portion for use by the acquisition engine, while the one or more application processors (or other processors (one or more)) are allocated the remaining portion of the cache memory (or other memory), the allocation being performed by an operating system executing on the one or more application processors or by firmware on the IC; and storing data related to GNSS signal acquisition processing in the allocated portion by the acquisition engine or the one or more application processors. One embodiment of the method may use static random access memory (SRAM) as a cache memory (or other memory) on an integrated circuit, and the capture engine may include ASIC (Application-Specific Integrated Circuit) hardware logic for performing Fast Fourier Transform (FFT) operations, such as Discrete Fourier Transform (DFT) operations using time decimation methods and also frequency decimation methods. In one embodiment, the method may further include an operation to deallocate an allocated portion after the GNSS processing system begins tracking GNSS signals already captured from at least three (3) GNSS SVs, the deallocation occurring in response to the capture of GNSS signals from at least three GNSS SVs prior to the tracking phase. In one embodiment, the GNSS processing system includes dedicated memory separate from the cache memory (or other memory) and dedicated to use by the GNSS processing system. In one embodiment, a memory controller coupled to the cache memory (or other memory) may include a first port controller controlling access to the allocated portion of the capture engine and a second port controller controlling access to the remaining portion of the cache memory (or other memory). In one embodiment, the capture engine performs capture of a GNSS signal from a GNSS SV, and the capture includes determining the main code phase and frequency of the received GNSS signal containing a pseudo-random noise (PRN) code to achieve tracking of the GNSS signal to generate a pseudorange to the GNSS SV (as a result of the tracking). In one embodiment of the method, the allocated portion will store one or more of the following: (1) the pseudo-random noise code of the GNSS SV or (2) an assumption about the identifier of the potentially captured GNSS signal and an assumption about its frequency.In one embodiment of this method, one or more application processors may generate GNSS PRN codes and / or their DFT-derived code spectra for at least the GNSS SVs in the system's field of view before the start of the acquisition phase. In one implementation of this embodiment, these PRN codes and / or their DFT-derived code spectra may be generated and used immediately without storing the codes, or alternatively, these PRN codes and / or their DFT-derived code spectra may be temporarily generated and stored when used during the acquisition and tracking phases. In an alternative embodiment, one or more application processors may generate GNSS PRN codes (or their code spectra, or both) and then copy these codes to a cache memory (or other memory) before the start of the acquisition phase or in response to a location request. In one embodiment, to save memory, the system may generate GNSS PRN codes and / or their DFT-derived code spectra only for healthy GNSS SVs in the field of view.

[0008] In one embodiment, a system according to this shared aspect may include: a group of one or more application processors configured to execute an operating system (OS) and one or more applications, the group of one or more application processors being implemented in an integrated circuit; a group of one or more buses coupled to the group of one or more application processors, the one or more buses being on the integrated circuit; a cache memory (or other memory) on the integrated circuit and coupled to the group of one or more buses and the group of one or more application processors for storing data for use by the operating system or for use by one or more applications and other memory (such as high-bandwidth modem memory or other memory that may also be on the IC and coupled to the one or more buses and used by one or more processors not in the group of one or more application processors). The system comprises: a GNSS processing system implemented on the integrated circuit, including an acquisition engine (AE) and a tracking engine (TE), the GNSS processing system being coupled to a cache memory (or other memory) via one or more buses; and a memory controller coupled to the cache memory (or other memory) and to the one or more application processors and to the GNSS processing system, the memory controller being used to allocate a portion of the cache memory (or other memory) for use by the AE in response to one or more instructions from the operating system (or other software component), thereby allowing GNSS signals to be acquired. In one embodiment, the cache memory may include static random access memory (SRAM), and the AE may include ASIC hardware logic for performing discrete Fourier transform operations (using both time-decimation and frequency-decimation methods). In one embodiment, the memory controller may include a first port controller for controlling reads and writes to a portion of the AE, and a second port controller for controlling reads and writes to the remaining portion of the cache memory (or other memory). In one embodiment, after the GNSS processing system begins tracking GNSS signals already captured from at least three GNSS SVs (but before location data such as latitude and longitude are determined), the memory controller may deallocate that portion of the cache memory (or other memory) used by the AE.

[0009] Another aspect that can help reduce memory usage in L5-band GNSS receivers is the on-demand generation of GNSS PRN codes and / or their DFT-derived code spectra, which are used to correlate with the received GNSS signals during the acquisition phase. In one embodiment, this on-demand generation can produce GNSS PRN codes and / or their DFT-derived code spectra during both the acquisition and tracking phases. For example, in one embodiment, these codes can be generated but not stored during both the acquisition and tracking phases; in an alternative embodiment, the codes can be generated and stored both instantaneously and on demand during both the acquisition and tracking phases, and are no longer stored once the location is determined. In one embodiment, the codes and code spectra are generated before each correlation operation, once every 1 ms for each channel, and then the memory is overwritten for use on the next channel. There is no storage of codes or spectra; only one memory is temporarily reused. For example, in the case of 24 signals being acquired, the codes for these 24 signals are regenerated 24 times every 1 ms. It is temporarily stored in memory for the first stage of the DFT performed during the frequency domain correlation algorithm.

[0010] Another aspect of this disclosure relates to an acquisition correlator using array processing. This array processing architecture initially arranges digitized GNSS sample data in rows, for example, an array, where these rows are time-ordered in baseband sample memory. DFT operations performed on the data can produce an output that can then be processed via DFT inverse operations without rotating, reformatting, rearranging, or transposing the data in the array prior to the DFT inverse operation. The data can be arranged such that each of a set of multiple ALUs processes a row or column of the array, thereby decomposing the processing into discrete fragments that can be processed by each of the DFT ALUs, such that each row or column can be computed by a single DFT ALU in atomic processing operations within one or several processing clock cycles. In one embodiment, the single DFT ALU can perform multiple DFT operations once instructed to do so. The baseband sample memory can be implemented in a circular buffer containing an ordered array of data. In one embodiment, the processing operation can be an in-place DFT computation, in which rows (or columns) of input data are retrieved from memory and processed (using the DFT), and the output from this processing is then stored back in the same memory location as input data (thus overwriting the input data in those memory locations).

[0011] In one embodiment where an array processing architecture can be used, the system for processing GNSS signals may include the following components: a radio frequency analog-to-digital converter (ADC) for generating a digital representation of the received GNSS signals; and a baseband sample memory for storing the digital representation of the received GNSS signals as digitized GNSS sample data in N2 rows (e.g., 1024 rows in one embodiment or 512 rows in another embodiment) and N1 columns (e.g., 20 columns in one embodiment or 40 columns in another embodiment), the array being stored in row-order in the baseband sample memory, and the row order containing digitized GNSS sample data received within a time period (including a first time period and a second time period), such that the first row in the row order contains digitized GNSS sample data received during the first time period, and the second row after the first row in the row order contains digitized GNSS sample data received during the second time period after the first time period, wherein the baseband sample memory is coupled to the RF... The system includes an ADC; and a set of arithmetic logic units (ALUs) configured to perform Discrete Fourier Transform (DFT) operations. This set of ALUs is coupled to a baseband sample memory and configured to execute N1 DFTs concurrently and in parallel over time, each of the N1 DFTs containing N2 points from the DFT, and the outputs of the N1 DFTs are stored in a partial sample array. The set of ALUs is then configured to execute N2 DFTs, each of the N2 DFTs containing N1 points from the partial sample array, providing outputs stored in a DFT result array arranged in column order. In one embodiment, the baseband sample memory is configured as a circular memory buffer to store digitized GNSS sample data. In one embodiment, the N1 DFTs are performed on different data using the same operations and the same program control instructions for the set of ALUs. In one embodiment, the N2 DFTs are executed sequentially over time. In one embodiment, the circular sample memory buffer stores more than one frame of pseudo-random GNSS signal (more than one millisecond). In one embodiment, N1 DFTs and N2 DFTs use a time decimation method, and N1 is one of the following integer values: 5, 10, 20, or 40. In another embodiment, N2 is set such that N1 × N2 = 20480 (or N1 × N2 is greater than 20480). In one embodiment, the change from row order to column order avoids reordering or transposition algorithms, and this change is produced by a combination of N1 DFTs followed by N2 DFTs configured to produce this change. In one embodiment, the GNSS code generator is configured to generate GNSS code spectra, and the set of ALUs performs a set of DFTs on the GNSS PRN codes to provide code spectrum result data, which is stored in code spectrum memory in column order.In one embodiment, the baseband sample spectrum is stored in a special / dedicated memory and recalculated every 1 ms, while the code spectrum is stored in a general variable memory and overwritten every ms for each channel. In one embodiment, the group of ALUs can be configured to multiply the code spectrum result data by the sample output stored in the DFT result array to produce a product array. In one embodiment, the group of ALUs can be configured to perform an inverse DFT on the product array using a frequency decimation method. In one embodiment, the inverse DFT can include: (1) in a first stage, N2 DFTs with conjugate inputs, each of the N2 DFTs containing N1 points, and (2) in a second stage following the first stage, N1 DFTs, each of the N1 DFTs containing N2 points. In one embodiment, the baseband sample memory can be a dual-port memory, which allows different processors or processes to access different portions of the baseband sample memory simultaneously. In one embodiment, when needed during the acquisition phase, the GNSS code generator can repeatedly generate pseudo-random noise codes every millisecond for each GNSS SV in the field of view, and the generated pseudo-random noise codes (and / or their code spectra from the DFT) are not stored after use, and the generated pseudo-random noise codes can be used to generate GNSS code spectra. In one embodiment, the GNSS code spectra are aligned in place in memory for both frequency and phase to match the code phase and frequency shift assumptions associated with the received GNSS signal. In one embodiment, this alignment can be performed by CORDIC hardware.

[0012] One or more embodiments of the GNSS receiver described herein can perform one of the following methods using DFT sequences. In one embodiment, a method may include the following operations:

[0013] Receive GNSS signals;

[0014] The received GNSS signal is digitized and output from an analog-to-digital converter (ADC) to provide GNSS sample data, the output including at least one of the following: (1) GNSS sideband A sample data of the received GNSS signal and (2) GNSS sideband B sample data of the received GNSS signal.

[0015] Calculate at least one of the following: (1) a first set of DFTs of GNSS sideband A sample data to provide a first set of results, and (2) a second set of DFTs of GNSS sideband B sample data to provide a second set of results;

[0016] Calculate at least one of the following: (1) the third DFT of the GNSS sideband A main PRN code data, which is adjusted for code Doppler and carrier Doppler before the third DFT, which includes at least one of the two components in GNSS sideband A, the third DFT providing the third result; and (2) the fourth DFT of the GNSS sideband B main PRN code data, which is adjusted for code Doppler and carrier Doppler before the fourth DFT, which includes at least one of the two components in GNSS sideband B, the fourth DFT providing the fourth result;

[0017] Calculate at least one of the following: (1) compute the first group correlation using the DFT of the complex conjugate product of the first and third group results to provide the fifth group result; and (2) compute the second group correlation using the DFT of the complex conjugate product of the second and fourth group results to provide the sixth group result; and

[0018] Integrate at least one of the following: (1) the integration of the fifth set of results with at least one prior sum for GNSS sideband A, (2) the integration of the sixth set of results with at least one prior sum for GNSS sideband B, wherein such integration includes at least one of the following: (1) storing at least one new sum for the GNSS sideband A component in a single hypothetical memory, and (2) storing at least one new sum for the GNSS sideband B component in a single hypothetical memory.

[0019] One implementation of this method can be summarized as ("Case 1"):

[0020] 1. Calculate the FFT of sideband A sample;

[0021] 2. Calculate the FFT of the sideband B sample;

[0022] 3. Calculate the FFT of at least one sideband A-component primary code that has been adjusted for code Doppler and carrier Doppler (e.g., a series of potential Dopplers to be searched);

[0023] 4. Calculate the FFT of at least one sideband B component main code that has been adjusted for code Doppler and carrier Doppler;

[0024] 5. Use the inverse FFT (IFFT) of the product of (a) the FFT calculated from 1 (FFT of sideband A sample) and (b) the FFT calculated from 3 (FFT of sideband A component) to calculate the correlation;

[0025] 6. Use the IFFT of the product of (a) the FFT calculated from 2 and (b) the FFT calculated from 4 to calculate the correlation.

[0026] This implementation offers several advantages. For example, it can perform very few FFTs on the received sideband samples and can reduce or eliminate the large amount of data transfer typically required to move pre-computed GNSS sample spectra from memory (e.g., DRAM or non-volatile memory) to the frequency domain correlator array processor. The frequency domain correlator engine can be highly efficient with low or small memory footprints by reusing it at a reasonable clock speed. For example, the frequency domain correlator engine can compute the master code and its spectrum in-situ within the pipelined architecture described herein (e.g., operations 3 and 4 in “Case 1” summarized above). Furthermore, applying code Doppler compensation and carrier Doppler compensation to the in-situ generated code (e.g., operations 3 and 4 in “Case 1” summarized above) reduces the input (received) sample FFT and also improves code Doppler accuracy.

[0027] There are various combinations and arrangements of this implementation scheme for capturing, for example, L5 GNSS signals. However, these combinations and arrangements may be less efficient than “Case 1” above because they require a faster processing clock and / or more memory (compared to “Case 1”), or because they have lower capture sensitivity or require a longer capture time for a given signal strength. The use of the six (6) operations in “Case 1” can be retained, but with an arrangement based on one or more of the following: (1) where and how code and carrier compensation are performed, for example: (a) carrier Doppler compensation can be “wipe-off” of the received GNSS sample or up-multiply of the locally generated (or pre-computed) PRN code sample; or (b) code Doppler adjustment can be applied to the received GNSS sample (“input sample”) or the locally generated (or pre-computed) PRN code sample by complex multiplication of the code spectrum (e.g., see Appendix 3) or by compensating for the post-correlation result and its integration in memory (see Appendix 1); (2) whether the code spectrum is generated locally in place in the capture engine (AE) or pre-computed and loaded into the AE based on the GNSS SV in the field of view; or (3) alternative hardware architectures such as parallel FFT kernels or higher radix kernels (instead of sequential time-decimation FFT and frequency-decimation FFT) to reduce the number of processing clocks per FFT. The following six arrangements are examples of possible layouts.

[0028] Case 2 (Switch code and carrier Doppler to samples: More input sample FFT required)

[0029] 1. FFT for the sideband A with code and carrier Doppler adjustment

[0030] 2. FFT for the sideband B with code and carrier Doppler adjustment

[0031] 3. FFT of at least one A component primary key

[0032] 4. FFT of at least one B-component primary key

[0033] 5. The correlation is performed using the IFFT of the product of 1 and 3, and its integration is stored in a single hypothesis memory.

[0034] 6. The correlation is performed using the IFFT of the product of 2 and 4, and its integration is stored in a single hypothesis memory.

[0035] Case 2B (same as case 2 where the code spectrum is pre-computed: requires more memory and data bandwidth)

[0036] 1. FFT for the sideband A with code and carrier Doppler adjustment

[0037] 2. FFT for the sideband B with code and carrier Doppler adjustment

[0038] 3. Obtain the pre-computed FFT of at least one A-component primary key.

[0039] 4. Obtain the pre-computed FFT of at least one B-component primary key.

[0040] 5. The correlation is performed using the IFFT of the product of 1 and 3, and the integral is stored in a single hypothesis memory.

[0041] 6. Using the correlation of the IFFT of the product of 2 and 4, the integral is stored in a single hypothesis memory.

[0042] Case 3 (same as case 2 with correlated code Doppler compensation)

[0043] 1. FFT for sideband A with carrier Doppler adjustment

[0044] 2. FFT for sideband B with carrier Doppler adjustment

[0045] 3. FFT of at least one A component primary key

[0046] 4. FFT of at least one B-component primary key

[0047] 5. The correlation is performed using the IFFT of the 1-3 product adjusted for code Doppler, and its integration is stored in a single hypothesis memory.

[0048] 6. The correlation is performed using the IFFT of the 2- and 4-products adjusted for code Doppler, and the integral is stored in a single hypothesis memory.

[0049] Case 3B (same as 3, but with pre-computed code spectrum)

[0050] 1. FFT for sideband A with carrier Doppler adjustment

[0051] 2. FFT for sideband B with carrier Doppler adjustment

[0052] 3. Obtain the pre-computed FFT of at least one A-component primary key.

[0053] 4. Obtain the pre-computed FFT of at least one B-component primary key.

[0054] 5. The correlation is performed using the IFFT of the 1- and 3-products adjusted for code Doppler, and integrated into a single hypothesis memory.

[0055] 6. The correlation is performed using the IFFT of the 2- and 4-products adjusted for code Doppler, and integrated into a single hypothesis memory.

[0056] The following cases use the method described in Appendix 1, which computes the FFT of the input sample sideband samples every millisecond at multiple frequencies such as 0, 200, 400, 600, and 800 Hz, and then approximates the sample sideband A or B spectrum by selecting the closest sub-kHz FFT and then shifting it by + / - N samples to obtain ultra-kHz compensation. For example, 2450 Hz uses a 400 Hz FFT and shifts this FFT by +2 samples to obtain a combined 400 Hz + 2 kHz Doppler compensation.

[0057] Case 4 (similar to the method described in Appendix 1)

[0058] 1. Select at least one FFT from a set of sideband A-sample FFTs adjusted for carrier Doppler at a frequency group covering a k-Hz range, wherein the FFT is shifted by N samples to produce an approximate carrier Doppler.

[0059] 2. Select at least one FFT from a set of sideband B-sample FFTs adjusted for carrier Doppler at a frequency group covering a frequency range of one k-Hz, and shift the FFT by N samples to produce an approximate carrier Doppler.

[0060] 3. FFT for at least one A-component primary code with code Doppler adjustment

[0061] 4. FFT of at least one B-component primary code with code Doppler adjustment

[0062] 5. The correlation is performed using the IFFT of the product of 1 and 3, and its integration is stored in a single hypothesis memory.

[0063] 6. The correlation is performed using the IFFT of the product of 2 and 4, and its integration is stored in a single hypothesis memory.

[0064] Case 4A (similar to method 4, but with pre-computed code spectrum and correlated code Doppler)

[0065] 1. Select at least one FFT from a set of sideband A-sample FFTs adjusted for carrier Doppler at a frequency group covering a frequency range of one k-Hz, and shift the FFT by N samples to produce an approximate carrier Doppler.

[0066] 2. Select at least one FFT from a set of sideband B-sample FFTs adjusted for carrier Doppler at a frequency group covering a frequency range of one k-Hz, and shift the FFT by N samples to produce an approximate carrier Doppler.

[0067] 3. Obtain the pre-computed FFT of at least one A-component primary key.

[0068] 4. Obtain the pre-computed FFT of at least one B-component primary key.

[0069] 5. The correlation is performed using the IFFT of the 1- and 3-products adjusted for code Doppler, and integrated into a single hypothesis memory.

[0070] 6. The correlation is performed using the IFFT of the 2- and 4-products adjusted for code Doppler, and integrated into a single hypothesis memory.

[0071] In some embodiments described herein, adjustments or compensations are made for one or both code Doppler and carrier Doppler. As described herein, these adjustments can be performed independently and at different stages. Code Doppler adjustment is an adjustment of locally generated (or pre-computed) codes or received GNSS sample codes to compensate for Doppler effects on codes such as master GNSS PRN codes; for example, during the search or acquisition phase, various possible code Doppler adjustments can be made to locally generated codes or received GNSS sample codes to search for and acquire GNSS signals affected by Doppler effects. Carrier Doppler adjustment is an adjustment made to compensate for Doppler effects on the carrier frequency of the signal. Carrier Doppler is the observed offset relative to the transmission frequency caused by the relative motion between the satellite and the receiver, and the offset from the nominal values ​​of the satellite oscillator and the receiver oscillator. Code Doppler is the shift in the phase of the received code over time, which is coherent with carrier Doppler. In L5, there are 115 carrier cycles per chip. Therefore, code Doppler, measured in chips per second, is carrier Doppler divided by 115. Thus, for a carrier Doppler of 4321 Hz, the received code phase will shift by 37.57 chips per second. To receive weak signals, it is necessary to correlate the received signal with copies of multiple primary code frames from the receiver. This requires that each incoming code phase assumption be shifted according to the carrier Doppler assumption. This shift is called code Doppler.

[0072] Another aspect of this disclosure relates to the use of primary and / or secondary codes in an E5 GNSS signal from a GNSS SV to derive code phase data or time data based on those GNSS signals, and then using that information to estimate the code phase of other GNSS signals from other GNSS SVs to capture the code phase of other GNSS signals from other GNSS SVs. In this regard, a GNSS receiver can employ GNSS PRN code epochs shorter than 1 ms and can be offset from a 1 ms GNSS PRN code epoch. The GNSS receiver can use this processing to attempt coherent integration before capturing the code phase of other GNSS signals. For example, the GNSS processing system in the GNSS receiver can retrieve a complete 1 ms digitized GNSS sample data from a circular memory buffer every 0.25 ms and perform a set of DFTs and inverse DFTs on the retrieved data to coherently integrate for each frequency bin. This VFFDC process is then repeated in the next processing epoch, each processing epoch being 0.25 ms or another fraction of a code epoch, in one embodiment of which the code epoch length is 1 ms. This allows the GNSS receiver to reuse 1 ms of data from the circular buffer across multiple processing epochs to attempt coherent integration of other GNSS signals using information obtained through previously capturing the primary or secondary code phase of at least one GNSS signal. In this example, the satellite codes are searched to align with the approximate time segment in which they are expected to be received, thus reducing sub-millisecond coherent cancellation losses due to phase reversal associated with the auxiliary code phase. In another embodiment, the receiver clock may be sufficiently accurate (with an error much less than 1 ms), and the prior position may be well known to allow processing of all GNSS signals in this precise time acquisition mode.

[0073] Another aspect of this disclosure relates to using only a subset (selected component) of two or four components of a GNSS signal during coarse time acquisition to acquire that subset first (such as only one of the four components), and then acquire the remaining components. In one embodiment, this selected component is chosen based on the lowest probability of signal variation caused by symbol or phase reversal due to the coding scheme used in that selected component. In the case of Galileo's E5 GNSS signal, the E5BI component has the lowest probability of signal variation due to symbol or phase reversal, and can therefore be used as the selected component to perform coarse or precise time acquisition before attempting to acquire and / or track the remaining components in the Galileo GNSS signal. This use of only a subset of components can initially be done at the start of acquisition (such as coarse time acquisition), or as a fallback operation mode after conventional acquisition has failed, or as a method for faster acquisition of stronger satellites, because the correlation number is reduced, allowing a portion of the GNSS acquisition engine to search a large frequency space with many SVs more quickly and at lower power compared to when more GNSS signal components are acquired.

[0074] Another aspect of this disclosure relates to mitigating the effects of interference from certain known strong interference sources, such as aeronautical radio navigation (ARN) signals, which are typically present around, for example, airports or military bases. ARN signals, such as those from tactical air navigation systems (DME / TACAN), are typically strong impulse signals with noise levels well above their noise floor, while GNSS signals are typically below their noise floor. Furthermore, ARN signals can cause interference to GNSS in the L5 band. In one embodiment, this interference can be mitigated by detecting signal sources above their noise floor (e.g., detecting signals above a predetermined threshold, which may be several dB above the noise floor) and then removing the signal in the frequency domain. The interfering signal can be identified during the signal acquisition phase using the DFT array processing described herein, and then the interfering signal can be processed by an FIR (finite impulse response) filter to remove the interfering signal before time-domain correlation processing. Alternatively, frequencies with strong interference can be observed in the input data spectrum, since the input sample spectrum is processed once per millisecond and at each upper and lower sideband. Another aspect of this disclosure relates to mitigating the effects of interference from certain known sources by reducing the processing bandwidth of a radio receiver, focusing on one of the two sidebands E5a or E5b depending on the location of the interference source. Once the approximate location of the interference frequency is determined using DFT array processing detection or other methods, various analog and mixed-signal techniques can be used to reduce the effects of the interference before quantization. In one case, radio filtering can reduce the effective radio bandwidth from 52 MHz to 26 MHz or less. While this may result in a small performance penalty, it allows the receiver to operate with a greater interference margin. In another case, in Figure 4D, 4F During the IF bandpass filtering of the 4J radio architecture, a configurable notch can be placed at the effective frequency location. Furthermore, in Figure 4B , 4D During the low-pass filtering period of the architecture shown in Figure 4F, the notch filter can also be placed at the effective frequency. In yet another case, it can be modified... Figure 4J The IF frequency and / or sampling frequency of the radio architecture improve the immunity of frequency planning to aliasing interference.

[0075] Another aspect of this disclosure relates to a method for reducing memory usage by computing but not storing the outputs from certain DFTs. This method can reduce the size of the integration or hypothesis memory by eliminating the storage of selected outputs from the DFT computation. In one embodiment, the outputs are evaluated to determine whether to save them. This can be employed when the DFT method is used to perform correlation. In this case, the DFT produces correlation results for all code hypotheses within one millisecond. If the uncertainty of the full range of epoch positions is much less than one millisecond, only integration and storage of a portion around the estimated positions are required.

[0076] The aspects and embodiments described herein may include a non-transitory machine-readable medium storing executable computer program instructions that, when executed by one or more data processing systems, cause the one or more data processing systems to perform the methods described herein. The instructions may be stored in non-volatile memory such as flash memory or volatile dynamic random access memory or other forms of memory.

[0077] The above overview does not include an exhaustive list of all embodiments in this disclosure. All systems and methods can be practiced from all suitable combinations of the aspects and embodiments outlined above, as well as those disclosed in the detailed description below. Attached Figure Description

[0078] The patent or application documents contain at least one color drawing. Copies of the patent or patent application publication and the color drawing will be provided by the Patent Office upon request, at the cost of which payment is required.

[0079] This disclosure is illustrated by way of example rather than limitation in the accompanying drawings, wherein similar reference numerals indicate similar elements.

[0080] Figure 1 is a block diagram illustrating an example of a data processing system including a GNSS processor and one or more application processors.

[0081] Figure 2 This is a block diagram illustrating an example embodiment including a GNSS processing system and one or more application processors and a cache memory.

[0082] Figure 3 This is a flowchart illustrating a method for sharing a cache memory between one or more application processors and a GNSS processor according to one embodiment.

[0083] Figure 4 An example of the front end of a GNSS receiver that digitizes received GNSS signals according to one embodiment is shown.

[0084] Figure 4A An example of a convention or nomenclature used to describe the radio section of a GNSS receiver is shown.

[0085] Figure 4B An example of a conventional IQ receiver architecture that can be used in a GNSS receiver is shown.

[0086] Figure 4C It shows Figure 4B An example of frequency planning for the receiver architecture is shown.

[0087] Figure 4D An example of a GNSS receiver according to one embodiment is shown.

[0088] Figure 4E It shows Figure 4D An example of frequency planning for the receiver architecture shown.

[0089] Figure 4F The diagram shows... Figure 4D The variant of the GNSS receiver shown.

[0090] Figure 4G It shows Figure 4F An example of frequency planning for the receiver architecture shown.

[0091] Figure 4H Examples of subsampling arrangements that can be used in one or more embodiments of the invention described herein are shown.

[0092] Figure 4I It shows that it can be used Figure 4H The example shown is an example of frequency planning in a secondary sampling architecture.

[0093] Figure 4J It shows that it can be used Figure 4H An example of the architecture of a GNSS receiver with different layout aspects.

[0094] Figure 4K It shows Figure 4J An example of frequency planning for the receiver architecture shown.

[0095] Figure 4L An example of an embodiment of a GSSS receiver configured to fold the sidebands of a GNSS signal onto each other is shown.

[0096] Figure 4M Another example of an embodiment of a GSSS receiver configured to fold the sidebands of a GNSS signal onto each other is shown.

[0097] Figure 4N An example of another embodiment of a GSSS receiver configured to fold the sidebands of GNSS signals onto each other is shown; Figure 4O The spectrum of the Galileo E5 signal is shown, and Figure 4P The spectrum of the Galileo E5B signal is shown.

[0098] Figure 5A and 5B An example of a method using array processing leveraging DFT is shown according to one embodiment.

[0099] Figure 6 This is a block diagram illustrating a frequency domain correlator architecture using array processing according to one embodiment.

[0100] Figure 7 An example of a processing component for performing array processing according to one embodiment is shown in block diagram form.

[0101] Figure 8 An example of an additional processing component for performing array processing according to one embodiment is shown in block diagram form.

[0102] Figure 9A , 9B Examples of processing components, 9C and 9D, are shown and can be used to generate PRN code spectra for use in... Figure 6 , 7 The array processing architecture shown in Figure 8.

[0103] Figure 10 An example of a component that can be used in one embodiment of a GNSS receiver is shown.

[0104] Figure 11 This is a flowchart illustrating a method according to one embodiment.

[0105] Figure 12 An example of a GNSS receiver using only the L5 WB band is shown in block diagram form.

[0106] Figure 13 An example of an embodiment is shown in which a selected signal from a set of GNSS signal components is used to initially capture a GNSS signal in certain situations.

[0107] Figure 14A An example of an embodiment of the front-end processing flow in a GNSS receiver is shown.

[0108] Figure 14B A timing diagram is shown for an embodiment using a series of captured GNSS signals stored in a buffer and then processed to accumulate the code phase hypothesis.

[0109] Figure 14C A coarse time capture processing timeline is shown according to one embodiment.

[0110] Figure 14D A timeline of precise time capture processing according to one embodiment is shown.

[0111] Figure 14E and 14F An example of an FFT processor architecture according to one embodiment is shown.

[0112] Figure 14G This is a flowchart illustrating methods that can be used in frequency domain correlators (especially correlators using array processors).

[0113] Figure 14H Another example of an FFT processor architecture according to one embodiment is shown.

[0114] Figure 14I This is a flowchart illustrating methods that can be used in frequency domain correlators (especially correlators using array processors).

[0115] Figure 14J This is a flowchart illustrating methods that can be used in frequency domain correlators (especially correlators using array processors).

[0116] Figure 14K This is a block diagram of a system-on-a-chip (SOC) including a GNSS receiver and one or more application processors according to one embodiment.

[0117] Figure 14L This is a flowchart illustrating a method that can be used for frequency domain correlators (especially correlators using array processors) during coarse time capture mode.

[0118] Figure 14M This is a flowchart illustrating a method that can be used for frequency domain correlators (especially correlators using array processors) during precise time capture mode.

[0119] Figure 14N An example of the arrangement of a hypothetical memory for incoherent integration in a coarse time mode during code phase acquisition of a GNSS signal is shown.

[0120] Figure 14O An example of the arrangement of a hypothetical memory for coherent integration in a precise time mode (when the time is known to be within, for example, 0.5 ms) during code phase acquisition of a GNSS signal is shown.

[0121] Figure 14P This is a flowchart illustrating a method for configuring a hypothetical memory according to one embodiment.

[0122] Figure 15A This is a flowchart illustrating a method for mitigating interference (such as ARN interference) according to one embodiment.

[0123] Figure 15B This is a flowchart illustrating another method for mitigating interference (such as ARN interference) according to one embodiment.

[0124] Figure 16A A processing flow for capturing GNSS signals using rotation or interpolation with DFT according to one embodiment is shown.

[0125] Figure 16B A processing flow for capturing GNSS signals using rotation or interpolation in conjunction with DFT, according to another embodiment, is shown.

[0126] Figure 16C A processing flow for capturing GNSS signals using rotation or interpolation in conjunction with DFT, according to another embodiment, is shown.

[0127] Figure 17 An example of a method to reduce power consumption is shown, which involves capturing a set of GNSS signal components during the capture phase and then using only a subset of these captured components for tracking. Detailed Implementation

[0128] Various embodiments and aspects will be described with reference to the details discussed below, and the accompanying drawings will illustrate various embodiments. The following description and drawings are illustrative and should not be construed as limiting. Numerous specific details are described to provide a thorough understanding of various embodiments. However, in some cases, well-known or conventional details have not been described to provide a concise discussion of the embodiments.

[0129] References to "one embodiment" or "embodiment" in this specification mean that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment. The appearance of the phrase "in one embodiment" in various places in this specification does not necessarily refer to the same embodiment. The processes depicted in the following figures are performed by processing logic including hardware (e.g., circuitry, dedicated logic, etc.), software, or a combination of both. Although these processes are described below in some order, it should be understood that some of the described operations may be performed in a different order. Furthermore, some operations may be performed in parallel rather than sequentially.

[0130] One aspect of the embodiments described herein relates to the sharing of cache memory between one or more application processors and a GNSS processing system. Before describing these shared embodiments, a description of existing architectures in the prior art will be provided with reference to FIG1. ​​FIG1 illustrates a system 10 including one or more application processors 12 and a GNSS processor 20 coupled via a bus 14, which is also coupled to system main memory as dynamic random access memory (DRAM) 24. System 10 includes one or more input / output (I / O) devices 26, such as, for example, one or more touchscreens, speakers, microphones, and one or more sensors such as cameras, face detection sensors, etc. System 10 also includes a cellular phone modem and processor 16, which may include its own cache memory, which may be SRAM 16A. The cellular phone modem and processor 16 are coupled to a cellular phone RF component 17 to receive cellular phone signals via an antenna 18. The GNSS processor 20 is configured to receive and process GNSS signals in both the L1 and L5 frequency bands. Furthermore, the GNSS radio frequency (RF) component 21 is configured to receive GNSS signals in both the L1 and L5 frequency bands via antennas 22A and 22B, and the GNSS RF component 21 includes one or more RF mixers and an RF-to-IF downconverter and includes an RF local oscillator. These GNSS signals are processed by a GNSS processor 20, which includes its own dedicated processor memory as part of the GNSS processor 20. The GNSS processor does not use or shares a cache memory 12A, which is used by one or more application processors 12 using techniques known in the art to utilize the cache memory. The GNSS processor receives and processes GNSS signals and provides location outputs, such as latitude and longitude outputs, to one or more application processors 12 via bus 14. The GNSS processor receives and processes GNSS signals without utilizing the cache memory 12A and requires two separate GNSS antennas 22A and 22B and two separate GNSS RF paths originating from the two GNSS antennas 22A and 22B.

[0131] Figure 2 An example of a system in which the cache memory is shared between one or more application processors and a GNSS processing system is shown. Figure 2 The system 50 shown includes a system-on-a-chip (SOC) 52, which includes one or more application processors 66, a cache memory 70, and a GNSS processing system 68. In one embodiment, the SOC 52 may be a single monolithic semiconductor device embodied in a substrate of an integrated circuit, which includes, for example... Figure 2 All components shown are within the periphery of the SOC 52. The SOC 52 may include a memory controller 72 that controls access to a cache memory 70 (or other memory), coupled to both one or more application processors 66 and the GNSS processing system 68. Thus, the memory controller 72 may arbitrate the use of the cache memory 70 to allow both the GNSS processing system 68 and one or more application processors 66 to use the cache memory, which in one embodiment may be implemented as SRAM memory. In one embodiment, the memory controller 72 may allocate a portion of the cache memory 70 for use by the GNSS processing system and allow the remaining portion of the cache memory 70 to be used by one or more application processors 66. In one embodiment, the cache memory 70 may be used to store program code or program instructions and data manipulated by the processing system. Also as described below, when the acquisition engine of the GNSS processing system 68 is acquiring a GNSS signal, the acquisition engine may use the cache memory to store hypotheses, for example, in a hypothesis memory used during the acquisition phase, or may use the cache memory 70 to store PRN codes (and / or their code spectra derived from the DFT) generated for the GNSS signal. The GNSS processing system 68 can be coupled to one or more application processors 66 via bus 74. The one or more application processors 66 and the GNSS processing system 68 can also be coupled to a cellular phone modem and processor 76 via bus 74. In one embodiment, bus 74 is a set of buses on the SOC 52. The SOC 52 also includes a bus interface 78, which allows the SOC 52 to be coupled to a system bus 54 external to the SOC 52. Several other components are located external to the SOC 52, and these include a GNSS radio frequency component 63. Figure 2 The example shown is configured to operate only in the L5 wideband (WB) for receiving and processing only. Figure 2The illustrated embodiment shows an L5 wideband (WB) GNSS signal. The terms or phrases L5 WB band, L5 WB signal, or L5 WB GNSS are intended to include or refer to modernized GNSS signals and modernized GNSS systems (e.g., SV constellations and receivers) operating in a modernized frequency band centered at 1191.795 MHz and having a chip rate of 10.23 MHz or significantly higher than the conventional chip rate or the 1.023 MHz of GPS L1, and these modernized GNSS systems include, for example, the US L5 GPS system, the European E5 Galileo system, the Chinese Beidou / Compass B2 system, GLONASS K2, and QZSS. A cellular phone modem and processor 76 is coupled to a cellular phone radio frequency component 64 to receive and transmit cellular phone signals. DRAM 56 is coupled to a bus 54 and can store user data, applications, and the operating system. Furthermore, system 50 may also include non-volatile memory 57, such as flash memory, in addition to DRAM 56. Non-volatile memory 57 can store user data and applications, as well as the operating system of system 50. System 50 may also include various input / output devices that can interface with the rest of the system via one or more I / O controllers 58. Input / output devices may include one or more sensors 62 and other input / output devices 60. For example, sensors may include one or more of a 3-axis accelerometer, a 3-axis gyroscope, an ambient light sensor (ALS), a barometer, a magnetometer, one or more cameras, etc. In addition, system 50 may include other radio frequency components 62, such as Bluetooth, Wi-Fi, etc. The method for operating system 50 will now be described in reference. Figure 3 It is provided at that time.

[0132] In operation 101 ( Figure 3As shown, system 50 can receive a request from an application to determine a location. This request can originate from a foreground application or a background application. For example, a map application in the foreground, and therefore displaying a map to the user, requests a location, and this request can cause GNSS processing system 68 to be activated. Alternatively, a background daemon can make the location request. The nature of the request can determine the priority of memory controller 72 in determining how and when to allocate a portion of cache memory 70 for use by GNSS processing system 68. For example, in some embodiments, a foreground application request for a location can make allocating a portion of cache memory 70 for use by GNSS processing system 68 a high-priority task, causing that portion to be allocated as quickly as possible. Alternatively, a background application request for a location can make the allocation of a portion of cache memory 70 by memory controller 72 a deferred process or task, thereby giving memory controller 72 more time to allocate a portion of cache memory 70.

[0133] In operation 103, the GNSS processing system 68 may receive auxiliary data from, for example, a cellular phone modem and processor 76. In one embodiment, satellite almanacs or other data sources about satellites in the field of view over a period of time may be received by system 50 and stored for later use by the GNSS processing system 68. Based on the satellites or space vehicles (SVs) in the field of view (e.g., from the received satellite almanac), the GNSS processing system 68 may, in operation 105, generate pseudo-random noise (PRN) codes and / or their code spectra from the DFT for those GNSS SVs in the field of view (see, for example, see...). Figure 6 (Code spectrum memory 263 in the text). In one embodiment, the GNSS processing system 68 may generate and use these codes on demand during the acquisition and tracking phase for processing GNSS signals without storing them. In another embodiment, the GNSS processing system 68 may generate these codes and / or their code spectra from the DFT on demand during the acquisition and tracking phase for processing GNSS signals (see, for example, code spectrum memory 263 in the text). Figure 6 The code spectrum memory 263 in the document uses these codes and / or their codes derived from the DFT (see, for example, the code spectrum memory 263 in the document). Figure 6The code spectrum (in the code spectrum memory 263) also stores them, but these codes are no longer stored once the tracking phase is complete. In one embodiment, a code spectrum (which is generated from the GNSS PRN code of the GNSS SV in the field of view) can be generated but not stored (for more than about 1 millisecond), and the code spectrum can be generated repeatedly for every millisecond (ms) of received and stored (e.g., in a circular memory buffer) GNSS sample data; thus, in the first ms, code Doppler (e.g., time shift) and carrier frequency Doppler adjustment (see, for example) are applied to the generated GNSS master PRN code before the DFT (e.g., via DFT ALU 261). Figure 6 and Figure 9D The code spectrum is generated by [method name missing], and then a new code spectrum is generated in the second ms (the next millisecond after the first ms). The code spectrum is generated (e.g., by [method name missing]). Figure 6 The advantage of applying code Doppler and carrier frequency adjustment before the DFT ALU 261 generation is that the code spectrum cannot be pre-computed or even used in subsequent milliseconds because the code Doppler rate of the E5 GNSS signal is high and therefore the code Doppler should be shifted about every millisecond interval to maintain high correlation. In one embodiment, the code spectrum shifted by code Doppler can be stored for a short period of time if memory is available to reduce computational resource usage. Generating these codes on demand (which continues until the location data is determined) without long-term storage or any storage can reduce the amount of memory used by the GNSS processing system 68. Similarly, sharing the cache memory 70 with one or more application processors 66 can also reduce the memory usage of the GNSS processing system 68. In operation 107, a portion of the cache memory (such as SRAM memory) can be allocated on the integrated circuit containing the GNSS processing system and one or more application processors via, for example, a memory controller 72. This can then allow the acquisition engine in the GNSS processing system 68 to use the allocated portion at least during the acquisition phase.

[0134] The acquisition phase typically involves determining the frequency and primary code phase of the acquired PRN codes, as well as the identifier of the satellite that transmitted these acquired PRN codes. A PRN code is acquired when a correlation operation indicates a match between a locally generated PRN code and a received PRN code. In one embodiment, in operation 109, the acquisition engine in the GNSS processing system allocates a portion of its space to store hypothetical data and / or GNSS PRN codes. Then, in operation 111, the acquisition engine acquires one or more GNSS signals to allow the tracking engine in the GNSS processing system to track the acquired GNSS signals, thereby determining the pseudorange of the GNSS SV that transmitted the GNSS signal already acquired by the acquisition engine. In one embodiment, in operation 113, this portion of the cache memory can be deallocated after the start of the tracking phase. For example, the memory controller 72 can deallocate the portion containing the hypothetical data while retaining the GNSS PRN codes and / or their code spectra from the DFT (e.g., see the description below of code spectrum memory 263) (if they are stored in the cache memory) for tracking. In embodiments where PRN codes and / or their spectra derived from the DFT (e.g., see the description of spectra memory 263 below) are not stored during use but are generated on-the-fly, the deallocation of the cache memory portion used by the capture engine can be a complete deallocation, thereby freeing cache memory 70 for use by one or more application processors 66. Then, in operation 115, the GNSS processing system 68 can derive pseudorange and can use the pseudorange and GNSS SV ephemeris data to determine the position data of the system (e.g., system 50).

[0135] In one embodiment, the GNSS processing system 68 may include dedicated memory separate from and dedicated to the use of the GNSS processing system, separate from the cache memory 70. In one embodiment, the memory controller 72 may include a first port controller controlling reads and writes to a portion of the acquisition engine and a second port controller controlling reads and writes to the remainder of the cache memory 70. In one embodiment, the generation of GNSS PRN codes and / or their code spectra derived from the DFT may be performed only for healthy GNSS SVs in the field of view at the time of requesting location data (e.g., based on information about the health of the SVs and information about the SVs in the field of view in the received satellite ephemeris). This selective generation of GNSS PRN codes and / or their code spectra derived from the DFT without storing the codes (not stored in memory outside the registers and buffers of the pipelined processing logic) after the tracking phase or during the acquisition and tracking phases can reduce the memory usage of the GNSS processing system. The pipelined processing logic may include registers and buffers that momentarily store codes and code spectra during one or several clock cycles. In one embodiment, the GNSS processing system 68 may use an array processing architecture as described below, such as... Figure 6 , 7 The architectures shown in 8 and 9 provide additional reductions in memory usage for GNSS processing systems by, for example, using in-situ DFT algorithms.

[0136] In one embodiment, the operating system (or processor firmware) can perform the allocation of a portion of the cache memory for the GNSS processing system based on information about the data stored in the cache memory (which may be referred to as metadata). For example, this metadata may indicate whether the data stored in the cache memory is "dirty" (e.g., it was modified while stored in the cache memory) or whether it already exists in backup storage such as non-volatile memory (e.g., flash memory) or even DRAM memory before allocating a portion of the cache memory for use by the capture engine. For example, if the cache memory is storing computer program instructions or code that were already stored in non-volatile memory before allocating a portion of the cache memory for use by the capture engine, and these computer program instructions have not been modified while they were in the cache memory, then that portion of the cache memory can be allocated to the capture engine without having to write the data in that portion to DRAM memory or non-volatile memory. This allows the operating system (or processor firmware) to quickly refresh a portion of the cache memory; making it quickly available for use by the GNSS processing system's capture engine. Figure 2In the example shown, the GNSS processing system shares memory (e.g., cache memory 70) with one or more application processors (APs); in an alternative embodiment, the GNSS processing system may share additional memory with other processing systems on the IC (e.g., one or more other processors). In this alternative embodiment, the GNSS processing system shares another memory and does not use or shares the cache memory of one or more APs. The other memory and the GNSS processing system and other processing systems may all be on the same IC (e.g., a SOC that also includes the one or more APs and their cache memory). The other processing systems may be one or more modem processors or graphics processors or codecs that use additional memory separate from the cache memory used by one or more APs, and this separate (on-chip) additional memory may also be a two-port (“dual-port”) memory that supports high-bandwidth data access (both reading and writing). As described herein, when both the GNSS processing system and one or more other processing systems are seeking concurrent access to the other memory, the memory controller may arbitrate access to the other memory. In one implementation of this alternative embodiment, the additional memory may be the processor local storage of one or more other processing systems, and these one or more other processing systems exclusively use their processor local storage unless the GNSS processing system needs to use the processor local storage.

[0137] Another aspect of this disclosure relates to using an array processing architecture that leverages the DFT to capture and track GNSS signals from, for example, the E5GNSS SV. This aspect... Figure 4 , 5A Figures 5B, 6, 7, 8, 9A-9D and 10 are shown and will now be described with reference to these figures. Figure 4 An example of a portion 150 of a GNSS receiver is shown, which receives GNSS signals and stores them in a two-dimensional (2D) baseband sample array after analog-to-digital conversion. The GNSS receiver may include a GNSS radio frequency (RF) front end 153 that receives GNSS signals via an antenna 151 coupled to the GNSS RF front end 153. In one embodiment, the GNSS RF front end 153 receives only L5 WB GNSS signals.

[0138] Figure 12 Examples of components and architecture that can be used in one embodiment of the GNSS radio receiver 153 are shown. Figure 12As shown, the GNSS receiver includes an RF front-end module 701, an RF and mixed-signal section 702 and a digital front-end 703, both of which can be integrated into an ASIC (which may be part of an SOC 52); the RF front-end module 701 can be decoupled from the ASIC containing the digital front-end 703 and possibly the RF and mixed-signal section 702. The RF front-end module 701 can be implemented in an RF integrated circuit (IC) coupled to a GNSS antenna 707, which is tuned to receive L5 WB GNSS signals; the GNSS antenna 707 is typically off-chip and therefore not on the RF IC. The GNSS antenna 707 receives GNSS signals and provides these signals to a bandpass filter 709, which is configured to allow signals centered at 1192 MHz with a 51 MHz bandpass bandwidth to pass through, thus GNSS signals between approximately 1166.5 MHz and 1217.5 MHz pass through the bandpass filter 709. The output of bandpass filter 709 is coupled to LNA 711 to provide the bandpass-filtered GNSS signal to LNA 711. In one embodiment, GNSS antenna 707 is tuned to receive only L5 WB GNSS frequency signals. The RF front-end module may include a low-noise amplifier (LNA) 711, which is tuned for L5 WB band only and is therefore optimized to receive L5 WB band signals. Figure 12 The GNSS receiver shown does not contain an additional LNA for receiving other GNSS signals (e.g., L1 GPS). The output of LNA 711 can be filtered by bandpass filter 713, and the output from filter 713 is amplified in amplifier 715 (located on the ASIC containing the RF and mixed-signal section 702), and then ADC 71 generates digitized GNSS sample data, which in one embodiment is processed to generate two digitized GNSS sample data streams: one for GNSS sideband A and another for GNSS sideband B. Clock generation phase-locked loop 719 and clock dividers 723 and 725 generate clock signals used by ADC 717 and CIC decimators 721 and 729 to generate digitized GNSS sample data for up to four GNSS signal components (e.g., E5AI, E5AQ, E5BI, and E5BQ). Downconverter 727 separates the I and Q signals, and sideband separation downconverter 731 separates the upper sideband from the lower sideband to provide GNSS sample data, which is stored in baseband sample memory (such as...). Figure 6 In the baseband sample memory 253). Figure 12In one embodiment of the GNSS receiver shown, the GNSS receiver has a direct connection from an LNA (e.g., LNA 711) through one or more filters (e.g., bandpass filter 713) and / or one or more gain stages (e.g., amplifier 715) to an analog-to-digital converter (ADC 717), and this GNSS receiver does not have an RF mixer, therefore there is no RF mixer in the RF front-end module 701 and no RF mixer in the digital front-end 703. Furthermore, this GNSS receiver does not have an RF reference local oscillator (e.g., no phase-locked loop), and there is no (frequency) down-conversion in the RF signal path prior to the ADC (e.g., ADC 717). In conventional GNSS receivers, an RF local oscillator and one or more RF mixers are used to perform RF down-conversion in the RF signal path prior to the ADC.

[0139] Reference Figure 4 The output from the GNSS RF front-end 153 can be provided to a radio frequency (RF) analog-to-digital converter (ADC) 155, which can generate digitized GNSS sample data from the digitized GNSS signal. In one embodiment, the output from the RF ADC 155 can be stored in a baseband sample array (such as... Figure 4 The baseband sample array 157 shown is used in this embodiment. In one embodiment, the baseband sample array 157 may have N2 or more rows and N1 columns to provide an array of N2 × N1 (N2 × N1). The number of samples in the array can be configured to satisfy the Nyquist criterion to provide a sufficient number of samples. If in one embodiment, N1 = 20 and N2 = 1024, then there are 20480 samples that satisfy the Nyquist criterion over time (e.g., 1 ms or slightly more, such as 1.05 ms). The RF ADC 155 is configured to repeatedly receive analog samples from the GNSS RF front end 153 over time and convert them into digitized GNSS samples stored in the array 157. For example, the RF ADC may repeatedly convert samples of the GNSS signal, resulting in them being stored in the array 157. In one embodiment, the array 157 may be implemented as a circular memory buffer that stores digitized samples; as is known in the art, the circular memory buffer may use a write pointer to indicate the next write position in the array and a read pointer to indicate the next read position. The write pointer is used when the ADC 155 provides its output to be stored in the circular buffer, and the read pointer is used when the ALU reads the next set of inputs for processing. Array 157 can provide data to a set of arithmetic logic units (ALUs) 159, which are configured to perform DFT and inverse DFT to provide GNSS signal capture and (in one embodiment) GNSS signal tracking. Figure 6 , 7 Figures 8 and 9 illustrate embodiments of the ALU 159. Before describing these ALUs 159, refer to... Figure 5A and 5B At that time, methods for processing the schema using this array will now be provided. Figure 5A and 5B The method shown can be used Figure 6 The array processing architecture shown.

[0140] exist Figure 5A In the illustrated operation 201, digitized GNSS sample data is stored in a two-dimensional memory array, which may be a circular buffer (such as a 1.05 or 1.25 ms GNSS signal data frame) containing slightly more than one 1-millisecond frame of GNSS signal data. Figure 6 The memory in the array is 253. A single frame of E5 GNSS PRN code data in the GNSS signal is 1.0 millisecond long. Additional memory exceeding one millisecond can be determined based on the time required to compute the spectrum of the input data before it is overwritten (via the DFT). Therefore, a faster DFT means that a shorter additional time exceeding one millisecond is sufficient. In one embodiment, the data in the memory array is formatted such that consecutive rows contain consecutive time samples. For example, the first row may contain samples over time periods t1 to t20, and the second row may contain samples over time periods t21 to t40. Figure 4 The array 157 shown illustrates an example of such an array, which in one embodiment can be stored in... Figure 6The baseband sample memory 253 is used. In one embodiment, the aim of these optimizations is to minimize the number of clock cycles required to perform the correlation process implemented using frequency domain operations: that is, the inverse DFT of the input sample multiplied by the complex conjugate product of the code sample adjusted for the carrier frequency yields the correlation of the input sample under all possible code assumptions under the carrier frequency assumption. This single step, as defined herein, is called Very Fast Frequency Domain Correlation (VFFDC), a form of Frequency Domain Correlation (FDC). Optimizing the data flow through these operations reduces the number of clock cycles required to perform the correlation. The advantage is that, for a given system clock, it increases the number of carrier frequency estimates or assumptions that can be checked within one millisecond. Furthermore, reducing the clock cycle means that system timing requirements can be relaxed, allowing for more reliable chip designs, or designs that can operate at lower voltages to reduce power consumption, or faster clocks to achieve higher throughput. Alternatively, methods that require more clock cycles but then require higher clock frequencies to perform FDC can be employed. The clock required to perform FDC can be reduced by using a matrix configuration (e.g., array 157), whereby the outputs of the samples and code spectra are ordered to reduce the clock required to perform the complex conjugate IDFT of the product. Then, in operation 203, the GNSS processing system (such as...) Figure 6 The GNSS processing system shown or Figure 2 The GNSS processing system 68 shown can retrieve GNSS baseband data from the two-dimensional memory array and load the retrieved GNSS baseband data into a set of DFT ALUs. For example, this set of DFT ALUs can be a set of four ASIC hardware DFT ALUs in the capture engine, where each DFT ALU can execute 20 parallel DFT operations in each DFT ALU in response to a single program instruction. In one embodiment, the set of DFT ALUs can be... Figure 6 The DFT ALU 255 is shown. In operation 205, the GNSS processing system can generate PRN code data (or alternatively retrieve such PRN code data from memory) and / or their derived code spectra for each expected GNSS signal source (such as each set of E5, L5, or B2GNSS SVs known to be in the field of view) for each expected GNSS signal source (such as each set of E5, L5, or B2GNSS SVs known to be in the field of view). Once the PRN code data is generated, it can be time-shifted and frequency-shifted, and can also be line-upsampled and interpolated (e.g., by adding zeros to fill the last bit in the code) to generate a set of DFTs (e.g., using...). Figure 6 The DFT ALU 261 in the code is used to generate code data that can be stored in a code spectrum array (such as...). Figure 6 The code spectrum data is stored in the code spectrum memory 263 shown. In one embodiment, operation 205 can be performed by a code generator 259, which generates code array data, which can then be processed by... Figure 6The DFT ALU 261 shown is used to generate a code spectrum array (in column order) temporarily stored in the code spectrum memory 263.

[0141] It should be noted that code Doppler on E5 band signals is much faster than code Doppler on L1 band. This code Doppler is a carrier Doppler scaled by the ratio of carrier period to chip. In L1, there are 1540 carrier periods per chip. For example, in L5, there are 116 carrier periods per chip. Therefore, L5 has 13.28 times more chips, meaning that correlations in the E5 band require much faster updates to the code phase to accommodate consistent correlations across consecutive frames of PRN codes. This means that it is generally not possible to pre-calculate this effect. An alternative solution is to apply the code Doppler effect to the correlation results before adding them to the hypothesis memory. The memory address can be shifted to account for the code Doppler, but this incurs some loss because the shift is quantized as the number of hypotheses, typically about 2 hypotheses per chip. Therefore, it is preferable to apply the code Doppler to the generated code before generating the code spectrum. Another optimization is to multiply the carrier Doppler by the generated code to match the carrier information in the input samples. In this way, for each sideband and / or centerband, the DFT of the input sample only needs to be performed once per millisecond, and the same input spectrum can be used for all correlations within that millisecond.

[0142] In operation 207, a set of DFT ALUs (such as...) Figure 6 The DFT ALU 255 shown can perform multiple DFTs in parallel on loaded GNSS baseband data using a time-decimation method and store the results in a frequency domain results memory (such as...). Figure 6 In the memory shown 257). Figure 6 In the example shown, operation 207 performed by DFT ALU 255 produces an array that is stored in memory 257 in column order, and the data in memory 257 can be retrieved to provide Figure 6 The output 258 shown is an example. Output 258 in operation 209 can be multiplied by a code spectrum stored in a code spectrum memory such as code spectrum memory 263; in Figure 6 In the example shown, multiplier 265 performs this multiplication of operation 209 and produces an array of product data. Then, in operation 211, a set of inverse DFTs can be performed on the data in the product array using a frequency decimation method, and these DFTs can be used with conjugate inputs to produce inverse DFTs. In one embodiment, Figure 6 The inverse DFT ALU 267 shown can perform operation 211, and the output from the inverse DFT ALU 267 can be... Figure 6 The relevant post-processing operation 269 is shown, and then the data is stored in operation 213 in what may be called an integration memory (e.g., Figure 6In the memory of the memory 271 shown, in one embodiment, the integration memory can store hypothetical data during the capture phase. In one embodiment, this integration memory may be located in a location allocated for including Figure 6 The array correlator in the GNSS processing system is located in a portion of the cache memory (e.g., cache memory 70) used by the capture engine. The GNSS processing system can then perform operation 215 by determining the frequencies of the captured PRN codes, which identify the GNSS SV that transmitted the captured PRN codes. Once it is confirmed that a GNSS signal has been captured from a particular GNSS SV, operation 217 can be performed for each captured GNSS SV signal by entering a tracking mode for those captured GNSS signals. In one embodiment, the tracking mode can use a conventional correlator or other techniques (such as DFT) to determine the pseudorange to the captured and tracked GNSS SV. This is in Figure 5B This is illustrated as operation 219. The GNSS processing system can then use the determined pseudorange to derive the position of the GNSS receiver, by using pseudorange and ephemeris data to the tracked GNSS SV to derive the position (e.g., the latitude and longitude of the GNSS receiver), as is known in the art.

[0143] Figure 6 It shows that it can be executed Figure 5A and 5B The method shown is an example of a fast frequency domain correlator architecture. Memory 253 can be a circular buffer memory storing N2 x N1 digitized GNSS signal samples. In one embodiment, memory 253 can be two circular memory buffers storing 1.05 or 1.25 ms of GNSS sample data; one of these circular memory buffers can store GNSS sideband A sample data, and the other can store GNSS sideband B sample data. The two different sidebands can be separated and then stored using the following method. To obtain the upper sideband (e.g., E5B or B2B), the GNSS sample data is down-shifted by the digital carrier (for a sampler centered at 1191.795 MHz) for example, 15.345 MHz (and thus will now represent the information originally at 1207.14 MHz in the sample data), and then the shifted sample data is filtered by a low-pass filter to capture a data bandwidth of + / - 10.23 MHz, and then the filtered sample data is decimated from the wideband sample to a lower sampling rate for use in... Figure 6The process is carried out in the pipeline shown. To obtain the lower sideband (e.g., E5A, B2A, L5, or QZSS), the GNSS sample data is up-shifted by the digital carrier (for a sample centered at 1191.795MHz), for example, by 15.345MHz (and thus will now represent the information originally at 1176.45MHz in the sample data), and the shifted sample data is then filtered by a low-pass filter (LPF) to capture a data bandwidth of + / -10.23MHz, and the filtered data is then decimated from the wideband sample to a lower sampling rate for use in... Figure 6 The process is handled in the pipeline shown. The DFTALU 255 retrieves data from memory 253 and performs a set of DFTs in the DFT ALU 255; Figure 7 An example of the components within the DFT ALU 255 is shown. Figure 7 The example shown has a two-stage DFT. The first stage uses N1 DFTs, each operating on 1024 points based on inputs, which include phase factor inputs from array 301 and data inputs from memory 253, which can be similar to... Figure 4 The data shown in array 157 is used. The input to this array is input 251, which can be obtained from, for example... Figure 4 Analog-to-digital converters such as the RF ADC 155 shown are provided. Figure 7 A set of 20 DFT operations is shown, three of which are designated as operations 303, 304, and 306. The results of these operations can be stored in a partial result sample array 308, which in turn provides the output used as input for a second stage (containing N² DFTs); these N² DFT operations include... Figure 7 The two operations 313 and 315 are shown. One of the inputs to these N² DFTs is a set of phase factors from array 311. Figure 7 The outputs of these DFT operations in the second stage shown are stored in the FFT result array 257, and the data is stored in column order, which is the reverse of the row order of the data stored in memory 253. This reversal allows data to be prepared for inverse DFT operations, such as those performed by the inverse DFT ALU 267, without transposing or otherwise reformatting the data.

[0144] Figure 8 An embodiment of the inverse DFT ALU 267 is shown. Figure 8In the example shown, the inverse DFT ALU may include a two-stage DFT operation that receives data from the product array of multiplier 265. The first stage may include N2 DFT operations that use data (with conjugate inputs) from the product array generated by multiplier 265 and also use phase factors from phase factor array 351 to generate an output that can be stored in the first-stage sample array 361. Figure 8 Each of the N2 DFT operations is performed on 20 data points. Figure 8 This demonstrates two DFT operations, 355 and 357, out of a total of N² DFT operations. Figure 8 In the example shown, the second stage of the DFT operation uses N1 DFT operations, where each operation is performed on N2 points; Figure 8 The diagram shows three of these operations, 363, 365, and 367, where each operation receives a column of data from the first-stage sample array 361. These DFT operations in the second stage also receive phase factor inputs from the phase factor array 353, and these second-stage DFT operations produce 20 outputs, which can be... Figure 8 The result of the post-processing is shown in post-processor 371. The result of the post-processing can be stored in integral array 373 (which can be combined with...). Figure 6 (The same as the integration memory 271 shown). From arrays 301 and 311 (in...) Figure 7 (in) and arrays 351 and 353 (in Figure 8 The phase factor (in the FFT) specifies the amount of phase shift required for each radix-20 / 16 / 8 DFT at each stage of the FFT. In one embodiment, these phase shifts are used to decompose a 20480-point DFT into multiple stages of radix-20 / 16 / 8 DFTs, which forms the basis of the FFT implementation of the DFT. The phase factor is also known as the "rotation factor" of the FFT.

[0145] Figure 9A , 9B 9C and 9D demonstrate the ability to generate data stored in a code spectrum memory (such as...). Figure 6 and 8 An example of a spectral code generator (and a portion thereof) in the spectral code memory 263. In one embodiment, Figure 9DThe code generator 259 and DFT ALU 261 shown can generate PRN codes and / or their DFT-derived code spectra on demand and in real-time for GNSS SVs in the field of view as the GNSS processing system captures and tracks these GNSS SVs, without storing (except for transient storage in registers and buffers in the processing pipeline) the PRN codes and / or their DFT-derived code spectra. This can improve the memory usage of the GNSS processing system by reducing the amount of memory required to operate the GNSS processing system. In an alternative embodiment, the code generator can generate PRN codes and / or their DFT-derived code spectra on demand for GNSS SVs in the field of view during the capture and tracking phase, but store those codes until one or more locations, such as one or more latitude and longitude values, are determined. Thereafter, the PRN codes and / or their DFT-derived code spectra can be deleted from storage to allow for further use of the storage. In one embodiment, as Figure 9D As shown, code spectrum generator 259 can use polynomial type generator 402 ( Figure 9A (As shown) a code seed 401 is used to generate a PRN code for each GNSS SV in the field of view. A set of programmable coefficients can then be used to time-shift the generated PRN code in a time shifter 404 (based on these coefficients). The time-shifted PRN code can then be frequency-shifted by a frequency shifter that can use CORDIC phase shifts, three of which are considered CORDIC phase shifts 408, 410, and 412. The phase shifts can be based on a programmable phase split input 406. Another set of CORDIC phase shifts, including phase shifts 417, 419, and 421, can then produce an output, which is subsequently subjected to the same DFT operation performed on the digitized GNSS sample data (in one embodiment by...). Figure 6 The output is processed by the DFT ALU 261 in one embodiment. Then, in one embodiment, the DFT operation (in another embodiment, performed by...) is performed... Figure 6 The results of the DFT ALU 261 execution are stored in a code spectrum memory (such as...). Figure 6 The code spectrum memory 263 shown is used.

[0146] An embodiment of the polynomial type generator 402 is in Figure 9A As shown in the figure. This embodiment can be used to perform... Figure 9B and 9CThe method is illustrated. This generator 402 includes two pre-computed (pre-computed) code advance matrices 501 and 502, which, if pre-computed, are retrieved, for example, from a lookup table. For example, for each of the four components of the Galileo E5A and E5B signals, there are corresponding code seeds and master code polynomial data; this information is well known in the art and is published in the ICD of the GNSS constellation source. Generator 402 can generate more than two master PRN code bits in a single clock cycle using the pre-computed code advance matrices 501 and 502; see [link to relevant documentation]. Figure 9B Operations 955 and 957 in the example. Figure 9A As shown, the computed code advance matrix 501 includes a first input for receiving a generator polynomial 503 (which may be master code polynomial data for a given GNSS constellation and a given GNSS signal component), a second input for receiving a value fed back from register 515, and an output that serves as a first input to a multiplexer (MUX) 511. The second input 507 of MUX 511 is a constant initial value of all 1s (14 bits, each set to a value of 1 in one embodiment); this second input 507 is used only for the initial output from register 515, and thereafter MUX 511 selects (to MUX 511) the first input as its output, which is stored in register 515 (which may be a clock register) such that in the next clock cycle, the last output from MUX 511 is fed back to the second input of code advance matrix 501 and also provided as a first input to XOR logic gate 519. The output from MUX 511, fed back to the second input (of code advance matrix 501), is multiplied by a constant value in code advance matrix 501 (derived from generator polynomial 503) to generate the next output from code advance matrix 501, and this next output passes through MUX 511 and is stored in register 515; this process of feeding back the output from register 515 and performing matrix multiplication of this output with the constant value in code advance matrix 501 is repeated in each clock cycle (or alternatively in a set of several clock cycles) to generate an N-bit master PRN code for a given GNSS constellation (e.g., Galileo E5) and a given GNSS signal component (e.g., E5AI) in each clock cycle. In one embodiment, N can be greater than 2, for example, 10 or 14 bits. Thus, generator 402 can rapidly generate many (e.g., N) bits of master GNSS PRN code in one or several clock cycles. Figure 9AIn the example shown, 14 bits are generated at the output of register 515, but XOR gate 519 (which performs the XOR operation) uses only the last 10 bits. Code advance matrix 502 is used in a similar manner to code advance matrix 501. For a given GNSS constellation and GNSS signal component, and a given seed for the GNSS SV in the given constellation, code advance matrices 501 and 502 (in one embodiment) are pre-computed to generate the next N-bit (N-bit "advance") master GNSS PRN code for that GNSS signal component from that GNSS SV (at the output of XOR gate 519) based on the values ​​in the matrices and the previous outputs from registers 515 and 517. The Matlab appendix includes examples of generator 402 in the well-known Matlab code form that can create and use these pre-computed code advance matrix codes. In one embodiment, for each clock cycle, the pre-computed code advance matrix can be pre-computed (or computed at runtime) by multiplying the original matrix containing master polynomial data by N times to provide an N-bit advance in the PRN code. For example, if an N=3 advance is required, the original matrix ("A") is multiplied three times (A*A*A) to provide the next 3 bits of the PRN code for the N=3 bit code advance matrix. Figure 9AAs shown, the calculated code advance matrix 502 includes a first input for receiving a generator polynomial 505 (which may be master code polynomial data for a given GNSS constellation and a given GNSS signal component), a second input for receiving a value fed back from register 517, and an output that serves as the first input to MUX 513. The second input 509 of MUX 513 is a seed value for the corresponding GNSS SV in a given GNSS constellation. This seed value is used only for the initial outputs from multiplexer 513 and register 517, and thereafter MUX 513 selects the first input (to MUX 513) as its output, which is stored in register 517 (which may be a clock register) such that in the next clock cycle, the last output from MUX 513 is fed back to the second input of code advance matrix 502 and also serves as the second input to XOR logic gate 519. The output from MUX 513, fed back to the second input (of code advance matrix 502), is multiplied (in a matrix multiplication operation) by a pre-computed value in code advance matrix 502 to generate the next output from code advance matrix 502. This next output passes through MUX 513 and is stored in register 517. The outputs of registers 515 and 517 are XORed by XOR gate 519 each clock cycle to provide 10 new bits (i.e., a 10-bit advance PRN code). The 14-bit output is truncated to provide 10 new bits in the current clock cycle. Code advance ten bits 524 can select this truncation. Then, XOR gate 521 performs an XOR operation on the output from XOR gate 519 and the auxiliary bit 523 of a given GNSS signal component from a given GNSS SV to "erase" or "remove" the auxiliary bit from the code generated at the output of XOR gate 519. Left shift logic 527, upsampling logic block 529, and left shift logic 533, together with registers 526 and 531, further process the generated master PRN code to provide code samples that can be "aligned" with GNSS samples received at a specific sampling rate, ensuring sampling rate matching and alignment. The shift logic can be used to shift or move to different parts of the PRN code. The output of left shift logic 533 is provided to... Figure 9D The time shifter 404 in the code spectrum processing pipeline shown.

[0147] Figure 9B and 9CA method for operation code generator 402 is illustrated. In operation 951, the GNSS processing system determines the GNSS SV in the field of view from conventional auxiliary data (such as a recently downloaded version of a GNSS satellite almanac) or from ephemeris data in equation form. In one embodiment, the GNSS SV in the field of view may be limited to L5 WB GNSS SVs, such as one or more of the Galileo E5 GNSS constellation, the US L5 GNSS constellation, and the Chinese Beidou / Compass B2 constellation. Then, in operation 953, the GNSS processing system can determine a code seed and a code generating polynomial for each GNSS signal component from the GNSS SV in the field of view (e.g., E5AI and E5BI of the Galileo E5 GNSS SV) to generate a master PRN code for that GNSS signal component, the code generating polynomial being a set of known coefficients for that signal component. Then, in operation 955, the G1 code advance matrix is ​​calculated (or the G1 code advance matrix is ​​pre-calculated and retrieved from a lookup table in non-volatile memory), and in operation 957, the G2 code advance matrix is ​​calculated (or the G2 code advance matrix is ​​pre-calculated and retrieved from a lookup table in non-volatile memory). In one embodiment, each of the G1 and G2 code advance matrices is pre-calculated by multiplying the original matrix of the master code polynomial data by N times, where N represents the number of code bits to be generated. For example, if the amount of code "advance" is 10 bits of the master PRN code data, the original matrix is ​​multiplied (by itself) 10 times to create a 10-bit code advance matrix. In one embodiment, the amount of code "advance" is the number of bits of the master PRN code data generated in one clock cycle, so if N = 10, the code generator generates 10 bits of new master PRN code data for each clock cycle. After the G1 and G2 code advance matrices are retrieved (if pre-calculated) or calculated, the method can continue in operation 959. In operation 959, the system uses an initialization vector (all 1s) to provide the first G1 output (therefore the first G1 output is an initialization vector of all 1s) and uses a code seed to provide the first G2 output (therefore the first G2 output is the code seed); in operation 961, the system performs an XOR operation on the first G1 output and the first G2 output to provide the first set of N-bit PRN code data. After operation 961, the first set of N-bit PRN code data is processed in operations 969, 971, and 973 (e.g., ...). Figure 9B and 9C As shown, when processing proceeds from operation 961 to operation 969 via 9X, and the N-bit PRN code advance of all subsequent groups is generated in the loop of operations 963, 965, 967, 969, 971, 973, and 975. In operation 963, (e.g., from...) Figure 9A The G1 output of register 515 in the code is fed back to the G1 code advance matrix, and (e.g., from...) Figure 9AThe G2 output (from register 517) is fed back to the G2 code advance matrix. Then in operation 965, the final G1 output (e.g., from register 515) is multiplied by the G1 code advance matrix to generate the next G1 output, and the final G2 output (e.g., from register 517) is multiplied by the G2 code advance matrix to generate the next G2 output. In operation 967, the G1 and G2 outputs are XORed (e.g., in...). Figure 9A (In XOR logic gate 519). In operation 969, the code output from XOR logic gate 519 is XORed with the expected auxiliary bits (e.g., auxiliary bit 523) (e.g., in XOR logic gate 521) to erase or remove the auxiliary bits from the code output. Then, in operations 971 and 973, code samples are generated and fed to the remaining code spectrum processing pipeline. These operations prepare the code samples such that their sampling rate can be matched to the sampling rate of the received GNSS sample data. Operation 975 determines whether to continue generating GNSS master PRN code data. In one embodiment, PRN code data generation can terminate when tracking of all required GNSS signals is complete, but if such tracking is required, the process continues in the loop of operations 963-975.

[0148] Figure 10 An example of a GNSS processing system is shown that can be used to perform the methods described herein or to implement the systems described herein. The GNSS processing system 450 may be implemented on its own integrated circuit (such as navigation chip 451) or as part of a system-on-a-chip architecture as part of a larger system such as a smartphone or tablet. The GNSS processing system 450 may include processing logic, such as an ARM processor 466 that uses ARM program and data memory 467 to control the operation of the GNSS processing system 450. Furthermore, the GNSS processing system 450 may include components that can be similar to... Figure 4The RF ADC 465 is shown as RF ADC 155. GNSS processing system 450 may also include clock phase-locked loop generation and gating circuitry 464 to generate a clock using the phase-locked loop and for other operations within GNSS processing system 450. GNSS processing system 450 may include both logic modules and memory to perform the acquisition and tracking processes described herein. For example, logic module 457 may include an acquisition engine 458, which may include a set of DFT and inverse DFT processors or ALUs to perform the DFT operations described herein. Furthermore, logic module 457 may include a digital front-end 460 that can provide processing both before and after the RF ADC 465 in all digital E5 GNSS front-ends. Logic module 457 may also include multiple satellite signal generators, such as satellite signal generator 459 that generates GNSS PRN codes for GNSS satellites (SVs) in the field of view based on auxiliary data, for example, data that may be received from a cellular data communication network. Logic module 457 may also include a time base and control module 461 and a memory interface and bus control module 462 to allow the GNSS processing system to be coupled to one or more application processors. Logic module 457 may be coupled to one or more memories to store various data in various data structures, including, for example, a baseband sample memory 468, a capture engine command memory 469, an FFT program memory 470, an FFT constant memory 471, an FFT variable memory 472, an FFT result memory 473, a code spectrum generation memory 474, a coherent integration memory 475, an IFFT memory 476, an IFFT memory 477, an IFFT variable memory 478, and a non-coherent integration memory 479. These memories can be used with logic module 457 to perform the operations described herein. It will be understood that alternative architectures can be used with... Figure 10 The different processor and memory arrangements are shown.

[0149] In another embodiment, the clock frequency required to perform the DFT operation is reduced by executing multiple kernel operations in parallel. For example, if the sampling rate is chosen to be 2^N, such as N = 14, the DFT can be implemented using a radix-4 kernel with 7 stages. Each step of each stage processes 4 samples in-place. Assuming only dual-port memory with one read and one write per cycle, the required clock frequency is 4 * 4096 per stage, and 114,688 clock cycles for 7 stages. Figure 6The VFFDC shown can implement a DFT in approximately 4096 clock cycles. To achieve similar performance, 32 cores can be implemented in parallel, allowing one stage to complete in 512 clock cycles, and seven stages to complete after 3584 clock cycles. However, this approach would require the ability to achieve 32 parallel input samples. Therefore, the advantage of VFFDC is that it can achieve low clock rates, reading only 10 memory entries in parallel. Another embodiment uses four times the clock rate and then only requires 8 cores in parallel, reducing the parallel memory read requirement to 8 inputs / outputs per clock cycle. The advantage of VFFDC is that it maintains both low clock rates and low parallel memory read / write configurations. Such optimization will allow for low power consumption because the system can operate at low clock speeds and achieve reliable timing at low voltages.

[0150] In one embodiment, VFFDC implements a processing chain with minimal memory requirements. Every millisecond, there are two DFTs on the input sample, one for each of the upper and lower sidebands of E5. Thus, for each component of each satellite signal (4 for E5, 2 for L5, and 4 for B2), there is one DFT that includes the code Doppler and carrier frequency effects, eliminating the need to apply a different DFT to the input sample to remove the carrier frequency assumption. Then there is another DFT to implement the inverse DFT of the input and code spectrum product. Therefore, the total number of DFTs per millisecond is 2 + 2 * N channels * M components, where the first 2 is the original input DFT and the second 2 is for deriving the IDFT of the code spectrum and spectral product. For 22 channels with a maximum of 4 components per channel, this is 2 + 2 * (22 * 4) = 178 DFTs per millisecond. If the code spectrum DFT is pre-computed, then for each frequency of each PRN, the input sample must be unique. In this case, for M = 4 and N = 22, the number of DFTs is (2 * M * N) = 176. However, this requires memory to store the code spectrum. Such a system also needs a method to generate the code Doppler after each IFFT and before updating the hypothesis memory. Therefore, even if this alternative has a nearly identical number of DFTS, it requires additional memory and may have higher power consumption to move the code spectrum DFT into the AE per millisecond. For example, at 20480 hypotheses per millisecond, it would require 22 channels * 4 components * 2 bytes for I and Q of the code spectrum * 20480 hypotheses * 8 bits per byte = 28 Mbit per millisecond = 28 Gbit per second bus rate. Such a configuration would be virtually impossible to achieve. Therefore, in-place computing power makes the system feasible.

[0151] Another optimization for reducing system memory is allowing all four components of the E5 band signal (such as Galileo E5 and the future B2) to be processed into a single hypothetical memory for long-term integration to overcome weak signals (caused by high system losses in the phone and / or high losses due to signal attenuation from leaves or the user's body). The B2's common domain interface control documentation only describes the lower sideband, but other technical papers indicate that the upper sideband signal structure will be available in late 2019 or later. Therefore, GPS L5, with only one sideband, will have only two components, while E5 and B2 will have four components: two components per sideband (upper and lower).

[0152] The main challenge in coherently integrating the sum of code correlations per millisecond is reducing the cancellation loss caused by phase reversal at 1 ms epoch. When the received signal main code phase can be estimated to be on the order of approximately 0.5 ms or less, it is possible for the received signal spectrum to be at least partially aligned temporally with the estimated code phase, thus avoiding sub-millisecond cancellation. Figure 11 An embodiment that can provide accurate time coherent integration is shown.

[0153] In one embodiment, estimating the expected fractional main (ms-long) code phase of a candidate signal requires knowledge of both the precise time and the initial position. The precise time can be derived from the secondary code phase of the first received signal, or it can be derived from a fine-time source, as is well known in the art. This estimation can be... Figure 11 Operation 601 in the middle.

[0154] Once the primary code phase uncertainty is reduced to well below 1 ms, the sub-millisecond cancellation problem can be addressed by at least partially aligning the received 1 ms signal epoch with the expected reception time of the code from each SV. This means that multiple received signal spectra must be calculated every millisecond and interleaved in time to match the primary code spectrum, thus reducing the level of sub-millisecond coherent cancellation.

[0155] The search order determines which SVs, their signal components, and Doppler segments will be searched at each fractional phase shift. This is in Figure 11This is illustrated as operation 603. Because longer coherent integrals produce greater sensitivity, the E5Aq and E5Bq pilot signals can be preferentially used due to their 100ms long auxiliary codes and lack of data bit inversion. In one embodiment, E5Ai and E5Bi can also be used in cases where navigation message symbols are predicted and removed, thereby eliminating or reducing their corresponding coherent cancellation losses. It should be noted that while the main code phase of all signals is expected to be uniformly distributed over milliseconds, there may be cases where the only available processing slot for a given signal is suboptimal. In any case, it is always possible to avoid the worst-case scenario where, in the case of auxiliary code bit inversion, the first 1 / 2ms of signal will cancel out the second 1 / 2ms of signal.

[0156] In one embodiment of the invention, M 1ms signal spectra are calculated every millisecond, each offset by 1 / M ms. For example, if M=4, then every 0.25 milliseconds, a complete 1ms (or more) of received and digitized GNSS sample data will be processed by FFT correlation (e.g., using...). Figure 6 The VFFDC architecture shown in the diagram means that in this case, processing epochs are separated by 0.25ms and offset (one to the next) by 0.25ms, and the received GNSS sample data is also offset by 0.25ms. In this example, the first processing epoch at a relative time of 0.0ms will process the FFT correlation with the 1ms GNSS sample data generated in operation 605. The correlation is as follows: Figure 11 Operation 607 is illustrated in the diagram. At a second processing epoch at a relative time of 0.25 ms, the FFT correlation is processed using 1 ms of GNSS sample data (operation 607), which ends at a relative time of 0.25 (operation 605) and is offset by 0.25 ms from the previous 1 ms GNSS sample data. At a third processing epoch at a relative time of 0.5 ms, the FFT correlation is processed using 1 ms of GNSS sample data (607), which ends at a relative time of 0.5 (operation 605) and is offset by 0.25 ms from the previous 1 ms GNSS sample data. Therefore, operations 605, 607, and 609 are repeated four times during a 1 ms time interval. In an alternative, more sensitive embodiment, the signal spectrum is calculated to be aligned as closely as possible to the phase of each expected satellite code.

[0157] In the case of coarse time mode, candidate signal codes (received GNSS sample data) and their associated spectra must be generated and aligned every millisecond, and correlated with the signal spectrum using VFFDC or a similar FFT-based method.

[0158] Having generated these correlation results, they must be added in a coherent hypothesis memory specific to each SV band and frequency segment, while removing the phase inversion associated with the auxiliary code phase. This is shown as operation 607. This process requires calculating the complete 1ms correlation, even with code phase uncertainties much smaller than 1ms. However, only the portion of the complete PN code that may contain correlation peaks must be stored in the hypothesis memory.

[0159] At the boundaries of the secondary code epochs, or in some cases even more frequently, the coherent hypothesis memory must be incoherently added to a noncoherent hypothesis memory that reflects the coherent hypothesis memory but contains only amplitude information, and thus can remain half the size of the memory. This is shown as operation 611.

[0160] Figure 11 The process continues in operation 613 (by looping back to operation 605) until the correlation peak rises above the noise floor. Once the correlation peak rises above the noise floor with sufficient confidence, the search result is reported, and the capture search for the specific SV of interest can be stopped, thus making way for the next SV in the search order for its sub-digital phase. The search may also time out after a preset time interval, and search failure can be reported.

[0161] Figure 11 An example of a method is shown regarding how to search for satellite codes in alignment with the approximate time segment of the expected received satellite code, thereby reducing sub-millisecond coherent cancellation losses due to phase reversal. This search can be performed based on an initial information set, which in one embodiment may include at least two of the following: (1) the code phase of the primary or secondary code signal received from at least one GNSS SV; (2) an estimated GNSS time based on one or more time sources, the uncertainty of which is estimated (e.g., based on the known accuracy of the sources) or known to be within + / -0.5 milliseconds of the actual GNSS time; and (3) the approximate location of the GNSS receiver. Using this initial set, the following can be performed: Figure 11 Operation 601 in the context of GNSS. In fact, this initial group provides an estimate of the system's GNSS time, enabling acquisition using GNSS time.

[0162] Another aspect of this disclosure relates to using only a subset (selected component) of two or four components of a GNSS signal during coarse time acquisition to first acquire that subset (such as only one of the four components), and then acquire the remaining components. In one embodiment, this selected component is chosen based on the lowest probability of signal variation due to symbol or phase inversion caused by the coding scheme used in that selected component. In the case of Galileo's E5 GNSS signal, the E5BI component has the lowest probability of signal variation due to symbol or phase inversion (see Appendix for a detailed description of the various probabilities for different signal components), and can therefore be used as the selected component to perform coarse or precise time acquisition before attempting to acquire and / or track the remaining components in the Galileo GNSS signal. Figure 13 An embodiment of the method using this aspect is shown, which uses only a subset of the components. The method can be derived from... Figure 13 Operation 801 is shown to begin; in operation 801, the GNSS processing system in the GNSS receiver receives a request for location information, such as a request from the application processing system. In operation 803, the GNSS processing system determines that a switch to a simplified acquisition mode is needed or desired; this need or desire may be triggered by the failure of a conventional acquisition attempt to acquire a complete set of GNSS signal components from a set of GNSS SVs in the GNSS receiver's field of view. For example, the GNSS may be unable to acquire the E5AI and E5AQ signal components from several SVs in the Galileo constellation within a predetermined time period. This failure may trigger the GNSS processing system to switch to a simplified acquisition mode, in which the GNSS processing system will attempt to acquire only selected components from each of the set of SVs in the field of view during the initial acquisition phase. In operation 805, the GNSS processing system attempts to acquire only the selected components; in one embodiment, this is the E5BI signal component, and the GNSS processing system may attempt to acquire this signal component from several GNSS SVs. In operation 807, if the GNSS processing determines that the selected component has not yet been acquired, the processing system can revert to operation 805 to continue attempting to acquire the selected component. In operation 807, if the GNSS processing determines that one or more selected components have been acquired, the GNSS processing system can proceed to operation 809 to acquire other components from the same SV; for example, in operation 809, the GNSS processing system can attempt to acquire other signal components from the same SV, such as E5BQ, E5AI, and E5AQ. In operation 809, the GNSS processing system can use the time and phase information obtained from the acquisition process of the selected component from each SV to facilitate the acquisition of other signal components. As the number of correlated components decreases, Figure 13The method shown can also be used as a way to acquire stronger satellites faster, allowing a portion of the GNSS acquisition engine to search for multiple SVs in a larger frequency space more quickly and with lower power compared to when more GNSS signal components are used.

[0163] Modern GNSS signals in the L5 band are susceptible to interference from air navigation radio (ARN) signals that are typically nearby, such as those from airports or military bases. One or more embodiments described herein (such as...) can be used... Figure 15A and 15B The embodiment shown in the figure is used to mitigate this interference.

[0164] exist Figure 15A In the illustrated embodiment, the GNSS receiver can receive both GNSS signals and ARN signals in the L5 band in operation 821. Typically, the GNSS receiver may include hardware capable of measuring signal levels (such as signal strength levels), which can be compared to a predetermined noise floor in operation 825. This predetermined noise floor may be fixed or dynamically adjusted over time, but in most cases, the GNSS signal from the GNSS SV will be below the noise floor. The noise floor can be set based on the known signal strength of the GNSS signal relative to the known signal strength of the ARN signal. When the GNSS receiver is near an ARN signal source (e.g., near an airport), the ARN signal will typically be above the noise floor. Therefore, operation 825 can be used to detect the presence of an ARN signal by comparing the received signal to the noise floor. In one embodiment, a predetermined threshold above the noise floor can be used such that the ARN signal must exceed this predetermined threshold (the predetermined threshold is above the noise floor) before operation 829 is used to remove the ARN signal. In one embodiment, the ARN signal can be detected during the signal acquisition phase using the DFT array processing technique described herein; in this embodiment, operation 829 can be invoked when the ARN signal is detected in the frequency domain. When the ARN signal is detected above the noise floor (or when the ARN signal is detected in the frequency domain), in operation 829, the GNSS processing system in the GNSS receiver can remove the ARN signal before the correlation processing of the GNSS signal. In one embodiment, the ARN signal can be removed using a finite impulse response (FIR) filter; the FIR filter can receive a signal containing both the GNSS signal and the ARN signal and provide a filtered output containing the GNSS signal (with a significantly reduced amount of ARN signal in the output). In another embodiment, an intermediate frequency (IF) bandpass filtering operation (e.g., at...) Figure 4D , 4FThe configurable notch filter used in the receiver architecture shown in 4J can be used to filter out ARN signals before GNSS correlation processing.

[0165] exist Figure 15B In the illustrated embodiment, known mitigation of interference signals (such as ARN signals) can be achieved by reducing the bandwidth of the GNSS radio receiver. Figure 15B An example of a method for narrowing the bandwidth to one of two sidebands in a GNSS signal is shown. In operation 835, a radio receiver can receive a GNSS signal and an ARN signal via one or more antennas. The GNSS signal may include two sidebands, such as the E5A sideband and the E5B sideband. In operation 839, the GNSS receiver can detect interference in one of the two sidebands caused by an interfering signal such as an ARN signal. In one embodiment, this detection can be performed by observing the input data spectrum at each of the upper and lower sidebands as the input data spectrum is received and processed every millisecond. This detection may involve detecting differences in the interference levels such that one sideband has little or no interference, while the other sideband has considerable interference. In response to this detection, the GNSS processing system in the GNSS receiver can be configured in operation 842 to process the sideband with less interference (such as less ARN interference) and not process (e.g., no related processing) the sideband with more interference. In this case, only one sideband is used to derive code phase measurements and determine position data, while the other sideband is not used to determine the position of the GNSS receiver. In one embodiment, the GNSS receiver can continue to monitor for interference and switch between using two sidebands in response to changes in interference; for example, if the GNSS receiver experiences greater interference in the upper sideband, it may initially use the lower sideband (so that GNSS signals from the lower sideband are processed while GNSS signals from the upper sideband are not processed to determine location), and then switch to using the upper sideband when the lower sideband experiences greater interference.

[0166] Single Hypothetical Memory

[0167] Another aspect of this disclosure relates to using a single hypothesis memory to accumulate or sum the amplitudes of code phase hypotheses for multiple signal components from the same GNSS SV (such as GNSS SVs in a Galilean constellation of GNSS satellites). This technique can improve sensitivity by summing the code phase hypotheses for, for example, the E5BI, E5BQ, E5AI, and E5AQ signal components from the same GNSS SV in a Galilean constellation of GNSS satellites. This accumulation can be performed incoherently when the time uncertainty is greater than 0.5 milliseconds (ms). This accumulation can also reduce the amount of memory used by the GNSS receiver.

[0168] Galileo E5 has four components: a data component and a pilot component in each of the two sidebands. GPS L5 has only two components: a data component and a pilot component, but only one sideband. BDS B2A and B2B also have four components: a data component and a pilot component in each of the two sidebands. QZSS has two components: a data component and a pilot component, but only one sideband.

[0169] Typically, each component has its own primary code and secondary code. For multiple components, it is also assumed that the number of bits in the primary code is the same across all components and that they are repeated simultaneously. It is assumed that the secondary code can change as each primary code is completed. The length of the secondary code does not need to be the same across each component, and generally each system has a secondary code of different length for each component. For modern signals, the chip rate is 10230 bits per millisecond.

[0170] Typically, the sampling clock is chosen to be close to twice the chip rate to minimize the worst-case loss (when the signal arrival time is the midpoint between two adjacent samples). A faster sampling rate (i.e., more than twice the chip rate) reduces this loss but increases the number of correlations to be performed and also increases the size of the integration memory. A slower rate (i.e., less than twice the chip rate) increases the loss but also reduces the number of correlations to be performed and also decreases the size of the integration memory. Generally, the average loss is considered more important than the worst-case loss.

[0171] The preferred embodiment has a sampling rate close to twice the chip rate, but also a rate that can be expressed as the product of N1 and N2, where N2 is a large power of 2, allowing the use of FFT to reduce the computation of DFT. Here, the sampling rate is chosen to be 20480 samples per millisecond, such that N1 = 20 and N2 = 1024. Another option is N1 = 5 and N2 = 4096, and N1 = 10 and N2 = 2048.

[0172] For two samples per chip, the worst-case loss occurs when the true arriving code phase is in the middle between the two samples. The correlation function is + / - 1 chip, and therefore there are 0.25 chips on each side of the true code phase. In this case, the correlation produces 75% correlation, resulting in a loss of approximately 2.5 dB. (0.75 = 1 - 0.5 / 2 = 1 - 0.25)

[0173] Another embodiment is N1 = 1 and N2 = 16384. This arrangement uses the largest possible FFT size, but is undersampled relative to the 2 samples per chip approach described above. Here we have 10230 / 16384 = 0.6244 chips / sample, or 1.6 samples per chip. The worst-case correlation is now 69% of the maximum: 0.69 = (1 - 0.624 / 2), and the worst-case loss is 3.25 dB, or the loss increases by only 0.75 dB. This configuration reduces the number of correlations by 25% and the integration memory by 25%.

[0174] Modern satellite broadcasting involves additional power across multiple component distributions. One method to improve sensitivity is to correlate more than one component of the same input sample data signal in parallel, and then sum the amplitudes or power of all individual components at each correlation hypothesis to the signal detection test. The signal information of all components at each code phase hypothesis is compressed into a single value by summation, which is integrated over each code phase hypothesis. In each frequency band to be searched, the number of code phase hypotheses is equal to the number of correlations for each primary code phase; for a sampling clock of 20.48 MHz and a primary code with 10230 chips per millisecond, the number of correlations is 20480.

[0175] At each code phase, each primary code sequence is tested at all possible candidate phases for each component. This can be optimally accomplished using a DFT implemented with an N1- and N2-point FFT; see, for example, [link to DFT implementation]. Figure 6-8 The embodiment shown here. This produces 20,480 amplitudes for each component.

[0176] There are two combinations: coherent or incoherent.

[0177] The preferred embodiment is a noncoherent combination because the time uncertainty is typically greater than 1 / 2 millisecond, making it impossible to predict the auxiliary code phase. Furthermore, the random data bit phase makes it difficult to predict the phase between the data and the pilot channel, even if the auxiliary code phase is known.

[0178] The magnitude of the complex correlation at the same code phase assumption is calculated for each component and added to a single value, which is then integrated into a single memory segment. Figure 14N An example of a hypothetical memory arrangement with multiple segments is shown; each of these segments can store the cumulative sum of the code phase hypothesis across several signal components. Power can also be calculated, but amplitude is preferred because fewer bits are required.

[0179] Typically, it is assumed that the memory is an integration memory. For each master code phase assumption, the new sum of the amplitudes of all components from the same GNSS SV in the current millisecond is added to the previous sum in the integration memory, and this current sum (running sum) overwrites the previous sum.

[0180] Summarize,

[0181] 1) At msec(k) and at each primary key phase assumption (j), form the correlation amplitude of the primary key (i) for each component:

[0182] a.AMP(i,j,k) = real(i,j,k) 2 +imaginary(i,j,k) 2 For i = 1, 4 and

[0183] j = 1,20480, and k = current msec, AMP(i,j,k) = real(i,j,k) 2 +imaginary(i,j,k) 2 ,

[0184] 2) For each code phase, the sum of the amplitudes (AMPs) formed at each component.

[0185] a.AMP_ALL(j,k)=sum{AMP(i,j,k)}, for i=1,4, at the kmsec-th position. That is, AMP_ALL(j,k)=AMP(1,j,k)+AMP(2,j,k)+AMP(3,j,k)+AMP(4,j,k), where i=1 is the E5A data channel component, i=2 is the E5A pilot channel component, i=3 is the E5B data channel component, and i=4 is the E5B pilot channel component.

[0186] 3) Retrieve the integration segment of the j-th code phase hypothesis in the previous (k-1) milliseconds.

[0187] aX(j,k-1)=INT_MEM(j,k-1)

[0188] 4) Add new amplitudes from all 4 components.

[0189] aX(j,k)=X(j,k-1)+AMP_ALL(j,k)

[0190] Store the updated current integral and X(j,k) back into the hypothesis memory of the j-th code phase hypothesis.

[0191] In this method described above, the number of memory segments is equal to the number of code phase assumptions, which is smaller than the case where there is an integral memory of similar size for each component.

[0192] Then, signal detection uses a single integration memory, so that there is no independent signal detection for each component. This test is typically:

[0193] The maximum integral memory value is obtained from the integral memory spanning 20480 hypotheses, and its corresponding memory index X for a specific phase is remembered, where each segment stores the current sum of the amplitudes of all primary code components at that code phase.

[0194] The mean and standard deviation of the noise floor are estimated from 20480-Y hypotheses, where Y is the integral memory value adjacent to the maximum value at code phase X. Here, Y = 7, which includes the maximum value at X, as well as the three integral memory samples before and after it. In this way, a total of seven samples are removed and ignored, making the noise floor statistics unaffected by the peak hypothesis.

[0195] Test the signal-to-noise ratio estimate to be higher than the threshold to set the false alarm rate.

[0196] test:

[0197] If SNR = 10 * log10((X 2 -noiseFloor 2 If the predefined threshold () / noiseVariance)>K, the false alarm rate will be set to an acceptablely small level. If this condition is met, the false alarm signal is found and integration is stopped. Otherwise, the false alarm signal is not found, and integration continues.

[0198] It should be noted that, based on the well-known relationship between the number of carrier cycles in a chip of the master code sequence, the carrier frequency generates the code Doppler. For E5a at 1176.45 MHz, there are exactly 116 carrier cycles per chip. This phase also has a negative rate. Therefore, long integration requires shifting the locally generated code by dividing the carrier frequency assumption by a rate of -116 chips per second, so that the code is kept corresponding to the initial code phase assumption at the start of integration.

[0199] Coherent integration of multiple components into a single hypothetical memory is also possible when both the auxiliary code phase and the data bit phase are known. This is feasible when fine-grained timing assistance is available and the data bit stream is observed from a second receiver and rapidly transmitted. This is only possible when data is repeated or known data is available, as is the case with communications like the Internet.

[0200] Besides the phase reversal from the auxiliary code sequence and the data sequence, signals in the same sideband have different but known 90-degree phase shifts between the data channel and the pilot channel. Due to the different carrier frequencies, signals in different sidebands have different phase shifts. However, the frequency shift of each sideband from the center channel is known because the Doppler shift has the same amplitude but different signs with respect to the center frequency. For example, if the E5 frequency Doppler is 1000 Hz, then the E5A Doppler is 992 Hz, and the E5B Doppler is 1008 Hz. The carrier phase difference alternates with opposite signs, but the amplitude is equal between the A and B sidebands. The known phase shift is applied to the complex correlation by multiplying by a complex exponent with the known phase. In this way, the real and complex components of all adjusted components can be added to a single complex correlation value. The amplitude or power is then integrated into a single hypothesis memory segment for each code phase hypothesis.

[0201] Frequency domain Doppler compensation

[0202] GNSS (Global Navigation Satellite System) signals are typically incorporating pseudo-random modulation (PRN) waveforms to enable accurate time-of-arrival measurements at the receiving terminal. Typically, the PRN waveform incorporates a repeating code whose duration is called the frame length. The received waveform is processed using signal processing structures such as correlator arrays and matched filters. This invention focuses on GNSS signal acquisition based on the Fast Fourier Transform (FFT) method, which efficiently implements a matched filter corresponding to the received signal. This method is particularly attractive when the spreading ratio (SR) of the PRN waveform is large, i.e., when the ratio of signal bandwidth to frame length is large. In many modern GNSS systems, this spreading ratio can exceed 10,000. FFT is a very efficient algorithm for computing the Discrete Fourier Transform (DFT), and although we always use the term "FFT", we by FFT refer to any method used to compute the DFT, including various FFT algorithms such as the Cooley-Tukey algorithm, the prime factor algorithm, the chirp z-transform algorithm, etc.

[0203] Capturing GNSS signals with high SR is difficult because the arrival time must be tested over a large set of time moments (e.g., more than 10,000 in the example above) and, in addition, over a large set of potential frequency offsets from the nominal hypothetical carrier frequency (the latter due to Doppler effects and local clock errors). Furthermore, testing must be performed on groups of possible satellite signals that exist. These groups of time moments, frequency offsets, and the number of satellite signals are called “hypotheses.” As can be seen from the above, capturing GNSS signals requires searching over a large three-dimensional hypothesis space. The use of the FFT method is very effective for performing time hypothesis searches because it can process each possible time hypothesis in parallel over the frame length. The FFT method performs a matched filtering operation on a set of incoming time samples by (1) performing a forward FFT on a set of incoming time samples to produce a set of “signal frequency samples”, (2) multiplying the signal frequency samples by the frequency samples of the PRN reference signal (called “reference frequency samples”), and (3) performing an inverse FFT on the result. Then, the output sample set is further accumulated with the previous output set to perform "coherent processing," or the output samples (usually by amplitude or amplitude squared operation) are detected and accumulated with the previous data set that has undergone similar processing. The accumulated processed data set is observed to look for the occurrence of large peaks above the background noise samples, where the location of such peaks indicates the arrival time of the incoming signal.

[0204] As indicated above, during the acquisition process, the incoming signal may have an associated carrier frequency offset, which must also be determined. Conventional methods for such determination involve assuming Doppler frequencies, compensating for Doppler in the time domain by multiplying the incoming sample set by a complex sine curve with the assumed frequencies to remove the Doppler components, and then performing the three steps described above. This process is performed for each of a set of assumed Doppler frequencies. In FFT implementations, the problem with this method is that it requires one forward FFT and one backward FFT for each assumed Doppler frequency. In many cases, a set of such assumed frequencies, numbering 20 or more, must be searched. These embodiments of the present invention reduce the number of such FFTs to approximately half or less of that required in the prior art methods described above, thereby reducing the total processing time by approximately half or less.

[0205] In the following discussion, we will refer to frequency uncertainty as “Doppler,” but frequency uncertainty can also be caused by local oscillator frequency errors. For simplicity, we will use the term “Doppler” for any type of frequency uncertainty, but when we do, we are actually referring to any source of frequency uncertainty, including possible errors on components of the GNSS transmitter. Furthermore, in the initial discussion below, for simplicity, we omit the multiplication of the forward FFT data with the reference frequency sample (as described above). In the first example in the following discussion, this is done just before performing the inverse FFT operation.

[0206] Refer to the following discussion Figure 16A This may be helpful. After the forward FFT (1101), considering the FFT output as a vector, if one were to rotate the vector by m positions (1102), this would be equivalent to a frequency shift equal to m × the segment spacing, where the segment spacing equals the sampling rate divided by the number of samples per FFT. Here, m is an integer, which can be positive for positive shifts or negative for negative shifts. If the input signal has a positive Doppler frequency shift, then to compensate, one would typically rotate the vector negatively, and vice versa. This has the effect of shifting the signal to near 0 frequencies or some other desired frequency. The advantage of this method is that after a forward FFT, one can test multiple Dopplers by a series of inverse FFTs, each inverse FFT following a frequency shift via the rotation operation. The data in the frequency domain is considered cyclic in the sense that the data sample after the last frequency sample is the data sample of the first frequency sample. Therefore, this is often referred to as rotation rather than shift. The invention also applies to normal shifts in which zeros are appended to the data as needed. For example, if 20 Doppler frequencies are tested in this manner, only one forward FFT and 20 inverse FFTs are needed, each inverse FFT targeting one of the Doppler frequencies to be tested. In this example, only 21 FFT operations are required, compared to 40 in the standard method. Operation 1102 is performed multiple times to provide a series of Doppler-compensated frequency vectors, each used for one of the Doppler segments being tested.

[0207] In many cases, examining the Doppler uncertainty region in increments of integer segment spacing is coarse, resulting in a worst-case loss of sinc(0.5) or 3.9 dB. To reduce this loss, it is desirable to perform a rotation of 1 / 2 segment spacing on the above vector, i.e., to perform the test for the Doppler frequency offset of segment m+1 / 2. This can be done in one of three ways.

[0208] In the first method, two forward FFTs are performed: one without modification and the second with a time-domain frequency shift equal to half the segment spacing, i.e., a frequency shift of sampling rate / (2′no_FFT_samples). This frequency shift is performed in the time domain by multiplying by a complex sine curve in the usual way (or using an equivalent algorithm such as CORDIC cyclic). Each of these forward FFTs is stored. To test the Doppler error for an integer number of segments, the first forward FFT vector is cyclicated with the required number of segments. To test the Doppler error incorporating half the segment spacing, a second forward FFT vector is selected and cyclicated with an appropriate integer number of segments. For example, if you want to test the Doppler error for m+1 / 2 segments (where m is an integer), i.e., you want a total compensation shift of -m-1 / 2 segments, the second forward FFT vector is cyclicated by -m-1 positions. Here we note that the second FFT data group incorporates a shift of +1 / 2 segment (by assumption), resulting in a total shift of -m-1 + 1 / 2 = -m-1 / 2. Of course, this technique also works if the data used before the second forward FFT is a segment offset by half the first frequency, or actually an offset of half a segment plus a positive or negative integer multiple. In this case, the data vector after the second forward FFT will need to be rotated with appropriate integers to achieve the required overall Doppler compensation.

[0209] The first method described above is very accurate, but it, of course, doubles the number of forward FFT operations. In the previous example, a total of 22 forward FFTs are required compared to 40 FFTs in the standard method, which is still a significant saving. However, another drawback is that twice the number of forward FFT vectors must be retained, which can be costly in terms of memory, especially when multiple parallel FFTs are needed to achieve the overall capture time.

[0210] refer to Figure 16A In the above discussion, switches (1109, 1110) pass data from the forward FFT through processing block 1102, but switches (1111, 1112) bypass block 1103 (interpolation operation). For alternative approaches to these embodiments, the switches are placed in other locations. Note that these "switches" are not necessarily hardware elements, but can be considered as flowchart decision paths.

[0211] A second method to achieve the 1 / 2 segment spacing offset is to use interpolation in the frequency domain on the forward FFT samples to construct intermediate samples from each original frequency sample with a 1 / 2 segment spacing. The vector of the intermediate samples then replaces the second forward FFT as described above. This intermediate sample vector also rotates the required number of positions to achieve the 1 / 2 segment spacing plus the required number of integer segments of Doppler frequency shift. Depending on the required complexity and accuracy, many different interpolation functions can be used to determine the intermediate samples. For example, a sinc interpolator, i.e., sin(2pf) / (2pf), where f is in units of segment spacing, can be used. Alternatives include polynomial interpolators, splines, etc. Typically, the most suitable interpolator can be determined empirically, as it depends on the frequency response of the time samples and the maximum complexity of the interpolator. By achieving the 1 / 2 segment spacing via either method, the worst-case loss due to Doppler error becomes -0.91 dB. This does not include any additional implementation errors (e.g., interpolation errors).

[0212] The above interpolation method can be used Figure 16A As can be seen in the diagram, switches 1111 and 1112 allow data transmission through interpolation vector block 103. If the frequency shift is not in the + / - 1 / 2 band, switches 1109 and 1110 can be used additionally.

[0213] In a third approach, interpolation is performed, but not in the frequency domain. Instead, the input set of data samples is augmented or "zero-padded" with additional frequency samples of zero values ​​appended to the beginning or end of the sample set. If the set of zero-value samples equals the original set, the FFT of the resulting augmented set will have an FFT with a spacing of half a segment relative to the FFT of the unaugmented set. Thus, a simple rotation of the FFT vector now provides a frequency conversion in either the positive or negative direction, similar to what was discussed above. A spacing of less than half a segment can be achieved by augmenting the original set with more zero-value samples (e.g., adding more than twice the number of zero-value samples would provide a spacing of one-third of a segment, etc.). The third approach has the disadvantage of requiring an FFT of twice the size or larger, and twice the storage space required to perform this processing. This may be less efficient than methods 1 and 2, although it may be competitive in some cases, especially for relatively small FFT sizes. Zero-padding can be... Figure 16A The step is considered an optional step at the input of block 1101, which is used to perform the FFT.

[0214] The choice between the first and second methods for testing Dopplers with m+1 / 2 segment spacing depends on the complexity of the interpolation and the storage requirements of the first method. In terms of computational speed, it is desirable for the interpolator method to use fewer operations per frequency sample than FFT. While the interpolation process appears computationally more efficient, a closer examination reveals this is not entirely clear, especially when only a few distinct Doppler frequencies are being searched. In terms of operations per data sample, FFT is very efficient. A radix-2 FFT of length N requires only approximately 2log2(N) real multiplications per data sample. For example, an FFT of size 1024 requires only approximately 20 real multiplications per data sample. An interpolator of equivalent complexity would have an interpolation filter with a length (number of taps) equal to 10, as it requires two real multiplications per frequency sample. Since frequency data tends to be very noisy, it is unclear whether such a short length is sufficient for the required accuracy. Note that even when using the first method, one can still advantageously employ the alternating vector block 1102 to reduce processing time when searching over a wide range of Doppler frequencies.

[0215] In addition to the m+1 / 2 segment spacing, the above method can also be extended to offsets of m+e segment spacing, where e is any number between 0 and 1. An additional forward FFT can be computed and stored for later use after the frequency transformation of the input data (corresponding to the amount of e segments), where this vector is used in conjunction with an appropriate number of vector position shifts. Alternatively, interpolation methods can be used to determine intermediate samples from any pre-computed FFT dataset (e.g., a set with 0 frequency offsets and 1 / 2 segment offsets). Again, there is a trade-off between the required more forward FFTs and the resulting increase in storage compared to the computational complexity of acceptable interpolation methods.

[0216] It should be clear from the above discussion that the three methods discussed above can be combined in various ways. For example, the third method can be combined with the second method to achieve very small segment spacing without the need for additional FFT operations.

[0217] In another aspect of these embodiments, corresponding to more than one received GNSS satellite signal, a set of Doppler frequencies can be tested for more than one PRN without performing additional forward FFTs. That is, as previously discussed, a forward FFT or several forward FFTs are performed on the data, and then a set of inverse FFTs are performed to test various Doppler shifts, all corresponding to a specific satellite signal, i.e., a specific PRN. As indicated above, as part of the overall processing, the frequency samples are multiplied with the frequency samples of the PRN reference signal. This occurs after the aforementioned Doppler shift operation. This is because the PRN frequency samples are assumed to have zero frequency shift. By using the corresponding frequency samples of these other PRNs, a similar set of inverse FFTs can be performed for other PRNs, and additional Doppler frequencies can be tested again without having to perform another forward FFT corresponding to these additional PRNs. In all the above methods, the frequency-changed data is multiplied with the reference data from 1105 in multiplication block 1104 and then processed by the inverse transform process 1106. The output can then be accumulated in 1107, either for pre-detection or detection. Finally, the accumulated data is examined to find strongly correlated peaks that indicate the arrival time of the GNSS signal via a specified Doppler and PN sequence. This, of course, is the case where reference generator 1105 generates a Fourier-transformed PRN sequence. Such a transformed sequence can be stored in memory for later use or calculated on the fly.

[0218] In another aspect of the invention, instead of alternating or shifting the frequency sample vector provided by the forward FFT of the signal samples, a similar operation can be performed on the frequency samples of the PRN reference signal. That is, Doppler compensation is performed on the PRN frequency samples instead of the signal frequency samples. This is in Figure 16B As shown in the middle diagram, switches 1209, 1210, 1211, and 1212 allow for similar... Figure 16A The discussion may involve rotation or interpolation, or both.

[0219] The problem with this method is that the product of the signal frequency sample and the Doppler-compensated PRN sample will no longer be at zero frequency, even if the assumed Doppler happens to be associated with the signal. Therefore, the inverse FFT will contain a frequency shift. To perform multiple coherent summs of these inverse FFT vectors, it may be necessary to first compensate for this frequency shift by multiplying with a complex sine wave to convert such a vector to zero frequency. However, the amplitude of the inverse FFT will remove the frequency shift component. Therefore, this method works well for applications that only perform incoherent summs of these inverse FFT vectors. The advantage of this method is that the Doppler-shifted PRN frequency samples can be pre-computed, thus eliminating any additional forward FFT of the signal data, as might be indicated by the previously mentioned method (using Doppler-shifted signal frequency samples). Of course, such prediction comes at a cost in terms of memory storage.

[0220] In the above description, we describe Doppler shift as vector rotation or cyclic rotation. For a small number of rotations, the loss is minimal when one can replace the rotation with a shift operation, in which one replaces samples near the beginning (or end) with samples of zero or other values, instead of rotating samples from the end of the vector to the beginning (or vice versa). The above method still works in this case, and the resulting performance of GNSS acquisition is almost unchanged. For example, if the frequency vector is rotated 5 segments in the positive direction, such a rotation will move the last 5 elements of the vector to the first 5 elements of the vector, which will be the 5 most negative frequency segments. If a shift is used instead, these first 5 segments will usually be replaced with zero-value data. In all cases, we call it "rotation" or "cyclic rotation," which also includes such a shift operation. Typical Doppler shift due to GNSS satellite motion is typically in the range of + / 5 kHz, and the typical PRN frame rate is 1 kHz. Therefore, Doppler shift due to satellite motion is typically in the range of + / - 5 FFT segments. Since the FFT size corresponds to the PRN length, which is typically over 1000, there are cases where frequency shifts and rotations produce similar results. We should also note that due to filtering of the input data, the amplitude of the frequency band edges in the FFT data tends to be low, making the edge effects associated with rotations or shifts generally minimal.

[0221] One or more embodiments may combine frequency rotation / interpolation methods with reference signal rotation / interpolation. For example, Figure 16A and 16B The embodiments in can be combined, such as Figure 16C As shown, switches are used to facilitate the manner and type of rotation and / or interpolation.

[0222] Of course, among all the methods described above, it may be possible to process data blocks using more than one PN reference (corresponding to more than one satellite signal) without having to perform multiple forward FFT operations. After the forward FFT operation, different PN sequences and different frequency assumptions can be used for the transformed data, and then each undergoes an inverse transform without additional forward FFT operations.

[0223] All previous cases were incorporated into the term-by-term multiplication of frequency data and reference data, inverse FFT, accumulation operation, and peak detection operation, such as... Figure 16A Blocks 1104, 1106, 1107, and 1108. Figure 16B 1204, 1206, 1207, 1208 and Figure 16C As shown in 1304, 1308, 1309 and 1310.

[0224] For clarity of terminology, we often use the general notation to refer to a set of samples (whether signal samples or reference samples) as a vector. When we say vector multiplication, the output is a vector of similar size; multiplication is the term-by-term multiplication of two vectors, sometimes called the "Hadamard product." We sometimes use the term "set of function samples," which can also be considered a vector. This multiplication may also involve complex operations on frequency samples or reference samples.

[0225] Receiver architecture examples

[0226] To achieve flexible and power-efficient sideband A or sideband B processing, numerous GNSS radio architectures have been proposed, modifying the overall frequency planning, filtering, ADC clocking, and subsequent decimation planning. This configuration allows for an optimal tradeoff between performance and power consumption. These architectures utilize varying degrees of digital circuitry, as described below.

[0227] Figure 4A This diagram illustrates the conventions used to describe the radio section of a GNSS receiver. These conventions relate to and distinguish the following radio architecture and distinguish the RF front-end components 1401, which tend to be external to integrated circuits; the mixed-signal section 1402, which may include switches, mixers, filters, amplifiers, and local oscillator circuitry; and the analog-to-digital converter (ADC) block 1403, which provides signal sampling and quantization functions. Any additional subsequent processing blocks are beyond this scope. Figure 4A The range of radio receivers defined in [the standard].

[0228] Figure 4BA typical IQ quadrature receiver architecture requiring significant analog circuitry is illustrated. The signal received by the antenna is passed through an RF front-end 1401, which provides low-noise amplification and filtering. The RF signal is then down-converted to baseband (zero IF or ultra-low IF) by a set of quadrature passive or active mixers 1404 and 1405, then low-pass filtered by a set of active low-pass filters (LPFs) 1406 and 1407 and quantized at a given sampling rate Fs by a set of quadrature ADCs 1408 and 1409. Quadrature local oscillator signals IQLO 1426 provide I-channel ILO and Q-channel QLO signals with a 90-degree phase difference, and each of them drives one branch of quadrature mixers 1405 and 1406. The IQLO frequency is derived by dividing the output frequency fPLL 1421 of the RF phase-locked loop (RF PLL) 1420 in a frequency divider D2 1425. The RF PLL 1420 synthesizes the output frequency fPLL 1421 based on the reference frequency fREF 1419 obtained from the crystal reference oscillator 1418. fREF 1419 is typically shared with other radio circuitry on the board of a given device. Note that the value of D2 can be 1 or higher. In this diagram, the frequency division function 1425 and the quadrature generation function 1427 are shown as two separate blocks. Depending on the actual design, they can be implemented in the same block (e.g., using a quadrature binary clock divider). Figure 4B The signals ILO and QLO shown are essentially the same signal, but with a 90-degree phase difference. The sampling clock at frequency Fs 1423 is also derived from the RF PLL 1420 via frequency division in 1422. The clock signal 1423 is also fed to the digital front-end block 1450 to aid in further processing of the digitized signal.

[0229] Frequency planning for IQ quadrature receivers is also underway. Figure 4C The graphs are shown below. Each graph is a frequency domain representation of the signal, with the horizontal axis in frequency units and the vertical axis showing the power spectral density or discrete spectral components. The first graph shows the spectrum of the desired signal at RF. The next graph shows the location of the ILO and the low-pass down-converted BB-I signal, with the low-pass filter response indicated by dashed lines. Similarly, the QLO and the down-converted low-pass Q-path signal BB-Q are also shown below.

[0230] Figure 4D The diagram illustrates the pair Figure 4BThe architecture is modified in that a switching mixer 1410 converts the RF signal at the output of the RF front-end 1401 into an intermediate frequency (IF) signal. The IF signal is then amplified and filtered using a continuous or discrete-time bandpass filter (e.g., N-channel) 1411, and then down-converted to a low-pass baseband using a set of quadrature mixers 1404 and 1405. This is then passed to a set of anti-aliasing active LPFs 1406 and 1407, which provide low-pass I and Q signals centered at low or zero IF to the quadrature ADCs 1408 and 1409 as described above. The receiver is time-synchronized via a single RF PLL 1420, and all clock and LO frequencies are derived by dividing the fPLL 1421 signal. The RF PLL 1420 synthesizes the output frequency PLL 1421 based on a reference frequency fREF 1419 obtained from a crystal reference oscillator 1418. The fREF 1419 is typically shared with other radio circuits on a given device. For increased flexibility, but at the cost of complexity and area, the RF-PLL 1420 can be implemented using a fractional-N divider. Divider D1 1422 provides the sampling clock Fs 1423, and divider D2 1425 provides the IQLO signal 1426 to the quadrature phase generator 1427. As mentioned above, the quadrature generation function 1427 can also be integrated with divider 1425. Alternative quadrature phase generation techniques include passive resistor-capacitor or inductor-capacitor circuits on the IQLO or RF paths, and are well known to those skilled in the art. The RF mixer 1410 is driven by the local oscillator signal RFLO 1428, which is generated by divider D3 1427. Note that D3 can take a value of 1 or higher.

[0231] Figure 4D Frequency planning for the mid-architecture architecture revolves around the following relationships:

[0232] 1) Intermediate frequency: IF = RFLO - RF (for high-side injection)

[0233] IF = RF - RFLO (for injection on the lower side)

[0234] 2) Baseband center frequency: fcBB = IF - IQLO (minimizes for extremely low IF and zero IF)

[0235] 3) RF local oscillator frequency: RFLO = fPLL / D3

[0236] 4) IQ local oscillator frequency: IQLO = fPLL / D2

[0237] 5) Sampling clock frequency Fs = fPLL / D1

[0238] 6) Harmonic relationship between RF and IF: IF = RF × M / L

[0239] 7) RF PLL frequency: fPLL=(N+J / K)×fREF (assuming fractional division - N-division)

[0240] fPLL = N × fREF (assuming an integer frequency division of N)

[0241] If RF is related to IF via the M / L factor, the following relationships can be derived algebraically: for high-side injection, RFLO = RF(1 + M / L), and for low-side injection, RFLO = RF(1 - M / L). Furthermore, since fPLL = (N + J / K) × fREF = RFLO × D3, therefore RFLO = (N + J / K) × x D3 × fREF. Additionally, in the case of zero-IF receiver frequency planning, IF = IQLO, and since RFLO, IQLO, and Fs are related to the fPLL harmonics via integer division, the following relationships can be derived between D2 and D3: for high-side injection, D2 = D3 × (L / M + 1), and for low-side injection, D2 = D3 × (L / M - 1). Figure 4D Frequency planning in medium architecture, such as Figure 4E As shown, the high-side RFLO injection is illustrated as an example.

[0242] The table below describes four frequency planning schemes related to a desired signal centered at 1191.795MHz. Each scheme has different RFLO, IF, and IQLO positioning. For example, Scheme A features a PLL frequency of 4×RFLO at 5952MHz and places the IF at 296.2MHz, or 1 / 4 of the desired RF center frequency. Similarly, Scheme B places the fPLL at 4×RFLO and the IF at 1 / 3 of the RF. Scheme C places the fPLL at 2×RFLO and the IF at 1 / 4 of the RF, while Scheme D places the fPLL at 2×RFLO and the IF at 1 / 3 of the RF. For each scheme, the table also lists the D2 and D1 divider values, the sampling frequency fS, and the baseband signal center frequency fcBB. The position of fcBB indicates how close the receiver operation is to the zero IF condition. In the following schemes, an integer N RF PLL is used with a reference frequency fREF of 19.2MHz. Using an integer N PLL causes a slight offset in fcBB, which can be eliminated by de-rotating the final digital down-converted baseband signal in the digital front end.

[0243] fDes fPLL D3 fRFLO IF / RF fIF D2 fIQLO D1 fS fcBB plan MHz MHz - MHz - MHz - MHz - MHz MHz A 1191.795 5952.00 4 1488.00 1 / 4 296.205 20 297.6 42 141.7143 -1.395 B 1191.795 6355.20 4 1588.80 1 / 3 397.01 16 397.2 48 132.4 -0.195 C 1191.795 2976.00 2 1488.00 1 / 4 296.21 10 297.6 24 124 -1.395 D 1191.795 3187.20 2 1593.60 1 / 3 401.81 8 398.4 24 132.8 3.405

[0244] Figure 4F The diagram shows Figure 4DA variant of the architecture shown is in which the analog LPF and mixer are replaced by an orthogonal sampling arrangement. The RF signal at the output of the RF front-end 1401 is down-converted by the mixer 1410 with the aid of the RFLO signal 1428, which is derived by dividing the fPLL signal 1421 by the divider D2 1427. The RF PLL 1420 synthesizes the output frequency PLL 1421 based on the reference frequency fREF 1419 obtained by the crystal reference oscillator 418. fREF 1419 is typically shared with other radio circuitry on a given device. For increased flexibility, but at the cost of complexity and area, the RF-PLL 1420 can be implemented using a fractional-N divider. The IF signal obtained at the output of the mixer 1410 is then amplified and filtered by a bandpass filter 1411, which serves as an anti-aliasing filter. The amplified and filtered IF signal is then sampled by an orthogonal ADC consisting of an I-channel ADC 1409 and a Q-channel ADC 1408. The quadrature sampling function is achieved through a 90-degree phase difference between the two sampling clocks, Fs-I and Fs-Q. This phase difference is obtained by a quadrature phase generator 1424, which is implemented as a divider-4 that can provide four different phases of the Fs signal. Note that by combining the divider D1 with the quadrature phase generator and the divider-4 1424, the effective sampling frequency Fs is derived from the signal fPLL 1421. Therefore, Fs is derived as fPLL / [D1×4]. The two quadrature sampling clocks, Fs-I and Fs-Q, are also provided to the digital front end 1450, and these two clocks are also synchronized with each other using the 4×Fs clock signal 1423. Figure 4F The architecture is better suited for digital implementations because the RF mixer can be implemented as a passive block with switches and resistors, while the BPF can be implemented as a discrete-time block with switches, resistors, and capacitors (e.g., an N-way filter). The larger division ratio of D1×4 (e.g., 8 or 12) also provides a greater number of different phase states, and therefore can produce better N-way filter resolution and suppression characteristics. Quadrature ADCs effectively resample the signal at the IF position.

[0245] Figure 4F Frequency planning for the mid-architecture architecture revolves around the following relationships:

[0246] Mid-frequency: IF = RFLO - RF (for high-side injection)

[0247] IF = RF - RFLO (for low-side injection)

[0248] RF local oscillator frequency: RFLO = fPLL / D2

[0249] Quadrature sampling frequency: Fs-I=Fs-Q=fPLL / (D1×4)

[0250] Harmonic relationship between RF and IF: IF = RF × M / L

[0251] RF PLL frequency: fPLL=(N+J / K)×fREF (fractional N divider)

[0252] fPLL = N × fREF (integer N divider)

[0253] If RF is related to IF via an integer N, the following relationships can be derived algebraically: for high-side injection, RFLO = RF(1 + M / L), and for low-side injection, RFLO = RF(1 - M / L). Furthermore, since fPLL = (N + J / K) × fREF = RFLO × D2, therefore RFLO = (N + J / K) × D2 × fREF. Moreover, since true zero-IF receiver frequency planning is preferred in this case, fractional PLL should provide the necessary flexibility in the synthesis of fPLL. Note that IF = Fs - I = Fs - Q, and since RFLO, Fs - I, and Fs - Q are related to fPLL harmonics via integer division, the following relationships can be derived between D1 and D2 after some algebraic operations: for high-side injection, D1 = D2(L / M + 1) / 4, and D1 = D2 × (L / M - 1) / 4.

[0254] A schematic diagram of the frequency domain processing in the above arrangement is also included. Figure 4G The diagram shows a high-side RFLO injection used as an example because it provides greater image rejection by low-pass filtering the input signal at the RF front end. The IF signal is anti-aliasing filtered, and the sampling clocks Fs-I and Fs-Q generate the digital baseband signals BB-I and BB-Q. Note that the BB-I and BB-Q signals are in discrete time compared to the signals before digitization, and therefore their frequency axes are defined as radian frequencies from -2π to +2π radians.

[0255] The table below describes four frequency planning schemes related to a desired signal centered at 1191.795MHz. Each scheme has different RFLO and IQLO positioning. For example, Scheme A features a PLL frequency of 5958.975MHz with a 4×RFLO and places the IF at a frequency of 297.949MHz, or 1 / 4 of the desired RF center frequency. Similarly, Scheme B places the fPLL at 4×RFLO and the IF at 1 / 3 of the RF. Scheme C places the fPLL at 2×RFLO and the IF at 1 / 5 of the RF, while Scheme D places the fPLL at 2×RFLO and the IF at 1 / 3 of the RF. Note that all the schemes below utilize a fractional N PLL, which ensures a zero baseband frequency offset, i.e., the receiver downconverts to zero IF. Slight baseband conversion frequency offsets may be observed when an integer PLL is required to be used with a given crystal oscillator frequency fREF. As mentioned above, these can be downconverted to zero DC offset.

[0256] fDes fPLL D2 RFLO IF / RF IF D1 fS plan MHz MHz - MHz - MHz - MHz A 1191.795 5958.975 4 1489.7438 1 / 4 297.949 20 297.949 B 1191.795 5720.616 4 1430.154 1 / 3 238.359 24 238.359 C 1191.795 2860.308 2 1430.154 1 / 5 238.359 12 238.359 D 1191.795 3178.12 2 1589.06 1 / 3 397.265 8 397.265

[0257] In yet another implementation, Figure 4H The sampling architecture for the GNSS system implementation described herein is illustrated. As previously stated, the RF front-end 1401 typically consists of discrete RF components (low-noise amplifiers and filters) and provides the filtered and amplified signal to the amplifier assembly BPF block 1411, which can be integrated into a SoC. Low-noise amplifiers and selective filters typically require inductors, which are expensive to integrate into the SoC and are usually located off-chip, especially if a fully digital manufacturing process is utilized. After the RF signal is adequately anti-aliased filtered through modules 1401 and 1411, it is sampled by the RF ADC 1460. The sampled signal is down-converted / mixed by the nearest sampling clock harmonic and processed by the digital front-end 1450, which includes complex down-conversion with complex multipliers, de-rotators, and similar modules to ultimately produce the digital complex quadrature baseband I1451 and Q1452 signals. Although... Figure 4H The architecture appears better suited for integration in digital CMOS processes, but it suffers from linearity and noise immunity issues. Anti-aliasing filtering is implemented via the BPF in block 1411, and it could be better integrated if implemented in discrete time (i.e., with some form of sample-and-hold circuitry preceding it). Mixed-signal techniques, such as N-channel filters, could also be used, although they operate at very high radio frequencies and at the cost of power consumption. One approach that saves power but requires a spectrally clean clock is double sampling, where a lower-frequency sampling clock creates many aliasing bands, thus downconverting a large amount of signal aliased by various sampling harmonics. The amplifier and the anti-aliasing filtering function in BPF 1411 are designed to ensure that unwanted aliasing components (including noise) are adequately suppressed. Figure 4I The diagram illustrates the frequency planning for a double-sampling arrangement. Two double-sampling schemes are considered. Scheme 1 uses a basic bandpass sampler that down-converts the RF signal to the lowest digital Nyquist band, while Scheme 2 uses a double-sampled harmonic to bandpass sample the RF signal and convert it to either the first image band or the lowest digital Nyquist band but with an inverted spectrum. Again, note that the digitized IF signals are defined in discrete time, therefore their frequency axes refer to radian frequencies from -2π to 2π.

[0258] In yet another implementation, Figure 4J The diagram illustrates the pair Figure 4H Improvements to the architecture Figure 4H The architecture suffers from low aliasing immunity due to limited selectivity and higher power consumption due to higher quality clock requirements. Similar to... Figure 4D In the architecture described, the RF signal from the antenna is passed through an external RF front-end 1401 with appropriate amplification and band filtering, and then enters a passive mixer 1410, which down-converts the signal to an intermediate frequency (IF) based on the RFLO signal. This RFLO signal is again derived by a division (in divider D2) of the fPLL signal 1421 originating from the RF PLL 1420. The IF signal at the output of the mixer 1410 is fed into an arrangement of amplification and bandpass filtering in an amplifier and BPF block 1411. The amplifier and BPF block 1411 ensure that sufficient low-noise anti-aliasing filtering is provided. It can also utilize discrete-time signal processing techniques, such as N-way filtering, which can be easily implemented in fully digital IC manufacturing processes. The filtered output IF signal is then resampled at an ADC 1460 operating at a rate of Fs 1423. This again simplifies the filtering implementation requirements as well as the ADC clock requirements. By filtering the IF signal, a favorable power-performance tradeoff can be achieved in the anti-aliasing filtering performance of the LNA and BPF block 1411, resulting in lower clock rates and power consumption, as well as better suppression characteristics. Furthermore, by resampling the IF signal, the ADC 1460 can now operate at a lower sampling rate while ensuring less aliasing and allowing for higher resolution and lower power consumption. Note that the large clock phase obtained through a divider including a factor of 4 can lead to further performance improvements in the N-way filters integrated into the amplifier and BPF block 1411. Figure 4J Frequency planning in medium architecture, such as Figure 4KAs shown. Consider the two schemes again. In Scheme 1, sampling and down-conversion employ a mechanism of secondary sampling via the higher Nyquist band of the base frequency. In Scheme 2, sampling and down-conversion employ a mechanism of secondary sampling via the lower image band of the secondary sampling harmonic. Note that the constraint of frequency fPLL 1421 being divided by dividers D1 1422 and D2 1427 optimizes the IF placement. For efficient IF down-conversion to baseband in the digital front-end 1450, it is best to position the IF at Fs / 4, 3Fs / 4, 5Fs / 4, 7Fs / 4, etc. Other positions such as Fs / 8, 7Fs / 8, 9Fs / 8, and 15Fs / 8 can also operate efficiently.

[0259] 52MHz wide Galileo E5 signal ( Figure 4O The spectrum shown presents interference immunity and power consumption challenges for GNSS receivers operating in this band. To mitigate interference and reduce power consumption, three general possibilities are identified for radio receivers:

[0260] (1) Optimal power consumption is achieved by selecting E5a+E5b or E5a or E5b signal processing through time-division (i.e., time-duplex / multiplexing) with adaptive duty cycle.

[0261] (2) Select E5a+E5b or E5a or E5b through RF or mixed signal filtering (i.e., frequency reuse).

[0262] (3) By using real mixing and appropriate local oscillator frequency positions, E5a is intentionally folded onto E5b (i.e., code domain multiplexing), or E5a is folded onto itself, or E5b is folded onto itself.

[0263] Besides using a duty cycle for the receiver based on interference suppression, power consumption on the analog / RF and digital front-ends can be reduced to varying degrees and, depending on the given architecture, by selecting or using different portions of the signal spectrum. Since the receiver can be tuned to either of the two sidebands, it can be operated in the following ways:

[0264] (1) The upper sideband (E5b) or lower sideband (E5a) is selected and processed at half the rate (20 × 1.023 MHz) compared to the full 52 MHz band. For example, the selection of the E5B sideband is as follows: Figure 4P As shown.

[0265] (2) The upper sideband (E5b) or the lower sideband (E5a) is selected and processed. In addition, the processing can be cyclical to achieve optimal power consumption.

[0266] (3) The upper sideband (E5b) is selected and the receiver switches to the lower (E5a) sideband if excessive DME / TACAN interference is detected. The reverse may also occur.

[0267] (4) The two sidebands are folded together by using the real mixing operation described below.

[0268] (5) By folding into itself and by using the real mixing operation described below, the upper sideband (E5b) or the lower sideband (E5a) is selected and processed at half the rate (20 × 1.023 MHz) and at half the low-pass bandwidth (e.g., 12 MHz).

[0269] The selection of E5a and E5b can occur in real time or in a predetermined manner as described above. For example... Figure 4B , 4D The radio receiver architectures shown in 4F allow for flexible processing by switching between double-sideband and single-sideband signals, while making performance and power trade-offs. Receiver configurations include appropriately changing the RFLO and IQLO frequencies, and, if applicable, modifying the passband of the filters.

[0270] Real mixing, by using a single mixer and placing the local oscillator frequency within the operating bandwidth of the desired signal, results in the bandpass desired signal being folded into itself. With the two sidebands E5a and E5b folded together, real mixing results in a form of code domain multiplexing. To illustrate this concept, Figure 4B The configuration of the radio architecture is as follows Figure 4L As shown, the quadrature mixer, LPF, and Q-path of the ADC are turned off. The local oscillator ILO 426 frequency is maintained at 1191.795MHz. Referring to the analysis shown in Appendix 3, at the output of mixer 405, the two sidebands E5a and E5b are converted to baseband and folded together, and E5a is spectrally inverted. The low-pass bandwidth of the folded signal in a single real path remains the same as before, i.e., 26MHz. Furthermore, the corner frequency of the anti-aliasing LPF 407 and the sampling rate of the ADC 409 remain the same as in the double-sideband case. Although it carries two folded sidebands, the resulting signal is not entirely in baseband, but rather centered at a frequency offset of 15.345MHz. At the digital front end, further processing downconverts the signal to zero frequency and despreads one or the other sideband. The processing gain is assumed to remain good on the inverse code. Since the mixer output noise increases by 3dB, this implementation assumes a reasonable SNR margin. This technique can also reduce receiver processing load and power consumption, especially... Figure 4B , 4D In the 4F architecture, because they are reconfigured to be respectively as Figure 4L , 4M Operate like 4N.

[0271] In real mixing, by folding a given sideband (E5a or E5b) onto itself, the local oscillator is positioned near the center of that sideband (1176.450MHz for E5a and 1207.140MHz for E5b), while simultaneously reducing the low-pass bandwidth to well less than 26MHz (because the effective bandwidth is now bilateral due to folding onto the negative frequency axis). Folding results in a 3dB SNR decrease, but the extended signal can still be retrieved because each sideband is extended by a pseudo-random code with sufficient coding gain. Depending on the frequency tracking loop bandwidth, small frequency offsets (e.g., 10kHz or greater) may need to be applied to the local oscillator signal so that the negative folded spectrum does not interfere with receiver synchronization. This technique results in a significant reduction in radio power, especially... Figure 4B , 4D In the 4F architecture, because they are reconfigured to be respectively as Figure 4L , 4M It operates in the same way as 4N. Furthermore, compared to full double-sideband operation, further interference immunity can be achieved by reducing the effective receiver bandwidth.

[0272] One way to save power during tracking is to use a single sideband, as this reduces the clock rate requirements in the digital front end and subsequent stages. In a particular implementation, during acquisition, the full double-sideband signal (E5a and E5b sidebands) is transmitted through a fully complex radio receiver (such as...). Figure 4B (As shown) the signal is processed, and a complex 52MHz bandwidth (2 × actual 26MHz bandwidth) is processed. The low-pass filter bandwidth, ADC clock, and decimation schedule are adapted to the wideband signal, as shown in the spectrum of the E5A or E5B signal. When the receiver enters tracking mode, the radio receiver... Figure 4L The configuration involves a single mixer handling 2 × 26MHz bandwidth, resulting in a 26MHz complex signal bandwidth shifted to 15.345MHz IF, but also carrying two sidebands that are folded together. As mentioned above, although Figure 4B The architecture in [the specific architecture] is particularly well-suited to this feature, but it is also applicable to other architectures. Specifically, Figure 4D The radio architecture described in [the document] can be as follows: Figure 4M Configuration in the middle. In addition... Figure 4F The radio architecture described in [the document] can be as follows: Figure 4N Configuration.

[0273] Figure 17An example of a method is shown that uses multiple signal components during acquisition and switches between subsets of these acquired signal components during tracking after successfully acquiring at least one signal component from a GNSS SV. This method can save power by reducing power consumption in the digital processing of the received GNSS signal and potentially (depending on the implementation) in the RF section of the GNSS receiver. Typically, the acquisition phase lasts only a short period, while the tracking phase lasts a longer period; reducing power consumption during tracking can significantly improve the performance of the GNSS receiver (at least in terms of its power consumption metrics). Now refer to... Figure 17 The method described in section 1701. In operation 1701, the GNSS receiver can begin acquiring GNSS signals; for example, the GNSS receiver can use one of the receiver architectures described above (e.g., Figure 4M (or 4N) to use, for example, the capture array processor described herein (e.g., see [link]). Figure 6-8To acquire GNSS signals, the receiver may attempt to acquire multiple GNSS signal components from one or more GNSS SVs during the acquisition phase of Operation 1703. For example, during the acquisition phase of Operation 1703, the receiver may attempt to acquire four signal components from GNSS SVs in the Galilean constellation (e.g., E5AI, E5AQ, E5BI, and E5BQ signal components from a specific SV in the Galilean constellation). Typically, the GNSS receiver (at least in a "cold start" scenario) will attempt to acquire multiple signal components from a sufficient number of GNSS SVs (e.g., at least four or five SVs) during Operation 1703 to allow for location determination. After one or more signal components have been acquired, as determined in operation 1705, the GNSS receiver may select or determine in operation 1707 a subset of the successfully acquired signal components to be tracked; therefore, instead of tracking all successfully acquired signal components (which are determined to have been successfully acquired in operation 1705), the GNSS receiver selects a subset of the successfully acquired signal components and tracks only the signal components in the subset in operation 1709. For example, if the GNSS receiver has acquired all four signal components from the first SV in the Galilean constellation (e.g., E5AI, E5AQ, E5BI, and E5BQ signal components from the first SV in the Galilean constellation) and has acquired two signal components from the second SV in the Galilean constellation (e.g., E5BI and E5BQ signal components from the second SV in the Galilean constellation), the GNSS receiver may choose during the tracking phase to track only one or all four signal components from the first SV and one of the two signal components from the second SV. Those unselected signal components will not be tracked, thus reducing power consumption in the GNSS receiver. The selection in operation 1707 can attempt to choose the "best" signal component to track, and some examples of possible selection criteria or algorithms are provided below. In one embodiment, "best" may be close to optimal rather than truly optimal, because being close to optimal can still reduce power consumption while still providing acceptable tracking.

[0274] One or more of the following algorithms can be used to select the optimal sideband:

[0275] 1) Sidebands with minimal interference. DME / TACAN will typically only be seen in one sideband. The best sideband is one without current DME interference. Later, in different regions, interference may dominate in different sidebands.

[0276] 2) It has the sideband with the most satellite launches. Currently, the lower sideband centered at 1176.45MHz has the most satellites: namely, the US L5, China B2a, Japan QZSS L5, and Europe E5a. Therefore, the upper sideband can be disabled after acquisition.

[0277] 3) The fringe containing the most visible satellites at the current time and location (determined by calculating the elevation angles of all launched satellites). Visible satellites have a positive elevation angle above the horizon, followed by non-zero obscuration angles (such as 10 degrees). At a given time, one fringe may contain more satellites than another.

[0278] 4) The sideband with the fastest data rate is used when the receiver has not yet determined the fine time. For example, the upper sideband of the B2 has a data rate of 1 kHz and the lower sideband has a data rate of 200 Hz, while the upper sideband of the E5 has a data rate of 250 Hz and the lower sideband has a data rate of 50 Hz. Faster decoding of timestamps allows for improved accuracy by learning the fine time.

[0279] 5) Several of these “best” sidebands can change dynamically, for example, starting with data decoding, then transitioning to the most visible, and then modulating in the case of interference.

[0280] 6) Sidebands containing satellites from a selected constellation required by a specific country, based on import regulations. For example, if Russia requires the use of Russian L5 satellites, and they are specifically placed in a sideband, then based on import requirements, that sideband would be the best single-track sideband.

[0281] Spoofing can be seen on one sideband but not on another. If the receiver can process each system independently, identify the spoofing (where the spoofing is identified using the independent positioning (fix) of a constellation), and the best sideband of the non-spoofing constellation is identified.

[0282] To reduce power consumption, tracking can be performed on the optimal sideband instead of multiple sidebands from the same GNSS SV. This means that RF and digital processing for non-optimal sidebands can be disabled, thus reducing power consumption. For example, RF mixers, filters, A2D, and digital front-ends can be disabled for these other sidebands. Baseband dependencies can also be disabled.

[0283] After capturing enough satellite SVs and determining at least one auxiliary code, a single fix allows for the determination of the remaining auxiliary codes, and thus allows for almost direct capture of the remaining satellites with a significantly narrower code search. In this case, the capture engine can be shut down. Tracking can be recovered from the system loss via coherent tracking of the pilot channel. Therefore, the additional sideband (which is not tracked) is not critical.

[0284] Exemplary embodiments

[0285] The following text presents the numbered embodiments in a claim-like format, and it should be understood that these embodiments may be presented as claims in one or more future filings, such as one or more continuations or divisions. Although individual embodiments are described in detail below, it should be understood that these embodiments may be combined or modified in whole or in part. At least some of these numbered embodiments were presented as claims in a previous provisional application.

[0286] Example 1: A system comprising:

[0287] A group of one or more application processors (APs) configured to execute an operating system (OS) and one or more applications, said group of one or more application processors being implemented in an integrated circuit (IC);

[0288] A group of one or more buses, coupled to the group of one or more APs, the one or more buses being on the IC;

[0289] A cache memory, on the IC and coupled to the set of one or more buses and the set of one or more APs, to store data for use by the OS and the one or more applications;

[0290] A bus interface, coupled to one or more buses, the bus interface coupling one or more APs to a dynamic random access memory (DRAM) external to the IC;

[0291] A GNSS processing system, implemented on the IC, comprising an acquisition engine AE and a tracking engine TE, the GNSS processing system being coupled to a shared memory via the one or more buses, the shared memory being one or both of the following: (a) the cache memory or (b) other memory on the IC;

[0292] A memory controller, coupled to the shared memory and the GNSS processing system, allocates a portion of the shared memory for use by the AE in response to one or more instructions from the operating system to allow GNSS signals to be captured.

[0293] Example 2: The system as described in Example 1, wherein the shared memory includes SRAM (Static Random Access Memory), and the AE includes ASIC hardware logic for performing Fast Fourier Transform (FFT) operations using a time-decimation method.

[0294] Example 3: The system as described in Example 2, wherein the GNSS processing system includes a dedicated memory separate from the shared memory and dedicated to the use of the GNSS processing system, and wherein the other memory is processor local storage for a processor that is not one of the one or more APs.

[0295] Example 4: The system as described in Example 1, wherein the memory controller includes a first port controller for controlling the reading and writing of the portion of the AE and a second port controller for controlling the reading and writing of the remaining portion of the shared memory.

[0296] Example 5: The system as described in Example 3, wherein the AE performs the acquisition of GNSS signals from one or more GNSS space vehicles (SVs), and the acquisition includes determining the frequency of the received GNSS signal containing a pseudo-random code to achieve tracking of the GNSS signal to generate a pseudorange to the GNSS SV as a result of the tracking.

[0297] Example 6: The system as described in Example 5, wherein the shared memory has a first port for use when the portion is allocated for use by the AE, and a second port for use by the processor or the one or more APs when the portion is allocated.

[0298] Example 7: The system as described in Example 5, wherein the allocated portion will store one or more of the following: (1) a pseudo-random code of GNSS SV or (2) an assumption of the identifiers of the potentially captured GNSS signals and an assumption of their frequencies.

[0299] Example 8: The system as described in Example 7, wherein after the GNSS processing system begins tracking GNSS signals already captured from at least three (3) GNSS SVs, the memory controller releases the portion.

[0300] The systems described in Examples 9 and 8 further include:

[0301] Antenna input, used to receive GNSS signals in the L5 WB band;

[0302] A low-noise amplifier (LNA) is coupled to the antenna input to amplify the GNSS signal;

[0303] A radio frequency analog-to-digital converter (ADC) is coupled to the output of the LNA. The radio frequency ADC and the LNA are used to receive and process GNSS signals in the L5 WB band, and the GNSS processing system is configured to process only GNSS signals in the L5 WB band.

[0304] Example 10: A system as described in Example 1, wherein one or more APs generate GNSS pseudo-random codes for at least GNSS SVs in the system's field of view before or during the acquisition phase, the generated GNSS pseudo-random codes being initially stored in the DRAM outside the IC and then copied to the shared memory during or at the start of the acquisition phase.

[0305] Example 11: A system as in Example 10, wherein the one or more APs generate the GNSS pseudo-random code in the background only for healthy GNSS SVs that are in the field of view or will be in the field of view for a period of time, and wherein the OS reserves a portion of the shared memory for use by the AE in response to the one or more APs receiving a request to provide location data.

[0306] Example 12: A method for an operating system, the method comprising:

[0307] A request to generate location data is received from one or more application processors (APs) on an integrated circuit (IC) by using a GNSS processing system on the IC, the GNSS processing system including an acquisition engine (AE) configured to acquire a plurality of GNSS signals, each of which is transmitted from one of the GNSS space carrier (SV) constellations;

[0308] A portion of the shared memory on the IC is identified and allocated for use by the AE in response to the request, while one or more other processors are allocated the remaining portion of the shared memory, the allocation being performed by an operating system running on the one or more APs or by firmware running on the IC;

[0309] The AE or one or more APs store data related to GNSS signal acquisition and processing in the allocated portion.

[0310] Example 13: The method as described in Example 12, wherein the shared memory includes SRAM (Static Random Access Memory) on the IC and the AE includes ASIC hardware logic for performing Fast Fourier Transform (FFT) operations using a time-decimation method.

[0311] Example 14: The method as described in Example 13, wherein the method further includes:

[0312] After the GNSS processing system begins tracking GNSS signals captured from at least three (3) GNSS SVs, the allocated portion is released in response to the GNSS signals being captured from at least three (3) GNSS SVs prior to the tracking phase.

[0313] Example 15: The method as described in Example 14, wherein the GNSS processing system includes a dedicated memory separate from the shared memory and dedicated to the use of the GNSS processing system.

[0314] Example 16: The method as described in Example 14, wherein the memory controller coupled to the shared memory includes a first port controller for controlling access to the allocated portion for the AE and a second port controller for controlling access to the remaining portion of the shared memory.

[0315] Example 17: The method as described in Example 14, wherein the AE performs the acquisition of a GNSS signal from a GNSS SV, and the acquisition includes determining the frequency of a received GNSS signal containing a pseudo-random code to track the GNSS signal to generate a primary code phase of the GNSS SV as a result of the tracking.

[0316] Example 18, the method as described in Example 17, wherein the allocated portion is used to store one or more of the following: (1) a pseudo-random code of a GNSS SV or (2) an assumption of the identifiers of potentially captured GNSS signals and an assumption of their frequencies.

[0317] Example 19: The method as described in Example 13, wherein one or more APs generate GNSS pseudo-random codes for at least GNSS SVs in the system's field of view before or during the acquisition phase, the generated GNSS pseudo-random codes being initially stored in DRAM outside the IC and then copied to the shared memory during the acquisition phase or in response to a location request.

[0318] Example 20: The method as described in Example 19, wherein one or more APs generate the GNSS pseudo-random code in the background only for healthy GNSS SVs that are in the field of view or will be in the field of view for a period of time, and wherein the system reserves the portion of the shared memory for use by the AE by determining the data stored in the non-volatile memory in the cache memory.

[0319] Example 21: A non-transitory machine-readable medium storing executable program instructions that, when executed by a data processing system, cause the data processing system to perform the method as described in any one of Examples 12-20.

[0320] Example 22: A data system, comprising:

[0321] A group of one or more application processors (APs) for executing the operating system and one or more applications;

[0322] A group of one or more buses coupled to the group of one or more application processors;

[0323] Dynamic random access memory (DRAM) is coupled to one or more application processors via one or more of the same set of buses;

[0324] A GNSS processing system is located on an integrated circuit IC, the IC including a cache memory located on the IC and coupled to the GNSS processing system, the GNSS processing system being coupled to a group of one or more application processors, the GNSS processing system including an acquisition engine (AE) and a tracking engine (TE);

[0325] The group of one or more application processors is configured to receive requests for location data and generate GNSS pseudo-random codes for the GNSS space vehicle (SV) for use by the AE. The generated GNSS pseudo-random codes are stored in the DRAM and then copied to the cache memory for use by the AE during the acquisition phase.

[0326] Example 23: The data processing system as described in Example 22, wherein the generated GNSS pseudo-random code is generated in response to the request.

[0327] Example 24: A data processing system as described in Example 22, wherein the cache memory includes SRAM (Static Random Access Memory) and the AE includes ASIC hardware logic for performing Fast Fourier Transform (FFT) operations using a time-decimation method.

[0328] Example 25: A data processing system as described in Example 24, wherein one or more APs generate GNSS pseudo-random codes for at least GNSS SVs in the field of view of the data processing system before or during the acquisition phase.

[0329] Example 26: A data processing system as described in Example 25, wherein one or more APs generate the GNSS pseudo-random code only for healthy GNSS SVs that are in the field of view or will be in the field of view for a period of time.

[0330] Example 27: The data processing system as described in Example 26, further comprising:

[0331] Antenna input, used to receive GNSS signals in the E5 band;

[0332] A low-noise amplifier (LNA) is coupled to the antenna input to amplify the GNSS signal;

[0333] A radio frequency analog-to-digital converter (ADC) is coupled to the output of the LNA, the radio frequency ADC and the LNA are used to receive and process GNSS signals in the E5 band, and the data processing system is configured to process only GNSS signals in the E5 band.

[0334] Example 28: A data processing system as described in Example 27, wherein the AE performs the acquisition of a GNSS signal from a GNSS SV, and the acquisition includes determining the frequency of a received GNSS signal containing a pseudo-random code to track the GNSS signal to generate a pseudorange to the GNSS SV as a result of the tracking, and wherein the generated GNSS pseudo-random code includes a GNSS pseudo-random code shifted in frequency or time or both to generate a code spectrum for use by the AE in the acquisition phase.

[0335] Example 29: A data processing system as described in Example 28, wherein during the capture of the AE, a portion of the allocated cache memory stores hypotheses of identifiers of potentially captured GNSS signals and hypotheses of their frequencies.

[0336] Example 30: A GNSS processing system, comprising:

[0337] Antenna input, used to receive GNSS signals in the E5 band;

[0338] A low-noise amplifier (LNA) is coupled to the antenna input to amplify the GNSS signal;

[0339] A radio frequency (RF) analog-to-digital converter (ADC) coupled to the output of the LNA, the RF ADC and the LNA being used to receive and process GNSS signals in the E5 band;

[0340] A circular memory buffer, coupled to the output of the RF ADC, is used to receive and store digitized GNSS sample data, the circular memory buffer storing digitized GNSS sample data for more than 1 millisecond and digitized GNSS sample data for less than 2 milliseconds.

[0341] Example 31: A GNSS processing system as described in Example 30, wherein the circular memory buffer stores the digitized GNSS sample data in an array of rows and columns, and the sample data is arranged in row order and also in time order, wherein 1 millisecond is the frame duration of the main code of the modernized GNSS signal, and the main code is further covered by a secondary code at a rate of 1 kHz.

[0342] Example 32: The GNSS processing system as described in Example 31 further includes:

[0343] A GNSS processor includes an acquisition engine and a tracking engine. The acquisition engine includes a set of DFT ALUs that process the digitized GNSS sample data in the array and produce intermediate outputs that do not require transposing the data in the array.

[0344] Example 33: A GNSS processing system as described in Example 32, wherein the first set of DFT ALUs in the set of DFT ALUs uses a time decimation method to generate the intermediate output stored in a variable memory, and the second set of DFT ALUs in the set of DFT ALUs uses the intermediate output to generate an output stored in an FFT result memory.

[0345] Example 34: The GNSS processing system as described in Example 33, wherein the cyclic memory buffer includes a first cyclic memory buffer for storing A sidebands in the E5 band and a second cyclic memory buffer for storing B sidebands in the E5 band.

[0346] Example 35: A method for processing GNSS signals in a GNSS receiver, the method comprising:

[0347] Determine an initial information set comprising at least two of the following: (1) the code phase of a primary or secondary code signal received from at least one GNSS space vehicle (SV); (2) an estimated GNSS time based on one or more time sources, said estimated GNSS time being estimated or known to be within + / - 0.5 milliseconds less than the actual GNSS time; and (3) the approximate location of said GNSS receiver.

[0348] Based on the initial information group, the expected fractional main code phase of the GNSS signal to be received is estimated;

[0349] The first DFT correlation is performed using at least the first complete master epoch of digitized GNSS sample data received within a time period corresponding to the time period of the GNSS signal's epochs, and the first FFT-based correlation uses the digitized GNSS sample data that begins at the first time.

[0350] The second DFT correlation is performed using at least a second complete epoch of the received digitized GNSS sample data, the at least second complete epoch of the digitized GNSS sample data including at least some of the received GNSS sample data in the first complete epoch, the second DFT correlation using digitized GNSS sample data starting at a second time, the second time being after the first time and offset from the first time by a period of time less than the epoch.

[0351] Remove the auxiliary code from the results of the first DFT correlation and the second DFT correlation to provide input for coherent integration.

[0352] Integrate at least one of these inputs into the coherent hypothesis memory;

[0353] The result from the coherent hypothesis memory is squared or its magnitude is taken to capture GNSS signals from at least one GNSS SV.

[0354] Example 36: The method as described in Example 35, wherein the I data and Q data are summed in each of the first and second complete code epochs.

[0355] Example 37, the method as described in Example 35, further includes: summing the squared results in the incoherent hypothesis memory, wherein the summation of the squared results occurs several milliseconds after the first time.

[0356] Example 38: The method as described in Example 35, wherein the method further includes:

[0357] A search order is established for GNSS signals from GNSS SV, the search order being at least partially based on the expected fractional primary code phase.

[0358] Example 39: The method as described in Example 35, wherein the method further includes:

[0359] A subset of the relevant hypotheses is selected within a window that includes the expected digital phase for storage in the coherent hypothesis memory.

[0360] Example 40: The method as described in Example 35, wherein the method further includes:

[0361] Among several factors, each SV is assigned to an input sample offset group based on the expected primary code phase of the SV.

[0362] Example 41: The method as described in Example 40, wherein the method further includes:

[0363] One SV is assigned to an estimated code epoch, and another SV is assigned to another estimated code epoch, wherein each SV is assigned to the code epoch of the code epoch that is closer to the SV in time.

[0364] Example 42: A method for processing GNSS signals, the method comprising:

[0365] Receive GNSS signals;

[0366] The received GNSS signal is digitized and an output of GNSS sample data is provided from the analog-to-digital converter (ADC), the output including at least one of the following: (1) GNSS sideband A sample data of the received GNSS signal and (2) GNSS sideband B sample data of the received GNSS signal;

[0367] Calculate at least one of the following: (1) a first set of DFTs of the GNSS sideband A sample data to provide a first set of results and (2) a second set of DFTs of the GNSS sideband B sample data to provide a second set of results;

[0368] Calculate at least one of the following: (1) a third DFT for the GNSS sideband A main PRN code data with code Doppler and carrier Doppler adjusted prior to the third DFT, the GNSS sideband A main PRN code data including at least one of two components in GNSS sideband A, the third DFT providing a third result; and (2) a fourth DFT for the GNSS sideband B main PRN code data with code Doppler and carrier Doppler adjusted prior to the fourth DFT, the GNSS sideband B main PRN code data including at least one of two components in GNSS sideband B, the fourth DFT providing a fourth result;

[0369] Calculate at least one of the following: (1) use the DFT of the complex conjugate of the product of the first set of results and the third set of results to calculate the first set of correlations to provide the fifth set of results, and (2) use the DFT of the complex conjugate of the product of the second set of results and the fourth set of results to calculate the second set of correlations to provide the sixth set of results;

[0370] Integrate at least one of the following: (1) the integration of the fifth set of results with at least one prior sum for GNSS sideband A, (2) the integration of the sixth set of results with at least one prior sum for GNSS sideband B, wherein such integration includes at least one of the following: (1) storing at least one new sum for the GNSS sideband A component in a single hypothetical memory, and (2) storing at least one new sum for the GNSS sideband B component in the single hypothetical memory.

[0371] Example 43: The method as described in Example 42, wherein the fourth set of results includes the IDFT results of the two components of the GNSS sideband A, and the sixth set of results includes the IDFT results of the two components of the GNSS sideband B.

[0372] Example 44: The method as described in Example 43, wherein the GNSS sideband A sample data is stored in a first circular memory buffer, and the GNSS sideband B sample data is stored in a second circular memory buffer.

[0373] Example 45: The method as described in Example 44, wherein the GNSS sideband A sample data is stored in a first circular memory buffer in an array format of rows and columns, and the GNSS sideband B sample data is stored in a second circular memory buffer in the same array format of rows and columns.

[0374] Example 46, the method as described in Example 45, wherein the GNSS sample data is processed to separate the GNSS sideband A sample data from the GNSS sideband B sample data by: (1) for the GNSS sideband A, shifting the sample centered at a first frequency upward by a first offset frequency, performing a low-pass filter to capture a first bandwidth of the data, and decimating the output of the low-pass filter to a lower sampling rate; and (2) for the GNSS sideband B, shifting the sample centered at the first frequency downward by a first offset frequency, performing a low-pass filter to capture a second bandwidth of the data, and decimating the output of the low-pass filter to a lower sampling rate.

[0375] Example 47: The method described in Example 45, wherein the computation operation does not require a separate operation to transpose or rearrange the sample data or generated code spectrum data at the inputs of the first and second sets of correlations.

[0376] Example 48: The method as described in Example 45, wherein the code generator generates at least one of the following: (1) GNSS sideband A main PRN code data per millisecond while the GNSS signal is being acquired and tracked, and the GNSS sideband A main PRN code data is not stored after the Fourier transform; and (2) GNSS sideband B main PRN code data per millisecond while the GNSS signal is being acquired and tracked, and the GNSS sideband B main PRN code data is not stored after the Fourier transform.

[0377] Example 49: The method as described in Example 48, wherein the integration is incoherent during at least a portion of the acquisition phase when the GNSS signal is received.

[0378] Example 50: A system for processing GNSS signals, the system comprising:

[0379] Radio frequency analog-to-digital converter (ADC) is used to generate a digital representation of the received GNSS signal;

[0380] A baseband sample memory is provided for storing the digital representation of a received GNSS signal as digitized GNSS sample data. The baseband sample memory is configured to store an array of the digitized GNSS sample data in N2 rows and N1 columns. The digitized GNSS sample data in the array is stored in row order in the baseband sample memory, and N2 is greater than N1. The row order includes the digitized GNSS sample data received during a time period including a first time period and a second time period, such that the first row in the row order contains the digitized GNSS sample data received during the first time period, and the second row after the first row in the row order contains the digitized GNSS sample data received during the second time period after the first time period. The baseband sample memory is coupled to the radio frequency ADC.

[0381] A set of arithmetic logic units (ALUs) is configured to perform Discrete Fourier Transform (DFT) operations. The set of ALUs is coupled to the baseband sample memory and configured to execute N1 DFTs in parallel and simultaneously in time. Each of the N1 DFTs contains N2 points from the DFT, and the outputs of the N1 DFTs are stored in a partial result sample array. The set of ALUs is then configured to execute N2 DFTs, each of the N2 DFTs containing N1 points from the partial result sample array, providing outputs stored in a column-ordered array of DFT result data.

[0382] Example 51: The system as described in Example 50, wherein the baseband sample memory is configured as a circular memory buffer to store the array.

[0383] Example 52: The system as described in Example 51, wherein the N1 DFTs use the same operations and the same program control instructions for the set of ALUs to operate on different data.

[0384] Example 53: The system as described in Example 52, wherein the N2 DFTs are executed sequentially over time, and wherein the circular memory buffer stores more than one frame of pseudo-random GNSS code, the more than one frame of pseudo-random GNSS code being greater than 1 millisecond.

[0385] Example 54: The system as described in Example 52, wherein the N1 DFTs and the N2 DFTs use a time decimation method, and wherein N1 is one of the following integer values: 5, 10, 20, or 40.

[0386] Example 55: The system as described in Example 52, wherein the change from row order to column order avoids a reordering algorithm, the change being generated by a combination of the N1 DFTs and the subsequent N2 DFTs.

[0387] Example 56: The system as described in Example 52, wherein a GNSS code generator is configured to generate GNSS codes, and a set of ALUs performs a set of DFTs on the GNSS codes to provide code spectrum result data stored in column order in a code spectrum memory, the code spectrum result data including GNSS PRN code data offset by frequency and / or time.

[0388] Example 57: The system as described in Example 56, wherein a set of ALUs is configured to multiply the code spectrum result data by the output stored in the DFT result array to produce a product array.

[0389] Example 58: The system as described in Example 57, wherein a set of ALUs is configured to perform an inverse DFT on the product array using a frequency decimation method.

[0390] Example 59: The system as described in Example 58, wherein the inverse DFT comprises: (1) in a first stage, N2 DFTs having conjugate inputs, each of the N2 DFTs containing N1 points, and (2) in a second stage following the first stage, N1 DFTs, each of the N1 DFTs containing N2 points.

[0391] Example 60: The system as described in Example 51, wherein the baseband sample memory is a dual-port memory.

[0392] Example 61: The system as described in Example 56, wherein when needed during the acquisition phase, the GNSS code generator generates a pseudo-random code every millisecond for each GNSS SV in the field of view, and does not store the generated pseudo-random code after use, and the generated pseudo-random code is used to generate the GNSS code spectrum.

[0393] Example 62: The system as described in Example 61, wherein the GNSS code spectrum is in-situ aligned in both frequency and phase in the memory to match the code phase assumption and frequency shift assumption associated with the received GNSS signal.

[0394] Example 63: The system as described in Example 62, wherein the alignment is performed by CORDIC hardware.

[0395] Example 64, a system as in Example 50, wherein the digitized GNSS sample data is stored in column order rather than row order.

[0396] Example 65: A system for processing GNSS L5 band signals, the system comprising:

[0397] Radio frequency analog-to-digital converter (ADC) is used to generate a digital representation of the received GNSS signal;

[0398] A baseband sample memory for storing the digital representation of the received GNSS signal, the baseband sample memory being coupled to the ADC;

[0399] A GNSS processing system, coupled to the baseband sample memory, to process the digital representation of the received GNSS signal, the GNSS processing system being configured to process four GNSS signal components of the GNSS signal to incoherently integrate all four GNSS signal components to generate incoherent integrated data for each of the four GNSS signal components and store the incoherent integrated data in a single hypothetical memory to capture the GNSS signal.

[0400] Example 66: The system as described in Example 65, wherein the single hypothetical memory is a memory of less than 2 megabytes, and wherein the four GNSS signal components include Galileo E5AI signal components, Galileo E5BI signal components, Galileo E5BQ signal components, and Galileo E5AQ signal components, or four GNSS signal components for the BeiDou B2 system, or both Galileo E5 and BeiDou B2 signal components.

[0401] Example 67: The system as described in Example 66, wherein the GNSS processing system processes GNSS signals received from at least two GNSS constellations, the at least two GNSS constellations including: the Galileo E5 constellation of GNSS SV; the L5 GPS constellation of GNSS SV; the GLONASS K2 constellation of GNSS SV; the QZSS constellation of GNSS SV; and the BeiDou B2 constellation of GNSS SV.

[0402] Example 68: The system as described in Example 65 further includes:

[0403] A code generator is used to generate GNSS PRN codes during the acquisition and tracking of GNSS signals, but does not store the GNSS PRN codes after tracking is completed.

[0404] Example 69: The system as described in Example 68, wherein the code generator generates more than two master PRN code points in one clock cycle during the acquisition and tracking.

[0405] Example 70: The system as described in Example 69, wherein for a given GNSS constellation and GNSS signal components in that GNSS constellation, the code generator generates more than two primary PRN code points in one clock cycle by calculation using a calculated code advance matrix derived from an N-fold multiplication of a code polynomial matrix, where N represents the number of primary PRN code points generated in one clock cycle.

[0406] Example 71: The system as described in Example 70, wherein the GNSS processing system shares memory with one or more processors, and the GNSS processing system, the cache memory, and the one or more application processors are all arranged on the same single integrated circuit.

[0407] Example 72: A system as described in Example 71, wherein the GNSS processing system includes an acquisition engine and a tracking engine, and the acquisition engine includes processing logic for receiving an array of GNSS sample data arranged in row or column order according to the reception time, and the acquisition engine includes processing logic for performing a DFT on the GNSS sample data array using a time decimation algorithm to produce a frequency domain result, the frequency domain result being multiplied by the code spectrum of the GNSS PRN code of the GNSS SV in the field of view, and then the product of the resulting frequency domain result and the code spectrum is processed by an IDFT using a frequency decimation algorithm in the processing logic to generate hypotheses of possible captured GNSS signals, the hypotheses being incoherently accumulated in a single hypothesis memory.

[0408] Example 73: The system as described in Example 72, wherein the GNSS sample data array is stored in two circular memory buffers, the two circular memory buffers including a first circular memory buffer for storing A-band GNSS sample data and a second circular memory buffer for storing B-band GNSS sample data, wherein multiple GNSS constellations can be received in at least one of the frequency bands.

[0409] Example 74: The system as described in Example 70, wherein before applying a set of DFTs using a time-decimation algorithm, the GNSS master PRN code from the output of the code generator is shifted in frequency and in time to generate a code spectrum, which is multiplied by the frequency domain result of a set of DFTs performed on the received GNSS signal using a time-decimation algorithm.

[0410] Example 75: The system as described in Example 73, wherein the GNSS master PRN code from the output of the code generator is shifted in frequency and in time to generate the code spectrum.

[0411] Example 76: In the system of Example 72, the order in the array is changed by the sequence of the DFT, such that no transposition or rearrangement of the data is required when the IDFT is performed.

[0412] Example 77 is a system like that of Example 76, wherein the sequence of DFTs avoids using memory or processing resources that would otherwise be used for the transpose or rearrangement.

[0413] Example 78: A system for processing GNSS signals; the system includes:

[0414] An analog-to-digital converter (ADC) is used to generate a digital representation of a received GNSS signal;

[0415] A baseband sample memory for storing the digital representation of the received GNSS signal, the baseband sample memory being coupled to the ADC;

[0416] A GNSS processing system, coupled to the baseband sample memory, processes the digital representation of the received GNSS signal. The GNSS processing system captures up to four GNSS signal components by incoherently integrating up to four GNSS signal components over a period of time in an array processing system located in the capture engine of the GNSS processing system. The array processing system receives GNSS sample data from the baseband memory, and the GNSS sample data is formatted as a row and column array having multiple rows and multiple columns.

[0417] Example 79: The system as described in Example 78, wherein the array processing system includes processing logic that performs a set of DFTs using a time decimation algorithm and then performs a set of inverse DFTs using a frequency decimation algorithm.

[0418] Example 80, the system as described in Example 79, wherein the output from the array processing system provides a frequency and a GNSS SV identifier for storage in a hypothesis memory to integrate hypotheses about GNSS signals.

[0419] Example 81: The system as described in Example 78, wherein the array processing system receives GNSS sample data in a first order and generates output in a second order different from the first order, wherein the first order is one of the row order or column order in the row and column array, and the second order is one of the row order or the column order, and wherein the first order and the second order are based on the reception time of the GNSS sample data.

[0420] Example 82, the system as described in Example 81, wherein the GNSS sample data is stored in the row and column arrays in two circular memory buffers, the two circular memory buffers including a first circular memory buffer for storing a first GNSS signal component from the GNSSSV sample data and a second circular memory buffer for storing a second GNSS signal component from the GNSSSV sample data, the first circular memory buffer and the second circular memory buffer being coupled to the array processing system.

[0421] Example 83: A system for processing GNSS signals, the system comprising:

[0422] A memory for storing the master code seed of GNSS signals from one or more GNSS constellations GNSS SVs and storing a representation of the master code polynomial data for generating master PRN codes for the GNSS signals;

[0423] A code generator, coupled to the memory, is used to receive the master code seed and the master code polynomial data, and to generate more than two master PRN code points in a single clock cycle using the master code seed and the master code polynomial data during the acquisition and tracking of the GNSS signal.

[0424] Example 84: The system as described in Example 83, wherein for a given GNSS constellation and GNSS signal components in that GNSS constellation, the code generator generates more than two primary PRN code points in a single clock cycle by calculation using a pre-computed code advance matrix derived from an N-fold multiplication of the primary code polynomial matrix, where N represents the number of primary PRN code points generated in one clock cycle.

[0425] Example 85: The system as described in Example 84, wherein the system generates the master PRN code points without storing the master PRN code points after tracking is completed or after the DFT transformation of the current master code epoch is completed.

[0426] Example 86: The system as described in Example 84, wherein the calculated code advance matrix is ​​pre-computed and stored in the memory before capture begins, and wherein N represents the code advance amount provided by the code generator between clock cycles.

[0427] Example 87: The system as described in Example 84, the system further comprising:

[0428] A GNSS processing system, coupled to the code generator, captures at least two GNSS signal components of a GNSS signal by incoherently integrating at least two of the four GNSS signal components over a period of time in an array processing system, the array processing system receiving GNSS sample data from a baseband memory, and the GNSS sample data being formatted as a row and column array having multiple rows and columns.

[0429] Example 88, the system as described in Example 87, wherein the generation of GNSS PRN codes by the code generator is dynamic, based on the GNSS SV in the field of view during the acquisition and tracking of the GNSS signal.

[0430] Example 89: The system as described in Example 88, wherein the GNSS master PRN code from the output of the code generator is shifted in frequency and time to generate a code spectrum, which, together with the frequency result of the DFT of the received GNSS signal, is used in the DFT.

[0431] Example 90: A GNSS receiver, comprising:

[0432] A radio frequency (RF) receiver, comprising at least one first RF filter and a low-noise amplifier (LNA) tuned to the L5 WB band only to receive L5 WB GNSS signals;

[0433] An analog-to-digital converter (ADC) is coupled to the LNA to generate GNSS sample data stored in a baseband sample memory, wherein the RF receiver is the only GNSS receiver among the GNSS receivers.

[0434] Example 91: A GNSS receiver as described in Example 90, wherein the RF receiver does not include an amplifier for GNSS signals other than the L5 WB band, and wherein the RF receiver includes a first RF filter coupled to a GNSS antenna, the output of the first RF filter being coupled to the input of the LNA, and the output of the LNA being coupled to a second RF filter.

[0435] Example 92: A GNSS receiver as described in Example 91, wherein the input of a first amplifier is coupled to the output of a second RF filter, and the output of the first amplifier is coupled to the ADC, wherein the LNA and the first RF filter are arranged on a first IC, and the ADC and the first amplifier are arranged on a second IC.

[0436] Example 93: A GNSS receiver as described in Example 92, wherein the GNSS receiver further includes:

[0437] The sideband separation converter separates GNSS sideband A sample data from GNSS sideband B sample data; and the second RF filter is arranged in the first IC.

[0438] Example 94: The GNSS receiver as described in Example 93 further includes:

[0439] A first circular memory buffer is used to store the GNSS sideband A sample data; and

[0440] The second circular memory buffer is used to store the GNSS sideband B sample data.

[0441] Example 95: A GNSS receiver as described in Example 94, wherein the RF receiver does not include an RF mixer.

[0442] Example 96: A GNSS receiver as described in Example 95, wherein the RF receiver does not include an RF reference local oscillator, and wherein the GNSS antenna is tuned to the L5 WB band only.

[0443] Example 97: A GNSS receiver as described in Example 95, wherein the sideband separation downconverter generates GNSS sideband A sample data arranged in a first array of rows and columns, and generates GNSS sideband B samples arranged in a second array of rows and columns.

[0444] Example 98: A GNSS receiver as in Example 95, wherein the RF receiver is tuned to receive a GNSS signal centered at 1191.795 MHz, and the L5 WB GNSS signal has a chip rate of 10.23 MHz.

[0445] Example 99: A GNSS receiver as in Example 97, wherein the GNSS antenna is the only GNSS antenna in the GNSS receiver, and wherein the RF receiver is tuned to receive a GNSS signal centered at 1191.795MHz, and the L5 WB GNSS signal has a chip rate of 10.23MHz.

[0446] Example 100: A system for processing GNSS signals, the system comprising:

[0447] Analog-to-digital converter (ADC) is used to generate a digital representation of GNSS signals received in the L5 WB GNSS band;

[0448] A baseband sample memory for storing the digital representation of the received GNSS signal, the baseband sample memory being coupled to the ADC;

[0449] A GNSS processing system, coupled to the baseband sample memory, for processing the digital representation of the received GNSS signal, the GNSS processing system being configured to receive and process at least one of the four GNSS signal components of the L5 WB band GNSS signal without using the L1 GNSS signal.

[0450] Example 101: A system as described in Example 100, wherein the system comprises only a single GNSS antenna tuned to the L5 WB band centered at 1191.795 MHz, and the received GNSS signal has a chip rate of 10.23 MHz or a chip rate significantly higher (e.g., more than twice) than the L1 GPS chip rate of 1.023 MHz.

[0451] Example 102, the system as described in Example 101, wherein the baseband sample memory stores the digital representation in an array of rows and columns arranged according to the reception time.

[0452] Example 103: The system as described in Example 101, wherein the baseband sample memory stores the digital representation in an array of rows and columns arranged according to the reception time.

[0453] Example 104: The system as described in Example 102, wherein the GNSS processing system processes the received GNSS signal by a sequence of DFTs, the sequence of DFTs including a first set of DFTs using a time decimation method and then a second set of DFTs using a frequency decimation method, without requiring transposition or rearrangement of the data in the array containing the data.

[0454] Example 105: The system as described in Example 100, wherein an initial signal is captured in a coarse time capture mode, further signals are captured in a precise time capture mode, and all signals are tracked in a tracking mode.

[0455] Example 106: The system as described in Example 105, wherein capture-specific hardware usage is reduced when in coherent tracking mode.

[0456] Example 107: The system as described in Example 65, wherein the GNSS processing system does not receive and capture L1 GNSS signals.

[0457] Example 108: The system as described in Example 78, wherein the GNSS processing system does not receive and capture L1 GNSS signals.

[0458] Example 109: A GNSS receiver, comprising:

[0459] Input, coupled to the antenna;

[0460] RF front end, coupled to the input;

[0461] An ADC converter, coupled to the RF front end;

[0462] A GNSS processing system coupled to the ADC converter receives GNSS signals from the ADC converter, wherein the GNSS processing system captures only selected components of the GNSS signals during an initial acquisition phase, the selected components having a low probability of signal variation relative to the probability of signal variation of other components of the GNSS signals, based on the coding scheme used in the selected components.

[0463] Example 110: A GNSS receiver as described in Example 109, wherein after the initial acquisition phase, the GNSS processing system acquires other components of the GNSS signal.

[0464] Example 111: A GNSS receiver as described in Example 110, wherein the selected component is the E5BI component of the SV in the Galileo constellation of GNSS satellites, and the other components include one or more of the following: the E5BQ component, the E5AI component, and the E5AQ component from the same SV.

[0465] Example 112: A GNSS receiver as described in Example 110, wherein the signal change is a sign inversion in the coding scheme of the selected component.

[0466] Example 113: A GNSS receiver as described in Example 110, wherein the initial acquisition phase is one of acquisition using coarse time or acquisition using precise time.

[0467] Example 114: The GNSS receiver as described in Example 110, wherein the initial acquisition phase is performed after a set of other components of the GNSS signal has failed to be acquired within a predetermined time period.

[0468] Example 115: A method for operating a GNSS receiver, the method comprising:

[0469] Switch to simplified capture mode, in which only selected components of the GNSS signal from the SV in the GNSS constellation are captured during the initial capture phase;

[0470] The selected component is captured, and relative to the signal variation probabilities of other components in the GNSS signal from the SV, the selected component has a low signal variation probability based on the coding scheme used in the selected component.

[0471] After capturing the selected component, the other components are captured.

[0472] Example 116: The method as described in Example 115, wherein the selected component is the E5BI component of the SV in the Galileo constellation from the GNSS satellite, and the other components include one or more of the following: the E5BQ component, the E5AI component, and the E5AQ component from the same SV.

[0473] Example 117: The method as described in Example 116, wherein the switching occurs in response to the failure to capture other components within a predetermined time period.

[0474] Example 118: A method for mitigating interference from aviation radio navigation (ARN) signals, the method comprising:

[0475] GNSS and ARN signals are received through one or more antennas;

[0476] Detecting interference signal sources with signal strength above the noise floor, said signal source including ARN signals;

[0477] The detected interference signal sources are removed before performing correlation processing on the GNSS signal.

[0478] Example 119: The method as described in Example 118, wherein a predetermined threshold higher than the noise floor is used in the detection of the signal source.

[0479] Example 120: The method as described in Example 118, wherein the detected signal source is removed in the frequency domain by a finite impulse response (RF) filter or an infinite impulse response (IIR) filter.

[0480] Example 121: The method as described in Example 118, wherein the signal source is detected by an array processor that calculates the discrete Fourier transform of the GNSS signal.

[0481] Example 122: A method for mitigating interference from aviation radio navigation (ARN) signals, the method comprising:

[0482] GNSS signals and ARN signals from GNSS SV are received through one or more antennas, wherein the received GNSS signals have a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband;

[0483] Interference from the signal source is detected based on the ARN signal. The interference interferes with the first sideband but does not substantially interfere with the second sideband.

[0484] In response to detected interference, the GNSS processing system is configured to process the second sideband from the GNSS SV and not process the first sideband in order to capture or track GNSS signals from the GNSS SV.

[0485] Example 123: The method as described in Example 122, wherein the first sideband is a higher frequency sideband and the second sideband is a lower frequency sideband.

[0486] Example 124: The method as described in Example 122, wherein the interference is detected when (1) the intensity of the signal source is higher than a threshold above the noise floor or (2) the post-correlation signal-to-noise ratio of a particular sideband is lower than a given threshold.

[0487] Example 125: The method as described in Example 124, wherein the GNSS processing system processes the second sideband but not the first sideband during the duration of the detected interference, and resumes processing both after the interference decreases to below the noise floor.

[0488] Example 126: A GNSS receiver, comprising:

[0489] Input, used to receive GNSS signals from the antenna;

[0490] An RF front end, coupled to the input, is used to receive the GNSS signal;

[0491] An RF switching mixer is coupled to the RF front end;

[0492] A discrete-time filter, coupled to the RF switching mixer, the discrete-time filter including a bandpass response for selecting the desired GNSS signal and suppressing out-of-band interference and noise;

[0493] The local oscillator signal, originating from a phase-locked loop (PLL) circuit, is coupled to the RF switching mixer to provide a local reference signal.

[0494] Example 127: A GNS receiver as described in Example 126, wherein the discrete-time filter is configured with a notch response for suppressing interference from aviation radio navigation (ARN) signals at specific locations.

[0495] Example 128: A GNSS receiver as described in Example 126, wherein the GNSS receiver further includes:

[0496] One or more direct-sampling or double-sampling analog-to-digital converters (ADCs) are coupled to the discrete-time filter.

[0497] Example 129: A GNSS receiver as described in Example 128, wherein the bandwidth of the discrete-time filter can be dynamically adjusted to switch between single-sideband signal processing and double-sideband signal processing.

[0498] Example 130, a GNSS receiver as in Example 128, wherein the clock signal operatively received by the RF switching mixer and the discrete-time filter can be adjusted to position the high sideband or low sideband at the baseband or at the low intermediate frequency (IF), or to position the center between the high sideband and the low sideband at the baseband or at the low intermediate frequency (IF).

[0499] Example 131: A GNSS receiver as in Example 128, wherein the local reference signal from the PLL local oscillator is harmonic-dependent with respect to the sampling clock of the ADC and the discrete-time filter.

[0500] Example 132: A GNSS receiver, comprising:

[0501] Input, used to receive GNSS signals from the antenna;

[0502] An RF switching mixer, coupled to the input, is used to receive GNSS signals.

[0503] Discrete-time filter, coupled to the RF switching mixer;

[0504] One or more analog-to-digital converters (ADCs) are coupled to the discrete-time filter;

[0505] A phase-locked loop (PLL) circuit is coupled to the RF switching mixer to provide a local oscillator signal, the output of which is harmonically related to the sampling clock of one or more ADCs and the clock signal of the discrete-time filter.

[0506] Example 133: A GNSS receiver as described in Example 132, wherein one or more ADCs perform down-conversion and provide a digitized GNSS signal.

[0507] Example 134: A GNSS receiver as described in Example 132, wherein the bandwidth of the discrete-time filter can be dynamically adjusted to switch between single-sideband and double-sideband signal processing or double-sideband signal processing.

[0508] Example 135: A GNSS receiver as described in Example 132, wherein the clock signal received by the discrete-time filter is adjustable to position the high sideband or low sideband at the baseband or at a low intermediate frequency (IF), or to position the center between the high sideband and the low sideband at the baseband or at a low intermediate frequency (IF).

[0509] Example 136: A GNSS receiver as in Example 132, wherein the one or more ADCs include an in-phase branch portion and a quadrature phase branch portion, wherein the quadrature phase branch portion can be disabled to fold the received modulated signal onto itself, and wherein a subsequent despreading operation restores the original signal present before folding.

[0510] Example 137: A method for operating a GNSS receiver, the method comprising:

[0511] Receive GNSS signals from GNSS SV, the GNSS signals including a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband;

[0512] The first or second mode of operation is selected based on the required power state of the GNSS receiver;

[0513] In response to selecting a first mode and while in the first mode, the first GNSS signal component in the first sideband is processed and the second GNSS signal component in the second sideband is not processed to capture or track GNSS signals from the GNSS SV;

[0514] In response to selecting a second mode and while in the second mode, the first GNSS signal component in the first sideband is processed and the second GNSS signal component in the second sideband is processed in order to capture GNSS signals from the GNSS SV.

[0515] Example 138: The method as described in Example 137, wherein in a first mode, at least a portion of the GNSS receiver operates at a reduced processing rate.

[0516] Example 139: The method as described in Example 138, wherein the first mode reduces power consumption in the GNSS receiver, and wherein the GNSS receiver operates in a second mode when acquiring GNSS signals and is then configured to operate in the first mode when tracking GNSS signals.

[0517] Example 140: A method for operating a GNSS receiver, the method comprising:

[0518] Receive GNSS signals from GNSS SV, the GNSS signals including a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband;

[0519] The first GNSS signal component and the second GNSS signal component are mixed in the mixer to fold the first signal component and the second GNSS signal component together;

[0520] After the mixing, a GNSS signal is obtained from the first GNSS signal component and the second GNSS signal component.

[0521] Example 141: A method for operating a GNSS receiver, the method comprising:

[0522] During the acquisition phase, multiple GNSS signal components are acquired from one or more GNSS SVs;

[0523] After the acquisition phase is completed, a subset of the plurality of GNSS signal components is tracked.

[0524] Example 142: The method as described in Example 141, wherein the method further includes:

[0525] The subset is selected based on one or more criteria or algorithms, and the selection occurs before the location of the GNSS receiver is determined.

[0526] Example 143, the method as described in Example 142, wherein one or more standards or algorithms provide sufficient signals for tracking while reducing power consumption.

[0527] Example 144: The method as described in Example 142, wherein one or more standards or algorithms provide sufficient GNSS signals to determine the location of the GNSS receiver while reducing power consumption.

[0528] Example 145: The method as described in Example 142, wherein the plurality of GNSS signal components from one or more GNSS SVs include upper and lower sideband signals and a lower sideband signal, and wherein the subset is limited to one of the upper and lower sidebands.

[0529] Example 146: A method for determining the time of arrival of a GNSS signal, wherein more than one Doppler assumption is required for the received signal, the method comprising:

[0530] Perform a forward fast Fourier transform operation on the signal sample block to construct a frequency vector.

[0531] Perform at least one of the following to provide a first Doppler-compensated frequency vector: (A) cyclically alternating the frequency vector with non-zero integers, or (B) performing an interpolation operation on the frequency vector.

[0532] The first Doppler-compensated frequency vector is multiplied by the first reference function vector to form a first weighted Doppler-compensated frequency vector, and an inverse fast Fourier transform operation is performed on the first weighted Doppler-compensated frequency vector to generate a first output time vector, which is used to determine the arrival time of the GNSS signal.

[0533] The methods described in Examples 147 and 146, wherein the signal sample block is first multiplied by a complex sine curve to frequency shift the signal sample block before performing the fast Fourier transform operation.

[0534] The methods described in Examples 148 and 146, wherein the signal sample block is first augmented with a set of zero-value samples before performing the fast Fourier transform operation.

[0535] The methods described in Examples 149 and 146 further include:

[0536] Perform at least one of the following to provide a second Doppler-compensated frequency vector: (A) cyclically alternating the frequency vector with a non-zero integer number, or (B) performing an interpolation operation on the frequency vector, wherein the second Doppler-compensated frequency vector is different from the first Doppler-compensated frequency vector.

[0537] The second Doppler-compensated frequency vector is multiplied by the first reference function vector to form a second weighted Doppler-compensated frequency vector, and an inverse fast Fourier transform is performed on the second weighted Doppler-compensated frequency vector to produce a second output time vector for determining the arrival time of the GNSS signal.

[0538] The methods described in Examples 150 and 146 further include:

[0539] The first Doppler-compensated frequency vector is multiplied by the second reference function vector to form a second weighted Doppler-compensated frequency vector, wherein the second reference function vector is different from the first reference function vector.

[0540] And perform an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

[0541] The methods described in Examples 151 and 146 further include:

[0542] Perform at least one of the following to provide a second Doppler-compensated frequency vector: (A) cyclically alternating the frequency vector with a non-zero integer number of elements, or (B) performing an interpolation operation on the frequency vector, wherein the second Doppler-compensated frequency vector differs from the first Doppler-compensated frequency vector.

[0543] The second Doppler-compensated frequency vector is multiplied by the second reference function vector to form a second weighted Doppler-compensated frequency vector, wherein the second reference function vector is different from the first reference function vector.

[0544] And perform an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

[0545] Example 152: A method for determining the arrival time of a GNSS signal, wherein more than one Doppler assumption is required for the received signal, the method comprising:

[0546] Perform a forward fast Fourier transform operation on the signal sample block to construct a frequency vector.

[0547] Perform at least one of the following to provide a first Doppler-compensated reference function vector: (A) cyclically alternating the first reference function vector with a non-zero integer number of elements, or (B) performing an interpolation operation on the reference function vector.

[0548] The first Doppler-compensated reference function vector is multiplied by the frequency vector to form a first weighted Doppler-compensated frequency vector.

[0549] And perform an inverse fast Fourier transform operation on the first weighted Doppler compensated frequency vector to generate a first output time vector for determining the arrival time of the GNSS signal.

[0550] Example 153: The method as described in Example 152, wherein before performing the fast Fourier transform operation, the signal sample block is first multiplied by a complex sine curve to frequency shift the signal sample block.

[0551] The methods described in Examples 154 and 152, wherein the signal sample block is first expanded with a set of zero-value samples before performing the fast Fourier transform operation.

[0552] The methods described in Examples 155 and 152 further include:

[0553] Perform at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically rotate the first reference function vector by a non-zero integer number, or (B) perform an interpolation operation on the reference function vector.

[0554] The second Doppler-compensated reference function vector differs from the first Doppler-compensated reference function vector.

[0555] The second Doppler-compensated reference function vector is multiplied by the frequency vector to form a second weighted Doppler-compensated frequency vector.

[0556] And perform an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

[0557] The methods described in Examples 156 and 152 further include:

[0558] Perform at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically alternating the second reference function vector with a non-zero integer number, or (B) performing an interpolation operation on the second reference function vector, wherein the second reference function vector is different from the first reference function vector.

[0559] The second Doppler-compensated reference function vector is multiplied by the frequency vector to form a second weighted Doppler-compensated frequency vector.

[0560] And perform an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

[0561] The methods described in Examples 157 and 152 further include:

[0562] Perform at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically rotate the second reference function vector by a non-zero integer number, or (B) perform an interpolation operation on the reference function vector.

[0563] The second Doppler-compensated reference function vector differs from the first Doppler-compensated frequency vector.

[0564] The second Doppler-compensated reference function vector is multiplied by the frequency vector to form a second weighted Doppler-compensated frequency vector.

[0565] And perform an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

[0566] Example 158: A method for determining the time of arrival of a GNSS signal, wherein more than one Doppler assumption is required for the received signal, the method comprising:

[0567] Perform a forward fast Fourier transform operation on the signal sample block to construct a frequency vector.

[0568] Perform at least one of the following to provide a first Doppler-compensated frequency vector: (A) cyclically alternating the frequency vector with non-zero integers, or (B) performing an interpolation operation on the frequency vector.

[0569] Perform at least one of the following to provide a first Doppler-compensated reference function vector: (A) cyclically rotate the first reference function vector by non-zero integers, or (B) perform an interpolation operation on the reference function vector.

[0570] The first Doppler-compensated frequency vector is multiplied by the first Doppler-compensated reference function vector to form the first weighted Doppler-compensated frequency vector.

[0571] And perform an inverse fast Fourier transform operation on the first weighted Doppler compensated frequency vector to generate a first output time vector for determining the arrival time of the GNSS signal.

[0572] The methods described in Examples 159 and 158 further include:

[0573] Perform at least one of the following to provide a second Doppler-compensated frequency vector: (A) cyclically rotate the frequency vector by a non-zero integer number, or (B) perform an interpolation operation on the frequency vector.

[0574] Perform at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically rotate the second reference function vector by non-zero integers, or (B) perform an interpolation operation on the second reference function vector.

[0575] The first Doppler-compensated frequency vector is multiplied by the first Doppler-compensated reference function vector to form a second weighted Doppler-compensated frequency vector, wherein the second weighted Doppler-compensated frequency vector is different from the first weighted Doppler-compensated frequency vector; and

[0576] An inverse fast Fourier transform is performed on the second weighted Doppler compensated frequency vector to produce a second output time vector for determining the arrival time of the GNSS signal.

[0577] Machine-readable media include any mechanism (e.g., a computer or processing logic implemented in hardware) used to store information in a machine-readable form. For example, machine-readable media include read-only memory (“ROM”); random access memory (“RAM”) such as dynamic random access memory; disk storage media; optical storage media; flash memory devices; and so on.

[0578] The article of manufacture can be used to store program code. The article of manufacture storing program code can be embodied in, but is not limited to, one or more memories (e.g., one or more flash memories, random access memory (static, dynamic, or other)), optical discs, CD-ROMs, DVD-ROMs, EPROMs, EEPROMs, magnetic cards or optical cards, or other types of machine-readable media suitable for storing electronic instructions. The program code can also be downloaded from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via data signals embodied in a propagation medium (e.g., via, through a communication link (e.g., a network connection)). The processing logic of one or more hardware processing systems (e.g., microprocessors or microcontrollers, etc.) can execute the program code to cause a data processing system to perform the methods of one or more embodiments described herein.

[0579] Specific exemplary embodiments have been described in the foregoing specification. It is obvious that various modifications can be made to those embodiments without departing from the provisions of the appended claims.

[0580] The broader spirit and scope. Therefore, the specification and drawings should be regarded as illustrative.

[0581] It has sexual meaning rather than restrictive meaning.

Claims

1. A system comprising: A group of one or more application processors (APs) configured to execute an operating system (OS) and one or more applications, said group of one or more application processors being implemented in an integrated circuit (IC); A group of one or more buses, coupled to the group of one or more APs, the one or more buses being on the IC; A cache memory, on the IC and coupled to the set of one or more buses and the set of one or more APs, to store data for use by the OS and the one or more applications; A bus interface, coupled to one or more buses, the bus interface coupling one or more APs to a dynamic random access memory (DRAM) external to the IC; A GNSS processing system, implemented on the IC, comprising an acquisition engine AE and a tracking engine TE, the GNSS processing system being coupled to a shared memory via the one or more buses, the shared memory being one or both of the following: (a) the cache memory or (b) other memory on the IC; A memory controller, coupled to the shared memory and the GNSS processing system, allocates a portion of the shared memory for use by the AE in response to one or more instructions from the operating system to allow GNSS signals to be captured.

2. The system of claim 1, wherein the shared memory includes SRAM (Static Random Access Memory), and the AE includes ASIC hardware logic for performing Fast Fourier Transform (FFT) operations using a time-decimation method.

3. The system of claim 2, wherein the GNSS processing system includes a dedicated memory separate from the shared memory and dedicated to the use of the GNSS processing system, and wherein the other memory is processor local storage for a processor that is not one of the one or more APs.

4. The system of claim 1, wherein the memory controller includes a first port controller for controlling reads and writes to the portion of the AE and a second port controller for controlling reads and writes to the remaining portion of the shared memory.

5. The system of claim 3, wherein the AE performs the acquisition of GNSS signals from one or more GNSS space vehicles (SVs), and the acquisition includes determining the frequency of the received GNSS signal containing a pseudo-random code to achieve tracking of the GNSS signal to generate a pseudorange to the GNSS SV as a result of the tracking.

6. The system of claim 5, wherein the shared memory has a first port for use when the portion is allocated for use by the AE, and a second port for use by the processor or the one or more APs when the portion is allocated.

7. The system of claim 5, wherein the allocated portion stores one or more of the following: (1) a pseudo-random code for GNSSSV or (2) an assumption of the identifiers of the potentially captured GNSS signals and an assumption of their frequencies.

8. The system of claim 7, wherein the memory controller releases the portion after the GNSS processing system begins tracking GNSS signals already captured from at least three (3) GNSS SVs.

9. The system of claim 8, further comprising: Antenna input, used to receive GNSS signals in the L5WB band; A low-noise amplifier (LNA) is coupled to the antenna input to amplify the GNSS signal; A radio frequency analog-to-digital converter (ADC) is coupled to the output of the LNA. The radio frequency ADC and the LNA are used to receive and process GNSS signals in the L5WB band, and the GNSS processing system is configured to process only GNSS signals in the L5WB band.

10. The system of claim 1, wherein the one or more APs generate GNSS pseudo-random codes for at least GNSS SVs in the field of view of the system before or during the acquisition phase, the generated GNSS pseudo-random codes being initially stored in the DRAM outside the IC and then copied to the shared memory during or at the start of the acquisition phase.

11. The system of claim 10, wherein the one or more APs generate the GNSS pseudo-random code in a background operation only for healthy GNSS SVs that are in or will be in the field of view for a period of time, and wherein the OS reserves a portion of the shared memory for use by the AE in response to the one or more APs receiving a request to provide location data.

12. A method for an operating system, the method comprising: A request to generate location data is received from one or more application processors (APs) on an integrated circuit (IC) by using a GNSS processing system on the IC, the GNSS processing system including an acquisition engine (AE) configured to acquire a plurality of GNSS signals, each of which is transmitted from one of the GNSS space carrier (SV) constellations; A portion of the shared memory on the IC is identified and allocated for use by the AE in response to the request, while one or more other processors are allocated the remaining portion of the shared memory, the allocation being performed by an operating system running on the one or more APs or by firmware running on the IC; The AE or one or more APs store data related to GNSS signal acquisition and processing in the allocated portion.

13. The method of claim 12, wherein the shared memory includes SRAM (Static Random Access Memory) on the IC and the AE includes ASIC hardware logic for performing Fast Fourier Transform (FFT) operations using a time-decimation method.

14. The method of claim 13, wherein the method further comprises: After the GNSS processing system begins tracking GNSS signals captured from at least three (3) GNSS SVs, the allocated portion is released in response to the GNSS signals being captured from at least three (3) GNSS SVs prior to the tracking phase.

15. The method of claim 14, wherein the GNSS processing system includes a dedicated memory separate from the shared memory and dedicated to the use of the GNSS processing system.

16. The method of claim 14, wherein the memory controller coupled to the shared memory includes a first port controller for controlling access to the allocated portion for the AE and a second port controller for controlling access to the remaining portion of the shared memory.

17. The method of claim 14, wherein the AE performs the acquisition of a GNSS signal from a GNSS SV, and the acquisition includes determining the frequency of a received GNSS signal containing a pseudo-random code to track the GNSS signal to generate a primary code phase to the GNSS SV as a result of the tracking.

18. The method of claim 17, wherein the allocated portion is used to store one or more of the following: (1) a pseudo-random code of a GNSS SV or (2) an assumption of the identifiers of potentially captured GNSS signals and an assumption of their frequencies.

19. The method of claim 13, wherein the one or more APs generate GNSS pseudo-random codes for at least GNSS SVs in the field of view of the system before or during the acquisition phase, the generated GNSS pseudo-random codes being initially stored in DRAM outside the IC and then copied to the shared memory during the acquisition phase or in response to a request for a location.

20. The method of claim 19, wherein the one or more APs generate the GNSS pseudo-random code in the background only for healthy GNSS SVs that are in the field of view or will be in the field of view for a period of time, and wherein the system reserves the portion of the shared memory for use by the AE by determining the data stored in the non-volatile memory in the cache memory.

21. A non-transitory machine-readable medium storing executable program instructions that, when executed by a data processing system, cause the data processing system to perform the method as described in any one of claims 12-20.

22. A data system, comprising: A group of one or more application processors (APs) for executing the operating system and one or more applications; A group of one or more buses coupled to the group of one or more application processors; Dynamic random access memory (DRAM) is coupled to one or more application processors via one or more of the same set of buses; A GNSS processing system is located on an integrated circuit IC, the IC including a cache memory located on the IC and coupled to the GNSS processing system, the GNSS processing system being coupled to a group of one or more application processors, the GNSS processing system including an acquisition engine (AE) and a tracking engine (TE); The group of one or more application processors is configured to receive requests for location data and generate GNSS pseudo-random codes for the GNSS space vehicle (SV) for use by the AE. The generated GNSS pseudo-random codes are stored in the DRAM and then copied to the cache memory for use by the AE during the acquisition phase.

23. The data processing system of claim 22, wherein the generated GNSS pseudo-random code is generated in response to the request.

24. The data processing system of claim 22, wherein the cache memory includes SRAM (Static Random Access Memory) and the AE includes ASIC hardware logic for performing Fast Fourier Transform (FFT) operations using a time-decimation method.

25. The data processing system of claim 24, wherein the one or more APs generate GNSS pseudo-random codes for at least GNSS SVs in the field of view of the data processing system before or during the acquisition phase.

26. The data processing system of claim 25, wherein the one or more APs generate the GNSS pseudo-random code only for healthy GNSS SVs that are in the field of view or will be in the field of view for a period of time.

27. The data processing system of claim 26, further comprising: Antenna input, used to receive GNSS signals in the E5 band; A low-noise amplifier (LNA) is coupled to the antenna input to amplify the GNSS signal; A radio frequency analog-to-digital converter (ADC) is coupled to the output of the LNA, the radio frequency ADC and the LNA are used to receive and process GNSS signals in the E5 band, and the data processing system is configured to process only GNSS signals in the E5 band.

28. The data processing system of claim 27, wherein the AE performs the acquisition of a GNSS signal from a GNSS SV, and the acquisition includes determining the frequency of a received GNSS signal containing a pseudo-random code to track the GNSS signal to generate a pseudorange to the GNSS SV as a result of the tracking, and wherein the generated GNSS pseudo-random code includes a GNSS pseudo-random code shifted in frequency or time or both to generate a code spectrum for use by the AE in the acquisition phase.

29. The data processing system of claim 28, wherein during the capture of the AE, the allocated portion of the cache memory stores hypotheses of identifiers of potentially captured GNSS signals and hypotheses of their frequencies.

30. A GNSS processing system, comprising: Antenna input, used to receive GNSS signals in the E5 band; A low-noise amplifier (LNA) is coupled to the antenna input to amplify the GNSS signal; A radio frequency (RF) analog-to-digital converter (ADC) coupled to the output of the LNA, the RF ADC and the LNA being used to receive and process GNSS signals in the E5 band; A circular memory buffer, coupled to the output of the RF ADC, is used to receive and store digitized GNSS sample data, the circular memory buffer storing digitized GNSS sample data for more than 1 millisecond and digitized GNSS sample data for less than 2 milliseconds.

31. The GNSS processing system of claim 30, wherein the circular memory buffer stores the digitized GNSS sample data in an array of rows and columns, and the sample data is arranged in row order and also in chronological order, wherein 1 millisecond is the frame duration of the main code of the modernized GNSS signal, and the main code is further covered by a secondary code at a rate of 1 kHz.

32. The GNSS processing system as described in claim 31, further comprising: A GNSS processor includes an acquisition engine and a tracking engine. The acquisition engine includes a set of DFT ALUs that process the digitized GNSS sample data in the array and produce intermediate outputs that do not require transposing the data in the array.

33. The GNSS processing system of claim 32, wherein the first set of DFT ALUs in the set of DFT ALUs uses a time decimation method to generate the intermediate output stored in a variable memory, and the second set of DFT ALUs in the set of DFT ALUs uses the intermediate output to generate an output stored in an FFT result memory.

34. The GNSS processing system of claim 33, wherein the cyclic memory buffer includes a first cyclic memory buffer for storing A sidebands in the E5 band and a second cyclic memory buffer for storing B sidebands in the E5 band.

35. A method for processing GNSS signals in a GNSS receiver, the method comprising: Determine an initial information group comprising at least two of the following: (1) the code phase of a primary or secondary code signal received from at least one GNSS space vehicle (SV); (2) An estimated GNSS time based on one or more time sources, wherein the estimated GNSS time is estimated or known to be within + / - 0.5 milliseconds less than the actual GNSS time; And (3) the approximate location of the GNSS receiver; Based on the initial information group, the expected fractional main code phase of the GNSS signal to be received is estimated; The first DFT correlation is performed using at least the first complete master epoch of digitized GNSS sample data received within a time period corresponding to the time period of the GNSS signal's epochs, and the first FFT-based correlation uses the digitized GNSS sample data that begins at the first time. The second DFT correlation is performed using at least a second complete epoch of the received digitized GNSS sample data, the at least second complete epoch of the digitized GNSS sample data including at least some of the received GNSS sample data in the first complete epoch, the second DFT correlation using digitized GNSS sample data starting at a second time, the second time being after the first time and offset from the first time by a period of time less than the epoch. Remove the auxiliary code from the results of the first DFT correlation and the second DFT correlation to provide input for coherent integration. Integrate at least one of these inputs into the coherent hypothesis memory; The result from the coherent hypothesis memory is squared or its magnitude is taken to capture GNSS signals from at least one GNSS SV.

36. The method of claim 35, wherein the I data and Q data are summed in each of the first complete code epoch and the second complete code epoch.

37. The method of claim 35, further comprising: The summation of the squared results in the incoherent hypothesis memory occurs several milliseconds after a first time.

38. The method of claim 35, wherein the method further comprises: A search order is established for GNSS signals from GNSS SV, the search order being at least partially based on the expected fractional primary code phase.

39. The method of claim 35, wherein the method further comprises: A subset of the relevant hypotheses is selected within a window that includes the expected digital phase for storage in the coherent hypothesis memory.

40. The method of claim 35, wherein the method further comprises: Among several factors, each SV is assigned to an input sample offset group based on the expected primary code phase of the SV.

41. The method of claim 40, wherein the method further comprises: One SV is assigned to an estimated code epoch, and another SV is assigned to another estimated code epoch, wherein each SV is assigned to the code epoch of the code epoch that is closer to the SV in time.

42. A method for processing GNSS signals, the method comprising: Receive GNSS signals; The received GNSS signal is digitized and an output of GNSS sample data is provided from the analog-to-digital converter (ADC), the output including at least one of the following: (1) GNSS sideband A sample data of the received GNSS signal and (2) GNSS sideband B sample data of the received GNSS signal; Calculate at least one of the following: (1) a first set of DFTs of the GNSS sideband A sample data to provide a first set of results and (2) a second set of DFTs of the GNSS sideband B sample data to provide a second set of results; Calculate at least one of the following: (1) a third DFT for the GNSS sideband A main PRN code data with code Doppler and carrier Doppler adjusted prior to the third DFT, the GNSS sideband A main PRN code data including at least one of two components in GNSS sideband A, the third DFT providing a third result; and (2) a fourth DFT for the GNSS sideband B main PRN code data with code Doppler and carrier Doppler adjusted prior to the fourth DFT, the GNSS sideband B main PRN code data including at least one of two components in GNSS sideband B, the fourth DFT providing a fourth result; Calculate at least one of the following: (1) use the DFT of the complex conjugate of the product of the first set of results and the third set of results to calculate the first set of correlations to provide the fifth set of results, and (2) use the DFT of the complex conjugate of the product of the second set of results and the fourth set of results to calculate the second set of correlations to provide the sixth set of results; Integrate at least one of the following: (1) the integration of the fifth set of results with at least one prior sum for GNSS sideband A, (2) the integration of the sixth set of results with at least one prior sum for GNSS sideband B, wherein such integration includes at least one of the following: (1) storing at least one new sum for the GNSS sideband A component in a single hypothetical memory, and (2) storing at least one new sum for the GNSS sideband B component in the single hypothetical memory.

43. The method of claim 42, wherein the fourth set of results includes the IDFT results of the two components of the GNSS sideband A, and the sixth set of results includes the IDFT results of the two components of the GNSS sideband B.

44. The method of claim 43, wherein the GNSS sideband A sample data is stored in a first circular memory buffer, and the GNSS sideband B sample data is stored in a second circular memory buffer.

45. The method of claim 44, wherein the GNSS sideband A sample data is stored in a first circular memory buffer in an array format of rows and columns, and the GNSS sideband B sample data is stored in a second circular memory buffer in the same array format of rows and columns.

46. ​​The method of claim 45, wherein the GNSS sample data is processed to separate the GNSS sideband A sample data from the GNSS sideband B sample data by: (1) for the GNSS sideband A, shifting the sample centered at a first frequency upward by a first offset frequency, performing a low-pass filter to capture a first bandwidth of the data, and decimating the output of the low-pass filter to a lower sampling rate; and (2) for the GNSS sideband B, shifting the sample centered at the first frequency downward by a first offset frequency, performing a low-pass filter to capture a second bandwidth of the data, and decimating the output of the low-pass filter to a lower sampling rate.

47. The method of claim 45, wherein the computational operation does not require a separate operation to transpose or rearrange the sample data or generated code spectrum data at the inputs of the first and second sets of correlations.

48. The method of claim 45, wherein the code generator generates at least one of the following: (1) GNSS sideband A main PRN code data per millisecond while the GNSS signal is being acquired and tracked, and the GNSS sideband A main PRN code data is not stored after the Fourier transform; and (2) GNSS sideband B main PRN code data per millisecond while the GNSS signal is being acquired and tracked, and the GNSS sideband B main PRN code data is not stored after the Fourier transform.

49. The method of claim 48, wherein the integration is incoherent during at least a portion of the acquisition phase when the GNSS signal is received.

50. A system for processing GNSS L5 band signals, the system comprising: Radio frequency analog-to-digital converter (ADC) is used to generate a digital representation of the received GNSS signal; A baseband sample memory for storing the digital representation of the received GNSS signal, the baseband sample memory being coupled to the ADC; A GNSS processing system, coupled to the baseband sample memory, to process the digital representation of the received GNSS signal, the GNSS processing system being configured to process four GNSS signal components of the GNSS signal to incoherently integrate all four GNSS signal components to generate incoherent integrated data for each of the four GNSS signal components and store the incoherent integrated data in a single hypothetical memory to capture the GNSS signal.

51. The system of claim 50, wherein the single hypothetical memory is a memory of less than 2 megabytes, and wherein the four GNSS signal components include Galileo E5AI signal components, Galileo E5BI signal components, Galileo E5BQ signal components and Galileo E5AQ signal components, or four GNSS signal components for the BeiDou B2 system, or both Galileo E5 and BeiDou B2 signal components.

52. The system of claim 51, wherein the GNSS processing system processes GNSS signals received from at least two GNSS constellations, the at least two GNSS constellations comprising: Galileo E5 constellation in GNSS SV; The L5 GPS constellation of GNSS SV, the GLONASS K2 constellation of GNSS SV, the QZSS constellation of GNSS SV, and the Beidou B2 constellation of GNSS SV.

53. The system of claim 50, further comprising: A code generator is used to generate GNSS PRN codes during the acquisition and tracking of GNSS signals, but does not store the GNSS PRN codes after tracking is completed.

54. The system of claim 53, wherein the code generator generates more than two master PRN code points in one clock cycle during the acquisition and tracking.

55. The system of claim 54, wherein for a given GNSS constellation and GNSS signal components in that GNSS constellation, the code generator generates more than two primary PRN code points in one clock cycle by calculation using a calculated code advance matrix derived from an N-fold multiplication of a code polynomial matrix, where N represents the number of primary PRN code points generated in one clock cycle.

56. The system of claim 55, wherein the GNSS processing system shares memory with one or more processors, and the GNSS processing system, the cache memory, and the one or more application processors are all arranged on the same single integrated circuit.

57. The system of claim 56, wherein the GNSS processing system includes an acquisition engine and a tracking engine, and the acquisition engine includes processing logic for receiving an array of GNSS sample data, the array of GNSS sample data being arranged in row or column order according to the reception time, and the acquisition engine includes processing logic for performing a DFT on the GNSS sample data array using a time decimation algorithm to produce a frequency domain result, the frequency domain result being multiplied by the code spectrum of the GNSS PRN code of the GNSS SV in the field of view, and then the product of the resulting frequency domain result and the code spectrum is processed in the processing logic by an IDFT using a frequency decimation algorithm to generate hypotheses of possible captured GNSS signals, the hypotheses being noncoherently accumulated in the single hypothesis memory.

58. The system of claim 57, wherein the GNSS sample data array is stored in two circular memory buffers, the two circular memory buffers comprising a first circular memory buffer for storing A-band GNSS sample data and a second circular memory buffer for storing B-band GNSS sample data, wherein multiple GNSS constellations are capable of being received in at least one of the frequency bands.

59. The system of claim 55, wherein before applying a set of DFTs using a time-decimation algorithm, the GNSS master PRN code from the output of the code generator is shifted in frequency and in time to generate a code spectrum, which is multiplied by the frequency domain result of a set of DFTs performed on the received GNSS signal using a time-decimation algorithm.

60. The system of claim 58, wherein the GNSS primary PRN code from the output of the code generator is shifted in frequency and shifted in time to generate the code spectrum.

61. The system of claim 57, wherein the order in the array is changed by the sequence of the DFT such that no transposition or rearrangement of the data is required when the IDFT is performed.

62. The system of claim 61, wherein the sequence of said DFTs avoids the use of memory or processing resources that would otherwise be used for said transpose or rearrangement.

63. A system for processing GNSS signals; said system comprising: An analog-to-digital converter (ADC) is used to generate a digital representation of a received GNSS signal; A baseband sample memory for storing the digital representation of the received GNSS signal, the baseband sample memory being coupled to the ADC; A GNSS processing system, coupled to the baseband sample memory, processes the digital representation of the received GNSS signal. The GNSS processing system captures up to four GNSS signal components by incoherently integrating up to four GNSS signal components over a period of time in an array processing system located in the capture engine of the GNSS processing system. The array processing system receives GNSS sample data from the baseband memory, and the GNSS sample data is formatted as a row and column array having multiple rows and multiple columns.

64. The system of claim 63, wherein the array processing system includes processing logic that performs a set of DFTs using a time decimation algorithm and then performs a set of inverse DFTs using a frequency decimation algorithm.

65. The system of claim 64, wherein the output from the array processing system provides a frequency and a GNSS SV identifier for storage in a hypothesis memory for integration of hypotheses about GNSS signals.

66. The system of claim 63, wherein the array processing system receives GNSS sample data in a first order and generates output in a second order different from the first order, wherein the first order is one of the row order or column order in the row and column array, and the second order is one of the row order or the column order, and wherein the first order and the second order are based on the reception time of the GNSS sample data.

67. The system of claim 66, wherein the GNSS sample data is stored in the row and column arrays in two circular memory buffers, the two circular memory buffers comprising a first circular memory buffer for storing a first GNSS signal component from the GNSS SV sample data and a second circular memory buffer for storing a second GNSS signal component from the GNSS SV sample data, the first and second circular memory buffers being coupled to the array processing system.

68. A system for processing GNSS signals, the system comprising: A memory for storing the master code seed of GNSS signals from one or more GNSS constellations GNSS SVs and storing a representation of the master code polynomial data for generating master PRN codes for the GNSS signals; A code generator, coupled to the memory, is used to receive the master code seed and the master code polynomial data, and to generate more than two master PRN code points in a single clock cycle using the master code seed and the master code polynomial data during the acquisition and tracking of the GNSS signal.

69. The system of claim 68, wherein for a given GNSS constellation and GNSS signal components in that GNSS constellation, the code generator generates more than two primary PRN code points by computation in a single clock cycle, the computation using a computed code advance matrix derived from an N-fold multiplication of the primary code polynomial matrix, where N represents the number of primary PRN code points generated in one clock cycle.

70. The system of claim 69, wherein the system generates the master PRN code points without storing the master PRN code points after tracking is completed or after the DFT transformation of the current master code epoch is completed.

71. The system of claim 69, wherein the calculated code advance matrix is ​​pre-computed and stored in the memory before capture begins, and wherein N represents the amount of code advance provided by the code generator between clock cycles.

72. The system of claim 69, further comprising: A GNSS processing system, coupled to the code generator, captures at least two GNSS signal components of a GNSS signal by incoherently integrating at least two of the four GNSS signal components over a period of time in an array processing system, the array processing system receiving GNSS sample data from a baseband memory, and the GNSS sample data being formatted as a row and column array having multiple rows and columns.

73. The system of claim 72, wherein the generation of GNSS PRN codes by the code generator is dynamic, based on the GNSS SV in the field of view during the acquisition and tracking of the GNSS signal.

74. The system of claim 73, wherein the GNSS master PRN code from the output of the code generator is shifted in frequency and time to generate a code spectrum, which, together with the frequency result of the DFT of the received GNSS signal, is used in the DFT.

75. A GNSS receiver, comprising: A radio frequency (RF) receiver, comprising at least one first RF filter and a low noise amplifier (LNA) tuned to the L5WB band only to receive L5WB GNSS signals; An analog-to-digital converter (ADC) is coupled to the LNA to generate GNSS sample data stored in a baseband sample memory, wherein the RF receiver is the only GNSS receiver among the GNSS receivers.

76. The GNSS receiver of claim 75, wherein the RF receiver does not include an amplifier for GNSS signals other than the L5WB band, and wherein the RF receiver includes a first RF filter coupled to the GNSS antenna, the output of the first RF filter being coupled to the input of the LNA, and the output of the LNA being coupled to a second RF filter.

77. The GNSS receiver of claim 76, wherein the input of the first amplifier is coupled to the output of the second RF filter, and the output of the first amplifier is coupled to the ADC, and wherein the LNA and the first RF filter are arranged on the first IC, and the ADC and the first amplifier are arranged on the second IC.

78. The GNSS receiver of claim 77, wherein the GNSS receiver further comprises: The sideband separation converter separates GNSS sideband A sample data from GNSS sideband B sample data. Furthermore, the second radio frequency filter is arranged within the first IC.

79. The GNSS receiver of claim 78, further comprising: The first circular memory buffer is used to store the GNSS sideband A sample data; as well as The second circular memory buffer is used to store the GNSS sideband B sample data.

80. The GNSS receiver of claim 79, wherein the RF receiver does not include an RF mixer.

81. The GNSS receiver of claim 80, wherein the RF receiver does not include an RF reference local oscillator, and wherein the GNSS antenna is tuned to the L5WB band only.

82. The GNSS receiver of claim 80, wherein the sideband separation downconverter generates GNSS sideband A sample data arranged in a first array of rows and columns, and generates GNSS sideband B samples arranged in a second array of rows and columns.

83. The GNSS receiver of claim 80, wherein the RF receiver is tuned to receive a GNSS signal centered at 1191.795 MHz, and the L5WB GNSS signal has a chip rate of 10.23 MHz.

84. The GNSS receiver of claim 82, wherein the GNSS antenna is the only GNSS antenna in the GNSS receiver, and wherein the RF receiver is tuned to receive a GNSS signal centered at 1191.795 MHz, and the L5WB GNSS signal has a chip rate of 10.23 MHz.

85. A system for processing GNSS signals, the system comprising: Analog-to-digital converter (ADC) is used to generate a digital representation of GNSS signals received in the L5WB GNSS band; A baseband sample memory for storing the digital representation of the received GNSS signal, the baseband sample memory being coupled to the ADC; A GNSS processing system, coupled to the baseband sample memory, for processing the digital representation of the received GNSS signal, the GNSS processing system being configured to receive and process at least one of the four GNSS signal components of the L5WB band GNSS signal without using the L1 GNSS signal.

86. The system of claim 85, wherein the system comprises only a single GNSS antenna tuned to the L5WB band centered at 1191.795 MHz, and the received GNSS signal has a chip rate of 10.23 MHz or a chip rate significantly higher than (e.g., more than twice) the L1GPS chip rate of 1.023 MHz.

87. The system of claim 86, wherein the baseband sample memory stores the digital representation in an array of rows and columns arranged according to the reception time.

88. The system of claim 86, wherein the baseband sample memory stores the digital representation in an array of rows and columns arranged in columns according to the reception time.

89. The system of claim 87, wherein the GNSS processing system processes the received GNSS signal by a sequence of DFTs, the sequence of DFTs including a first set of DFTs using a time decimation method and then a second set of DFTs using a frequency decimation method, without requiring transposition or rearrangement of the data in the array containing the data.

90. The system of claim 85, wherein the initial signal is captured in a coarse time capture mode, further signals are captured in a precise time capture mode, and all signals are tracked in a tracking mode.

91. The system of claim 90, wherein capture-specific hardware usage is reduced when in coherent tracking mode.

92. The system of claim 50, wherein the GNSS processing system does not receive and capture L1 GNSS signals.

93. The system of claim 63, wherein the GNSS processing system does not receive and capture L1 GNSS signals.

94. A GNSS receiver, comprising: Input, coupled to the antenna; RF front end, coupled to the input; An ADC converter, coupled to the RF front end; A GNSS processing system coupled to the ADC converter receives GNSS signals from the ADC converter, wherein the GNSS processing system captures only selected components of the GNSS signals during an initial acquisition phase, the selected components having a low probability of signal variation relative to the probability of signal variation of other components of the GNSS signals, based on the coding scheme used in the selected components.

95. The GNSS receiver of claim 94, wherein after the initial acquisition phase, the GNSS processing system acquires other components of the GNSS signal.

96. The GNSS receiver of claim 95, wherein the selected component is the E5BI component of an SV from a Galilean constellation of GNSS satellites, and the other components include one or more of the following: the E5BQ component, the E5AI component, and the E5AQ component from the same SV.

97. The GNSS receiver of claim 95, wherein the signal change is a sign inversion in the coding scheme of the selected component.

98. The GNSS receiver of claim 95, wherein the initial acquisition phase is one of acquisition using coarse time or acquisition using precise time.

99. The GNSS receiver of claim 95, wherein the initial acquisition phase is performed after a set of the other components of the GNSS signal has failed to be acquired within a predetermined time period.

100. A method for operating a GNSS receiver, the method comprising: Switch to simplified capture mode, in which only selected components of the GNSS signal from the SV in the GNSS constellation are captured during the initial capture phase; The selected component is captured, and relative to the signal variation probabilities of other components in the GNSS signal from the SV, the selected component has a low signal variation probability based on the coding scheme used in the selected component. After capturing the selected component, the other components are captured.

101. The method of claim 100, wherein the selected component is the E5BI component of an SV in the Galileo constellation from a GNSS satellite, and the other components include one or more of the following: the E5BQ component, the E5AI component, and the E5AQ component from the same SV.

102. The method of claim 101, wherein the switching occurs in response to failure to capture other components within a predetermined time period.

103. A method for mitigating interference from aviation radio navigation (ARN) signals, the method comprising: GNSS and ARN signals are received through one or more antennas; Detecting interference signal sources with signal strength above the noise floor, said signal source including ARN signals; The detected interference signal sources are removed before performing correlation processing on the GNSS signal.

104. The method of claim 103, wherein a predetermined threshold above the noise floor is used in the detection of the signal source.

105. The method of claim 103, wherein the detected signal source is removed in the frequency domain by a finite impulse response (RF) filter or an infinite impulse response (IIR) filter.

106. The method of claim 103, wherein the signal source is detected by an array processor that calculates the discrete Fourier transform of the GNSS signal.

107. A method for mitigating interference from aviation radio navigation (ARN) signals, the method comprising: GNSS signals and ARN signals from GNSS SV are received through one or more antennas, wherein the received GNSS signals have a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband; Interference from the signal source is detected based on the ARN signal. The interference interferes with the first sideband but does not substantially interfere with the second sideband. In response to detected interference, the GNSS processing system is configured to process the second sideband from the GNSS SV and not process the first sideband in order to capture or track GNSS signals from the GNSS SV.

108. The method of claim 107, wherein the first sideband is a higher frequency sideband and the second sideband is a lower frequency sideband.

109. The method of claim 107, wherein the interference is detected when (1) the intensity of the signal source is above a threshold above the noise floor or (2) the post-correlation signal-to-noise ratio of a particular sideband is below a given threshold.

110. The method of claim 109, wherein the GNSS processing system processes the second sideband but not the first sideband during the duration of the detected interference, and resumes processing both after the interference decreases to below the noise floor.

111. A GNSS receiver, comprising: Input, used to receive GNSS signals from the antenna; An RF front end, coupled to the input, is used to receive the GNSS signal; An RF switching mixer is coupled to the RF front end; A discrete-time filter, coupled to the RF switching mixer, the discrete-time filter including a bandpass response for selecting the desired GNSS signal and suppressing out-of-band interference and noise; The local oscillator signal, originating from a phase-locked loop (PLL) circuit, is coupled to the RF switching mixer to provide a local reference signal.

112. The GNS receiver of claim 111, wherein the discrete-time filter is configured with a notch response for suppressing interference from aviation radio navigation (ARN) signals at specific locations.

113. The GNSS receiver of claim 111, wherein the GNSS receiver further comprises: One or more direct-sampling or double-sampling analog-to-digital converters (ADCs) are coupled to the discrete-time filter.

114. The GNSS receiver of claim 113, wherein the bandwidth of the discrete-time filter is dynamically adjustable to switch between single-sideband signal processing and double-sideband signal processing.

115. The GNSS receiver of claim 113, wherein the clock signal operatively received by the RF switching mixer and the discrete-time filter can be adjusted to position the high sideband or low sideband at the baseband or at the low intermediate frequency (IF), or to position the center between the high sideband and the low sideband at the baseband or at the low intermediate frequency (IF).

116. The GNSS receiver of claim 113, wherein the local reference signal from the PLL local oscillator is harmonic-dependent with respect to the sampling clock of the ADC and the discrete-time filter.

117. A GNSS receiver, comprising: Input, used to receive GNSS signals from the antenna; An RF switching mixer, coupled to the input, is used to receive GNSS signals. Discrete-time filter, coupled to the RF switching mixer; One or more analog-to-digital converters (ADCs) are coupled to the discrete-time filter; A phase-locked loop (PLL) circuit is coupled to the RF switching mixer to provide a local oscillator signal, the output of which is harmonically related to the sampling clock of one or more ADCs and the clock signal of the discrete-time filter.

118. The GNSS receiver of claim 117, wherein the one or more ADCs perform down-conversion and provide a digitized GNSS signal.

119. The GNSS receiver of claim 117, wherein the bandwidth of the discrete-time filter is dynamically adjustable to switch between single-sideband and double-sideband signal processing or double-sideband signal processing.

120. The GNSS receiver of claim 117, wherein the clock signal operatively received by the discrete-time filter is adjustable to position the high sideband or low sideband at the baseband or at a low intermediate frequency (IF), or to position the center between the high sideband and the low sideband at the baseband or at a low intermediate frequency (IF).

121. The GNSS receiver of claim 117, wherein the one or more ADCs include an in-phase branch portion and a quadrature phase branch portion, and wherein the quadrature phase branch portion can be disabled to fold the received modulated signal onto itself, and wherein a subsequent despreading operation restores the original signal present before the folding.

122. A method for operating a GNSS receiver, the method comprising: Receive GNSS signals from GNSS SV, the GNSS signals including a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband; The first or second mode of operation is selected based on the required power state of the GNSS receiver; In response to selecting a first mode and while in the first mode, the first GNSS signal component in the first sideband is processed and the second GNSS signal component in the second sideband is not processed to capture or track GNSS signals from the GNSS SV; In response to selecting a second mode and while in the second mode, the first GNSS signal component in the first sideband is processed and the second GNSS signal component in the second sideband is processed in order to capture GNSS signals from the GNSS SV.

123. The method of claim 122, wherein in the first mode, at least a portion of the GNSS receiver operates at a reduced processing rate.

124. The method of claim 123, wherein the first mode reduces power consumption in the GNSS receiver, and wherein the GNSS receiver operates in a second mode when acquiring GNSS signals and is then configured to operate in the first mode when tracking GNSS signals.

125. A method for operating a GNSS receiver, the method comprising: Receive GNSS signals from GNSS SV, the GNSS signals including a first GNSS signal component in a first sideband and a second GNSS signal component in a second sideband; The first GNSS signal component and the second GNSS signal component are mixed in the mixer to fold the first signal component and the second GNSS signal component together; After the mixing, a GNSS signal is obtained from the first GNSS signal component and the second GNSS signal component.

126. A method for operating a GNSS receiver, the method comprising: During the acquisition phase, multiple GNSS signal components are acquired from one or more GNSS SVs; After the acquisition phase is completed, a subset of the plurality of GNSS signal components is tracked.

127. The method of claim 126, wherein the method further comprises: The subset is selected based on one or more criteria or algorithms, and the selection occurs before the location of the GNSS receiver is determined.

128. The method of claim 127, wherein the one or more criteria or algorithms provide sufficient signals for tracking while reducing power consumption.

129. The method of claim 127, wherein the one or more standards or algorithms provide sufficient GNSS signals to determine the location of the GNSS receiver while reducing power consumption.

130. The method of claim 127, wherein the plurality of GNSS signal components from one or more GNSS SVs include upper and lower sideband signals and a lower sideband signal, and wherein the subset is limited to one of the upper and lower sidebands.

131. A method for determining the time of arrival of a GNSS signal, wherein more than one Doppler assumption is required for the received signal, the method comprising: Perform a forward fast Fourier transform operation on the signal sample block to construct a frequency vector. Perform at least one of the following to provide a first Doppler-compensated frequency vector: (A) cyclically alternating the frequency vector with non-zero integers, or (B) performing an interpolation operation on the frequency vector. The first Doppler-compensated frequency vector is multiplied by the first reference function vector to form a first weighted Doppler-compensated frequency vector, and an inverse fast Fourier transform operation is performed on the first weighted Doppler-compensated frequency vector to generate a first output time vector, which is used to determine the arrival time of the GNSS signal.

132. The method of claim 131, wherein before performing the fast Fourier transform operation, the signal sample block is first multiplied by a complex sine curve to frequency shift the signal sample block.

133. The method of claim 131, wherein the signal sample block is first augmented with a set of zero-value samples before performing the fast Fourier transform operation.

134. The method of claim 131, further comprising: Perform at least one of the following to provide a second Doppler-compensated frequency vector: (A) cyclically alternating the frequency vector with a non-zero integer number, or (B) performing an interpolation operation on the frequency vector, wherein the second Doppler-compensated frequency vector is different from the first Doppler-compensated frequency vector. The second Doppler-compensated frequency vector is multiplied by the first reference function vector to form a second weighted Doppler-compensated frequency vector, and an inverse fast Fourier transform is performed on the second weighted Doppler-compensated frequency vector to produce a second output time vector for determining the arrival time of the GNSS signal.

135. The method of claim 131, further comprising: The first Doppler-compensated frequency vector is multiplied by the second reference function vector to form a second weighted Doppler-compensated frequency vector, wherein the second reference function vector is different from the first reference function vector. And perform an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

136. The method of claim 131, further comprising: Perform at least one of the following to provide a second Doppler-compensated frequency vector: (A) cyclically alternating the frequency vector with a non-zero integer number of elements, or (B) performing an interpolation operation on the frequency vector, wherein the second Doppler-compensated frequency vector differs from the first Doppler-compensated frequency vector. The second Doppler-compensated frequency vector is multiplied by the second reference function vector to form a second weighted Doppler-compensated frequency vector, wherein the second reference function vector is different from the first reference function vector. And perform an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

137. A method for determining the time of arrival of a GNSS signal, wherein more than one Doppler assumption is required for the received signal, the method comprising: Perform a forward fast Fourier transform operation on the signal sample block to construct a frequency vector. Perform at least one of the following to provide a first Doppler-compensated reference function vector: (A) cyclically alternating the first reference function vector with a non-zero integer number of elements, or (B) performing an interpolation operation on the reference function vector. The first Doppler-compensated reference function vector is multiplied by the frequency vector to form a first weighted Doppler-compensated frequency vector. And perform an inverse fast Fourier transform operation on the first weighted Doppler compensated frequency vector to generate a first output time vector for determining the arrival time of the GNSS signal.

138. The method of claim 137, wherein before performing the fast Fourier transform operation, the signal sample block is first multiplied by a complex sine curve to frequency shift the signal sample block.

139. The method of claim 137, wherein the signal sample block is first augmented with a set of zero-value samples before performing the fast Fourier transform operation.

140. The method of claim 137, further comprising: Perform at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically rotate the first reference function vector by a non-zero integer number, or (B) perform an interpolation operation on the reference function vector. The second Doppler-compensated reference function vector differs from the first Doppler-compensated reference function vector. The second Doppler-compensated reference function vector is multiplied by the frequency vector to form a second weighted Doppler-compensated frequency vector. And perform an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

141. The method of claim 137, further comprising: Perform at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically alternating the second reference function vector with a non-zero integer number, or (B) performing an interpolation operation on the second reference function vector, wherein the second reference function vector is different from the first reference function vector. The second Doppler-compensated reference function vector is multiplied by the frequency vector to form a second weighted Doppler-compensated frequency vector. And perform an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

142. The method of claim 137, further comprising: Perform at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically rotate the second reference function vector by a non-zero integer number, or (B) perform an interpolation operation on the reference function vector. The second Doppler-compensated reference function vector differs from the first Doppler-compensated frequency vector. The second Doppler-compensated reference function vector is multiplied by the frequency vector to form a second weighted Doppler-compensated frequency vector. And perform an inverse fast Fourier transform operation on the second weighted Doppler compensated frequency vector to generate a second output time vector for determining the arrival time of the GNSS signal.

143. A method for determining the time of arrival of a GNSS signal, wherein more than one Doppler assumption is required for the received signal, the method comprising: Perform a forward fast Fourier transform operation on the signal sample block to construct a frequency vector. Perform at least one of the following to provide a first Doppler-compensated frequency vector: (A) cyclically alternating the frequency vector with non-zero integers, or (B) performing an interpolation operation on the frequency vector. Perform at least one of the following to provide a first Doppler-compensated reference function vector: (A) cyclically rotate the first reference function vector by non-zero integers, or (B) perform an interpolation operation on the reference function vector. The first Doppler-compensated frequency vector is multiplied by the first Doppler-compensated reference function vector to form the first weighted Doppler-compensated frequency vector. And perform an inverse fast Fourier transform operation on the first weighted Doppler compensated frequency vector to generate a first output time vector for determining the arrival time of the GNSS signal.

144. The method of claim 143, further comprising: Perform at least one of the following to provide a second Doppler-compensated frequency vector: (A) cyclically rotate the frequency vector by a non-zero integer number, or (B) perform an interpolation operation on the frequency vector. Perform at least one of the following to provide a second Doppler-compensated reference function vector: (A) cyclically rotate the second reference function vector by non-zero integers, or (B) perform an interpolation operation on the second reference function vector. The first Doppler-compensated frequency vector is multiplied by the first Doppler-compensated reference function vector to form a second weighted Doppler-compensated frequency vector, wherein the second weighted Doppler-compensated frequency vector is different from the first weighted Doppler-compensated frequency vector; and An inverse fast Fourier transform is performed on the second weighted Doppler compensated frequency vector to produce a second output time vector for determining the arrival time of the GNSS signal.

145. A method for processing GNSS signals, the method comprising: GNSS signals are received by a GNSS receiver; The received GNSS signal is digitized and GNSS sample data is output via an analog-to-digital converter (ADC) in the GNSS receiver, the GNSS sample data comprising one or more of the following: (1) GNSS sideband A sample data from the received GNSS signal; or (2) GNSS sideband B sample data from the received GNSS signal; Calculate the first set of Discrete Fourier Transforms (DFTs) of the GNSS sample data to provide the first set of results; Calculate the second set of DFTs for the first GNSS primary PRN code data, which is adjusted for code Doppler and carrier Doppler before the second set of DFTs. The second set of DFTs provides the second set of results. Based on the first set of results and the second set of results, the first set of correlations between the received GNSS signal and the first GNSS master PRN code is calculated to provide the third set of results; The third set of results is integrated with at least one previous sum, wherein the integration includes storing at least one new sum for the correlation between the first GNSS master PRN code and the received GNSS signal.

146. The method of claim 145, wherein the GNSS receiver receives and processes only GNSS signals in the L5 radio frequency (RF) band, and does not use GNSS signals in the L1 RF band.

147. The method of claim 145, wherein the second set of results provides a code spectrum for correlating the first GNSS master code data with the GNSS sample data.

148. The method of claim 145, wherein the first GNSS master PRN code data is stored in the GNSS receiver, or generated in the GNSS receiver during an acquisition phase in the GNSS receiver.

149. The method of claim 147, wherein the GNSS receiver further receives and processes GNSS signals in the L1RF band.

150. The method of claim 147, wherein the GNSS sample data comprises GNSS sideband A sample data from the received GNSS signal, and the GNSS sideband A sample data comprises one or more components.

151. The method of claim 150, wherein the one or more components of the GNSS sideband A sample data comprise: The E5AI component contains the second GNSS master PRN code data; And the E5AQ component containing the first GNSS master PRN code data, and the method further includes: A third set of DFTs is calculated for the second GNSS primary PRN code data, which is adjusted for code Doppler and carrier Doppler before the third set of DFTs, and the third set of DFTs provides a fourth set of results; Based on the first set of results and the fourth set of results, the second set of correlations between the received GNSS signal and the second GNSS master PRN code is calculated to provide the fifth set of results; The fifth set of results is integrated with at least one previous sum, wherein the integration of the fifth set of results includes at least one new sum for the correlation storage of the second GNSS master PRN code data and the received GNSS signal.

152. The method of claim 151, wherein the GNSS sample data comprises GNSS sideband B sample data from the received GNSS signal, and the GNSS sideband B sample data comprises one or more components, the one or more components comprising: The E5BI component contains the third GNSS master PRN code data; And the E5BQ component containing fourth GNSS master PRN code data, and the method further includes: Calculate the fourth set of DFTs for the GNSS sideband B sample data to provide the sixth set of results; The fifth DFT of the third GNSS primary PRN code data is calculated. The third GNSS primary PRN code data is adjusted for code Doppler and carrier Doppler before the fifth DFT. The fifth DFT provides the seventh result. Based on the sixth and seventh sets of results, the third set of correlations between the received GNSS signal and the third GNSS master PRN code is calculated to provide the eighth set of results; The eighth set of results is integrated with at least one previous sum, wherein the integration of the eighth set of results includes storing at least one new sum for the correlation between the third GNSS master PRN code data and the received GNSS signal; The sixth DFT of the fourth GNSS primary PRN code data is calculated. The fourth GNSS primary PRN code data is adjusted for code Doppler and carrier Doppler before the sixth DFT. The sixth DFT provides the ninth result. Based on the sixth and ninth results, the correlation between the received GNSS signal and the fourth group of the fourth GNSS master PRN code is calculated to provide the tenth result. The tenth set of results is integrated with at least one previous sum, wherein the integration of the tenth set of results includes at least one new sum for the correlation storage of the fourth GNSS master PRN code data and the received GNSS signal.

153. The method of claim 147, wherein the GNSS sample data comprises GNSS sideband B sample data from the received GNSS signal, and the GNSS sideband B sample data comprises: an E5BI component comprising second GNSS main PRN code data; And the E5BQ component containing the first GNSS master PRN code data, and the method further includes: The third set of DFTs of the second GNSS primary PRN code data is calculated. The second GNSS primary PRN code data is adjusted for code Doppler and carrier Doppler before the third set of DFTs. The third set of DFTs provides a fourth set of results. Based on the first set of results and the fourth set of results, the second set of correlations between the received GNSS signal and the second GNSS master PRN code is calculated to provide the fifth set of results; The fifth set of results is integrated with at least one previous sum, wherein the integration of the fifth set of results includes at least one new sum for the correlation storage of the second GNSS master PRN code data and the received GNSS signal.

154. The method of claim 151, wherein the GNSS receiver includes a time-domain correlator, and the time-domain correlator is used in the tracking mode after the processing logic for calculating the DFT has captured the GNSS signal.

155. The method of claim 154, wherein the GNSS receiver includes a GNSS processing system, the GNSS processing system including an acquisition engine and a tracking engine, the acquisition engine including the processing logic for receiving an array of GNSS sample data arranged in row or column order according to the reception time and stored in one or more circular buffers.

156. The method of claim 155, wherein code spectrum data for each of the first GNSS primary PRN code data and the second GNSS primary PRN code data is repeatedly generated during a time period during the capture of GNSS signal components containing the first GNSS primary PRN code data and the second GNSS primary PRN code data, and wherein the code spectrum data is generated in place in the capture engine.

157. The method of claim 156, wherein the GNSS sample data is processed by the following steps to separate the GNSS sideband A sample data from the GNSS sideband B sample data: (1) for GNSS sideband A, shifting the sample centered at a first frequency up by a first offset frequency and performing low-pass filtering to capture data of a first bandwidth, and downsampling the output of the low-pass filtering to a lower sampling rate; and (2) for GNSS sideband B, shifting the sample centered at the first frequency down by the first offset frequency and performing low-pass filtering to capture data of a second bandwidth, and downsampling the output of the low-pass filtering to a lower sampling rate.

158. The method of claim 151, wherein the computation operation does not require separate transpose or rearrangement of the sample data or the generated code spectrum data.

159. The method of claim 151, wherein the code generator performs at least one of the following: (1) generating GNSS sideband A main PRN code data every millisecond when the GNSS signal is being acquired and tracked and the GNSS sideband A main PRN code data is not stored after Fourier transform; and (2) generating GNSS sideband B main PRN code data every millisecond when the GNSS signal is being acquired and tracked and the GNSS sideband B main PRN code data is not stored after Fourier transform.

160. The method of claim 159, wherein the integral is incoherent during at least a portion of the acquisition phase when receiving the GNSS signal.

161. A GNSS receiver, comprising: Radio frequency analog-to-digital converter (ADC) is used to generate a digital representation of the received GNSS signal; A sample memory for storing the digital representation of the received GNSS signal as digitized GNSS sample data, the sample memory being configured to store the digitized GNSS sample data; A GNSS processing system, coupled to the sample memory, is configured to process the GNSS sample data, the GNSS sample data comprising one or more of the following: (1) GNSS sideband A sample data from a received GNSS signal; or (2) GNSS sideband B sample data from a received GNSS signal; and The GNSS processing system is configured as follows: Calculate the first set of Discrete Fourier Transforms (DFTs) of the GNSS sample data to provide the first set of results; Calculate the second set of DFTs for the first GNSS primary PRN code data, which is adjusted for code Doppler and carrier Doppler before the second set of DFTs. The second set of DFTs provides the second set of results. Based on the first set of results and the second set of results, the first set of correlations between the received GNSS signal and the first GNSS master PRN code is calculated to provide the third set of results; The third set of results is integrated with at least one previous sum, wherein the integration of the third set of results includes at least one new sum for the correlation storage of the first GNSS master PRN code data and the received GNSS signal.

162. The GNSS receiver of claim 161, wherein the GNSS receiver receives and processes only GNSS signals in the L5 radio frequency (RF) band and does not use GNSS signals in the L1 RF band, wherein the second set of results provides a code spectrum for correlating the first GNSS master code data with the GNSS sample data, and wherein the first GNSS master PRN code data is stored in the GNSS receiver or generated in the GNSS receiver during the acquisition phase of the GNSS receiver.

163. The GNSS receiver of claim 161, wherein the GNSS receiver further receives and processes GNSS signals in the L1RF band.

164. The GNSS receiver of claim 161, wherein the GNSS sample data comprises GNSS sideband A sample data from the received GNSS signal, and the GNSS sideband A sample data includes: The E5AI component contains the second GNSS master PRN code data; and the E5AQ component containing the first GNSS master PRN code data, wherein the GNSS processing system is configured as follows: A third set of DFTs is calculated for the second GNSS primary PRN code data, which is adjusted for code Doppler and carrier Doppler before the third set of DFTs, and the third set of DFTs provides a fourth set of results; Based on the first set of results and the fourth set of results, the second set of correlations between the received GNSS signal and the second GNSS master PRN code is calculated to provide the fifth set of results; The fifth set of results is integrated with at least one previous sum, wherein the integration of the fifth set of results includes at least one new sum for the correlation storage of the second GNSS master PRN code data and the received GNSS signal.

165. The GNSS receiver of claim 161, wherein the GNSS sample data comprises GNSS sideband B sample data from the received GNSS signal, and the GNSS sideband B sample data includes: The E5BI component contains the second GNSS master PRN code data; And the E5BQ component containing the first GNSS master PRN code data, wherein the GNSS processing system is configured to: A third set of DFTs is calculated for the second GNSS primary PRN code data, which is adjusted for code Doppler and carrier Doppler before the third set of DFTs, and the third set of DFTs provides a fourth set of results; Based on the first set of results and the fourth set of results, the second set of correlations between the received GNSS signal and the second GNSS master PRN code is calculated to provide the fifth set of results; The fifth set of results is integrated with at least one previous sum, wherein the integration of the fifth set of results includes at least one new sum for the correlation storage of the second GNSS master PRN code data and the received GNSS signal.

166. The GNSS receiver of claim 161, wherein the GNSS receiver includes a time-domain correlator, and the time-domain correlator is used to track the mode after the processing logic for calculating the DFT has captured the GNSS signal.

167. The GNSS receiver of claim 161, wherein code spectrum data for each of the first GNSS master PRN code data and the second GNSS master PRN code data are repeatedly generated during a time period during the capture of GNSS signal components containing the first GNSS master PRN code data and the second GNSS master PRN code data.

168. The GNSS receiver of claim 167, wherein the code generator in the GNSS receiver performs at least one of the following: (1) generating GNSS sideband A main PRN code data every millisecond when the GNSS signal is being acquired and the GNSS sideband A main PRN code data is not stored after Fourier transform; and (2) generating GNSS sideband B main PRN code data every millisecond when the GNSS signal is being acquired and the GNSS sideband B main PRN code data is not stored after Fourier transform.

169. The GNSS receiver of claim 1-67, wherein the code spectrum data is generated in-situ in the acquisition engine.

170. A method for mitigating interference in a GNSS receiver, the method comprising: In the GNSS receiver, a GNSS signal from GNSS SV is received, the received GNSS signal having a first GNSS signal component in a first sideband of the GNSS signal from GNSS SV and a second GNSS signal component in a second sideband of the GNSS signal from GNSS SV; Interference from a signal source is detected, which interferes more with the first GNSS signal component in the first sideband than with the second GNSS signal component in the second sideband. In response to detected interference, the GNSS processing system in the GNSS receiver is configured to process the second sideband from the GNSS SV without processing the first sideband in order to capture or track GNSS signals from the GNSS SV.

171. The method of claim 170, wherein the method further comprises: In response to the detection of a change in the interference, the system switches to processing the first sideband instead of the second sideband.

172. The method of claim 170, wherein the interference is detected when: (1) the intensity of the signal source is above a threshold above the noise floor; or (2) the post-correlation signal-to-noise ratio of a particular sideband is below a given threshold.

173. The method of claim 172, wherein the GNSS processing system processes the second sideband but not the first sideband during the duration of the detected interference, and resumes processing both sidebands after the interference decreases to below the noise floor, the noise floor being fixed or dynamically adjusted.

174. The method of claim 170, wherein the source of the interference signal is an aviation radio navigation source.

175. The method of claim 170, wherein the first sideband is a Galileo E5A sideband, which includes E5AI signal components and E5AQ signal components, and the second sideband is a Galileo E5B sideband, which includes E5BI signal components and E5BQ signal components.

176. The method of claim 170, wherein the first sideband is a Galileo E5B sideband, which includes E5BI signal components and E5BQ signal components, and the second sideband is a Galileo E5A sideband, which includes E5AI signal components and E5AQ signal components.

177. The method of claim 170, wherein the GNSS receiver receives and captures GNSS signals in the L5 band without receiving and capturing GNSS signals in the L1 band.

178. The method of claim 170, wherein when the first sideband is not processed, one or more signal components in the first sideband are not used to determine location data.

179. The method of claim 170, wherein the GNSS receiver further receives and processes GNSS signals in the L1RF band.

180. A GNSS receiver, comprising: A GNSS antenna used to receive GNSS signals from GNSS SV; An analog-to-digital converter (ADC) is used to generate a digital representation of the received GNSS signal, the ADC being coupled to the GNSS antenna; A sample memory for storing the digital representation of the received GNSS signal as digitized GNSS sample data, the sample memory being configured to store the digitized GNSS sample data and coupled to the ADC; A GNSS processing system, coupled to the sample memory, is configured to process GNSS sample data, the GNSS sample data comprising: (1) a first signal component from a first sideband of a received GNSS signal; and (2) a second signal component from a second sideband of a received GNSS signal; and the GNSS processing system is configured to: Interference from a signal source is detected, which interferes more with the first GNSS signal component in the first sideband than with the second GNSS signal component in the second sideband. In response to detected interference, the GNSS processing system in the GNSS receiver is configured to process the second sideband from the GNSS SV without processing the first sideband in order to capture or track GNSS signals from the GNSS SV.

181. The GNSS receiver of claim 180, wherein the GNSS processing system is configured to: in response to detecting a change in the interference, switch to processing signal components in the first sideband instead of the second sideband.

182. The GNSS receiver of claim 180, wherein the interference is detected when: (1) the strength of the signal source is above a threshold above the noise floor; or (2) the post-correlation signal-to-noise ratio of a particular sideband is below a given threshold.

183. The GNSS receiver of claim 182, wherein the GNSS processing system processes one or more signal components in a second sideband instead of a first sideband during the duration of the detected interference, and resumes processing signal components in both sidebands after the interference decreases to below the noise floor, the noise floor being fixed or dynamically adjusted.

184. The GNSS receiver of claim 180, wherein the source of the interference signal is an aviation radio navigation source.

185. The GNSS receiver of claim 180, wherein the first sideband is a Galileo E5A sideband, which includes E5AI signal components and E5AQ signal components, and the second sideband is a Galileo E5B sideband, which includes E5BI signal components and E5BQ signal components.

186. The GNSS receiver of claim 180, wherein the first sideband is a Galileo E5B sideband, which includes E5BI signal components and E5BQ signal components, and the second sideband is a Galileo E5A sideband, which includes E5AI signal components and E5AQ signal components.

187. The GNSS receiver of claim 180, wherein the GNSS receiver receives and captures GNSS signals in the L5 band without receiving and capturing GNSS signals in the L1 band.

188. The GNSS receiver of claim 180, wherein when the first sideband is not processed, one or more signal components in the first sideband are not used to determine location data.

189. The GNSS receiver of claim 180, wherein the GNSS receiver further receives and processes GNSS signals in the L1RF band.

190. A method for operating a GNSS receiver, the method comprising: In the GNSS receiver, a code spectrum of the GNSS master PRN code is generated. The generation of the code spectrum includes frequency shifting and time shifting of the GNSS master PRN code, and then calculating the discrete Fourier transform (DFT) of the shifted GNSS master PRN code to generate the code spectrum. The product of the code spectrum representation and the result of the DFT of the GNSS sample data from the received GNSS signal is calculated.

191. The method of claim 190, wherein the GNSS processing system in the GNSS receiver calculates the DFT of the shifted GNSS master PRN code and calculates the correlation between the GNSS master PRN code and the received GNSS signal, the correlation being based on the product of the representation of the code spectrum and the result of the DFT of the GNSS sample data.

192. The method of claim 191, wherein the GNSS processing system captures at least two of at least four GNSS signal components of a GNSS signal from a GNSSSV by performing an incoherent integration for a period of time on the at least two of the four GNSS signal components in an array processing system of the GNSS processing system, the array processing system receiving GNSS sample data from a baseband memory and the GNSS sample data being formatted as a row-column array having a plurality of rows and columns.

193. The method of claim 192, wherein the GNSS receiver receives and captures GNSS signals in the L5 band without receiving and capturing GNSS signals in the L1 band.

194. The method of claim 193, wherein the GNSS receiver includes a time-domain correlator, and the time-domain correlator is used in tracking mode after the GNSS processing system for calculating the DFT has acquired the GNSS signal.

195. The method of claim 194, wherein the code spectrum for the GNSS primary PRN code is repeatedly generated during a time period during the acquisition of GNSS signal components containing the GNSS primary PRN code, wherein the code spectrum is generated in place within the acquisition engine of the GNSS receiver, wherein the time period is greater than 2 milliseconds, and wherein the generation of the code spectrum includes upsampling interpolation.

196. The method of claim 192, wherein the GNSS receiver includes a time-domain correlator, and the time-domain correlator is used in tracking mode after the GNSS processing system for calculating the DFT has acquired the GNSS signal, and wherein the GNSS receiver also receives and processes GNSS signals in the L1RF band.

197. The method of claim 196, wherein the code spectrum for the GNSS master PRN code is repeatedly generated during a time period during the acquisition of GNSS signal components containing the GNSS master PRN code, wherein the code spectrum data is generated in place within the acquisition engine of the GNSS receiver, and wherein the time period is greater than 2 milliseconds.

198. A method for processing GNSS signals in a Global Navigation Satellite System (GNSS) receiver, the method comprising: Time-aided data is received from a source coupled to the network via the network; In the GNSS receiver, the time-aided data is used to directly capture GNSS signals in the L5 radio frequency (RF) band.

199. The method of claim 198, wherein the GNSS receiver directly captures the GNSS signal in the L5RF band without using the capture of the GNSS signal in the L1RF band to assist in capturing the GNSS signal in the L5RF band.

200. The method of claim 199, wherein the time-aided data is a precise time-aided method.

201. The method of claim 199, wherein the time-aided data is estimated or known within + / - 0.5 milliseconds of the actual GNSS time.

202. The method of claim 199, wherein the GNSS receiver does not include radio frequency circuitry for capturing GNSS signals in the L1 RF band, and wherein the master code in the GNSS signals in the L5 band is directly captured.

203. The method of claim 202, wherein the GNSS receiver receives location assistance data through the network, the location assistance data providing an approximate location of the GNSS receiver.

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