Memory and forming method thereof
By using a dielectric structure of alumina and zirconium-doped hafnium oxide in DRAM, the problems of increased leakage current and reduced capacitance caused by size reduction in DRAM devices are solved, achieving higher capacitance and better data retention performance.
Patent Information
- Application Number
- CN202511090249.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2025-03-28
- Filing Date
- 2025-08-05
- Publication Date
- 2025-11-11
AI Technical Summary
As DRAM device sizes shrink, leakage current increases and capacitance decreases, leading to a decline in data retention performance. Existing technologies struggle to effectively address leakage issues and achieve the battery capacitance required for future trends.
A capacitor structure is formed by atomic layer deposition using a dielectric structure consisting of bottom and top barrier layers formed by alumina process, multiple dielectric layers made of zirconium-doped hafnium oxide, and alumina insertion layers, thereby enhancing dielectric performance and reducing leakage current.
By improving the crystal structure stability of the dielectric layer and the wide bandgap characteristics of the barrier layer, leakage current is reduced, capacitance is increased, and data retention performance is improved.
Smart Images
Figure CN120936027A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a memory and a method for forming the same. Background Technology
[0002] To improve the data retention of Dynamic Random Access Memory (DRAM) retention The cells need to have a high dielectric constant (ε) and low cell stack leakage (Ic). L Furthermore, due to the reduction in device size, the leakage current of DRAM cells increases, and the capacitance (C) s To address leakage current issues and achieve the battery capacitance required for future trends, this invention provides a novel structure and a material with a higher dielectric constant. Summary of the Invention
[0003] One aspect of the present invention provides a memory including a substrate and a capacitor structure above the substrate. The capacitor structure includes: a bottom electrode, a dielectric structure above the bottom electrode, and a top electrode above the dielectric structure. The dielectric structure includes a bottom barrier layer made of alumina, a top barrier layer made of alumina and located above the bottom barrier layer, and a stack consisting of a plurality of dielectric layers and at least one insertion layer, the plurality of dielectric layers being made of zirconium-doped hafnium oxide, and at least one insertion layer being made of alumina, the stack being located between the bottom barrier layer and the top barrier layer, wherein the at least one insertion layer is located between two adjacent dielectric layers; and a top electrode located above the dielectric structure.
[0004] In some embodiments, the zirconium concentration of the dielectric layer is from about 50% to about 100%.
[0005] In some embodiments, the bottom barrier layer and the top barrier layer contact the bottom electrode and the top electrode, respectively.
[0006] In some embodiments, the bottom electrode and the top electrode are made of titanium nitride.
[0007] In some embodiments, the bottom electrode is made of polysilicon, while the top electrode is made of titanium nitride.
[0008] In some embodiments, the memory further includes a silicon oxide layer located between the bottom electrode and the bottom barrier layer.
[0009] In some embodiments, the bottom barrier layer and the top barrier layer are thicker than at least one insert layer.
[0010] In some embodiments, the dielectric structure includes a plurality of insertion layers, wherein each of the plurality of insertion layers is located between two adjacent dielectric layers.
[0011] In some embodiments, the dielectric layer has a crystal structure of tetragonal and orthorhombic phases.
[0012] In some embodiments, the memory further includes: a word line structure located above a substrate; and a bit line structure located above the substrate and electrically connected to a doped region of the substrate located on a first side of the word line structure, wherein a capacitor structure is electrically connected to another doped region of the substrate located on a second side of the word line structure.
[0013] One aspect of the present invention provides a method for forming a memory, the method comprising: forming a capacitor structure above a substrate, comprising: depositing a bottom electrode; forming a dielectric structure above the bottom electrode, comprising: forming a bottom barrier layer made of alumina; forming a stack comprising a plurality of dielectric layers and at least one insertion layer, the plurality of dielectric layers being made of zirconium-doped hafnium oxide and the at least one insertion layer being made of alumina, wherein the stack is located above the bottom barrier layer, and wherein the at least one insertion layer is located between two adjacent dielectric layers; forming a top barrier layer made of alumina and located above the stack of the plurality of dielectric layers and the at least one insertion layer; and forming a top electrode above the dielectric structure.
[0014] In some embodiments, the zirconium concentration of the dielectric layer is from about 50% to about 100%.
[0015] In some embodiments, the bottom barrier layer and the top barrier layer contact the bottom electrode and the top electrode, respectively.
[0016] In some embodiments, the bottom electrode and the top electrode are made of titanium nitride.
[0017] In some embodiments, the bottom electrode is made of polycrystalline silicon, while the top electrode is made of titanium nitride.
[0018] In some embodiments, the method further includes oxidizing a portion of the bottom electrode into an oxide layer.
[0019] In some embodiments, the oxide layer comprises silicon oxide.
[0020] In some embodiments, forming the bottom barrier layer includes performing an atomic layer deposition (ALD) process by providing an oxygen source and an aluminum source, wherein the oxygen source oxidizes a portion of the bottom electrode into an oxide layer.
[0021] In some embodiments, the bottom barrier layer and the top barrier layer are thicker than at least one insert layer.
[0022] In some embodiments, the method further includes: forming a word line structure above a substrate; and forming a bit line structure above the substrate and electrically connected to a doped region of the substrate located on a first side of the word line structure, wherein a capacitor structure is electrically connected to another doped region of the substrate on a second side of the word line structure.
[0023] It should be understood that the foregoing general description and the following detailed description are by way of example and are intended to provide a further explanation of the claims made in this invention. Attached Figure Description
[0024] The scope of the invention is best understood by reading the accompanying drawings and the following detailed description. Note that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation.
[0025] Figures 1 to 3 This is a schematic diagram of a capacitor structure according to some embodiments of the present invention.
[0026] Figure 4 This is a circuit diagram of a memory cell according to some embodiments of the present invention.
[0027] Figure 5 This is a cross-sectional view of a memory according to some embodiments of the present invention.
[0028] Figures 6-14 This is a cross-sectional view of various stages of forming a memory according to some embodiments of the present invention. Detailed Implementation
[0029] Reference will now be made in detail to embodiments of the invention, examples of which are illustrated in the accompanying drawings. Where possible, the same reference numerals are used in the drawings and description to refer to the same or similar components.
[0030] As used herein, “approximately,” “about,” or “substantially” generally means within 20%, 10%, or 5% of a given value or range. The values given herein are approximate and the terms “approximately,” “about,” or “substantially” can be inferred unless explicitly stated otherwise. However, those skilled in the art will recognize that the values or ranges listed throughout the description are merely examples and can be reduced or changed as integrated circuits shrink.
[0031] Figure 1 This is a schematic diagram illustrating a capacitor structure according to some embodiments of the present invention. Please refer to... Figure 1The capacitor structure 100A includes a bottom electrode 110, a dielectric structure 140 above the bottom electrode 110, and a top electrode 150 above the dielectric structure 140. In some embodiments, the bottom electrode 110 may be made of the same material as the top electrode 150. For example, the bottom electrode 110 and the top electrode 150 may comprise titanium nitride (TiN). In other embodiments, the bottom electrode 110 may be made of a different material than the top electrode 150.
[0032] The dielectric structure 140 can be a multilayer structure with multiple stacked dielectric layers. The dielectric structure 140 in the capacitor structure 100A may include a barrier layer 120a, a dielectric layer 130a on the barrier layer 120a, an insertion layer 125a on the dielectric layer 130a, a dielectric layer 130b on the insertion layer 125a, and a barrier layer 120b on the dielectric layer 130b. For example... Figure 1 As shown, dielectric layers 130a and 130b can be separated in the vertical direction by an insertion layer 125a. Furthermore, barrier layers 120a and 120b are adjacent to and in contact with the bottom electrode 110 and the top electrode 150, respectively.
[0033] In some embodiments, barrier layer 120a, barrier layer 120b, and insertion layer 125a may comprise the same high-k dielectric material, such as aluminum oxide (Al₂O₃). x In some embodiments, dielectric layers 130a and 130b may comprise the same high-k dielectric material, such as hafnium oxide (HfO2). In some embodiments, dielectric layers 130a and 130b (e.g., HfO2) may be doped with zirconium (Zr) at a concentration between about 50% and about 100% (e.g., 70%). In some embodiments, barrier layers 120a, 120b, and insertion layer 125a may be zirconium-free. That is, the zirconium concentration in barrier layers 120a, 120b, and insertion layer 125a may be lower than the zirconium concentration in dielectric layers 130a and 130b.
[0034] Dielectric layers 130a and 130b have orthorhombic and tetragonal crystal structures, respectively. In some embodiments, by doping dielectric layers 130a and 130b with zirconium, each dielectric layer 130a and 130b includes a certain proportion of orthorhombic and tetragonal crystal phases, which can also be referred to as morphotropic phase boundaries (MPB). This configuration can achieve a conditional equivalent oxide thickness (EOT) due to a higher k value, thereby increasing capacitance and reducing leakage current.
[0035] The manufacturing method of the 100A capacitor structure will be described in more detail below. For example... Figure 1As shown, in some embodiments, the bottom electrode 110, barrier layers 120a and 120b, insertion layer 125a, dielectric layer 130a and 130b, and top electrode 150 can be sequentially deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD) processes (e.g., low-pressure CVD (LPCVD) and / or plasma-enhanced CVD (PECVD)), atomic layer deposition (ALD), and / or other suitable deposition processes.
[0036] In some embodiments, dielectric layers 130a and 130b are made of zirconium-doped hafnium oxide (HfO2), and dielectric layers 130a and 130b can be formed using an ALD process. The ALD process may include alternately performing several hafnium oxide (HfO2) deposition cycles and zirconium oxide (ZrO2) deposition cycles until each dielectric layer 130a and 130b reaches a desired thickness, for example, about 5 nm.
[0037] In some embodiments, when the barrier layer 120a and the barrier layer 120b are made of aluminum oxide (AlO4), x During fabrication, barrier layers 120a and 120b can be formed using an ALD process. Barrier layers 120a and 120b are perpendicularly adjacent to the bottom electrode 110 and top electrode 150, respectively, and can suppress leakage current due to their wide band gap characteristics and improved surface shallow defects. Furthermore, barrier layer 120a serves as a barrier layer to suppress diffusion between the bottom electrode 110 and dielectric layer 130a. Similarly, barrier layer 120b serves as a barrier layer to suppress diffusion between the top electrode 150 and dielectric layer 130b.
[0038] In some embodiments, the material of the insert layer 125a is alumina (AlO2). x The insertion layer 125a can be formed using the ALD process. For example... Figure 1 As shown, the insertion layer 125a separates the dielectric layer 130a from the dielectric layer 130b, thereby reducing the effective thickness, stack leakage, and monoclinic phase ratio. Furthermore, the barrier layers 120a, 120b, and insertion layer 125a stabilize the phase transition at the phase boundary (MPB). In some embodiments, if the insertion layer 125a is absent, the dielectric layer 130a will contact the dielectric layer 130b, resulting in a thicker composite dielectric layer. However, if the dielectric layer (e.g., HfZrO) is too thick, the crystal structure of the dielectric layer tends to contain more monoclinic phases, which degrade the ferroelectric properties of the dielectric layer, which is detrimental to the capacitor structure.
[0039] In some embodiments, barrier layers 120a and 120b may have the same thickness. In some embodiments, the thickness of barrier layers 120a and 120b is different from the thickness of insertion layer 125a. In some embodiments, the thickness of barrier layers 120a and 120b is greater than the thickness of insertion layer 125a. As described above, insertion layer 125a is used to separate dielectric layer 130a and dielectric layer 130b, therefore insertion layer 125a does not need to be excessively thick.
[0040] although Figure 1 Only planar capacitors are shown in this paper, but the spirit of the invention can also be applied to capacitors with different designs, such as cylindrical capacitors or base-type capacitors.
[0041] Figure 2 This is a schematic diagram of a capacitor structure according to some embodiments of the present invention. (Reference) Figure 2 The capacitor structure 100B includes a bottom electrode 110, a dielectric structure 142 above the bottom electrode 110, and a top electrode 150 above the dielectric structure 142. Figure 2 The capacitor structure 100B shown is... Figure 1 The capacitor structure shown is similar to the 100A capacitor. (And...) Figure 1 and Figure 2 Identical or similar components use the same reference number, and therefore their detailed descriptions are omitted.
[0042] The dielectric structure 142 may be a multilayer structure with multiple stacked dielectric layers. The dielectric structure 142 in capacitor structure 100B may include barrier layers 120, dielectric layers 130, and insertion layers 125 alternately stacked above the bottom electrode 110. For example, for ease of illustration, the dielectric structure 142 is shown as including two barrier layers 120, four dielectric layers 130, and three insertion layers 125. It will be understood that the dielectric structure 142 may include any number of insertion layers 125 and dielectric layers 130. Figure 2 As shown, the dielectric layer 130 can be separated by the insertion layer 125 in the vertical direction. In addition, the barrier layer 120 is adjacent to the bottom electrode 110 and the top electrode 150.
[0043] In some embodiments, the barrier layer 120 and the insertion layer 125 may comprise the same high-k dielectric material, such as aluminum oxide (Al₂O₃). xIn some embodiments, dielectric layer 130 may include a high-k dielectric material, such as hafnium oxide (HfO2). In some embodiments, dielectric layer 130 (e.g., HfO2) may be doped with zirconium (Zr) at a concentration between about 50% and about 100% (e.g., 70%). In some embodiments, barrier layer 120 and insert layer 125 may be zirconium-free. That is, the zirconium concentration in barrier layer 120 and insert layer 125 may be lower than the zirconium concentration in dielectric layer 130.
[0044] The dielectric layer 130 has a crystal structure of orthorhombic and tetragonal phases. In some embodiments, by doping the dielectric layer 130 with zirconium, the dielectric layer 130 may have a material composed of a type phase boundary (MPB) between the orthorhombic and tetragonal phases, thereby obtaining a conditionally equivalent oxide thickness (EOT) due to a higher k value, thereby increasing capacitance and reducing leakage current.
[0045] The manufacturing method of capacitor structure 100B will be described in more detail below. For example... Figure 2 As shown, in some embodiments, the bottom electrode 110, barrier layer 120, insertion layer 125, dielectric layer 130 and top electrode 150 can be deposited sequentially by physical vapor deposition (PVD), chemical vapor deposition (CVD) (e.g., low-pressure CVD (LPCVD) and / or plasma-enhanced CVD (PECVD)), atomic layer deposition (ALD) and / or other suitable deposition processes.
[0046] In some embodiments, the dielectric layer 130 is made of zirconium-doped hafnium oxide (HfO2), and the dielectric layer 130 can be formed using an ALD process. The ALD process may include alternating several hafnium oxide (HfO2) deposition cycles and zirconium oxide (ZrO2) deposition cycles until the dielectric layers 130a and 130b reach the desired thickness.
[0047] In some embodiments, when the barrier layer 120 is made of aluminum oxide (AlO) x During fabrication, a barrier layer 120 can be formed using an ALD process. The barrier layer 120 is perpendicularly adjacent to the bottom electrode 110 and the top electrode 150, enhancing the ferroelectric properties of the dielectric layer 130 and reducing leakage current due to its improved characteristics of a wide bandgap and shallow surface defects. Furthermore, the barrier layer 120 acts as a barrier, suppressing diffusion between the bottom electrode 110 and the dielectric layer 130, as well as between the top electrode 150 and the dielectric layer 130.
[0048] In some embodiments, the material of the insert layer 125 is alumina (AlO2). x The insertion layer 125 can be formed using the ALD process. For example... Figure 2As shown, the insertion layer 125 separates the dielectric layers 130 from each other, thereby reducing the effective thickness of the dielectric layer 130, stack leakage, and monoclinic crystal ratio. In addition, the barrier layer 120 and the insertion layer 125 stabilize the phase transition at the mode phase boundary (MPB).
[0049] In some embodiments, the thickness of each barrier layer 120 is different from the thickness of each insertion layer 125. In some embodiments, the thickness of each barrier layer 120 is greater than the thickness of each insertion layer 125.
[0050] exist Figure 2 In the process, the multilayer stacked unit structure of capacitor structure 100B can further improve the phase transition of MBP by reducing the effective thickness, and through multilayer AlO x Thin films are used to reduce leakage current.
[0051] although Figure 2 Only planar capacitors are shown in this paper, but the spirit of the invention can also be applied to capacitors with different designs, such as cylindrical capacitors or base-type capacitors.
[0052] Figure 3 A schematic diagram of a capacitor structure according to some embodiments of the present invention is shown. (Reference) Figure 3 The capacitor structure 100C includes a bottom electrode 112, an oxide layer 115 above the bottom electrode 112, a dielectric structure 144 above the oxide layer 115, and a top electrode 150 above the dielectric structure 144. Figure 3 The capacitor structure 100C shown is... Figure 1 and Figure 2 The capacitor structures 100A and 100B shown are similar. Throughout this document, unless otherwise stated, the same reference numerals in different figures denote the same or similar components formed using the same or similar materials by the same or similar methods.
[0053] In some embodiments, the material of the bottom electrode 112 may be different from the material of the top electrode 150. For example, the bottom electrode 112 may comprise polycrystalline silicon (poly-Si), while the top electrode may comprise titanium nitride (TiN). In some embodiments, the oxide layer 115 may be formed of silicon oxide (SiO2).
[0054] The dielectric structure 144 may be a multilayer structure with multiple dielectric layers stacked. The dielectric structure 144 in the capacitor structure 100C may include barrier layers 120, dielectric layers 130, and insertion layers 125 alternately stacked over the oxide layer 115. For example, for ease of illustration, the dielectric structure 144 is shown as including two barrier layers 120, two dielectric layers 130, and one insertion layer 125. It will be understood that the dielectric structure 144 may include any number of insertion layers 125 and dielectric layers 130. Figure 3 As shown, the dielectric layer 130 can be separated by the insertion layer 125 in the vertical direction. In addition, the barrier layer 120 is adjacent to the oxide layer 115 and the top electrode 150.
[0055] In some embodiments, the barrier layer 120 and the insertion layer 125 may comprise the same high-k dielectric material, such as aluminum oxide (Al₂O₃). x In some embodiments, dielectric layer 130 may include a high-k dielectric material, such as hafnium oxide (HfO2). In some embodiments, dielectric layer 130 (e.g., HfO2) may be doped with zirconium (Zr) at a concentration between about 50% and about 100% (e.g., 70%). In some embodiments, barrier layer 120 and insert layer 125 may be zirconium-free. That is, the zirconium concentration in barrier layer 120 and insert layer 125 may be lower than the zirconium concentration in dielectric layer 130.
[0056] The dielectric layer 130 has a crystal structure of orthorhombic and tetragonal phases. In some embodiments, by doping the dielectric layer 130 with zirconium, the dielectric layer 130 may have a material composed of a type phase boundary (MPB) between the orthorhombic and tetragonal phases, thereby obtaining a conditionally equivalent oxide thickness (EOT) due to a higher k value, thereby increasing capacitance and reducing leakage current.
[0057] The manufacturing method of capacitor structure 100C will be described in more detail below. For example... Figure 3 As shown, in some embodiments, the bottom electrode 112, barrier layer 120, insertion layer 125, dielectric layer 130 and top electrode 150 can be deposited sequentially by physical vapor deposition (PVD), chemical vapor deposition (CVD) (e.g., low-pressure CVD (LPCVD) and / or plasma-enhanced CVD (PECVD)), atomic layer deposition (ALD) and / or other suitable deposition processes.
[0058] In some embodiments, the dielectric layer 130 is made of zirconium-doped hafnium oxide (HfO2), and the dielectric layer 130 can be formed using an ALD process. The ALD process may include alternating several hafnium oxide (HfO2) deposition cycles and zirconium oxide (ZrO2) deposition cycles until the dielectric layers 130a and 130b reach the desired thickness.
[0059] In some embodiments, the barrier layer 120 is made of aluminum oxide (AlO2). xThe barrier layer 120 can be formed using an ALD process. The barrier layer 120 is perpendicularly adjacent to the bottom electrode 112 and the top electrode 150. It enhances the ferroelectric properties of the dielectric layer 130 and reduces leakage current due to its wide bandgap and improved surface shallow defects. Furthermore, the barrier layer 120 also acts as a barrier, suppressing diffusion between the top electrode 150 and the dielectric layer 130.
[0060] In some embodiments, the material of the insert layer 125 is alumina (AlO2). x The insertion layer 125 can be formed using the ALD process. For example... Figure 3 As shown, the insertion layer 125 separates the dielectric layers 130 from each other, thereby reducing the effective thickness of the dielectric layer 130, stack leakage, and monoclinic crystal ratio. In addition, the barrier layer 120 and the insertion layer 125 stabilize the phase transition at the mode phase boundary (MPB).
[0061] In some embodiments, during an ALD process in which a barrier layer 120 is formed over the bottom electrode 112, an oxygen source and an aluminum source may be supplied to the deposition chamber along with a carrier gas. In such an embodiment, the oxygen source may oxidize the top portion of the bottom electrode, made of polycrystalline silicon, during the ALD process, subsequently resulting in the formation of an oxide layer 115. In some embodiments, the oxide layer 115 may comprise silicon oxide (SiO2). Furthermore, after the formation of the oxide layer 115, the thickness of the bottom electrode 112 is reduced. In some embodiments, the oxygen source may comprise oxygen (O2), ozone (O3), water (H2O), or other suitable oxygen sources, and the aluminum source may comprise trimethylaluminum (TMA), aluminum chloride, or other suitable aluminum sources.
[0062] In some embodiments, the bottom electrode 112 is oxidized by providing an oxygen source, such as oxygen (O2), ozone (O3), water (H2O), or other suitable oxygen source, to form an oxide layer 115 over the bottom electrode 112. In some embodiments, the oxide layer 115 may comprise silicon oxide (SiO2). Furthermore, the thickness of the bottom electrode 112 is reduced after the oxide layer 115 is formed.
[0063] In some embodiments, the thickness of each barrier layer 120 is different from the thickness of each insertion layer 125. In some embodiments, the thickness of each barrier layer 120 is greater than the thickness of each insertion layer 125. In some embodiments, the oxide layer 115 is the thinnest layer in the dielectric structure 144.
[0064] exist Figure 3 In the process, the multilayer stacked unit structure of capacitor structure 100C can further improve the phase transition of MBP by reducing the effective thickness, and through multilayer AlO x Thin films are used to reduce leakage current.
[0065] although Figure 3 Only planar capacitors are shown in this paper, but the spirit of the invention can also be applied to capacitors with different designs, such as cylindrical capacitors or base-type capacitors.
[0066] Figure 4 This is a circuit diagram of a memory cell according to some embodiments of the present invention. (Reference) Figure 4 The memory 200 comprises a plurality of memory cells 202 arranged in a rectangular matrix structure. In some embodiments, the memory 200 is a dynamic random access memory (DRAM) device. Each memory cell 202 of the memory 200 is primarily composed of a transistor 200T and a capacitor 200C electrically connected to the transistor 200T. One side of the capacitor 200C is coupled to the drain region of the transistor 200T, while the other side of the capacitor 200C is coupled to ground. The memory 200 also includes a word line 200W coupled to the gate region of the transistor 200T, and a bit line 200B coupled to the source of the transistor 200T.
[0067] Figure 5 This is a cross-sectional view of a memory according to some embodiments of the present invention. Memory 300 is shown. In some embodiments, the cross-sectional view of memory 300 may be as follows: Figure 4 An example of the memory 200 discussed.
[0068] The memory 300 includes a substrate 301. In some embodiments, the substrate 301 may be a suitable semiconductor material, such as silicon, silicon carbide, gallium arsenide, gallium phosphide, germanium, indium antimonide, indium phosphide, indium arsenide, etc. The substrate 301 may also be doped with suitable dopants. For example, the substrate 301 may be doped with p-type dopants, such as boron (B), gallium (Ga), indium (In), aluminum (Al), etc. In other embodiments, the substrate 301 may be doped with n-type dopants, such as phosphorus (P), arsenic (As), or antimony (Sb), etc.
[0069] An isolation structure 302 is disposed within the substrate 301. The isolation structure 302 can be a suitable isolation structure, such as a shallow trench isolation (STI) structure. Figure 5 The cross-sectional view shows two isolation structures 302 that define an active region 301A, on which at least one transistor is formed. In some embodiments, the isolation structure 302 may be made of a suitable dielectric material, such as silicon oxide, silicon nitride, etc.
[0070] The memory 300 also includes multiple word line structures 316A and 316B. More specifically, in Figure 5 In the cross-sectional view, the character line structure 316A is embedded in the active region 301A of the substrate 301, while the character line structure 316B is embedded in the isolation structure 302.
[0071] The memory 300 also includes a dielectric layer 306A located above the corresponding word line structure 316A, and a dielectric pad 303A serving as a liner for the corresponding word line structure 316A and the corresponding dielectric layer 306A. In some embodiments, the dielectric layer 306A may include a suitable dielectric material, such as silicon oxide, silicon nitride, etc. In some embodiments, the dielectric pad 303A may include a suitable dielectric material, such as silicon oxide, silicon nitride, etc.
[0072] Similarly, the memory 300 also includes a dielectric layer 306B above the corresponding word line structure 316B, and a dielectric pad 303B serving as a backing for the corresponding word line structure 316B and the corresponding dielectric layer 306B. The materials of the dielectric layer 306B and the dielectric pad 303B may be similar to those described with respect to the dielectric layer 306A and the dielectric pad 303A, so for the sake of brevity, the relevant details will not be repeated.
[0073] In some embodiments, each character line structure 316A includes a bottom conductive material 304A and a top conductive material 305A above the bottom conductive material 304A. In some embodiments, the bottom conductive material 304A and the top conductive material 305A are made of different materials. In some embodiments, the bottom conductive material 304A may include a suitable conductive material, such as cobalt, nickel, titanium, titanium nitride, tungsten, tungsten nitride, etc., or combinations thereof. For example, in some embodiments, a combination of titanium nitride and tungsten is used as the bottom conductive material 304A. In some embodiments, the top conductive material 305A may be a suitable material that reduces band bending between the active region 301A and the dielectric pad 303A. The top conductive material 305A may be a semiconductor material or a conductive material. In some embodiments, polysilicon is used for the top conductive material 305A. In some other embodiments, doped polysilicon is used for the top conductive material 305A. Although the top conductive material 305A is illustrated as having a rectangular cross-section, the invention is not limited thereto. In other embodiments, the cross-section of the top conductive material 305A may also be semi-circular, triangular, trapezoidal, inverted trapezoidal, or irregular.
[0074] For each character line structure 316B, each character line structure 316B includes a bottom conductive material 304B and a top conductive material 305B above the bottom conductive material 304B. The materials of the bottom conductive material 304B and the top conductive material 305B can be similar to the materials described for the bottom conductive material 304A and the top conductive material 305A, so for the sake of brevity, the relevant details will not be repeated.
[0075] The memory 300 also includes a plurality of doped regions 301D within the active region 301A of the substrate 301, wherein a pair of doped regions 301D are disposed on opposite sides of the word line structure 316A. In some embodiments, the doped regions 301D may include a conductivity type opposite to that of the substrate 301. For example, when the substrate 301 is a p-type substrate, the doped region 301D may be an n-type doped region. Similarly, when the substrate 301 is an n-type substrate, the doped region 301D may be a p-type doped region.
[0076] Here, the word line structure 316A, the dielectric pad 303A, the pair of doped regions 301D on opposite sides of the word line structure 316A, and the active region 301A of the substrate 301 can collectively serve as the transistors of the memory 300 (e.g., Figure 4 (Transistor 200T). More specifically, the word line structure 316A can serve as the gate electrode of the transistor, the dielectric pad 303A can serve as the gate dielectric of the transistor, the active region 301A of the substrate 301 can serve as the channel region of the transistor, and the doped region 301D can serve as the source / drain region of the transistor.
[0077] The memory 300 also includes a bit line structure 317 located above the substrate 301 and electrically coupled to one of the plurality of doped regions 301D. In some embodiments, the bit line structure 317 may include a masking contact 312A and a bit line 311A above the masking contact 312A. In some embodiments, the masking contact 312A has a portion embedded in the substrate 301 and a portion protruding from the substrate 301. In some embodiments, the material of the masking contact 312A may be doped silicon or polycrystalline silicon. In some embodiments, the material of the bit line 311A may be a suitable conductive material, such as tungsten, tungsten nitride, titanium nitride, or combinations thereof.
[0078] The memory 300 also includes capacitor contact structures 318 that are located above the substrate 301 and electrically coupled to the doped region 301D. In some embodiments, each capacitor contact structure 318 may include a masking contact 312B and a metal contact 311B above the masking contact 312B. In some embodiments, the masking contact 312B has a portion embedded in the substrate 301 and a portion protruding from the substrate 301. In some embodiments, the materials of the masking contact 312B and the metal contact 311B may be similar to those described with respect to the masking contact 312A and the bit line 311A, so for the sake of brevity, the relevant details will not be repeated.
[0079] The memory 300 also includes capacitor structures 315 above the respective capacitor contact structures 318. In some embodiments, each capacitor structure 315 includes a lower electrode 308, a barrier layer 309A, a dielectric layer 309B, an insertion layer 309C, and an upper electrode 310, wherein the barrier layer 309A, the dielectric layer 309B, and the insertion layer 309C are disposed between the upper electrode 310 and the lower electrode 308. In some embodiments, the lower electrode 308, the barrier layer 309A, the dielectric layer 309B, and the insertion layer 309C may have a U-shaped profile.
[0080] Figure 5 The capacitor structure 315 can be similar to that in Figures 1 to 3 The capacitor structures 100A-100C are discussed. More specifically, the lower electrode 308, barrier layer 309A, dielectric layer 309B, insertion layer 309C, and upper electrode 310 of capacitor structure 315 may each have similar materials and formation methods to the bottom electrode 110 or bottom electrode 112, barrier layer 120, dielectric layer 130, insertion layer 125, and top electrode 150 of capacitor structures 100A-100C. Therefore, for the sake of brevity, the relevant details will not be repeated.
[0081] The memory 300 also includes a dielectric layer 307 located above the substrate 301 and laterally surrounding the bit line structure 317, the capacitor contact structure 318, and the capacitor structure 315. In some embodiments, the dielectric layer 307 may be formed of, for example, silicon oxide, borosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric materials, or combinations thereof.
[0082] Figures 6 to 14 This is a cross-sectional view illustrating various stages of forming a memory according to some embodiments of the present invention. More specifically, Figures 6 to 14 The diagram illustrates the method used to form such as Figure 5 The method for the memory 300 discussed. Therefore, similar elements are labeled with the same schematic symbols, and related details will not be repeated for the sake of brevity.
[0083] Please refer to Figure 6A substrate 301 is provided. An isolation structure 302 is formed in the substrate 301 to define an active region 301A. For example, a series of deposition processes can be performed to deposit a pad oxide layer (not shown) and a pad nitride layer (not shown) over the substrate 301. A photolithography process can be performed to define the location of the isolation structure 302. After the photolithography process, an etching process such as anisotropic dry etching can be performed to form trenches penetrating the pad oxide layer, the pad nitride layer, and the substrate 301. In some embodiments, a cleaning process can be performed by a suitable cleaning method, such as wet cleaning. An insulating material can be deposited into the trenches, and a planarization process such as chemical mechanical polishing can then be performed to remove excess filler material until the substrate 301 is exposed. After the isolation structure 302 is formed, a doped region 301D can be formed within the active region 301A of the substrate 301 by an implantation process.
[0084] Please refer to Figure 7 Trench 501A and trench 501B are formed in substrate 301 and isolation structure 302, respectively. In some embodiments, a patterned mask (e.g., a photoresist layer) is formed over substrate 301, wherein the patterned mask may include openings defining the locations of trench 501A and trench 501B. Subsequently, an etching process can be performed through the openings of the patterned mask to remove portions of substrate 301 and isolation structure 302 to form trench 501A and trench 501B. In some embodiments, the etching process may be a suitable etching process, such as wet etching or dry etching. In some embodiments, an anisotropic etching process may be performed, such as reactive-ion etching (RIE), deep reactive-ion etching (DRIE), etc. In some embodiments, the aspect ratio of trench 501A may be different from (or the same as) the aspect ratio of trench 501B.
[0085] Please refer to Figure 8 Dielectric pad 303A and word line structure 316A are formed in trench 501A, and dielectric pad 303B and word line structure 316B are formed in trench 501B. Word line structure 316A includes a bottom conductive material 304A and a top conductive material 305A above the bottom conductive material 304A. Word line structure 316B includes a bottom conductive material 304B and a top conductive material 305B above the bottom conductive material 304B.
[0086] In some embodiments, a first deposition process may be performed to form materials for dielectric pads 303A and 303B over substrate 301 and on the pad sidewalls of trenches 501A and 501B. In some embodiments, the first deposition process may be a suitable deposition method, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), low-pressure CVD (LPCVD), ultra-high vacuum CVD (UHVCVD), atomic layer deposition (ALD), or similar deposition methods.
[0087] Next, a second deposition process can be performed to form bottom conductive materials 304A and 304B on the substrate 301 and overfill trenches 501A and 501B. Then, an etch-back process is performed to reduce the top surface of the bottom conductive materials 304A and 304B.
[0088] Next, a third deposition process can be performed to form the top conductive material 305A and the top conductive material 305B and to overfill the trenches 501A and 501B.
[0089] Following the deposition process, a planarization process, such as CMP, can be performed on the top conductive materials 305A and 305B until the substrate 301 is exposed. As a result, the top surfaces of the substrate 301, the top surfaces of the top conductive materials 305A and 305B, and the top surface of the isolation structure 302 are substantially coplanar. In some embodiments, a cleaning process can be performed after the planarization process.
[0090] Please refer to Figure 9 An etch-back process can be performed to reduce the top surfaces of the top conductive materials 305A and 305B, so as to form grooves 701A and 701B above the character line structure 316A and 316B, respectively.
[0091] Please refer to Figure 10 Dielectric layers 306A and 306B are formed over word line structures 316A and 316B, respectively. In some embodiments, a deposition process may be performed to form dielectric material over substrate 301 and cover word line structures 316A and 316B. Next, a planarization process may be performed to remove excess dielectric material until substrate 301 is exposed. In some embodiments, a planarization process may be performed to make the top surfaces of dielectric layers 306A and 306B coplanar with the surface of substrate 301.
[0092] Please refer to Figure 11Grooves 911A and 911B are formed in the doped region 301D of substrate 301. In some embodiments, the bottom of grooves 911A and 911B may be higher than the top surface of the top conductive material 305A. In some embodiments, a patterned mask (not shown) is formed over substrate 301, and an etching process is performed to remove portions of substrate 301 exposed through the patterned mask to form grooves 911A and 911B. In some embodiments, a cleaning process may be performed after the etching process. In some embodiments, groove 911A may be formed between adjacent dielectric layers 306A. In some embodiments, groove 911B may be formed between adjacent dielectric layers 306A and 306B.
[0093] Please refer to Figure 12 A first conductive layer 121 is formed above the substrate 301, and a second conductive layer 123 is formed above the first conductive layer 121. In some embodiments, the first conductive layer 121 may fill the grooves 911A and 911B and may contact the doped region 301D. In some embodiments, a suitable deposition process may be used to form the first conductive layer 121 and the second conductive layer 123.
[0094] Please refer to Figure 13 The first conductive layer 121 and the second conductive layer 123 are patterned to form a bit line structure 317 and a capacitor contact structure 318. In some embodiments, the bit line structure 317 includes a masking contact 312A and a bit line 311A above the masking contact 312A, wherein the masking contact 312A is the remaining portion of the first conductive layer 121, and the bit line 311A is the remaining portion of the second conductive layer 123. On the other hand, the capacitor contact structure 318 includes a masking contact 312B and a metal contact 311B above the masking contact 312B, wherein the masking contact 312B is the remaining portion of the first conductive layer 121, and the metal contact 311B is the remaining portion of the second conductive layer 123.
[0095] Please refer to Figure 14 A dielectric layer 307 is formed over the substrate 301 and covers the bit line structure 317 and the capacitor contact structure 318. Next, a capacitor structure 315 is formed in the dielectric layer 307 and contacts the corresponding capacitor contact structure 318. In some embodiments, a suitable deposition process can be used to form the dielectric layer 307. In some embodiments, the capacitor structure 315 can be formed by, for example, patterning the dielectric layer 307 to form an opening exposing the capacitor contact structure 318, depositing a lower electrode 308, a barrier layer 309A, a dielectric layer 309B, an insertion layer 309C, and an upper electrode 310 in the opening, followed by a planarization process until the dielectric layer 307 is exposed.
[0096] In some embodiments, additional processes and steps may be performed to complete the manufacturing process of the memory. In some embodiments, additional back-end processes (BEOL) may be performed on the memory 300.
[0097] Although the invention has been described in detail with reference to certain embodiments thereof, other embodiments are also possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
[0098] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the invention without departing from the scope or spirit of the invention. In view of the foregoing, the present invention is intended to cover any modifications and variations of the invention that fall within the scope of the appended claims.
[0099] [Symbol Explanation]
[0100] 100A: Capacitor Structure
[0101] 100B: Capacitor Structure
[0102] 100C: Capacitor Structure
[0103] 110: Bottom electrode
[0104] 112: Bottom electrode
[0105] 115: Oxide layer
[0106] 120: Barrier Layer
[0107] 120a: Barrier layer
[0108] 120b: Barrier layer
[0109] 121: First conductive layer
[0110] 123: Second conductive layer
[0111] 125: Insertion layer
[0112] 125a: Insertion layer
[0113] 130: Dielectric layer
[0114] 130a: Dielectric layer
[0115] 130b: Dielectric layer
[0116] 140: Dielectric structure
[0117] 142: Dielectric Structure
[0118] 144: Dielectric Structure
[0119] 150: Top electrode
[0120] 200: Memory
[0121] 200B: Bitline
[0122] 200C: Capacitor
[0123] 200T: Transistor
[0124] 200W: Character Line
[0125] 202: Memory Unit
[0126] 300: Memory
[0127] 301:Substrate
[0128] 301A: Active Area
[0129] 301D: Doped region
[0130] 302: Isolation Structure
[0131] 303A: Dielectric Pad
[0132] 303B: Dielectric Pad
[0133] 304A: Conductive material
[0134] 304B: Conductive material
[0135] 305A: Conductive material
[0136] 305B: Conductive material
[0137] 306A: Dielectric layer
[0138] 306B: Dielectric layer
[0139] 307: Dielectric layer
[0140] 308: Lower electrode
[0141] 309A: Barrier Layer
[0142] 309B: Dielectric layer
[0143] 309C: Insertion layer
[0144] 310: Upper electrode
[0145] 311A: Bitline
[0146] 311B: Metal contacts
[0147] 312A: Shielding Contact
[0148] 312B: Shielding Contact
[0149] 315: Capacitor Structure
[0150] 316A: Character Line Structure
[0151] 316B: Character Line Structure
[0152] 317: Bitline Structure
[0153] 318: Capacitor contact structure
[0154] 501A: Trench
[0155] 501B: Trench
[0156] 701A: Groove
[0157] 701B: Groove
[0158] 911A: Groove
[0159] 911B: Groove.
Claims
1. A memory, characterized in that, Include: Substrate; and A capacitor structure, located above the substrate, includes: Bottom electrode; A dielectric structure, located above the bottom electrode, comprises: The bottom barrier layer is made of aluminum oxide; A top barrier layer, made of aluminum oxide, is located above the bottom barrier layer; and A stack comprising a plurality of dielectric layers and at least one insertion layer, wherein the plurality of dielectric layers are made of zirconium-doped hafnium oxide and the at least one insertion layer is made of aluminum oxide, the stack being located between a bottom barrier layer and a top barrier layer, wherein the at least one insertion layer is located between two adjacent dielectric layers; and The top electrode is located above the dielectric structure.
2. The memory according to claim 1, wherein the zirconium concentration of the plurality of dielectric layers is between 50% and 100%.
3. The memory according to claim 1, wherein the bottom barrier layer and the top barrier layer respectively contact the bottom electrode and the top electrode.
4. The memory of claim 1, wherein the bottom electrode and the top electrode are made of titanium nitride.
5. The memory of claim 1, wherein the bottom electrode is made of polycrystalline silicon and the top electrode is made of titanium nitride.
6. The memory according to claim 5, wherein, It further includes a silicon oxide layer located between the bottom electrode and the bottom barrier layer.
7. The memory of claim 1, wherein the bottom barrier layer and the top barrier layer are thicker than the at least one insertion layer.
8. The memory of claim 1, wherein the dielectric structure comprises a plurality of said insertion layers, wherein each of the plurality of said insertion layers is located between two adjacent dielectric layers.
9. The memory according to claim 1, wherein the plurality of dielectric layers have a tetragonal and orthorhombic crystal structures.
10. The memory according to claim 1, wherein, Further includes: Character line structure, located above the substrate; and A bit line structure is located above the substrate and electrically connected to a doped region of the substrate located on a first side of the bit line structure, wherein the capacitor structure is electrically connected to another doped region of the substrate on a second side of the bit line structure.
11. A method for forming a memory, characterized in that, Include: A capacitor structure is formed on top of a substrate and includes: Deposited bottom electrode; A dielectric structure is formed above the bottom electrode and includes: A bottom barrier layer is formed, made of aluminum oxide; A stack is formed, comprising a plurality of dielectric layers and at least one insertion layer, wherein the plurality of dielectric layers are made of zirconium-doped hafnium oxide and the at least one insertion layer is made of aluminum oxide, and the stack is located above the bottom barrier layer, wherein the at least one insertion layer is located between two adjacent dielectric layers; as well as A top barrier layer, made of aluminum oxide, is formed and is located above the stack of the plurality of dielectric layers and the at least one insertion layer; as well as A top electrode is formed above the dielectric structure.
12. The method of claim 11, wherein the zirconium concentration of the plurality of dielectric layers is between 50% and 100%.
13. The method of claim 11, wherein the bottom barrier layer and the top barrier layer respectively contact the bottom electrode and the top electrode.
14. The method of claim 11, wherein the bottom electrode and the top electrode are made of titanium nitride.
15. The method of claim 11, wherein the bottom electrode is made of polycrystalline silicon and the top electrode is made of titanium nitride.
16. The method according to claim 15, wherein, Further includes: A portion of the bottom electrode is oxidized into an oxide layer.
17. The method of claim 16, wherein the oxide layer comprises silicon oxide.
18. The method of claim 15, wherein forming the bottom barrier layer comprises performing an atomic layer deposition process by providing an oxygen source and an aluminum source, and wherein the oxygen source oxidizes a portion of the bottom electrode into an oxide layer.
19. The method of claim 11, wherein the bottom barrier layer and the top barrier layer are thicker than the at least one insertion layer.
20. The method according to claim 11, wherein, Further includes: Forming a character line structure located above the substrate; and A bit line structure is formed, located above the substrate and electrically connected to a doped region of the substrate located on a first side of the bit line structure, wherein the capacitor structure is electrically connected to another doped region of the substrate on a second side of the bit line structure.