Active correction of potential transfer errors in storage device

Abstract

All channels (both in-band channels and sideband channels) between the controller and the storage device are continuously tracked, thereby avoiding the initiation of interface errors caused by a power drop. The tracking will include extracting the correlation indications and using a predictive model that associates the tracked indications with later occurrences of power drop events. In response to the prediction results, the system may perform different recovery operations (countermeasures). The controller will monitor different indications from the storage element and the power supply to predict signal integrity degradation marginal events on the interface. Monitoring and mitigating policy dependence on an open system. The controller does not employ a real-time continuous return channel from the storage device, which may signal pass / fail conditions. Given the nature of the open system and the calibration tolerances for the data collection, processing and inference system, the controller will also have to handle right and false recognition events.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of the entire contents of U.S. Nonprovisional Application No. 18 / 513,949, filed November 20, 2023, with the United States Patent and Trademark Office, entitled “Proactive Correction of Potential Transmission Errors in a Storage Device,” which is incorporated herein by reference for all purposes. Background Technology Technical Field

[0003] The embodiments disclosed herein generally relate to mitigating interface errors caused by power degradation in storage elements based on system prediction.

[0004] Description of related technologies

[0005] The interface between the storage element and the storage controller is structured to optimize the trade-off between transfer speed and power consumption. Bit flips may occur when data is transferred over the interface. In some implementations, interface transfers can be protected by error-correcting codes (ECC). However, the additional overhead (and cost) of allocating ECC parity checks, as well as the power and latency consumed by the encoding / decoding process, are detrimental to the overall system. Therefore, the interface is typically implemented without ECC. Other implementations may use redundancy for error checking (e.g., CRC). While error checking is more economical in terms of the number of redundancy overhead bits, it requires a reverse-channel handshake method to enable retransmission in the event of a fault. Error checking and reverse-channel interfaces also add complexity and latency, so error checking and reverse-channel interfaces, along with ECC methods, are avoided here.

[0006] Bit flips occurring on the interface can originate from desynchronization of interface sampling, from varying power degradation, or other events that compromise signal integrity. Previously, the scheduling interface was recalibrated after a period of time and based on indications of errors in the interface. However, these mitigation methods are "passive" and only respond to already degraded signal integrity, thus introducing systemic effects of potential performance and data loss.

[0007] In this field, there is a need to improve signal integrity while reducing interface errors. Summary of the Invention

[0008] Continuous tracking of all channels (both in-band and sideband channels) between the controller and storage device is used to avoid interface errors caused by power degradation. This tracking involves extracting relevant indications and using a predictive model that correlates the tracked indications with the subsequent occurrence of a power degradation event. In response to the predictions, the system can perform different recovery actions (countermeasures). The controller will monitor different indications from storage elements and power supplies to predict marginal events of signal integrity degradation on the interface. Monitoring and mitigation strategies rely on an open system. The controller does not utilize the real-time continuous return channel from the storage device, which signals pass / fail conditions. Given the nature of the open system and the calibration tolerances for the data collection, processing, and inference systems, the controller must also handle positive and negative identification events.

[0009] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: predict power problems or timing violations on one or more of a plurality of monitored channels; and initiate corrective actions to mitigate the impact of power problems or timing violations.

[0010] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller includes a central processing unit (CPU) and is configured to: monitor signals from a channel between the controller and the memory device; write data to the memory device; predict that the data needs to be resubmitted; and write data to volatile memory.

[0011] In another embodiment, a data storage device includes: means for storing data; and a controller coupled to the means for storing data, wherein the controller includes a prediction module and a flash interface module (FIM), wherein the controller is configured to: predict power problems or timing violations at the interface between the controller and the means for storing data; and take corrective action in response to the prediction. Attached Figure Description

[0012] To gain a more detailed understanding of the features of this disclosure, a more specific description of the disclosure, which has been briefly outlined above, can be obtained by referring to embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only show typical embodiments of this disclosure and should not be considered as limiting the scope of this disclosure, as other equivalent embodiments are permissible.

[0013] Figure 1 This is a schematic block diagram illustrating a storage system in which a data storage device can be used as a storage device for a host device, according to certain embodiments.

[0014] Figure 2 This is a flowchart illustrating a method for inferring engine operation according to certain implementation schemes.

[0015] Figure 3 This is a flowchart illustrating a method for predicting retransmission timing according to certain implementation schemes.

[0016] Figure 4 This is a block diagram illustrating a system that uses a monitor to predict integrity problems according to certain implementation schemes.

[0017] Figure 5 This is a flowchart illustrating a method for a system strategy based on a predicted problem, according to certain implementation schemes.

[0018] For ease of understanding, the same reference numerals are used where possible to denote the same elements common in the figures. It is contemplated that elements disclosed in one embodiment may be advantageously used in other embodiments without specific description. Detailed Implementation

[0019] In the following text, reference is made to embodiments of this disclosure. However, it should be understood that this disclosure is not limited to the specifically described embodiments. Rather, any combination of the features and elements below, whether or not they relate to different embodiments, is contemplated for implementing and practicing this disclosure. Furthermore, while embodiments of this disclosure may achieve advantages over other possible solutions and / or over the prior art, whether a particular advantage is achieved by a given embodiment does not limit this disclosure. Therefore, the aspects, features, embodiments, and advantages below are merely illustrative and should not be considered elements or limitations of the appended claims unless expressly stated in the claims. Similarly, reference to “this disclosure” should not be construed as a generalization of any inventive subject matter disclosed herein and should not be considered elements or limitations of the appended claims unless expressly stated in the claims.

[0020] Continuous tracking of all channels (both in-band and sideband channels) between the controller and storage device is used to avoid interface errors caused by power degradation. This tracking involves extracting relevant indications and using a predictive model that correlates the tracked indications with the subsequent occurrence of a power degradation event. In response to the predictions, the system can perform different recovery actions (countermeasures). The controller will monitor various indications from the storage element, the controller itself, and the power supply to predict marginal events of signal integrity degradation on the interface. Monitoring and mitigation strategies rely on an open system. The controller does not utilize the real-time continuous return channel from the storage device, which signals pass / fail conditions. Given the nature of the open system and the calibration tolerances for the data collection, processing, and inference systems, the controller must also handle positive and negative identification events.

[0021] Figure 1 This is a schematic block diagram illustrating a storage system 100 having a data storage device 106 that can be used as a storage device for a host device 104, according to certain embodiments. For example, the host device 104 may utilize non-volatile memory (NVM) 110 included in the data storage device 106 to store and retrieve data. The host device 104 includes host dynamic random access memory (DRAM) 138. In some examples, the storage system 100 may include multiple storage devices, such as the data storage device 106, that can operate as a storage array. For example, the storage system 100 may include multiple data storage devices 106 configured as a redundant array of inexpensive / disk-only (RAID) that collectively serve as a large-capacity storage device for the host device 104.

[0022] Host device 104 can store data in one or more storage devices, such as data storage device 106, and / or retrieve data from said one or more storage devices. Figure 1 As shown, host device 104 can communicate with data storage device 106 via interface 114. Host device 104 can include any of a wide range of devices, including: computer servers, network attached storage (NAS) units, desktop computers, laptops, tablet computers, set-top boxes, telephone receivers (such as so-called "smart" phones, so-called "smart" tablets), televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, or other devices capable of sending or receiving data from data storage devices.

[0023] Host DRAM 138 may optionally include a host memory buffer (HMB) 150. HMB 150 is a portion of host DRAM 138 allocated to data storage device 106 for the dedicated use of controller 108 of data storage device 106. For example, controller 108 may store mapped data, buffered commands, logical-to-physical (L2P) tables, metadata, etc., in HMB 150. In other words, HMB 150 may be used by controller 108 to store data that would typically be stored in volatile memory 112, buffer 116, or internal memory of controller 108 such as static random-access memory (SRAM). In an example where data storage device 106 does not include DRAM (i.e., optional DRAM 118), controller 108 may utilize HMB 150 as DRAM for data storage device 106.

[0024] Data storage device 106 includes a controller 108, an NVM 110, a power supply 111, volatile memory 112, an interface 114, a write buffer 116, and optional DRAM 118. In some examples, data storage device 106 may include additional components, not shown for clarity. Figure 1 Additional components are shown. For example, data storage device 106 may include a printed circuit board (PCB) to which components of data storage device 106 are mechanically attached, and the PCB includes conductive traces that enable isoelectric interconnection of components of data storage device 106. In some examples, the physical dimensions and connector configuration of data storage device 106 may conform to one or more standard form factors. Some example standard form factors include, but are not limited to, 3.5-inch data storage devices (e.g., HDDs or SSDs), 2.5-inch data storage devices, 1.8-inch data storage devices, peripheral component interconnect (PCI), extended PCI (PCI-X), and fast PCI (PCIe) (e.g., PCIe x1, x4, x8, x16, PCIe mini-cards, mini PCI, etc.). In some examples, data storage device 106 may be directly coupled (e.g., directly soldered or inserted into a connector) to the motherboard of host device 104.

[0025] Interface 114 may include one or both of a data bus for exchanging data with host device 104 and a control bus for exchanging commands with host device 104. Interface 114 may operate according to any suitable protocol. For example, interface 114 may operate according to one or more of the following protocols: Advanced Technology Attachment (ATA) (e.g., Serial ATA (SATA) and Parallel ATA (PATA)), Fibre Channel Protocol (FCP), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), PCI and PCIe, High Speed ​​Non-Volatile Memory (NVMe), OpenCAPI, GenZ, Cache Coherent Interface Accelerator (CCIX), Open Channel SSD (OCSSD), etc. Interface 114 (e.g., a data bus, a control bus, or both) is electrically connected to controller 108, providing an electrical connection between host device 104 and controller 108, enabling data exchange between host device 104 and controller 108. In some examples, the electrical connection of interface 114 may also allow data storage device 106 to receive power from host device 104. For example, as Figure 1 As shown, power supply 111 can receive power from host device 104 via interface 114.

[0026] NVM 110 may include multiple memory devices or memory cells. NVM 110 may be configured to store and / or retrieve data. For example, a memory cell of NVM 110 may receive data from controller 108 and a message instructing the memory cell to store data. Similarly, a memory cell may receive a message from controller 108 instructing the memory cell to retrieve data. In some examples, each memory cell in the memory cell may be referred to as a die. In some examples, NVM 110 may include multiple dies (i.e., multiple memory cells). In some examples, each memory cell may be configured to store a relatively large amount of data (e.g., 128MB, 256MB, 512MB, 1GB, 2GB, 4GB, 8GB, 16GB, 32GB, 64GB, 128GB, 256GB, 512GB, 1TB, etc.).

[0027] In some examples, each memory cell may include any type of non-volatile memory device, such as flash memory device, phase-change memory (PCM) device, resistive random access memory (ReRAM) device, magnetoresistive random access memory (MRAM) device, ferroelectric random access memory (F-RAM), holographic memory device, and any other type of non-volatile memory device.

[0028] NVM 110 may include multiple flash memory devices or memory cells. The NVM flash memory device may include NAND- or NOR-based flash memory devices and may store data based on the charge contained in the floating gate of the transistors in each flash memory cell. In the NVM flash memory device, the flash memory device may be divided into multiple dies, each of which includes multiple physical blocks or logical blocks, which may be further divided into multiple pages. Each of the multiple blocks within a particular memory device may include multiple NVM cells. Rows of NVM cells may be electrically connected using word lines to define pages within the multiple pages. A corresponding cell in each page of the multiple pages may be electrically connected to a corresponding bit line. Furthermore, the NVM flash memory device may be a 2D or 3D device and may be a single-cell (SLC), multi-cell (MLC), three-cell (TLC), or four-cell (QLC) device. Controller 108 may write data to and read data from the NVM flash memory device at the page level and erase data from the NVM flash memory device at the block level.

[0029] Power supply 111 can provide power to one or more components of data storage device 106. When operating in standard mode, power supply 111 can use power provided by an external device such as host device 104 to power one or more components. For example, power supply 111 can use power received from host device 104 via interface 114 to power one or more components. In some examples, power supply 111 may include one or more power storage components configured to provide power to one or more components when operating in a shutdown mode (such as when power is stopped from external devices). In this way, power supply 111 can be used as an onboard backup power supply. Some examples of one or more power storage components include, but are not limited to, capacitors, supercapacitors, batteries, etc. In some examples, the electrical energy that can be stored by one or more power storage components can be a function of the cost and / or size (e.g., area / volume) of one or more power storage components. In other words, as the electrical energy stored by one or more power storage components increases, the cost and / or size of one or more power storage components also increases.

[0030] Controller 108 may use volatile memory 112 to store information. Volatile memory 112 may include one or more volatile memory devices. In some examples, controller 108 may use volatile memory 112 as a cache. For example, controller 108 may store cached information in volatile memory 112 before it is written to NVM 110. Figure 1As shown, volatile memory 112 can consume power received from power supply 111. Examples of volatile memory 112 include, but are not limited to, random access memory (RAM), dynamic random access memory (DRAM), static RAM (SRAM), and synchronous dynamic RAM (SDRAM (e.g., DDR1, DDR2, DDR3, DDR3L, LPDDR3, DDR4, LPDDR4, etc.)). Similarly, optional DRAM 118 can be used to store mapped data, buffered commands, logical-to-physical (L2P) tables, metadata, cached data, etc. In some examples, data storage device 106 does not include optional DRAM 118, making data storage device 106 DRAM-free. In other examples, data storage device 106 includes optional DRAM 118.

[0031] Controller 108 can manage one or more operations of data storage device 106. For example, controller 108 can manage reading data from and / or writing data to NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 can initiate a data storage command to store data in NVM 110 and monitor the progress of the data storage command. Controller 108 can determine at least one operational characteristic of storage system 100 and store at least one operational characteristic in NVM 110. In some embodiments, when data storage device 106 receives a write command from host device 104, controller 108 temporarily stores the data associated with the write command in internal memory or write buffer 116 before sending the data associated with the write command to NVM 110.

[0032] Controller 108 may include optional second volatile memory 120. Optional second volatile memory 120 may be similar to volatile memory 112. For example, optional second volatile memory 120 may be SRAM. Controller 108 may allocate a portion of the optional second volatile memory to host device 104 as a controller memory buffer (CMB) 122. CMB 122 may be directly accessed by host device 104. For example, host device 104 may utilize CMB 122 to store one or more submission queues that are normally maintained in host device 104, rather than maintaining those one or more submission queues in host device 104. In other words, host device 104 may generate commands and store the generated commands, with or without associated data, in CMB 122, where controller 108 accesses CMB 122 to retrieve the stored generated commands and / or associated data.

[0033] As will be discussed herein, a method for mitigating interface errors caused by power degradation in storage elements (e.g., memory devices) is disclosed based on system prediction. Different options for the prediction-based responses and their specific implementations are also presented. This disclosure is an active method for mitigating interface errors caused by power degradation to avoid signal degradation. This mitigation is based on system prediction. Prediction occurs by continuously tracking all channels (both in-band and sideband channels) between the controller and the storage element, extracting relevant indications, and using a prediction model that correlates the tracked indications with the subsequent occurrence of a power degradation event. In response to the prediction results, the system can perform different recovery operations (i.e., countermeasures) as discussed herein.

[0034] In the method discussed in this paper, the controller monitors various indications from the storage element, the controller itself, and the power controller to predict marginal events of signal integrity degradation at the interface. Monitoring and mitigation strategies rely on an open system (i.e., receiving input but not providing real-time feedback and correction of certain parameters). The controller does not utilize a real-time continuous feedback channel from the storage device, which signals pass / fail conditions. Given the nature of the open system and the calibration tolerances for the data collection, processing, and inference system, the controller must handle positive and negative identification events. Positive and negative identification events may result in the incorrect detection of lower voltages, and countermeasures against these events could be detrimental to the system.

[0035] In other words, the controller checks power stability. The detector can detect very short voltage drops affecting clock-driven components. Typically, reacting to events takes a long time and introduces errors before they can be fixed. Here, taking steps to fix the issue before it causes problems can have a detrimental impact on performance, even if it's to ensure good data integrity.

[0036] Figure 2 This is a flowchart illustrating a method 200 for operating an inference engine according to certain embodiments. Method 200 begins at block 202. At block 202, signals from the channel between the controller and the storage element (storage device) are monitored. The signals can be voltage detectors, clock counters, temperature detectors, silicon process corner detectors, or clock stability. At block 204, the inference engine in the storage controller issues a prediction after time has elapsed or when an event occurs. The inference engine is an intelligent detector and decision-maker. This means that several inputs go into the inference engine and one output goes out of the inference engine. The inputs and output can be artificial intelligence (AI) trained networks, simple controllers, logic controllers, fuzzy logic controllers. At block 206, the controller can perform operations based on the predictions.

[0037] Box 202 refers to the first step for continuous signal monitoring (performed by the controller) and includes the associated tracked indications (features). The quantities to be tracked and measured are the power supply status and the power drop ratio of peak power to average power. Other tracked qualities include read-correctable error counts, in which case the controller is able to detect the presence of errors in the interface engine and count the number of errors.

[0038] The primary interest lies in the ability of the interface between the memory device (e.g., NAND) and the controller to detect the number of errors read from the device. From the NAND's perspective, the controller typically doesn't know how many errors might be introduced when writing to the memory device because NAND is a passive device and lacks reverse-channel error information. NAND doesn't perform any intelligent error counting or error correction on the interface. Therefore, if data is being written and has already experienced some errors at the interface due to electrical issues (magnetic problems or crosstalk problems), the NAND is unaware of these issues. One way to detect if data has been corrupted is by rereading the data. The device can receive a collectible level error count by reading data from network data and control electrical parameter signals physically measured at the input / output (I / O) pins. These are capabilities used to sense the stability of the I / O pins. The controller can also read back some of the signals being transmitted to the NAND.

[0039] Sensing (return signaling) is performed on selected I / O pins, which can be sampled as close as possible to the package bumps. Sensing is a standard method that feeds back signals directly from the I / O pins to allow measurement of what is actually happening in the physical world of the silicon ASIC. The controller tracks rapid changes in the voltage supply to the I / O pins, including negative and / or positive spikes that can affect power integrity. The controller tracks the duty cycle distortion margins of the clock and strobe signals, whether differential or single-ended. The controller can track whether the clock or data that has been transmitted through one or more pins fits a specific envelope defined for signal integrity. The controller is looking at whether transitions from zero to one and from one to zero occur precisely at the timing the controller anticipates.

[0040] It can also track the timing margins of data signals relative to clock / strobe signals and other data signals. Typically, the controller is looking at the clock, and the controller is checking the clock against an internal version of the clock. The clock is a limiting signal that indicates to the other side that the data bus should be sampled at a certain event (either the falling edge or the rising edge of the signal). Here, tracking these two tracking markers (falling edge and rising edge) refers to one internal version of the tracking signal and the other to the actual version of the data or clock signal that is being tracked and measured.

[0041] In the digital domain, the amount of simultaneous switch-on (SSO) outputs and crosstalk of data transmitted on a data channel interacting with the storage device are measured across any number of consecutive bytes. Interaction can involve simultaneous switching and crosstalk at the output, and the amount of SSO can be measured before the data is output on the bus. The controller has a fairly deep pipeline, meaning that data has been waiting in the buffer for some time, and then the data is passed across the pipeline until it is transmitted through the I / O pin. Data that can be detected in the data buffer can indicate whether an abnormal amount of SSO is expected. Generally, the controller should not receive abnormal amounts of SSO because the bus and data are scrambled. There is a certain probability that switching power can fluctuate significantly, and this is a phenomenon that the controller can detect before the data is output on the bus because the data is part of the data structure.

[0042] The controller utilizes multiple data channels from multiple storage devices, employing monitoring techniques for each channel. The processing and inference engine aggregates data from all channels to obtain a complete set of parameters that could potentially affect signal integrity. Typically, a NAND controller uses multiple interfaces of the NAND chip, which resides on the PCB outside the controller. Controllers use 2, 4, 8, or 16 channels. Some controllers even use more than 16 channels, so each channel is a data path, and individual data channels are often more critical.

[0043] There can be some influence between channels. If a voltage drop exists, other channels using the same voltage from the same power rail are likely to experience a voltage drop as well. If an SSO event occurs, the SSO may also radiate enough energy to potentially damage other channels. Problems can also aggregate in the processing and interface engines. In this case, some interface engines can choose to increase integrity. The monitor can be implemented in the controller or in the NAND. In the latter scenario, the controller can use the "Get Characteristics" command or the same command to read the monitor's status.

[0044] NAND flash memory is typically a dumb device. In situations where NAND flash memory can become more intelligent, some of the monitors in a monitor can be implemented within the NAND flash itself, which is the optimal place to detect errors on the write interface because the NAND flash is naturally on the receiving side. If the controller writes to the NAND flash, the NAND flash will be able to check if the data has arrived correctly. Other monitors that might be present on the NAND flash are voltage detectors, temperature detectors, or the marginality of the clock signal.

[0045] Box 204 refers to the second step for generating predictions for anticipated power degradation risks and / or timing violations. The collected features are fed into an inference engine that provides predictions for anticipated power degradation and / or timing violation events. Tuning of this prediction engine can be done offline based on the collection of a large dataset of interface signals combined with power measurements. Identifications of power degradation events will be used as labels for the model. Predictions will be provided by a classification model, which can be a binary model (yes / no answer to an upcoming power degradation event) or a multi-class model, which may also indicate several types of power degradation events or also predict a time interval up to the time the upcoming power degradation event occurs. A regression model can be applied, which will predict a continuous estimate of the expected time until the upcoming power degradation event occurs.

[0046] Another outcome of the model is a risk level, which can be provided by probabilities and / or measures of uncertainty that the model might produce (beyond explicit yes / no predictions). The model can be classified as either a hard or soft decision-making model. If the model is soft, it will provide numerical or probability values ​​that offer more flexibility to the decision engine. The controller can use this risk level as additional information to summarize and determine appropriate actions.

[0047] There is also an option to fine-tune the model by adapting it online in a way that is potentially more specific to the device, host, and use case. Since power degradation patterns and frequencies can be related to user-specific factors such as compute-intensive applications (whose effects include internal CPU heat), external ambient temperature, internal silicon temperature on the controller and NAND, and the concentration of peak usage, it may be advantageous to adapt power degradation alerts to be user / use case specific. If power degradation is associated with a system using peak usage, that system is likely also increasing CPU load or having thermal effects. Based on these factors, the deterioration of electrical signal integrity conditions can be predicted.

[0048] Predictive alerts may be obtained by acquiring dynamic properties that would allow the use of feedback from actual power degradation. In this way, the power degradation prediction model could be fine-tuned during the device's lifespan by selecting one of several predefined sets of prediction model parameters (e.g., based on the density level of the use case) or by applying short-term post-training within the device (either internally or in collaboration with host computing resources). The model could be pre-trained or have an adaptive phase within the device, where some parameters are tracked throughout the device's lifespan.

[0049] Box 206 mentions the third step in taking countermeasures in the event of a predicted power degradation event based on a prediction-based warning. When an expected power degradation event is indicated, the controller can apply one or more measures to prevent / mitigate the consequences of the power degradation event. Countermeasure actions may include an interface calibration operation. NAND flash interfaces always calibrate the timing of all I / O pins to achieve maximum performance with the best possible signal integrity. Interface calibration means there is a training process in progress for the interface. Training the interface to achieve better signal integrity means the device is preparing for such issues. The recovery operation returns to the interface's initial conditions, reads the calibration register from the default state, and then regains the operating state. The recovery operation means the current state the device has reached is suboptimal, and the assumptions driving the current conditions should be reset and re-evaluated.

[0050] Risk reduction can include slower operation or reduced parallelism in relation to the number of NAND interfaces active simultaneously. A typical way to reduce risk is to simply reduce the clock rate. At the moment of reducing the clock rate, most problems are resolved. Because less power is consumed, a larger percentage of the problems are resolved. Power is essentially proportional to the switching rate of I / O pins, so reducing power consumption reduces the amount of noise experienced by the power supply. Power consumption reduction is achieved by slowing down the operation rate and / or reducing parallelism. Reducing parallelism means that the device operates using fewer channels at a time. Instead of using the maximum number of channels in parallel at full capacity, approximately half or a quarter of the channels will be used in parallel. The device does not allow multiple loads to be added to the power supply.

[0051] When the device detects a problem with the previous transmission, it performs a retransmission. The device can recover from a problematic transmission that was detected as faulty, and it can retransmit the correct data associated with that specific transmission. The reduced switching mode speed used on the interface also slows down operation. The device can also operate with larger interleaving intervals when it is operating at a low frequency. The interleaving interval refers to the switching mode speed, which is the frequency of data transmission. One option for reducing the effective data rate is to reduce the clock speed, which reduces the frequency. Another option is to effectively reduce the data rate, i.e., to transmit data at fixed time intervals. These time intervals allow the device's power to recover. This allows the device to operate more closely in sync with the way the power supply operates effectively.

[0052] Typically, there are charging and discharging cycles associated with switching power supplies (also known as DC-DC converters), and by inserting some time between transmissions, the device effectively reduces average power, allowing the power supply to replenish energy to the decoupling capacitors. Furthermore, the device reduces instantaneous power to some extent, assuming that instantaneous power is measured over a period slightly longer than the transmission period. For scaling purposes, a scaled number of packets that can be transmitted to the NAND can take 2 microseconds. If the device is transmitting continuously, there is a large load on the system. However, if the device is transmitting at 50% packet rate, the device transmits data for 2 microseconds. In the next 2 microseconds, the interface is silent. Therefore, the device's average transmission time is 4 microseconds. This 4-microsecond time utilizes 50% of the interface and uses 50% of the power.

[0053] Pausing and resuming introduce time gaps between packets, which can reduce power consumption and slow down operation. The device can extend pauses indefinitely, or it can decide how long to introduce a pause. Assuming a pause-to-resume period will be long enough for power to be restored, the device decides to resume transmission. Pausing and resuming are used to accumulate power, reduce thermal footprint, or other parameters the device is monitoring, allowing it to return to a more efficient operating state.

[0054] This indication can refer to the entire memory die or a portion of it, such as a specific block. It represents a prediction of whether the interface is likely to suffer signal integrity degradation. The inference engine can issue an urgency level for the actions recommended by the inference engine.

[0055] Figure 3 This is a flowchart illustrating a method 300 for predicting retransmission timing according to certain embodiments. In one embodiment, the write process may include using method 300 to predict whether data may need to be retransmitted from the controller to the device, and therefore the data should be placed in readily available RAM in the controller.

[0056] Method 300 begins at block 302. At block 302, signals from the channel between the controller and the storage element are monitored. At block 304, data is written to the storage element. At block 306, the inference engine in the storage controller makes a prediction about whether the data may need to be resubmitted. At block 308, the controller determines whether the prediction for signal integrity has failed. If the controller determines that the prediction for signal integrity has failed, method 300 proceeds to block 310. At block 310, the storage controller stores the data to be written in ready RAM. The device is buffering the data in preparation for rewriting. If the controller determines that the prediction for signal integrity has not failed, method 300 proceeds to block 312. At block 312, the controller relaxes the requirement for data to be written to the storage.

[0057] Figure 4 This is a block diagram illustrating a system 400 that uses monitors to predict integrity problems according to certain implementation schemes. System 400 includes a host, a device controller, and NAND flash memory. The device controller includes a host interface module (HIM), multiple processors, a command scheduler, a predictor engine, an encryption / decryption module, a data path, error correction code (ECC), a redundant array of independent disks (RAID) module, and a flash memory interface module (FIM). Both the FIM and the NAND flash memory include monitors. The monitors may be implemented in the device controller, the NAND flash memory, or both. The predictor engine collects data from the monitors and assesses the risk of power failures. The prediction results are reported to the processors, which determine the countermeasures to be taken. This may affect the behavior of the memory devices.

[0058] Figure 5 This is a flowchart illustrating a method 500 for system countermeasures based on a predicted problem, according to certain implementations. Method 500 begins at block 502. At block 502, the channel is monitored for power problems or timing violations. At block 504, the controller predicts potential power problems or timing violations. At block 506, the controller takes corrective action for the predicted potential problem. At block 508, the controller determines whether the problem has been resolved. If the controller determines the problem has been resolved, method 500 proceeds to block 510. At block 510, the operating conditions ready before the corrective action are returned. If the controller determines the problem has not been resolved, method 500 proceeds to block 512.

[0059] The inference engine improves the signal integrity of the interface between the storage controller and the storage elements, thereby eliminating performance fluctuations and increased power consumption, and also reducing the probability of uncorrectable read errors from the storage medium.

[0060] In one embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller is configured to: predict power problems or timing violations on one or more of a plurality of monitored channels; and initiate corrective actions to mitigate the effects of power problems or timing violations. Monitoring includes monitoring one or more of the following: power supply status; peak power to average power ratio; correctable error count; data electrical parameter signals at input / output (I / O) pins; control electrical parameter signals at I / O pins; and the amount of simultaneous switch output (SSO); controller and NAND temperature; process corner indication; crosstalk of transmitted data; controller silicon temperature; NAND memory temperature; and controller silicon process corner variation. Prediction is performed statically. Statically performed predictions are based on offline tuning. Prediction is performed dynamically, wherein dynamically performed predictions are based on offline tuning and some tuning parameters dynamically updated over the lifetime of the device, such as aging parameters for the NAND, controller silicon, and passive components. Prediction includes utilizing a risk level, wherein the risk level is a probability measure of whether the prediction is correct. Monitoring occurs in a monitoring module within the memory device. Monitoring also occurs in a monitoring module within the controller. Corrective actions are selected from the group consisting of: interface calibration operations; recovery operations; risk reduction operations; retransmission operations; reducing the switching mode speed used on the interface; and increasing the gap between packet transmissions. The controller is configured to write data to the memory device, and the prediction includes predicting whether the data written to the memory device needs to be resubmitted. The controller is configured to write data to volatile memory when it is determined that the data needs to be resubmitted. The controller includes a predictor module configured to receive information about multiple monitored channels.

[0061] In another embodiment, a data storage device includes: a memory device; and a controller coupled to the memory device, wherein the controller includes a central processing unit (CPU), and the controller is configured to: monitor signals from a channel between the controller and the memory device; write data to the memory device; predict that data needs to be resubmitted; and write data to volatile memory. The controller is configured to correlate the monitored signals with the later occurrence of a power degradation event. The prediction includes predicting the probability that a power degradation will occur. The power degradation is predicted based on monitoring the temperature of the memory device. The power degradation is predicted based on monitoring the number of compute-intensive applications executed by the CPU.

[0062] In another embodiment, a data storage device includes: means for storing data; and a controller coupled to the means for storing data, wherein the controller includes a prediction module and a flash interface module (FIM) comprising one or more physical channels, wherein the controller is configured to: predict power problems or timing violations at the interface between the controller and the means for storing data; and take corrective action in response to the prediction. The prediction module is coupled to a monitor that monitors the channel between the FIM and the means for storing data. The monitor is located within the FIM.

[0063] While the foregoing describes an embodiment of this disclosure, other and additional embodiments of this disclosure may be devised without departing from the basic scope of this disclosure, the scope of which is defined by the appended claims.

Claims

1. A data storage device, the data storage device comprising: Memory devices; and A controller, coupled to the memory device, wherein the controller is configured to: Predict power issues or timing violations on one or more of the multiple channels being monitored; as well as Initiate corrective actions to mitigate the impact of the power issue or the timing violation.

2. The data storage device of claim 1, wherein the monitoring includes monitoring one or more of the following: power supply status; peak power to average power ratio; correctable error count; data electrical parameter signals at input / output (I / O) pins; control electrical parameter signals at I / O pins; and the amount of simultaneous switch output (SSO); crosstalk of transmitted data; controller silicon temperature; memory device temperature; and controller silicon process angle variation.

3. The data storage device of claim 1, wherein the prediction is performed statically.

4. The data storage device of claim 3, wherein the prediction performed statically is based on tuning performed offline.

5. The data storage device of claim 1, wherein the prediction is performed dynamically, wherein the dynamically performed prediction is based on offline tuning and some tuning parameters that are dynamically updated over the lifetime of the device, such as aging parameters for NAND, controller silicon and passive components.

6. The data storage device of claim 1, wherein the prediction includes utilizing a risk level, wherein the risk level is a probability measure of whether the prediction is correct.

7. The data storage device according to claim 1, wherein the monitoring occurs in a monitoring module within the storage device.

8. The data storage device according to claim 1, wherein the monitoring occurs in the monitoring module of the controller.

9. The data storage device of claim 1, wherein the corrective action is selected from the group consisting of: interface calibration operation; recovery operation; risk reduction operation; retransmission operation; reducing the switching mode speed used on the interface; and increasing the gap between packet transmissions.

10. The data storage device of claim 1, wherein the controller is configured to write data to the memory device, and wherein the prediction includes predicting whether the data written to the memory device needs to be resubmitted.

11. The data storage device of claim 10, wherein the controller is configured to write the data to volatile memory when it is determined that the data needs to be resubmitted.

12. The data storage device of claim 1, wherein the controller includes a predictor module configured to receive information about the plurality of channels being monitored.

13. A data storage device, the data storage device comprising: Memory devices; and A controller coupled to the memory device, wherein the controller includes a central processing unit (CPU) and is configured to: Monitor signals from the channel between the controller and the memory device; Write data to the memory device; The data is predicted to need to be resubmitted. as well as Write the data to the volatile memory.

14. The data storage device of claim 13, wherein the controller is configured to associate the monitored signal with a later occurrence of a power degradation event.

15. The data storage device of claim 13, wherein the prediction includes predicting the probability that a power drop will occur.

16. The data storage device of claim 15, wherein the power drop is predicted based on monitoring the temperature of the memory device.

17. The data storage device of claim 15, wherein the power degradation is predicted based on monitoring the number of compute-intensive applications executed by the CPU.

18. A data storage device, the data storage device comprising: Devices for storing data; and A controller coupled to the means for storing data, wherein the controller includes a prediction module and a flash interface module (FIM), the flash interface module (FIM) including one or more physical channels, wherein the controller is configured to: Predicting power issues or timing violations at the interface between the controller and the device for storing data; and Corrective measures are taken in response to the prediction.

19. The data storage device of claim 18, wherein the prediction module is coupled to a monitor that monitors the channel between the FIM and the means for storing data.

20. The data storage device of claim 19, wherein the monitor is disposed in the FIM.

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