Semiconductor device parameter testing method and structure

Abstract

The invention discloses a semiconductor device parameter testing method and structure, and belongs to the field of semiconductor testing. The testing method comprises the steps that a testing structure is provided, the testing structure comprises a two-dimensional electron gas channel and a multi-end testing pattern, testing branches are arranged at the positions, close to the two ends, in the two-dimensional electron gas channel, and the two ends of the two-dimensional electron gas channel and the testing branches are connected with the testing ends of the multi-end testing pattern in a one-to-one correspondence mode; respectively connecting the test ends connected with the two ends of the two-dimensional electron gas channel with a bias voltage and the ground, and measuring the channel current and the voltage of the test ends connected with the test branches; and calculating one or more of the source end contact resistance, the drain end contact resistance, the channel square resistance and the current surface density of the two-dimensional electron gas channel according to the size parameters of the two-dimensional electron gas channel and the measured voltage and channel current. The method is more accurate in test result, richer in data dimension and high in test flexibility.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor testing, and more specifically, relates to a method and structure for testing semiconductor device parameters. Background Technology

[0002] In recent years, third-generation wide-bandgap semiconductor materials, represented by gallium nitride (GaN), have been widely studied in the field of high-frequency and high-power devices due to their excellent properties such as high breakdown electric field, wide bandgap, and high chemical stability. Heterostructures such as AlGaN / GaN induce the formation of high-concentration, high-mobility two-dimensional electron gases (2DEG) at the interface due to their polarization effect or modulation doping. High electron mobility transistors (HEMTs) based on these heterostructures can achieve high-conductivity channels without relying on traditional doping, making them one of the most promising structures for next-generation radio frequency power devices.

[0003] In practical device design and physical modeling, the resistive characteristics of two-dimensional electron gas channels (such as sheet resistance, contact resistance, and transmission length) play a crucial role in the overall device performance. Accurately extracting the sheet resistance, monitoring the quality of source and drain contact resistances, and analyzing the potential distribution within the conductive channel will greatly assist in designing high-performance HEMT devices.

[0004] Currently, experimental characterization of the resistance characteristics of the channel and contact regions of HEMT devices mainly relies on the following test schemes. One is a circular capacitor-structured HEMT device channel electric field distribution measurement structure. This involves introducing multiple ring-shaped contact metals between ring-shaped ohmic electrodes and measuring the potential difference between adjacent rings to obtain the electric field distribution. However, this ring-shaped test structure does not conform to the rectangular channel of actual HEMT devices and is difficult to correspond to the potential distribution under operating conditions. Another scheme uses electric field-induced second harmonic generation to map the electric field distribution within the HEMT channel. This type of scheme has complex test system setup, extremely high experimental requirements, and cannot quantitatively extract resistance parameters. A third scheme uses traditional transmission line model (TLM) test structures to extract the channel sheet resistance and total contact resistance. This type of structure cannot separately measure the source / drain contact resistance and cannot provide accurate information on the potential distribution inside the channel, severely limiting the accuracy of contact behavior modeling and physical parameter extraction.

[0005] With the widespread application of semiconductor process simulation and device simulation tools (TCAD) in device development, higher demands are placed on test structures that can efficiently compare with simulation results and provide multi-dimensional experimental input. Therefore, there is an urgent need for a new type of test pattern and test method that can spatially measure the potential distribution in the channel and contact regions, thereby providing accurate data support for resistance modeling, contact mechanism analysis, and simulation verification of HEMT devices. Summary of the Invention

[0006] In view of the shortcomings of the prior art, the purpose of this invention is to provide a method and structure for testing semiconductor device parameters, so as to solve the problems that the prior art cannot separate the measurement of source / drain contact resistance and cannot provide accurate information on the potential distribution inside the channel.

[0007] Based on the above objectives, a first aspect of the present invention provides a method for testing semiconductor device parameters, comprising: providing a test structure, the test structure including a two-dimensional electron gas channel and a multi-terminal test pattern, the two-dimensional electron gas channel being identical to the two-dimensional electron gas channel in the semiconductor device under test, test branches being respectively arranged at positions adjacent to both ends of the two-dimensional electron gas channel, and the two ends of the two-dimensional electron gas channel and each test branch being respectively connected to each test terminal of the multi-terminal test pattern; connecting the test terminals connected to the two ends of the two-dimensional electron gas channel to a bias voltage and ground respectively, and measuring the channel current and the voltage of the test terminals connected to each test branch; and calculating one or more of the source-end contact resistance, drain-end contact resistance, channel sheet resistance, and current surface density of the two-dimensional electron gas channel based on the dimensional parameters of the two-dimensional electron gas channel and the measured voltage and channel current.

[0008] Optionally, the current surface density includes source current surface density and drain current surface density, and its calculation method includes: measuring and calculating a first voltage drop across the source contact resistance and a second voltage drop across the drain contact resistance under different bias voltages; using the ratio of the forward differential of the first voltage drop to the forward differential of the source current surface density as the source contact resistivity, and calculating the source current surface density according to the functional relationship between the source contact resistivity, channel sheet resistance, and source contact resistance; using the ratio of the forward differential of the second voltage drop to the forward differential of the drain current surface density as the drain contact resistivity, and calculating the drain current surface density according to the functional relationship between the drain contact resistivity, channel sheet resistance, and drain contact resistance.

[0009] Optionally, the source current surface density and the drain current surface density are respectively:

[0010]

[0011] Among them, J Sj J Sj-1 J represents the source current density under bias voltage j and bias voltage j-1, respectively. Dj J Dj-1 V represents the drain current density under bias voltage j and bias voltage j-1, respectively. C,Sj V C,Sj-1 These are the first voltage drops under bias voltage j and bias voltage j-1, respectively, V C,Dj V C,Dj-1 These are the second voltage drops under bias voltage j and bias voltage j-1, respectively. Bias voltage j is higher than bias voltage j-1. Rsh W represents the sheet resistance of the channel, and W represents the width of the two-dimensional electron gas channel.

[0012] Optionally, M ohmic contact electrodes are discretely distributed on the two-dimensional electron gas channel, dividing the two-dimensional electron gas channel into M+1 segments, where M≥1; test branches are respectively set at the positions near both ends of each segment of the two-dimensional electron gas channel, and the two ends of the two-dimensional electron gas channel, each test branch, and each ohmic contact electrode are respectively connected to each test end of the multi-end test pattern; the test method further includes: measuring the sheet resistance below each ohmic contact electrode using the test structure.

[0013] Optionally, for any of the ohmic contact electrodes, the sheet resistance measurement process below it includes: measuring the channel sheet resistance R of the first two-dimensional electron gas channel. sh,TOP The channel sheet resistance R of the second two-dimensional electron gas channel sh,SUB The first and second two-dimensional electron gas channels are two two-dimensional electron gas channels adjacent to the ohmic contact electrode. A bias voltage is applied to the first two-dimensional electron gas channel, the ohmic contact electrode, and the second two-dimensional electron gas channel, and the channel current I' and the voltage V' of the test branch adjacent to the ohmic contact electrode on the first two-dimensional electron gas channel are measured. BL The voltage V' of the test branch adjacent to the ohmic contact electrode on the second two-dimensional electron gas channel. DR According to R sh,TOP R sh,SUB 、I'、V' BL and V' DR Calculate the sheet resistance below the ohmic contact electrode.

[0014] Optionally, the sheet resistance below the ohmic contact electrode is:

[0015]

[0016] Among them, R sk L is the sheet resistance below the ohmic contact electrode; W is the width of the two-dimensional electron gas channel; L Metal L is the length of the ohmic contact electrode. BL L is the distance between the test branch adjacent to the ohmic contact electrode on the first two-dimensional electron gas channel and the ohmic contact electrode; ch,SUB L is the length of the second two-dimensional electron gas channel. DR For L ch,SUB With L' DR The difference between them, L' DR The distance between the test branch on the second two-dimensional electron gas channel and the ohmic contact electrode is the distance from the ohmic contact electrode.

[0017] Optionally, one end of the two-dimensional electron gas channel is connected to the test terminal via an ohmic alloy. The test method further includes: measuring and calculating the source-end contact resistance, drain-end contact resistance, and channel sheet resistance of the two-dimensional electron gas channel under different length ohmic alloy structures; and calculating the transmission distance of the two-dimensional electron gas channel based on the fitting relationship between the source-end contact resistance, drain-end contact resistance, channel sheet resistance, ohmic alloy length, and transmission distance in the two-dimensional electron gas channel.

[0018] Optionally, the fitting relationship includes:

[0019]

[0020] Among them, R C,S R is the source contact resistance. C,D RS is the drain contact resistance. K为 The sheet resistance of the channel below the ohmic alloy, W is the width of the two-dimensional electron gas channel, L T x represents the transmission distance, and x represents the length of the ohmic alloy.

[0021] A second aspect of the present invention provides a semiconductor device parameter testing structure, the testing structure including a two-dimensional electron gas channel and a multi-terminal test pattern, the two-dimensional electron gas channel being the same as the two-dimensional electron gas channel in the semiconductor device under test, test branches being respectively arranged at positions near both ends of the two-dimensional electron gas channel, and the two ends of the two-dimensional electron gas channel and each test branch being respectively connected to each test end of the multi-terminal test pattern.

[0022] Optionally, one end of the two-dimensional electron channel is connected to the test terminal via an ohmic alloy; or, M ohmic contact electrodes are discretely distributed on the two-dimensional electron channel, dividing the two-dimensional electron channel into M+1 segments, where M≥1; test branches are respectively set at positions near both ends of each segment of the two-dimensional electron channel, and the two ends of the two-dimensional electron channel, each test branch, and each ohmic contact electrode are respectively connected to each test terminal of the multi-terminal test pattern.

[0023] Compared with existing technologies, the advantages of this invention include: providing a method and structure for testing semiconductor device parameters; the provided test structure includes a two-dimensional electron gas channel and a multi-terminal test pattern; test branches are respectively arranged at positions near both ends of the two-dimensional electron gas channel; the two ends of the two-dimensional electron gas channel and each test branch are respectively connected to each test end of the multi-terminal test pattern; the multi-terminal test pattern is based on a rectangular channel structure design, which more directly reflects the potential distribution of the channel region in the actual semiconductor device and is closer to the electric field behavior of the device in the working state; using the channel branches as potential extraction probes avoids local damage or changes in the channel state caused by etching, metal deposition and high-temperature annealing of the channel region, thus improving measurement accuracy; it can realize the separation and extraction of the source and drain contact resistance, obtain the potential drop distribution in different regions, help to calculate the channel sheet resistance more accurately, and reveal potential physical mechanisms such as non-uniform current injection; the test results of this invention are more accurate, the data dimensions are richer, and the test flexibility is stronger. Attached Figure Description

[0024] Figure 1 A flowchart of a semiconductor device parameter testing method provided in an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of a test structure provided in an embodiment of the present invention.

[0026] Figure 3 for Figure 2 The fabrication process flow diagram of the test structure is shown.

[0027] Figure 4 In order to be in Figure 2 The diagram shows the voltage and channel current measured when a bias voltage is applied to the test structure.

[0028] Figure 5 According to Figure 4 The diagram shows the source / drain contact resistance and channel sheet resistance obtained from the test results.

[0029] Figure 6 To utilize Figure 2 The graph shows the relationship between the contact resistance voltage drop and the current surface density measured by the test structure shown.

[0030] Figure 7 A schematic diagram of the test structure provided in another embodiment of the present invention.

[0031] Figure 8 This is a schematic diagram of a test structure provided in another embodiment of the present invention.

[0032] Figure 9 for Figure 8 The fabrication process flow diagram of the test structure is shown.

[0033] Figure 10 To utilize Figure 8 The diagram shows the resistance measured by the test structure as a function of the effective length of the ohmic contact and its fitting curve. Detailed Implementation

[0034] In view of the shortcomings of the prior art, the inventors of this invention, through long-term research and extensive practice, have proposed the technical solution of this invention. The following will further explain and illustrate this technical solution, its implementation process, and its principles.

[0035] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and therefore the scope of protection of the invention is not limited to the specific embodiments disclosed below.

[0036] Furthermore, in the description of this invention, it should be understood that the terms "upper," "lower," "inner," "outer," "horizontal," "vertical," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0037] In the description of this specification, the references to terms such as "an embodiment," "a particular embodiment," or "the embodiment" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0038] This invention provides a method for testing semiconductor device parameters. (See attached document.) Figure 1 The semiconductor device parameter testing method includes steps S100-S300.

[0039] Step S100: Provide a test structure, which includes a two-dimensional electron gas channel and a multi-terminal test pattern. The two-dimensional electron gas channel is the same as the two-dimensional electron gas channel in the semiconductor device under test. Test branches are respectively set at the positions near the two ends of the two-dimensional electron gas channel. The two ends of the two-dimensional electron gas channel and each test branch are respectively connected to each test end of the multi-terminal test pattern.

[0040] See Figure 2The diagram illustrates a test structure with four-terminal test patterns. The test structure includes a two-dimensional electron gas channel (blue area in the diagram, representing the active region) and a multi-terminal test pattern (yellow area in the diagram, for example, the ohmic contact region formed after annealing a Ti / Al / Ni / Au metal stack). The metal stack composition, thickness, and annealing parameters of each test terminal are completely identical. However, for ease of differentiation, the four test terminals are numbered as test terminal A, test terminal B, test terminal C, and test terminal D. Compared to traditional TLMs, this test structure does not require changing the channel length. Instead, test branches (i.e., ground and bias terminals) are led out from the two ends of the two-dimensional electron gas channel. Figure 2 The test branch has two transverse two-dimensional electron gas channels connected to the test terminals B and C. This test branch can directly measure the channel electrostatic potential at the center line position of the test branch without affecting the intrinsic state of the conductive channel. The magnitude of the ohmic contact resistance can be deduced from the electric field distribution.

[0041] Figure 2 The dimensions of the two-dimensional electron gas channel are also shown. The width of the two-dimensional electron gas channel is W, and the distance between the middle of the test branch connected to test terminal B and test terminal D is represented by parameter L. B The distance between the middle of the test branch connected to test terminal C and test terminal D is represented by the parameter L. C The distance between test terminal A and test terminal D is represented by parameter L. ch The above dimensional parameters can be calibrated using a scanning electron microscope or a confocal microscope.

[0042] Figure 2 The fabrication process of the test structure shown is as follows: Figure 3 As shown, the specific steps are as follows: (1) Apply photoresist, perform photolithography and development on the epitaxial wafer so that the active area is protected by photoresist and the passive area is exposed; (2) Perform dry etching in a plasma etching machine with an etching depth of, for example, 200 nm, to pattern the active area; (3) Apply photoresist, perform photolithography and development again so that there is no photoresist on the ohmic contact area and the other areas are covered by photoresist; (4) Evaporate Ti / Al / Ni / Au (thickness of, for example, 22 nm / 140 nm / 55 nm / 45 nm) metal stack by electron beam evaporation; (5) After evaporation, strip the metal and perform high-temperature rapid annealing, for example, in a nitrogen atmosphere, with an annealing temperature of, for example, 870 °C and an annealing time of, for example, 30 s, to make a test structure.

[0043] Step S200: Connect the test terminals at both ends of the two-dimensional electronic gas channel to the bias voltage and ground respectively, and measure the channel current and the voltage of the test terminals connected to each test branch.

[0044] Apply a bias voltage to test terminal A, ground test terminal D, and measure the channel current I and the voltage V at test terminal B. Band the voltage V at the test terminal C C .

[0045] Step S300: Based on the dimensional parameters of the two-dimensional electron gas channel and the measured voltage and channel current, calculate one or more of the source-end contact resistance, drain-end contact resistance, channel sheet resistance, and current surface density of the two-dimensional electron gas channel.

[0046] Preferably, in this embodiment, the average value of each resistance parameter is calculated as the final resistance parameter. In step S200, it is necessary to obtain the channel current I and voltage V. B and voltage V C Multiple sampled values. For example, a bias voltage of +V is applied to test terminal A for 5 seconds. bias The test terminal D is grounded, and the channel current I and voltage V are continuously tested using the I / Vt sampling mode. B and voltage V C With n sampling points, the data V is obtained. B1 ~V Bn V C1 ~V Cn 、I1~I n The sampling results are as follows Figure 4 As shown. The calculated source-end contact resistance R of the two-dimensional electron gas channel. C,S Drain contact resistance R C,D Channel resistance R sh They are respectively:

[0047]

[0048] Among them, R C,Si R C,Di R shi E midi These represent the source-end contact resistance, drain-end contact resistance, channel sheet resistance, and average electric field strength in the middle of the channel, respectively, for the i-th sampling point.

[0049] Furthermore, by changing the bias voltage and repeating the above operation, the source-to-drain contact resistance, drain-to-source contact resistance, and channel sheet resistance under each bias voltage can be obtained. Plotting the resistance versus voltage graph allows for a clear observation of the changing resistance characteristics under different bias voltages. Figure 5 As shown.

[0050] In a preferred embodiment, the current surface density includes the source current surface density and the drain current surface density, and its calculation method includes: measuring and calculating a first voltage drop across the source contact resistance and a second voltage drop across the drain contact resistance under different bias voltages; using the ratio of the forward differential of the first voltage drop to the forward differential of the source current surface density as the source contact resistivity, and calculating the source current surface density according to the functional relationship between the source contact resistivity, channel sheet resistance, and source contact resistance; using the ratio of the forward differential of the second voltage drop to the forward differential of the drain current surface density as the drain contact resistivity, and calculating the drain current surface density according to the functional relationship between the drain contact resistivity, channel sheet resistance, and drain contact resistance.

[0051] Different bias voltages V biasj The first voltage drop V across the source contact resistance (distinguished by the subscript j) C,Sj The second voltage drop V across the drain contact resistance C,Dj They are respectively:

[0052] V C,Sj =V Cj -E midj ·L C

[0053] V C,Dj =V biasj -V Bj -E midj ·(L ch -L B )

[0054] The functional relationship between source / drain contact resistivity, channel sheet resistance, and source contact resistance is as follows: Approximate the contact resistivity ρ using forward differentiation C The following formula can be obtained:

[0055]

[0056] The surface current density at the source and the surface current density at the drain are respectively:

[0057]

[0058] Among them, J Sj J Sj-1 J represents the source current density under bias voltage j and bias voltage j-1, respectively. Dj J Dj-1 V represents the drain current density under bias voltage j and bias voltage j-1, respectively. C,Sj V C,Sj-1 These are the first voltage drops under bias voltage j and bias voltage j-1, respectively, V C,Dj V C,Dj-1These are the second voltage drops under bias voltage j and bias voltage j-1, respectively. Bias voltage j is higher than bias voltage j-1. R sh Let W be the channel sheet resistance, and W be the width of the two-dimensional electron gas channel.

[0059] The above processing yields the relationship between the source-side contact resistance voltage drop, the drain-side contact resistance voltage drop, and the current density. Furthermore, considering that electrons at the drain end flow from the semiconductor to the metal (positive direction), while electrons at the source end flow from the metal to the semiconductor (negative direction), the source-side current and voltage values ​​are assigned negative values. These are then plotted together as a current-voltage relationship graph, from which the relationship between the source / drain contact resistance voltage drop and the current surface density can be plotted, as shown below. Figure 6 As shown, this enables variable-temperature fitting of the ohmic contact formation mechanism, which is more conducive to establishing a nonlinear model of the voltage drop-current relationship, providing richer physical information support for the study of ohmic contact mechanisms and the evaluation of material behavior. In addition to variable-temperature fitting, it provides another dimension of research methods for verifying or exploring physical models.

[0060] In a preferred embodiment, M ohmic contact electrodes are discretely distributed on the two-dimensional electron gas channel, dividing the two-dimensional electron gas channel into M+1 segments, where M≥1; test branches are respectively arranged at the positions near both ends of each segment of the two-dimensional electron gas channel, and each end of the two-dimensional electron gas channel, each test branch, and each ohmic contact electrode are respectively connected to each test end of the multi-end test pattern; the test method further includes: measuring the sheet resistance below each ohmic contact electrode using the test structure.

[0061] Taking M=1 as an example, the test structure provided in step S100 is as follows: Figure 7 As shown, the fabrication process of this test structure is similar to... Figure 2 The fabrication process of the test structures shown is the same, only the pattern of the photomask is different. The test patterns with different planar structures but similar cross-sectional structures are achieved through the pattern design of the photomask.

[0062] For a two-dimensional electron gas channel with ohmic contact electrodes distributed thereon, its channel sheet resistance R sh It should actually be the sheet resistance R below the ohmic contact electrode. sk However, in the TLM test, R could not be extracted. sk Therefore, do R sk ≈R sh The approximation is correct. However, after high-temperature annealing, the channel state beneath the contact area changes, resulting in a significant difference from the active region covered by the ohmic contact electrode. This approximation introduces a large error, and it is necessary to extract the sheet resistance of the metal channel to eliminate this error.

[0063] For any ohmic contact electrode, the sheet resistance measurement process below it includes the following steps S101-S301.

[0064] Step S101: Measure the channel sheet resistance R of the first two-dimensional electron gas channel. sh,TOP The channel sheet resistance R of the second two-dimensional electron gas channel sh,SUB The first and second two-dimensional electron gas channels are two two-dimensional electron gas channels adjacent to the ohmic contact electrode.

[0065] R sh,TOP and R sh,SUB The measurement process and principle are the same as those in steps S200-S300 above, specifically the channel sheet resistance R. sh The measurement process and principle are the same, and will not be repeated here.

[0066] by Figure 7 Taking the test structure shown as an example, a bias voltage is applied to test terminal A, test terminal C is grounded, and the voltage value V at test terminal BR is measured simultaneously. BR The voltage value V at the test terminal BL BL and channel current I TOP R is calculated using the following formula. sh,TOP :

[0067]

[0068] A bias voltage is applied to test terminal C, and test terminal E is grounded. Simultaneously, the voltage V at test terminal DR is measured. DR The voltage value V at the test terminal DL DL and channel current I SUB R is calculated using the following formula. sh,SUB :

[0069]

[0070] Step S201: Apply a bias voltage to the first two-dimensional electron gas channel, the ohmic contact electrode, and the second two-dimensional electron gas channel, and measure the channel current I' and the voltage V' of the test branch adjacent to the ohmic contact electrode on the first two-dimensional electron gas channel. BL The voltage V' of the test branch adjacent to the ohmic contact electrode on the second two-dimensional electron gas channel. DR .

[0071] by Figure 7 Taking the test structure shown as an example, a bias voltage is applied to test terminal A, test terminal E is grounded, and the voltage value V' at test terminal BL is measured simultaneously. bL The voltage value V' at the test terminal DR DR And the channel current I'.

[0072] Step S301, according to R sh,TOP R sh,SUB 、I'、V'BL and V' DR Calculate the sheet resistance below the ohmic contact electrode.

[0073] In a preferred embodiment, the sheet resistance below the ohmic contact electrode is:

[0074]

[0075] Among them, R sk L is the sheet resistance below the ohmic contact electrode; W is the width of the two-dimensional electron gas channel; L Metal L is the length of the ohmic contact electrode. BL L represents the distance between the test branch adjacent to the ohmic contact electrode on the first two-dimensional electron gas channel and the ohmic contact electrode. ch,SUB L is the length of the second two-dimensional electron gas channel. DR For L ch,SUB With L' DR The difference between them, L' DR The distance between the test branch and the ohmic contact electrode on the second two-dimensional electron gas channel is the distance of the test branch adjacent to the ohmic contact electrode.

[0076] This embodiment also utilizes the channel branch as a probe to directly measure the electrostatic potential at a point in the channel, overcoming the problem of traditional methods being "unmeasurable" of the channel characteristics below the contact area. When extracting the sheet resistance, it eliminates the need to model the distributed resistance of the contact area and approximate the electrostatic potential. It enables quantitative characterization of the sheet resistance of the contact area after annealing at the experimental level, which is significant for demonstrating the impact of annealing on the intrinsic properties of the channel, optimizing contact electrode design, and evaluating local transport paths.

[0077] In a preferred embodiment, one end of the two-dimensional electron gas channel is connected to the test terminal via an ohmic alloy, and the test structure is as follows: Figure 8 As shown. See also Figure 8 One end of the two-dimensional electron gas channel is connected to test terminal A via an ohmic alloy, the length of which is L. Ohmic The width is W.

[0078] Figure 8 The fabrication process of the test structure shown is as follows: Figure 9As shown, the specific process is as follows: (1) Coating, photolithography, and development are performed on the epitaxial wafer to protect the active area with photoresist and expose the passive area; (2) Dry etching is performed in a plasma etching machine with an etching depth of, for example, 200 nm, to pattern the active area; (3) Coating, photolithography, and development are performed a second time to remove photoresist from the ohmic contact area and cover other areas with photoresist; (4) Ti / Al / Ni / Au is deposited by electron beam evaporation (thickness for example, 22 nm / 140 nm). (5) After evaporation, the metal stack is formed by high-temperature rapid annealing in a nitrogen atmosphere to form an ohmic contact. The annealing temperature is, for example, 870°C and the annealing time is, for example, 30s. (6) The third coating, photolithography and development are performed so that there is no photoresist on the electrode area and the other areas are covered with photoresist. (7) Ni / Au (thickness, for example, 55nm / 100nm) metal stack is deposited by electron beam evaporation. (8) After evaporation, the metal stack is removed to form a test structure.

[0079] In this embodiment, multiple Figure 8 The test structures shown have different ohmic alloy lengths x (i.e., L) for different test structures. Ohmic The size may vary, for example, from 1 μm to 30 μm. The test method also includes the following steps S102-S202.

[0080] Step S102: Measure and calculate the source-end contact resistance, drain-end contact resistance, and channel sheet resistance of two-dimensional electron gas channels under ohmic alloy structures of different lengths.

[0081] A bias voltage is applied to test terminal A, and test terminal D is grounded. The voltage values ​​at test terminals B and C, as well as the channel current, are measured. Based on the measured data, the contact resistance of the ohmic contact at terminal A is calculated. At this time, terminal A is considered the drain terminal. The bias directions are reversed, test terminal A is grounded, and a bias voltage is applied to test terminal D. The voltage values ​​at test terminals B and C, as well as the channel current, are measured. Based on the measured data, the contact resistance of the ohmic contact at terminal A is calculated. At this time, terminal A is considered the source terminal. The measurement process and principle of the source terminal contact resistance, drain terminal contact resistance, and channel sheet resistance in step S102 are the same as those in steps S200-S300 above, and will not be repeated here.

[0082] By repeating step S102 on a series of test patterns, the source-end contact resistance, drain-end contact resistance, and channel sheet resistance of two-dimensional electron gas channels under ohmic alloy structures of different lengths can be obtained.

[0083] Step S202: Calculate the transmission distance of the two-dimensional electron gas channel based on the fitting relationship between the source end contact resistance, drain end contact resistance, channel sheet resistance, ohmic alloy length, and transmission distance in the two-dimensional electron gas channel.

[0084] Plot R C,S R C,D With L Ohmic Relationship diagram, such as Figure 10 As shown, the transmission distance value is obtained by fitting the data to the theoretical formula. The fitting relationship is as follows:

[0085]

[0086]

[0087] Among them, R C,S R is the source contact resistance. C,D R is the drain contact resistance. SK The sheet resistance of the channel beneath the ohmic alloy is given by W, where W is the width of the two-dimensional electron gas channel, and L is the width of the channel. T x represents the transmission distance, and x represents the length of the ohmic alloy. Figure 10 In the fitted relationship shown, the ordinate is R when x is less than the source / drain boundary point. C,S When x is greater than the source-drain boundary point, the ordinate is R. C,D Specifically, R C,S R is the contact resistance when terminal A is used as the source terminal. C,D This is the contact resistance when terminal A is used as the drain terminal.

[0088] Figure 8 The test structure shown fully leverages the advantages of branch measurement structures in contact resistance separation, allowing for the extraction of the transmission lengths of the source and drain separately. This overcomes the limitation of TLMs, which can only obtain average values, and has significant application value for establishing more physically realistic current injection models, calibrating contact diffusion depth, and improving device reliability analysis.

[0089] The multi-terminal test pattern provided in this invention is simple in structure, easy to design, convenient in process steps, and highly compatible with processes. This multi-terminal test pattern can clearly distinguish between source-end contact resistance and drain-end contact resistance, providing accurate and stable technical support for physical modeling of contact behavior in devices, TCAD simulation input, and process monitoring. It provides more detailed data support for further research on the formation mechanism of ohmic contacts in HEMTs, and offers new ideas for structural improvement and process optimization of high-performance HEMTs, possessing broad scientific research and engineering application value.

[0090] Compared with the potential measurement structure of ring-shaped HEMT devices, the present invention has the following advantages: (1) Closer to real working conditions: The test pattern of the present invention is based on a rectangular channel structure design, which more directly reflects the potential distribution in the channel region of the actual HEMT device, and is closer to the electric field behavior of the device under working conditions, and is suitable for the verification of conventional planar device models. (2) Maintaining the intrinsic nature of the channel: Using channel branches as potential extraction probes avoids local damage or changes in channel state caused by etching and metal deposition and high-temperature annealing of the channel region, thus improving measurement accuracy. (3) High testing flexibility: Multiple branch probes can be set at different positions as needed to extract the potential at multiple points in the channel region, which has good scalability and flexibility.

[0091] Compared with EFISHG for extracting channel potential distribution, this invention has the following advantages: (1) Simple test system: This test structure is based on electrical measurement methods, and the test equipment is simple to configure and easy to operate, eliminating the need for complex laser and optical system setup, and significantly reducing test costs. (2) Good process compatibility: The pattern structure is highly compatible with existing HEMT device processes and can be embedded in standard fabrication processes as a process monitoring structure, facilitating large-scale process monitoring and device evaluation.

[0092] Compared with the TLM structure, this invention has the following advantages: (1) More accurate parameter extraction: It can separate and extract the source and drain contact resistances, obtain the potential drop distribution in different regions, which helps to calculate the channel sheet resistance more accurately and reveal potential physical mechanisms such as non-uniform current injection. (2) Rich data dimensions: It provides potential data at multiple spatial points, supports high-dimensional modeling and analysis, provides experimental basis for establishing more rigorous physical models and TCAD simulation verification, and plays an important role in promoting device mechanism research and the development of simulation tools.

[0093] In summary, the semiconductor device parameter testing method provided by the embodiments of the present invention, by designing a new test structure, corrects existing device models or empirical approximation formulas, further explores potential mechanisms, and overcomes the limitations of existing testing methods in separating and extracting R. C,S R C,D By addressing the constraints of the TCAD model, revealing its asymmetric phenomena, and obtaining a more accurate TCAD model, we can gain significant guidance for semiconductor simulation and device development.

[0094] A second aspect of the present invention provides a semiconductor device parameter testing structure, the testing structure including a two-dimensional electron gas channel and a multi-terminal test pattern, the two-dimensional electron gas channel being the same as the two-dimensional electron gas channel in the semiconductor device under test, test branches being respectively arranged at positions near both ends of the two-dimensional electron gas channel, and both ends of the two-dimensional electron gas channel and each test branch being respectively connected to each test end of the multi-terminal test pattern.

[0095] In a preferred embodiment, one end of the two-dimensional electron gas channel is connected to the test terminal via an ohmic alloy.

[0096] In a preferred embodiment, M ohmic contact electrodes are discretely distributed on the two-dimensional electron gas channel, dividing the two-dimensional electron gas channel into M+1 segments, where M≥1; test branches are respectively set at the positions near the two ends of each segment of the two-dimensional electron gas channel, and the two ends of the two-dimensional electron gas channel, each test branch, and each ohmic contact electrode are respectively connected to each test end of the multi-end test pattern.

[0097] The process of using the semiconductor device parameter testing structure in this embodiment is the same as the testing process in the semiconductor device parameter testing method described above, and will not be repeated here.

[0098] It should be understood that the above embodiments are merely illustrative of the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All equivalent changes or modifications made in accordance with the spirit and essence of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for testing semiconductor device parameters, characterized in that, include: A test structure is provided, which includes a two-dimensional electron gas channel and a multi-terminal test pattern. The two-dimensional electron gas channel is the same as the two-dimensional electron gas channel in the semiconductor device under test. Test branches are respectively arranged at the positions near the two ends of the two-dimensional electron gas channel. The two ends of the two-dimensional electron gas channel and each test branch are respectively connected to each test end of the multi-terminal test pattern. The test terminals connected to both ends of the two-dimensional electron gas channel are respectively connected to the bias voltage and ground, and the channel current and the voltage of the test terminals connected to each test branch are measured. Based on the dimensional parameters of the two-dimensional electron gas channel and the measured voltage and channel current, calculate one or more of the source-end contact resistance, drain-end contact resistance, channel sheet resistance, and current surface density of the two-dimensional electron gas channel.

2. The semiconductor device parameter testing method according to claim 1, characterized in that, The current surface density includes the source current surface density and the drain current surface density, and its calculation method includes: Measure and calculate the first voltage drop across the source contact resistance and the second voltage drop across the drain contact resistance under different bias voltages; The ratio of the forward differential of the first voltage drop to the forward differential of the source current surface density is taken as the source contact resistivity. The source current surface density is calculated based on the functional relationship between the source contact resistivity, the channel sheet resistance, and the source contact resistance. The ratio of the forward differential of the second voltage drop to the forward differential of the drain current surface density is taken as the drain contact resistivity. The drain current surface density is calculated based on the functional relationship between the drain contact resistivity, the channel sheet resistance, and the drain contact resistance.

3. The semiconductor device parameter testing method according to claim 2, characterized in that, The source current surface density and the drain current surface density are respectively: Among them, J Sj J Sj-1 J represents the source current density under bias voltage j and bias voltage j-1, respectively. Dj J Dj-1 V represents the drain current density under bias voltage j and bias voltage j-1, respectively. C,Sj V C,Sj-1 These are the first voltage drops under bias voltage j and bias voltage j-1, respectively, V C,Dj V C,Dj-1 These are the second voltage drops under bias voltage j and bias voltage j-1, respectively. Bias voltage j is higher than bias voltage j-1. R sh W represents the sheet resistance of the channel, and W represents the width of the two-dimensional electron gas channel.

4. The semiconductor device parameter testing method according to any one of claims 1-3, characterized in that, M ohmic contact electrodes are discretely distributed on the two-dimensional electron gas channel, dividing the two-dimensional electron gas channel into M+1 segments, where M≥1. Each two-dimensional electron gas channel has a test branch located near both ends. The two ends of the two-dimensional electron gas channel, each test branch, and each ohmic contact electrode are connected to each test end of the multi-end test pattern. The test method further includes: measuring the sheet resistance below each of the ohmic contact electrodes using the test structure.

5. The semiconductor device parameter testing method according to claim 4, characterized in that, For any of the ohmic contact electrodes, the sheet resistance measurement process below it includes: Measure the channel sheet resistance R of the first two-dimensional electron gas channel. sh,TOP The channel sheet resistance R of the second two-dimensional electron gas channel sh,SUB The first two-dimensional electron gas channel and the second two-dimensional electron gas channel are two two-dimensional electron gas channels adjacent to the ohmic contact electrode. A bias voltage is applied to the first two-dimensional electron gas channel, the ohmic contact electrode, and the second two-dimensional electron gas channel. The channel current I' and the voltage V' of the test branch adjacent to the ohmic contact electrode in the first two-dimensional electron gas channel are measured. BL The voltage V' of the test branch adjacent to the ohmic contact electrode on the second two-dimensional electron gas channel. DR ; According to R sh,TOP R sh,SUB 、I'、V' BL and V' DR Calculate the sheet resistance below the ohmic contact electrode.

6. The semiconductor device parameter testing method according to claim 5, characterized in that, The sheet resistance below the ohmic contact electrode is: Among them, R sk L is the sheet resistance below the ohmic contact electrode; W is the width of the two-dimensional electron gas channel; L Metal L is the length of the ohmic contact electrode. BL L is the distance between the test branch adjacent to the ohmic contact electrode on the first two-dimensional electron gas channel and the ohmic contact electrode; ch,SUB L is the length of the second two-dimensional electron gas channel. DR For L ch,SUB With L' DR The difference between them, L' DR The distance between the test branch on the second two-dimensional electron gas channel and the ohmic contact electrode is the distance from the ohmic contact electrode.

7. The semiconductor device parameter testing method according to any one of claims 1-3, characterized in that, One end of the two-dimensional electron gas channel is connected to the test terminal via an ohmic alloy, and the test method further includes: The source-end contact resistance, drain-end contact resistance, and channel sheet resistance of the two-dimensional electron gas channel under ohmic alloy structures of different lengths were measured and calculated. The transmission distance of the two-dimensional electron gas channel is calculated based on the fitting relationship between the source end contact resistance, drain end contact resistance, channel sheet resistance, ohmic alloy length and transmission distance in the two-dimensional electron gas channel.

8. The semiconductor device parameter testing method according to claim 7, characterized in that, The fitting relationship includes: Among them, R C,S R is the source contact resistance. C,D R is the drain contact resistance. SK The sheet resistance of the channel beneath the ohmic alloy is given by W, where W is the width of the two-dimensional electron gas channel, and L is the width of the channel. T x represents the transmission distance, and x represents the length of the ohmic alloy.

9. A semiconductor device parameter testing structure, characterized in that, The test structure includes a two-dimensional electron gas channel and a multi-terminal test pattern. The two-dimensional electron gas channel is the same as the two-dimensional electron gas channel in the semiconductor device under test. Test branches are respectively arranged at the positions near the two ends of the two-dimensional electron gas channel. The two ends of the two-dimensional electron gas channel and each test branch are respectively connected to each test end of the multi-terminal test pattern.

10. The semiconductor device parameter testing structure according to claim 9, characterized in that, One end of the two-dimensional electron gas channel is connected to the test terminal via an ohmic alloy. Alternatively, M ohmic contact electrodes are discretely distributed on the two-dimensional electron gas channel, dividing the two-dimensional electron gas channel into M+1 segments, where M≥1; test branches are respectively set at the positions near the two ends of each segment of the two-dimensional electron gas channel, and the two ends of the two-dimensional electron gas channel, each test branch, and each ohmic contact electrode are respectively connected to each test end of the multi-end test pattern.

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