Data analysis processing controller

Abstract

The invention relates to the technical field of industrial control, and discloses a data analysis processing controller. The controller comprises a cabinet, an aviation plug front panel and a cabinet VPX backboard. External 24V direct current is connected with a cabinet VPX backboard through the power supply filtering module and is reduced to 12V direct current through the power supply module. A main control module, a digital quantity input / output module, an analog quantity input / output module and two reserved slot positions are integrated on a VPX backboard of the case, and all the modules are inserted into the standard slot positions through VPX connectors. The main control module is communicated with the function module through an RS232 bus and is integrated with a gigabit Ethernet, an RS485 interface and a CAN (Controller Area Network) interface; the digital quantity module adopts a dual-channel optical coupler isolation and self-checking technology, and the analog quantity module realizes dynamic fault switching through redundant output and controllable voltage superposition. Internal cable connection is eliminated through a VPX framework, the reliability, expansibility and real-time response capability of the system are remarkably improved by combining multi-stage power supply filtering and cold conduction and heat dissipation design, and the system is suitable for ship distance adjusting devices and other complex industrial environments.

Description

Technical Field

[0001] This invention relates to the field of industrial control equipment technology, specifically to a data analysis and processing controller. Background Technology

[0002] In the electronic control system of a ship's controllable pitch propeller, the data analysis and processing controller, as one of the core components, is responsible for collecting, analyzing, and processing signals from multiple sensors and actuators to achieve real-time monitoring and precise control of the ship's navigation status. However, with the intelligent development of modern ship control systems, higher requirements are being placed on the real-time performance and reliability of data processing.

[0003] Traditional controllers often employ general-purpose processor architectures, whose computing power is insufficient to meet the multi-dimensional, high-concurrency data processing requirements of shipboard controllable pitch propeller systems. Especially in dynamic pitch adjustment and fault diagnosis scenarios, the insufficient floating-point computing power of traditional solutions leads to decreased real-time performance, making it difficult to achieve millisecond-level control responses and hindering the improvement of system dynamic performance. Furthermore, modern shipboard controllable pitch propeller devices require the acquisition of signals from multiple sensors (such as temperature, pressure, and speed) and actuators (such as hydraulic systems and motors), and these signals are diverse, including analog and digital signals. Existing controllers employ non-standardized modular designs, resulting in poor system scalability, complex maintenance, and an inability to meet the ever-increasing signal acquisition demands.

[0004] Therefore, a data analysis and processing controller is proposed to address the current shortcomings. Summary of the Invention

[0005] To address the problems of the prior art, the present invention provides a data analysis and processing controller.

[0006] The technical problem to be solved by the present invention is to overcome the defects of the above-mentioned technologies and provide a data analysis and processing controller.

[0007] To solve the above-mentioned technical problems, the technical solution provided by the present invention is a data analysis and processing controller: including a chassis, the chassis including an aviation plug front panel and a chassis VPX back panel;

[0008] The chassis is connected to an external power supply. The power supply is connected to the VPX backplane of the chassis through a power filter module and supplies power to the power module. The power module is connected to the front panel of the aviation connector and the VPX backplane of the chassis. The VPX backplane of the chassis is also connected to a main control module, a digital output module, a digital input module, an analog output module, and an analog input module. The main control module, digital output module, digital input module, analog output module, and analog input module are connected to the aviation connector plug on the front panel of the aviation connector through connectors.

[0009] As an improvement, the VPX backplane of the chassis is fixedly connected to the chassis. The VPX backplane of the chassis is provided with multiple module slots that are connected to the VPX backplane of the chassis via VPX connectors. The power filtering module, power module, main control module, digital output module, digital input module, analog output module, and analog input module are sequentially inserted along the module slots.

[0010] As an improvement, it also includes a reserved slot one and a reserved slot two, which are arranged side by side with the analog input module and are respectively connected to the front panel of the aviation plug and the back panel of the chassis VPX.

[0011] As an improvement, the power supply is 24V DC, and the power supply is through a power filter module. The power filter module includes a surge suppression circuit and a DC filter circuit. The power module steps down the voltage to 12V DC. The power module supplies power to the main control module, digital output module, digital input module, analog output module, analog input module, reserved slot one, and reserved slot two through the VPX chassis backplane.

[0012] As an improvement, the main control module is connected to the digital output module, digital input module, analog output module, analog input module, reserved slot one, and reserved slot two via the RS232 interface and the VPX backplane of the chassis, respectively.

[0013] As an improvement, the main control module is connected to the aviation connector on the front panel of the aviation connector via one 1000Base-T interface, two RS485 interfaces, and two CAN interfaces; the digital output module is connected to the aviation connector on the front panel of the aviation connector via 16 switch output interfaces, including four 4A switch output interfaces; the digital input module is connected to the aviation connector on the front panel of the aviation connector via 24 switch input interfaces; and the analog output module is connected to the front panel of the aviation connector via two non-isolated current output interfaces, two channel-isolated current output interfaces, and four non-isolated voltage output interfaces. The front panel of the aircraft connector is connected to the aircraft connector plug; the analog input module is connected to the aircraft connector plug on the front panel of the aircraft connector plug through 37 non-isolated analog input interfaces, 3 channel isolated current input interfaces, and 3 PT100 platinum resistance acquisition interfaces; the first reserved slot is connected to the aircraft connector plug on the front panel of the aircraft connector plug through 37 non-isolated analog input interfaces, 3 channel isolated current input interfaces, and 3 PT100 platinum resistance acquisition interfaces; the second reserved slot is connected to the aircraft connector plug on the front panel of the aircraft connector plug through 16 digital output interfaces, including 4 4A digital output interfaces.

[0014] As an improvement, the main control module includes a digital signal processing chip, which is powered by 12V DC. The digital signal processing chip is connected to DDR3, flash memory, PHY chip, hard disk and FPGA through interfaces. The FPGA is connected to RS232 transceiver, UART to CAN transceiver and RS485 transceiver through interfaces. The RS232 transceiver is connected to digital output module, digital input module, analog output module and analog input module through RS232. The UART to CAN transceiver is connected to the aviation plug on the front panel of the aviation plug through 2 CAN interfaces. The RS485 transceiver is connected to the aviation plug on the front panel of the aviation plug through 2 RS485 interfaces. The PHY chip is connected to 1 Ethernet.

[0015] As an improvement, the main control module integrates a GMII interface, and the main control module is connected to the PHY chip through the GMII interface. The PHY chip is connected to the transformer through the MDI interface.

[0016] The advantages of this invention compared to the prior art are:

[0017] 1. This invention adopts an open standard VPX modular architecture, achieving seamless interconnection of functional modules through standardized interfaces, thus solving problems such as poor system scalability and complex maintenance caused by traditional non-standard designs. Modules are directly plugged in through VPX connectors, eliminating defects such as poor contact and signal interference caused by traditional cable connections, significantly improving the reliability and maintainability of the system.

[0018] 2. The main control module adopts a domestically produced high-performance digital signal processing chip (DSP) and a multi-core architecture design. By integrating multiple RS232, CAN, RS485, and Ethernet interfaces, it achieves parallel processing of multiple bus protocols. This design overcomes the bottleneck of insufficient floating-point computing power of traditional general-purpose processors, meets the requirements of shipboard controllable pitch propeller systems for high-concurrency, multi-dimensional real-time data processing, and significantly improves control response speed.

[0019] 3. The digital input / output module employs dual-channel detection and optocoupler isolation technology, combined with a logic controller to perform real-time comparison of signal consistency, achieving module-level self-testing. The analog module, through controllable voltage superposition and redundant output design, can dynamically switch abnormal branches, ensuring the reliability of critical signal acquisition and output, and effectively addressing fault risks in complex electromagnetic environments.

[0020] 4. The power supply system adopts a multi-stage power filtering module, integrating surge suppression circuit and DC filtering circuit. It uses MOSFETs to control the gradual charging of the input current, suppressing the surge current at startup. The power module and the main control module are powered through the VPX backplane of the chassis, combined with thermal pads and cold plate wall-mounted heat dissipation, solving the stability problems caused by transient overcurrent and local overheating in traditional power supply designs.

[0021] 5. The front panel of the aviation connector integrates multiple digital, analog, and communication interfaces, enabling quick connection to external devices via standardized aviation connectors. The reserved slot design supports flexible expansion of functional modules, adapting to the signal acquisition and control needs of different application scenarios, significantly improving the system's versatility and secondary development efficiency. Attached Figure Description

[0022] Figure 1 This is a functional block diagram of a data analysis and processing controller according to the present invention.

[0023] Figure 2 This invention relates to the front panel of the chassis of a data analysis and processing controller.

[0024] Figure 3 This invention relates to the VPX backplane of the chassis in a data analysis and processing controller.

[0025] Figure 4 This is a schematic diagram of the internal structure of the chassis in a data analysis and processing controller according to the present invention.

[0026] Figure 5 This is a schematic diagram of a simulated mesh partitioning method for a data analysis and processing controller according to the present invention.

[0027] Figure 6 This is a thermal simulation diagram of each module of a data analysis and processing controller according to the present invention.

[0028] Figure 7 This is a thermal simulation diagram of the interior of the chassis in a data analysis and processing controller according to the present invention.

[0029] Figure 8 This is a schematic diagram of the main control module in a data analysis and processing controller according to the present invention.

[0030] Figure 9 This is a block diagram of the internal principle of the FT-M6678 chip, the main control module, in a data analysis and processing controller according to the present invention.

[0031] Figure 10 This is a schematic diagram of the network interface of a data analysis and processing controller according to the present invention.

[0032] Figure 11This is a schematic diagram of the power module MAC4650B of the main control module in a data analysis and processing controller of the present invention.

[0033] Figure 12 This is a schematic diagram of the XSC51200 memory terminal voltage regulator in the main control module of a data analysis and processing controller according to the present invention.

[0034] Figure 13 This is a schematic diagram of the 1.2V power supply module SGM6130 of the main control module in a data analysis and processing controller of the present invention.

[0035] Figure 14 This is a schematic diagram of the 1.1V power supply module SGM6033 of the main control module in a data analysis and processing controller of the present invention.

[0036] Figure 15 This is a functional block diagram of the power supply and filtering module in a data analysis and processing controller according to the present invention.

[0037] Figure 16 This is a schematic diagram of the surge suppression circuit in a data analysis and processing controller according to the present invention.

[0038] Figure 17 This is a waveform diagram of a data analysis and processing controller according to the present invention.

[0039] Figure 18 This is a functional block diagram of the digital output module in a data analysis and processing controller according to the present invention.

[0040] Figure 19 This is a functional block diagram of the digital input module in a data analysis and processing controller according to the present invention.

[0041] Figure 20 This is a functional block diagram of the analog output module in a data analysis and processing controller according to the present invention.

[0042] Figure 21 This is a functional block diagram of the analog input module in a data analysis and processing controller according to the present invention. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the invention clearer, the technical solutions of the embodiments of the invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the invention, not all embodiments. The components of the embodiments of the invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0044] In the description of the embodiments of the invention, it should be noted that if terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," or "outer" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use, they are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on the invention. Furthermore, terms such as "first," "second," and "third" are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0045] Furthermore, the use of terms such as "horizontal," "vertical," and "sag" does not imply that the component must be absolutely horizontal or suspended, but rather that it can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0046] In the description of the embodiments of the invention, "a plurality of" means at least two.

[0047] In the description of the embodiments of the invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the invention according to the specific circumstances.

[0048] Combined with appendix Figure 1 As shown, a data analysis and processing controller includes a chassis, which includes an aviation plug front panel and a chassis VPX back panel;

[0049] The chassis is connected to an external power supply. The power supply is connected to the VPX backplane of the chassis through a power filter module and supplies power to the power module. The power module is connected to the front panel of the aviation connector and the VPX backplane of the chassis. The VPX backplane of the chassis is also connected to the main control module, digital output module, digital input module, analog output module and analog input module. The main control module, digital output module, digital input module, analog output module and analog input module are connected to the aviation connector plug on the front panel of the aviation connector through connectors.

[0050] In this embodiment, the controller mainly consists of a chassis, a VPX backplane, a main control module, a power supply module, a power filtering module, a digital output module, a digital input module, an analog output module, and an analog input module. The specific hardware components are shown in the table below:

[0051] Table 1 Hardware Composition of Data Analysis and Processing Controller

[0052]

[0053]

[0054] Note: Component selection: Resistors, capacitors and other components are selected from domestic industrial grade or above components from Zhuzhou Hongda Electronics Co., Ltd.

[0055] Specifically, the main control module connects to the connector on the front panel of the connector via one 1000Base-T interface, two RS485 interfaces, and two CAN interfaces; the digital output module connects to the connector on the front panel of the connector via 16 switch output interfaces, including four 4A switch output interfaces; the digital input module connects to the connector on the front panel of the connector via 24 switch input interfaces; and the analog output module connects to the connector via two non-isolated current output interfaces, two channel-isolated current output interfaces, and four non-isolated voltage output interfaces. The front panel is connected to the aviation plug connector; the analog input module is connected to the aviation plug connector on the front panel via 37 non-isolated analog input interfaces, 3 channel isolated current input interfaces, and 3 PT100 platinum resistance acquisition interfaces; the reserved slot one is connected to the aviation plug connector on the front panel via 37 non-isolated analog input interfaces, 3 channel isolated current input interfaces, and 3 PT100 platinum resistance acquisition interfaces; the reserved slot two is connected to the aviation plug connector on the front panel via 16 digital output interfaces, including 4 4A digital output interfaces.

[0056] The main control module is connected to the digital output module, digital input module, analog output module, analog input module, reserved slot one, and reserved slot two via RS232 interface and VPX backplane of the chassis, respectively.

[0057] During implementation, the power supply is 24V DC, which is supplied through a power filter module. The power filter module includes a surge suppression circuit and a DC filter circuit. The power module steps down the voltage to 12V DC and supplies power to the main control module, digital output module, digital input module, analog output module, analog input module, reserved slot one, and reserved slot two through the VPX backplane of the chassis.

[0058] The VPX backplane is fixedly connected to the chassis. The VPX backplane has multiple module slots that are connected to the chassis via VPX connectors. The power filter module, power module, main control module, digital output module, digital input module, analog output module, and analog input module are sequentially inserted along the module slots.

[0059] It also includes reserved slot one and reserved slot two, which are set side by side with the analog input module and are respectively connected to the front panel of the aviation plug and the back panel of the chassis VPX.

[0060] Specifically, the VPX chassis backplane of this controller has 9 module slots, including 1 main control module slot, 1 power filter module slot, 2 digital output module slots (one of which is reserved), 1 digital input module slot, 1 analog output module slot, 1 analog input module slot, and a reserved slot, as well as 1 power module. A rectangular aviation connector is placed on the front panel of the aviation connector, serving as the electrical connection between the data analysis and processing controller and the external environment. The internal module layout of the controller is shown in the table below:

[0061] Table 2 Data Analysis and Processing Controller Module Layout Table

[0062]

[0063] Each module conforms to the general 3U VPX series standard. The power supply module, filter module and VPX backplane of the chassis are interconnected with high-reliability VPX connectors. Other modules are interconnected with the VPX backplane of the chassis with high-reliability VPX connectors. A rectangular aviation connector is placed on the front panel of the aviation connector, which serves as the electrical connection between the propulsion center controller and the outside world. Therefore, the modules inside the chassis are not connected to the aviation connector by cables, so as to realize the cable-free design inside the chassis and greatly ensure the reliability of the chassis.

[0064] To meet the requirements of miniaturization design, combined with the attached Figure 2-4 As shown, the controller is designed with a VPX architecture and a front-panel fully enclosed chassis. The installation method and dimensions of the chassis can be adjusted according to user requirements. In this embodiment, its length is 326mm, its width is 150mm, its height is 124mm, and its weight is 8.5Kg.

[0065] The controller's overall structure is milled from high-quality aluminum alloy and treated with anodized paint. Conductive rubber strips seal the joints of structural components, resulting in a lightweight design, high thermal conductivity, and excellent electromagnetic compatibility. Its chassis is made of lightweight, stainless aluminum alloy, and through a rational modular layout, the size of the chassis is minimized, ensuring excellent heat dissipation, structural strength, and reliability while reducing the device's weight to the greatest extent possible.

[0066] Combined with appendix Figure 4As shown, the controller's heat dissipation consists of a chassis assembly, a backplate, a power supply, a filter module, a CPU board, and six I / O boards. It adopts a board-based heat conduction design. The heat sources on the main control module and the power supply module are conducted to the board's cold plate using thermally conductive silicone pads. The cold plate then conducts the heat to the chassis wall by adhering to the wall. Since the analog / switching input module and the analog / switching output module have low power consumption, their corresponding slots are located between the main control module slot and the power supply module slot, allowing for natural heat dissipation.

[0067] In practice, the chassis's heat dissipation system primarily utilizes heat conduction. The main control module and power module are attached to the chassis via a heat-conducting plate, transferring heat to the chassis. In this embodiment, the total power consumption of the data analysis and processing controller is approximately 50W, which meets the requirements for wall-mounted heat dissipation. Simultaneously, the heat-generating chip in the controller is attached to the cold plate via a thermally conductive silicone pad, and the power module is attached to the cold plate via thermally conductive grease.

[0068] After complete bonding, the generated heat is conducted through the thermally conductive silicone pad to the main control module and power module cold plate, and the cold plate conducts the heat to the chassis wall through the wall.

[0069] Meanwhile, based on the output power of the chips and power modules, as well as the internal power distribution, a chassis thermal analysis model was established, the details of which are as follows:

[0070] 1) Based on the requirements of thermal analysis, the analysis model was simplified, and unnecessary structural details were removed to ensure the accuracy of the mesh generation. (See attached diagram) Figure 5 As shown;

[0071] 2) Generate a steady-state thermodynamic example;

[0072] 3) Assign material attributes;

[0073] 4) Define thermal loads and boundary conditions, etc.;

[0074] 5) Generate the mesh and view the thermal analysis results. See attached table for detailed analysis results. Figure 6-7 As shown.

[0075] Simulation conclusions:

[0076] Under conditions of an ambient temperature of 60℃ and a total power consumption of 50W, the maximum casing temperature is 75.44℃, which is lower than the rated junction temperature of 110℃ in the chip manual and the rated junction temperature of 100℃ in the power module, thus meeting the working environment requirements.

[0077] The highest average air temperature inside the chassis was 85.7℃.

[0078] Simulation reference value: The calculation results are basically convergent (after 500 iterations, the temperature residual is less than 10 and the temperature of the controlled point is stable), and the error with the actual result is less than 10%.

[0079] Thermal simulations demonstrate that the conductive heat dissipation method used in the aforementioned chassis can ensure that all system components operate within their rated temperature range, thus meeting the requirements for stable operation of the entire system.

[0080] Combined with appendix Figure 8 As shown, the main control module includes a digital signal processing chip, which is powered by 12V DC. The digital signal processing chip is connected to DDR3, flash memory, PHY chip, hard disk and FPGA through interfaces. The FPGA is connected to RS232 transceiver, UART to CAN transceiver and RS485 transceiver through interfaces. The RS232 transceiver is connected to digital output module, digital input module, analog output module and analog input module through RS232. The UART to CAN transceiver is connected to the aviation plug on the front panel of the aviation plug through 2 CAN interfaces. The RS485 transceiver is connected to the aviation plug on the front panel of the aviation plug through 2 RS485 interfaces.

[0081] In this embodiment, in conjunction with the appendix Figure 8 As shown, the core processor of the main control module is the FT-M6678N. The FT-M6678 adopts the Harvard architecture, which stores instructions and data separately, and the new Keystone multi-core architecture. Template matching based on correlation coefficients is one of the most important algorithms in the field of image matching. It is characterized by memory access / computation intensity, and there is considerable room for performance optimization based on the architecture of specific targets.

[0082] Combined with appendix Figure 9 As shown, the FT-M6678N has a single-core clock speed of 1GHz, with a single core capable of 32GMAC fixed-point and 16GFLOP floating-point operations. Each core contains 32KB of program memory, 32KB of data memory, and 512KB of L2 memory. The DSP's eight cores share a 4MB SRAM storage space, facilitating high-speed inter-core communication and providing storage protection for both the on-chip SRAM and off-chip DDR space. This processor features external interfaces including EMIF32, I2C, PCIe, SPI, two 4xSRIO channels, DDR3, and UART.

[0083] The main control module block diagram is attached. Figure 8 As shown, its main technical specifications are:

[0084] 1) Product shape: Standard VPX 3U size;

[0085] 2) Processor: Uses domestic DSP FT-M6678N, with a working frequency of 1GHz;

[0086] 3) Memory: Onboard DDR3 memory chips;

[0087] 4) Network: Provides one 10 / 100 / 1000Mbps adaptive Ethernet interface;

[0088] 5) Storage: Equipped with a PCIe interface electronic disk with a capacity of no less than 512GB;

[0089] 6) Serial ports: Provides 2 RS485 serial ports for external connection, 6 RS232 ports as communication bus with digital and analog I / O modules, and 2 UART ports converted into 2 CAN buses;

[0090] 7) Power consumption: 15W.

[0091] In this embodiment, the DDR3 memory chips on the main control module are SCB13H4G160AF from Unisplendour Corporation, with a single chip of 4Gb, an organization of x16, and four DDR3 chips are connected, for a total of four chips, with a speed of up to 1866Mbps and a total memory capacity of 2GB.

[0092] This chip has the following characteristics:

[0093] 1) The power supply voltage of VDD and VDDQ is 1.5V ± 0.075V;

[0094] 2) Data rate: 1600Mbps / 1866Mbps / 2133Mbps;

[0095] 3) SDRAM configuration with ×16 data inputs / outputs;

[0096] 4) Row addresses: A0 to A13;

[0097] 5) Column addresses: A0 to A9;

[0098] 6) Asynchronous reset #;

[0099] 7) Automatic precharge operation commands for reading and writing;

[0100] 8) Refresh, self-refresh, and power-saving power-off modes; Automatic self-refresh (ASR) and partial array self-refresh;

[0101] 9) Data masking function for write operations;

[0102] 10) The average refresh cycle is 7.8 μs when TCASE is low;

[0103] 11) Commands can be entered on each positive clock cycle;

[0104] 12) Data and data mask reference differential data gating pairs on both sides (dual data rate);

[0105] 13) CAS delay (CL): 5, 6, 7, 8, 9, 10, 11;

[0106] 14) Release CAS (AL=0, CL-1, and CL-2) with programmable additional delays, address and data bus efficiency;

[0107] 15) Read latency RL = AL + CL;

[0108] 16) Programmable CAS write latency (CWL);

[0109] 17) Write latency WL = AL + CWL;

[0110] 18) Burst length 8 (BL8) and burst chopper 4 (BC4) modes;

[0111] 19) Fixed or selectable On-The-Fly (OTF) via Mode Register (MRS);

[0112] 20) Pre-charge: Automatic refresh, self-refresh;

[0113] 21) Refresh: Automatic refresh, self-refresh;

[0114] 22) Refresh cycle;

[0115] 23) Multipurpose register (MPR) used to read non-memory-related information;

[0116] 24) Supports system-level timing calibration through writing;

[0117] 25) Differential clock inputs (CK and CK#);

[0118] 26) Bidirectional differential data strobe pairs (DQS and DQS#) are sent / received along with the data. Edges are aligned with read data and centered with write data.

[0119] 27) Dynamic ODT mode improves signal integrity and pre-selected termination impedance;

[0120] 28) ZQ calibration on the output driver and chip uses an external reference resistor;

[0121] 29) Actuator strength: RZQ / 7, RZQ / 6 (RZQ=240Ω);

[0122] 30) Operating temperature: -40~95℃.

[0123] The processor uses GigaDevice's GD25Q256DFIG NOR FLASH chip, which supports a voltage of 2.7V to 3.6V, has a wide operating temperature range, and has a capacity of 32MB.

[0124] This chip has the following characteristics:

[0125] 1) 8M-bit serial flash memory;

[0126] 2) Fast programming / erasing speed;

[0127] 3) 1024KB page programming time: typically 0.6ms;

[0128] 4) Each programmable page is 256 bytes - sector erase time: typical value is 45ms;

[0129] 5) Block erase time: typically 0.15 / 0.25s;

[0130] 6) Erasure time for standard, dual, and quad SPI chips: typically 4 seconds;

[0131] 7) Standard SPI: SCLK, CS#, SI, SO, WP#, HOLD#;

[0132] 8) Dual SPI: SCLK, CS#, IO0, IO1, WP#, HOLD#;

[0133] 9) Flexible architecture;

[0134] 10) Four-way SPI: SCLK, CS#, IO0, IO1, IO2, IO3 - a unified sector of 4K bytes;

[0135] 11) Uniform blocks of 32 / 64KB;

[0136] 12) High-speed clock frequency;

[0137] 13) 120MHz is used for fast readout of a 30pF load;

[0138] 14) Low power consumption;

[0139] 15) Up to 240 Mbits / s dual I / O data transfer - 1 μA typical deep power-off current;

[0140] 16) Four-channel I / O data transmission up to 480 Mbits / s - 1 μA typical standby current;

[0141] 17) Advanced security features;

[0142] 18) Software write protection for all / partial memory - a 128-bit unique ID for each device;

[0143] 19) Use WP#Pin to enable / disable protection - a 4x256-byte security register with OTP lock;

[0144] 20) Top / Bottom Block Protection - Discoverable Parameter (SFDP) Register;

[0145] 21) Single power supply voltage;

[0146] 22) Continuous read, 8 / 16 / 32 / 64 bytes wrapped - full voltage range: 2.7~3.6V;

[0147] 23) Minimum 100,000 programming / erase cycles;

[0148] 24) Data retention, 20-year data retention period.

[0149] The PHY chip connects to one Ethernet port. Specifically, the main control module integrates a GMII interface, which connects to the PHY chip. The PHY chip connects to the transformer via the MDI interface.

[0150] In this embodiment, in conjunction with the appendix Figure 10 As shown, the FT-M6678 processor integrates GMII, which connects to the domestic Yutai Automotive PHY chip YT8521S to enable gigabit network functionality. After passing through a transformer, it is connected to the rear panel of the chassis.

[0151] During implementation, in conjunction with the appendix Figure 11 As shown, the core power supply of the main control module uses the MAC4650 power supply module. The MAC4650 is a power supply module that can provide dual 25A or single 50A outputs, featuring excellent load and line regulation. The MAC4650 operates from 4V to 16V, with an output voltage range of 0.6V to 1.8V. The output voltages of the MAC4650 can be set separately using a resistor for each output. Employing a multi-phase constant on-time control mode, it provides ultra-fast transient response and minimal output capacitance. The DC / DC converter, power inductor, and other passive components are integrated in a 16mm x 16mm x 5.18mm BGA package.

[0152] The MAC4650 has the following characteristics:

[0153] 1) The pins are compatible with dual-channel 25A and single-channel 50A output power modules;

[0154] 2) Input voltage range: 4V to 16V;

[0155] 3) Output voltage range: 0.6V to 1.8V;

[0156] 4) The COT control mode enables ultra-fast transient response;

[0157] 5) Adjustable switching frequency;

[0158] 6) Adjustable soft-start time;

[0159] 7) Configurable working modes;

[0160] 8) Overcurrent and overvoltage protection;

[0161] 9) Differential remote sampling function for two output channels.

[0162] Combined with appendix Figure 12 As shown, the DDR3 memory chip power supply uses the Nanjing Tianyi XSC51200, a double data rate (DDR) terminating regulator for both sink and pull current. The XSC51200 maintains a fast transient response and requires a minimum of only 20μF output capacitor. The XSC51200 supports remote sampling and meets all power requirements for DDR, DDR2, DDR3, low-power DDR3, and DDR4 buses. Furthermore, the XSC51200 provides a PGOOD signal monitoring output function, offering an EN signal for VTT discharge against DDR during S3 (suspended to RAM).

[0163] Meanwhile, for other low-current power supplies, combined with the attached Figure 13-14 As shown, in this embodiment, for example, 1.2V and 1.1V are powered by SGM6130 and SGM6033 from Saint-Gobain. The SGM6130 has an input voltage range of 4.5 to 28.5V and a maximum load capacity of 3A. The SGM6033 has an input voltage range of 2.5 to 5.5V and a load capacity of 1A.

[0164] Combined with appendix Figure 15 As shown, in the controller, the power module completes the DC 24V power input and output DC 12V secondary power conversion, and completes the power filtering, surge suppression, overvoltage and overcurrent protection functions through the filter module. The power module is the domestic Funeng FDB504B24S10T, and the filter is the Zhongshi Weiye DC filter FLBR31D-10A.

[0165] The main technical specifications of the power module are as follows:

[0166] 1) AC input: DC 18~30V;

[0167] 2) DC output: Two +12V output currents not less than 25A;

[0168] 3) Output voltage ripple: ≤180mV;

[0169] 4) It has output short circuit and overcurrent protection functions.

[0170] In the filtering module, combined with the attached... Figure 16As shown, the surge suppression circuit utilizes the current amplification characteristics of the field-effect transistor to control the input current to gradually increase from 0, slowly charging the output capacitor until the field-effect transistor is fully turned on, thereby avoiding the large current generated due to the instantaneous short-circuit characteristics of the output capacitor.

[0171] Its working process is mainly divided into three stages: power-on stage, C1 charging stage, and Cin charging stage.

[0172] 1) Power-on phase:

[0173] At the moment of power-on, capacitor C1 is short-circuited, the voltage across SG of PMOS transistor Q1 is 0, Q1 is not conducting, the impedance across SD is infinite, and there is no current through Cin.

[0174] 2) C1 charging stage:

[0175] The input charges C1, with a charging time constant of approximately R2*C1. As C1 charges, the voltage across Q1's SG terminal gradually increases. When it reaches the PMOS transistor's turn-on voltage Vth, Q1 turns on.

[0176] 3) Cin charging stage:

[0177] As the voltage across C1 gradually increases, Q1 gradually turns on, and the current flowing through the tube gradually increases, thus charging Cin. The charging time constant is Rsd*Cin, where Rsd is the equivalent resistance when Q1 is turned on.

[0178] Charging ends when the voltage across C1 reaches the input voltage across R1. Charging also ends when the voltage across Cin reaches the input voltage.

[0179] Combined with appendix Figure 17 As shown, Vc1 is the voltage across C1, Vcin is the voltage across Cin, and Icin is the current flowing through Cin. Therefore, using this circuit in the front-end of the power module can effectively suppress the startup peak current.

[0180] In addition, during actual implementation, there are usage requirements for electromagnetic compatibility standards CE101, CE102, CS101, CS106, CS114, CS116, RE101, RE102, RS101, and RS103.

[0181] A filter board is added to the DC24V voltage input of the controller. The filter is a FLBR31D-10A DC filter from Zhongshi Weiye. The filter adopts a Π-type filtering method. This filter has been widely used in previous products to ensure the controller operates stably in electromagnetic environments.

[0182] The filter board provides a DC power interface to filter the input power. The panel also houses a power switch, indicator lights, and a fuse for power-off control and power voltage indication.

[0183] Combined with appendix Figure 18 As shown, the main chip of the digital input module is Gowin Semiconductor's GW1N-UV4PG256C6 / I5, which mainly implements 32-channel digital input interfaces.

[0184] The digital input module adopts a dual-channel detection method for input. Each external input signal is connected to the digital input module and is divided into two identical signal branches. Each signal is acquired through an independent channel, and the microcontroller compares whether the two branches are consistent. If they are consistent, the channel is working normally; if they are inconsistent, the channel is faulty. This realizes the self-testing function of the digital input module.

[0185] In the digital input module, to achieve complete isolation between digital and input signals, an OC333 optocoupler is used for isolation. This optocoupler contains four independent channels, with a current transfer ratio (CTR) of 100%–600% and a forward conduction voltage of approximately 1.3V. The input interface is designed with shunt resistors, current-limiting resistors, filter capacitors, and protection diodes. The diodes protect the optocoupler from breakdown, while the shunt resistors improve the anti-interference capability of the optocoupler's front end. The output of the optocoupler is connected to an LC164245BRFC inverter. After signal isolation processing, the signal is sent to the main chip of the digital input module, improving signal transmission reliability.

[0186] Combined with appendix Figure 19 As shown, the main chip of the digital (switch) output module is Gowin Semiconductor's GW1N-UV4PG256C6 / I5, which mainly realizes 20 channels of 2A switch output and 4 channels of 4A switch output.

[0187] In the digital (switching) output module, a single-pole-throw relay is used to output the digital signal. To achieve complete isolation between the digital signal and the output control signal, an OC333 optocoupler is used for isolation, with a current transfer ratio (CTR) of 100%–600% and a forward conduction voltage of 1.3V. The input interface is designed with shunt resistors, current-limiting resistors, filter capacitors, and protection diodes. The diodes provide protection against optocoupler breakdown, and the shunt resistors improve the anti-interference capability of the optocoupler front end.

[0188] The output signal of the relay is sampled back through the optocoupler circuit to realize the channel self-test of the DO digital quantity (switching quantity) output module.

[0189] Combined with appendix Figure 20As shown, the main chip of the analog input module is the GW1N-UV4PG256C6 / I5 from Gowin Semiconductor, which mainly realizes 20 channels of ±10V analog signal acquisition, 6 channels of isolated current signal input acquisition and 5 channels of PT100 / PT1000 acquisition.

[0190] The ADC uses Suzhou Yunxin Microelectronics' YA16S80, a 16-bit, 80MSPS single-channel analog-to-digital converter (ADC) supporting communication applications requiring high performance, low cost, small size, and multifunctionality. The ADC employs a multi-stage, differential pipelined architecture and integrates output error correction logic, supporting various user-selectable input ranges. An integrated reference voltage source simplifies the design. A duty cycle stabilizer compensates for ADC clock duty cycle fluctuations, maintaining excellent converter performance. ADC output data can be directly sent to an external 16-bit output port, configurable as 1.8V CMOS or LVDS. Flexible power-down options significantly reduce power consumption when needed. Programming for setup and control is accomplished using a three-wire SPI-compatible serial interface. The chip is available in a 48-pin QFN package.

[0191] The chip has the following characteristics:

[0192] 1) Low power consumption: 395mW@125MSPS;

[0193] 2) Power supply voltage: 1.8V;

[0194] 3) Output level: 1.8V CMOS or LVDS;

[0195] 4) Signal-to-noise ratio (SNR) = 76 dBFS (Fin = 70 MHz / Fs = 125 MSPS);

[0196] 5) Spurious-free dynamic range (SFDR) = 86dBc (Fin = 70MHz / Fs = 125MSPS);

[0197] 6) Built-in 1 to 8 times input clock integer divider;

[0198] 7) Small signal input noise: -153dBm / Hz (200Ω input impedance / Fin=70MHz / Fs=125MSPS);

[0199] 8) Programmable internal reference voltage source;

[0200] 9) Differential analog input range: analog signal conversion to acquire voltage -10~+10V and current 0~24mA;

[0201] 10) Differential analog input bandwidth: 650MHz.

[0202] A PT100 temperature sensor has been added to the analog input module. The PT100 temperature sensor is a platinum resistance thermometer, and its resistance changes with temperature. Its resistance is 100Ω at 0℃ and approximately 138.5Ω at 100℃. Using the PT100 temperature sensor, the current operating temperature of the equipment can be accurately and efficiently calculated from the sensor's output by inputting a standard voltage from an external power supply.

[0203] In the analog input module, a controllable voltage superposition method is used to controllably superimpose a voltage onto the input analog signal at the input terminal. A hardware distribution circuit then splits one analog signal into two independent analog signal branches. A controllable micro-voltage is superimposed at the input terminal, and the subsequent logic controller performs controllable calculations to restore the input signal. By comparing the calculated superimposed voltage with the input voltage, the operating status of the analog input circuit can be detected, and abnormal branches can be switched promptly.

[0204] Combined with appendix Figure 21 As shown, the main chip of the analog output module is Gowin Semiconductor's GW1N-UV4PG256C6 / I5, which mainly realizes 10 non-isolated 0-24mA analog current output, 2 isolated 0-24mA analog current output, and 4 non-isolated voltage output.

[0205] The DAC uses the Suzhou Yunxin Microelectronics YD16D250, a dual-channel 16-bit high dynamic range DAC that supports a maximum conversion rate of 250Msps and can output multi-carrier wideband signals within the Nyquist band. The YD16D250 is specifically designed for direct conversion transmit applications, including gain and bias compensation. The DAC output can be seamlessly connected to an analog quadrature modulator. The DAC uses a 4-wire SPI interface for configuration, reading, and other operations.

[0206] The chip has the following characteristics:

[0207] 1) Dual-channel digital-to-analog converter;

[0208] 2) Low noise and intermodulation distortion;

[0209] 3) Single-carrier WCDMA ACLR = 80dBc @ 61.44MHz;

[0210] 4) Dual-port or single-port interleaved LVCMOS data input interface;

[0211] 5) Programmable differential output current from 0mA to 24mA, voltage from -10 to +10V;

[0212] 6) The 10-bit auxiliary DAC supports external analog signal bias adjustment;

[0213] 7) Built-in 1.2V precision bias voltage;

[0214] 8) 1.8V and 3.3V power supply;

[0215] 9) 4-wire SPI control interface;

[0216] 10) 310mW power consumption;

[0217] In the analog output module, the selected DAC chip has a self-calibration function. To enhance the reliability of the device, each output uses redundant output. Through redundant output circuits, a default output circuit is selected when both outputs are normal, and the abnormal output circuit can be shut down promptly when one output malfunctions. This ensures the normal output of the analog output module. For critical analog outputs, a sampling detection circuit is designed to promptly detect problems and isolate faults.

[0218] In the analog output module, to achieve complete isolation between digital and analog signals, the GL1200P digital isolator from Zhongke Geliwei is used, with a maximum transmission rate of 25Mbps, a quality class of N, and an operating temperature of -55~125℃.

[0219] In practical implementation, the controller achieves its functions through integration with software, which is implemented through firmware software, operating system software, drivers, and FPGA programs for I / O modules.

[0220] Specifically, the function of the firmware software is to initialize the controller and guide the operating system to load, thus handing over control of the controller to the operating system.

[0221] The functions of operating system software include task management, inter-task synchronization and communication, clock / timer management, interrupt / exception management, memory management, etc., and input / output control of I / O modules through drivers.

[0222] The function of a driver is to establish communication between the operating system and the I / O module, so as to enable the operating system to control the I / O module.

[0223] The FPGA program function of the I / O module is to control digital input / output, analog input / output, and communication with the main control module.

[0224] The present invention and its embodiments have been described above. This description is not restrictive, and the accompanying drawings are only one embodiment of the present invention; the actual structure is not limited thereto. In conclusion, if those skilled in the art are inspired by this description and design similar structures and embodiments without departing from the spirit of the invention, such designs should fall within the protection scope of the present invention.

Claims

1. A data analysis and processing controller, comprising a chassis, characterized in that, The chassis includes an aviation-grade front panel and a chassis VPX back panel; The chassis is connected to an external power supply. The power supply is connected to the VPX backplane of the chassis through a power filter module and supplies power to the power module. The power module is connected to the front panel of the aviation connector and the VPX backplane of the chassis. The VPX backplane of the chassis is also connected to a main control module, a digital output module, a digital input module, an analog output module, and an analog input module. The main control module, digital output module, digital input module, analog output module, and analog input module are connected to the aviation connector plug on the front panel of the aviation connector through connectors.

2. The data analysis and processing controller according to claim 1, characterized in that: The VPX backplane of the chassis is fixedly connected to the chassis. The VPX backplane of the chassis has multiple module slots that are connected to the VPX backplane of the chassis via VPX connectors. The power filtering module, power module, main control module, digital output module, digital input module, analog output module, and analog input module are sequentially inserted along the module slots.

3. The data analysis and processing controller according to claim 2, characterized in that: It also includes reserved slot one and reserved slot two, which are arranged side by side with the analog input module and are respectively connected to the front panel of the aviation plug and the back panel of the chassis VPX.

4. A data analysis and processing controller according to claim 3, characterized in that: The power supply is 24V DC, which is supplied through a power filter module. The power filter module includes a surge suppression circuit and a DC filter circuit. The power module steps down the voltage to 12V DC. The power module supplies power to the main control module, digital output module, digital input module, analog output module, analog input module, reserved slot one, and reserved slot two through the VPX chassis backplane.

5. A data analysis and processing controller according to claim 4, characterized in that: The main control module is connected to the digital output module, digital input module, analog output module, analog input module, reserved slot one, and reserved slot two via RS232 interface and VPX backplane of the chassis, respectively.

6. A data analysis and processing controller according to claim 5, characterized in that: The main control module is connected to the aviation connector on the front panel of the aviation connector via one 1000Base-T interface, two RS485 interfaces, and two CAN interfaces. The digital output module is connected to the aviation connector on the front panel of the aviation connector via 16 switch output interfaces, including four 4A switch output interfaces. The digital input module is connected to the aviation connector on the front panel of the aviation connector via 24 switch input interfaces. The analog output module is connected to the aviation connector on the front panel of the aviation connector via two non-isolated current output interfaces, two channel-isolated current output interfaces, and four non-isolated voltage output interfaces. The analog input module is connected to the aviation connector on the front panel of the aviation connector via 37 non-isolated analog input interfaces, 3 isolated current input interfaces, and 3 PT100 platinum resistance acquisition interfaces; the first reserved slot is connected to the aviation connector on the front panel of the aviation connector via 37 non-isolated analog input interfaces, 3 isolated current input interfaces, and 3 PT100 platinum resistance acquisition interfaces; the second reserved slot is connected to the aviation connector on the front panel of the aviation connector via 16 digital output interfaces, including 4 4A digital output interfaces.

7. A data analysis and processing controller according to claim 6, characterized in that: The main control module includes a digital signal processing chip powered by 12V DC. The chip is connected to DDR3, flash memory, a PHY chip, a hard disk, and an FPGA via interfaces. The FPGA is connected to an RS232 transceiver, a UART-to-CAN transceiver, and an RS485 transceiver via interfaces. The RS232 transceiver is connected to digital output modules, digital input modules, analog output modules, and analog input modules via RS232. The UART-to-CAN transceiver is connected to the aviation connector on the front panel of the aviation connector via two CAN interfaces. The RS485 transceiver is connected to the aviation connector on the front panel of the aviation connector via two RS485 interfaces. The PHY chip is connected to one Ethernet port.

8. A data analysis and processing controller according to claim 7, characterized in that: The main control module integrates a GMII interface, which is connected to the PHY chip. The PHY chip is connected to the transformer via an MDI interface.

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