Inter-chip interconnection method and system based on AXI bus
By buffering and encoding signals on the AXI bus channels and then transmitting them in a time-division multiplexing manner, the hardware circuit pressure problem caused by the excessive signal line width of the AXI bus is solved, simplifying inter-chip interconnection and reducing the IO pin requirements.
Patent Information
- Application Number
- CN202511048770.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-29
- Publication Date
- 2025-11-14
AI Technical Summary
In a SoC system, when the CPU chip and the PHY chip inside the FPGA are interconnected, the AXI bus signal line width is too large, resulting in the need for too many IO pins, which increases the hardware circuit design and performance pressure.
By sending AXI signals on each channel of the AXI bus and buffering them in an asynchronous FIFO, then encoding them, and then sending them to the inter-chip signal lines in a time-division manner, the signal of each channel occupies the inter-chip signal lines at different times, thus reducing the number of inter-chip signal lines.
It reduces the pressure on hardware circuit design and performance, reduces the need for IO pins, simplifies hardware circuit wiring, and is suitable for inter-chip interconnection between different chips.
Smart Images
Figure CN120950444A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic technology, and in particular to an inter-chip interconnection method and system based on the AXI bus. Background Technology
[0002] With technological advancements, the CPU and PHY (Physical Theory Object) in a System-on-Chip (SoC) system are now widely used, as they are separated into two modules and placed on different ASIC / FPGA chips for verification. However, when the AXI bus is used for direct inter-chip interconnection, and the SoC system is placed on different chips (such as using dedicated CPU chips and FPGAs) for overall verification—that is, in the scheme of inter-chip interconnection and overall verification between the CPU chip and the PHY chip located inside the FPGA—the CPU chip often faces the challenge of excessively wide signal lines in the AXI bus, requiring too many I / O pins for connection, which puts significant pressure on the design and performance of the hardware circuit. Summary of the Invention
[0003] The purpose of this application is to provide a method and system for inter-chip interconnection based on the AXI bus.
[0004] In a first aspect, this embodiment provides an inter-chip interconnection method based on an AXI bus, applied to an AXI bus-based inter-chip interconnection system. The AXI bus-based inter-chip interconnection system includes a first chip, a second chip, and a verification module. The second chip is disposed inside the verification module, and the first chip is connected to the second chip disposed inside the verification module via inter-chip signal lines. The inter-chip signal lines are signal lines between the first chip and the verification module. The method includes:
[0005] The process of one chip sending an AXI signal to another chip includes:
[0006] A chip sends AXI signals through each channel of the AXI bus in a preset time sequence and buffers them into the asynchronous FIFO corresponding to each channel.
[0007] After the AXI signal comes out from its respective asynchronous FIFO, the AXI signal of the asynchronous FIFO corresponding to each channel is read, and the preset bit width of the AXI signal of each channel is encoded.
[0008] The encoded AXI signals of each channel are sent to the inter-chip signal line in a time-division manner; the AXI signal of each channel occupies the inter-chip signal line for a different period of time.
[0009] In some embodiments, the encoded AXI signals of each channel are sequentially sent to the inter-chip signal line, including:
[0010] Each channel's AXI signal after encoding is divided into a first AXI signal and a second AXI signal; the first AXI signal and the second AXI signal are AXI signals of the same channel;
[0011] In the first cycle, the first AXI signal is sent to the inter-chip signal line;
[0012] In the second cycle, the second AXI signal is sent to the inter-chip signal line; the first and second cycles are two consecutive cycles.
[0013] In some embodiments, the encoded AXI signal of each channel is divided into a first AXI signal and a second AXI signal, including:
[0014] Based on the bit width of the encoded AXI signal of each channel, the encoded AXI signal of each channel is divided into a first AXI signal and a second AXI signal with the same bit width.
[0015] In some embodiments, it also includes:
[0016] The process by which another chip receives an AXI signal sent by another chip includes:
[0017] Another chip receives a clock signal from the inter-chip signal line and samples the AXI signal from the inter-chip signal line according to the clock signal;
[0018] The sampled AXI signal is decoded to restore the encoded AXI signal, and the channel corresponding to the sampled AXI signal is determined according to the preset bit width of the encoded AXI signal.
[0019] The AXI signal of the determined channel is buffered into the corresponding asynchronous FIFO. After the AXI signal comes out of its respective asynchronous FIFO, it is transmitted to the corresponding channel.
[0020] In some embodiments, the sampled AXI signal is decoded to restore the encoded AXI signal, and the channel corresponding to the sampled AXI signal is determined according to the preset bit width of the encoded AXI signal, including:
[0021] The first AXI signal and the second AXI signal of two consecutive cycles on the inter-chip signal line are spliced together to restore the encoded AXI signal.
[0022] Based on the preset bit width of the encoded AXI signal, determine the channels corresponding to the first AXI signal and the second AXI signal.
[0023] In some embodiments, splicing two consecutive cycles of the first AXI signal and the second AXI signal on the inter-chip signal line includes:
[0024] If the valid line on the inter-chip signal line of the current cycle goes high, then the current cycle is determined to be the first cycle, the second cycle is the next cycle, and the first cycle and the second cycle are two consecutive cycles.
[0025] The first AXI signal of the first cycle and the second AXI signal of the second cycle are spliced together.
[0026] In some embodiments, it also includes:
[0027] The ready signal controls the normal operation or pause of the AXI signal transmission and reception process.
[0028] In some embodiments, it also includes:
[0029] When the first chip is the master and the second chip is the slave, the master sends an AXI signal to the slave through the first inter-chip signal line, and the slave sends a feedback signal of the AXI signal to the master through the second inter-chip signal line.
[0030] When the second chip is the master and the first chip is the slave, the master sends an AXI signal to the slave through the third inter-chip signal line, and the slave sends a feedback signal of the AXI signal to the master through the fourth inter-chip signal line.
[0031] The AXI signals include: AXI write signals sent through the write address channel and the write data channel, and AXI read signals sent through the read address channel; the feedback signals of the AXI signals include: AXI write signals sent through the write response channel, and AXI read signals sent through the read data channel.
[0032] The sum of the number of signal lines between the first and second plates is less than 50.
[0033] The total number of signal lines between the third and fourth plates is less than 50.
[0034] Secondly, embodiments of this application provide an inter-chip interconnection system based on an AXI bus, including: a first chip, a second chip, and a verification module; the second chip is disposed inside the verification module, and the first chip is connected to the second chip disposed inside the verification module via an inter-chip signal line; the inter-chip signal line is a signal line between the first chip and the verification module;
[0035] The first chip and the second chip perform the steps of the inter-chip interconnection method based on the AXI bus as described in any one of claims 1 to 8.
[0036] Thirdly, embodiments of this application provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the inter-chip interconnection method based on the AXI bus provided in any of the above embodiments.
[0037] The inter-chip interconnection method based on the AXI bus provided in this application embodiment is applied to an inter-chip interconnection system based on the AXI bus. The inter-chip interconnection system based on the AXI bus includes a first chip, a second chip, and a verification module. The second chip is disposed inside the verification module, and the first chip is connected to the second chip disposed inside the verification module through inter-chip signal lines. The inter-chip signal lines are signal lines between the first chip and the verification module. The process of one chip sending an AXI signal to another chip includes: one chip sending AXI signals through each channel of the AXI bus in a preset time sequence and buffering them into the asynchronous FIFO corresponding to each channel; after the AXI signals come out from their respective asynchronous FIFOs, reading the AXI signals of the asynchronous FIFOs corresponding to each channel, and encoding the preset bit width of the AXI signal of each channel; and sending the encoded AXI signals of each channel to the inter-chip signal lines in a time-division manner. The AXI signals of each channel occupy different times on the inter-chip signal lines. That is, by sending AXI signals separately in time through each channel of a chip, the number of inter-chip signal lines can be reduced, the first chip does not need too many IO pins for connection, and no additional hardware modules are required, reducing the pressure on the design and performance of the hardware circuit. Attached Figure Description
[0038] Figure 1 A flowchart illustrating the AXI signal transmission process of an inter-chip interconnection method based on the AXI bus provided in this application embodiment;
[0039] Figure 2 A flowchart illustrating the AXI signal reception process of an inter-chip interconnection method based on the AXI bus provided in this application embodiment;
[0040] Figure 3 A schematic diagram of an inter-chip interconnection system based on the AXI bus is provided for embodiments of this application;
[0041] Figure 4 A schematic diagram illustrating the signal transmission and reception process of an inter-chip interconnection method based on an AXI bus, provided in an embodiment of this application;
[0042] Figure 5 This application provides a schematic diagram illustrating the signal classification of an AXI bus according to an embodiment of the present application.
[0043] Figure 6A schematic diagram of an experimental test structure in which the CPU and SRAM are placed on different FPGAs, as provided in an embodiment of this application;
[0044] Figure 7 for Figure 6 The diagram illustrates the behavior of the AXI bus in FPGA2 by initiating a write command through the CPU inside FPGA1.
[0045] Figure 8 for Figure 6 The diagram illustrates how a read command is initiated by the CPU inside FPGA1 to observe the behavior of the AXI bus in FPGA2. Detailed Implementation
[0046] Various embodiments and features of this application are described herein with reference to the accompanying drawings.
[0047] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this application will be apparent to those skilled in the art.
[0048] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.
[0049] These and other features of this application will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.
[0050] It should also be understood that although this application has been described with reference to some specific examples, those skilled in the art can certainly implement many other equivalent forms of this application.
[0051] The above and other aspects, features and advantages of this application will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.
[0052] Specific embodiments of this application are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this application, which can be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure the application. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely serve as the basis and representative basis for the claims to teach those skilled in the art to use this application in a variety of substantially any suitable detailed structures.
[0053] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in other embodiments,” all of which may refer to one or more of the same or different embodiments according to this application.
[0054] First, we will introduce and explain several terms involved in this application.
[0055] SOC (System on Chip) refers to a chip that integrates the functions of an entire system.
[0056] FPGA (Field Programmable Gate Array) is a chip whose internal structure can be changed according to requirements to meet specific purposes.
[0057] AXI (Advanced eXtensible Interface) is a commonly used system interconnect bus within a System-on-a-Chip (SoC).
[0058] A serdes (serializer / deserializer) is a module that converts between multi-bit low-speed parallel signals and single-bit high-speed signals in some way.
[0059] The research and development approach of this application includes: In the inter-chip interconnection and overall verification scheme between the CPU chip and the PHY chip located inside the FPGA, the CPU chip often faces the problem of excessively large signal line widths for AXI signals, requiring too many IO pins for connection, which puts significant pressure on hardware circuit design and performance. Traditional solutions typically involve encoding the AXI signal and then using a SerDes module for transmission and reception. This proposed scheme involves: the transmitting end first encoding the AXI signal, then sending it to the SerDes module for transmission to the inter-chip signal lines; the receiving end's SerDes module decodes the received signal and finally restores it to the AXI signal for use by the on-chip modules.
[0060] However, there are still some problems with using the SERDE scheme or encoding / decoding AXI signals:
[0061] 1. The design of the SERDES module is relatively complex. If the SERDES solution is used, the ASIC / FPGA must first have the hardware module, and a lot of effort needs to be spent in the early design stage of the FPGA / ASIC.
[0062] 2. Using the SERDES module to transmit and receive signals poses a significant challenge to the hardware circuitry, potentially requiring substantial customization and hindering widespread adoption.
[0063] Therefore, this application provides an inter-chip interconnection method and system based on the AXI bus, which aims to solve the above-mentioned technical problems in the prior art.
[0064] The technical solution of this application will be described in detail below with reference to specific embodiments.
[0065] Combination Figure 1 and Figure 3 As shown, this embodiment provides an inter-chip interconnection method based on the AXI bus, applied to an AXI bus-based inter-chip interconnection system. The AXI bus-based inter-chip interconnection system includes a first chip, a second chip, and a verification module. The second chip is disposed inside the verification module, and the first chip is connected to the second chip disposed inside the verification module via inter-chip signal lines. The inter-chip signal lines are signal lines between the first chip and the verification module. The AXI bus-based inter-chip interconnection method includes:
[0066] The process of one chip sending an AXI signal to another chip includes:
[0067] S10: A chip sends AXI signals through each channel of the AXI bus in a preset time sequence and buffers them into the asynchronous FIFO corresponding to each channel.
[0068] In this application, one chip may be a first chip and the other chip may be a second chip, or one chip may be a second chip and the other chip may be a first chip.
[0069] Optionally, the first chip can be a CPU chip, the second chip can be a PHY chip, and the verification module can be an FPGA module.
[0070] The inter-chip signal lines in this application may include three types of signal lines: synchronous clock lines (i.e., clk lines), valid lines, and data lines (i.e., pad lines); among them, the clk lines provide clock signals for the pad lines and may be different from the AXI clock lines within the chip. Valid lines refer to the valid signal lines of each channel, which are pulled high during transmission on any channel.
[0071] Specifically, in combination Figure 4 In a chip, the AXI signal lines of each channel are buffered into their respective asynchronous FIFOs after the valid line of that channel is pulled high, thus completing the conversion from the clock domain of the AXI bus within the chip to the clock domain of the inter-chip signal lines.
[0072] S11, after the AXI signal comes out from its respective asynchronous FIFO, read the AXI signal of the asynchronous FIFO corresponding to each channel, and encode the preset bit width of the AXI signal of each channel.
[0073] Optionally, the preset bit width can be [2:0], or other preset bit widths, which are not limited in this application.
[0074] Taking a preset bit width of [2:0] as an example, in the data lines (pad lines): [n:3] are the actual signal lines, and [2:0] are the channel codes, which are used to determine which channel the signal actually belongs to.
[0075] Specifically, in combination Figure 4 After the AXI signal comes out from its respective asynchronous FIFO, the AXI signal of each channel's corresponding asynchronous FIFO is read, and the lower 3 bits of the AXI signal are encoded to facilitate the determination of which channel the AXI signal belongs to during subsequent decoding.
[0076] S12, the encoded AXI signals of each channel are sent to the inter-chip signal line in a time-division manner; the AXI signals of each channel occupy the inter-chip signal line for a different time.
[0077] Specifically, in combination Figure 4 The encoded AXI signals of each channel are sent to the inter-chip signal line separately in time. When it is the turn of a certain address instruction to be sent, the pad line on the inter-chip signal line is occupied, and the valid line is pulled high. After the transmission is completed, the pad line is released, and the valid line is pulled low again.
[0078] This application embodiment transmits AXI signals separately in time through the channels of a single chip, which reduces the number of inter-chip signal lines. The first chip does not require too many IO pins for connection, and no additional hardware modules are needed, thus reducing the pressure on the design and performance of the hardware circuit.
[0079] In some embodiments, the encoded AXI signals of each channel are sequentially sent to the inter-chip signal line, including:
[0080] Each channel's AXI signal after encoding is divided into a first AXI signal and a second AXI signal; the first AXI signal and the second AXI signal are AXI signals of the same channel;
[0081] In the first cycle, the first AXI signal is sent to the inter-chip signal line;
[0082] In the second cycle, the second AXI signal is sent to the inter-chip signal line; the first and second cycles are two consecutive cycles.
[0083] Specifically, the encoded AXI signal of each channel is divided into two groups according to the bit width of the AXI signal line of each channel, namely the first AXI signal and the second AXI signal. The first AXI signal and the second AXI signal are AXI signals of the same channel, and the first AXI signal and the second AXI signal are sent sequentially for two consecutive cycles.
[0084] The embodiments of this application can further reduce the number of inter-chip signal lines by sending the AXI signal of each channel to the inter-chip signal line in two consecutive cycles.
[0085] In some embodiments, the encoded AXI signal of each channel is divided into a first AXI signal and a second AXI signal, including:
[0086] Based on the bit width of the encoded AXI signal of each channel, the encoded AXI signal of each channel is divided into a first AXI signal and a second AXI signal with the same bit width.
[0087] For example, if the encoded width of a certain channel is 100 bits, then the width of the AXI signal line can be set to 50 bits, and AXI signals of [49:0] and [99:50] can be sent for two consecutive cycles. Generally, the write data channel w requires the largest signal width.
[0088] In some embodiments, combined with Figure 2 and Figure 3 As shown, the inter-chip interconnection method based on the AXI bus also includes:
[0089] The process by which another chip receives an AXI signal sent by another chip includes:
[0090] S20, another chip receives the clock signal from the inter-chip signal line and samples the AXI signal from the inter-chip signal line according to the clock signal;
[0091] Following the previous example, the inter-chip signal lines in this application can include three types of signal lines: synchronous clock lines (i.e., clk lines), valid lines, and data lines (i.e., pad lines). The clk lines provide clock signals to the pad lines and can be different from the AXI clock lines within the chip. The valid lines refer to the valid signal lines for each channel, which are pulled high during transmission on any channel. In the data lines (pad lines): [n:3] are the actual signal lines, and [2:0] are the channel codes, used to determine which channel the signal actually belongs to.
[0092] Specifically, in combination Figure 4 When the valid signal line of the inter-chip signal line is pulled high, another chip receives the clock signal from the clk line of the inter-chip signal line and samples the AXI signal from the pad line of the inter-chip signal line according to the received clock signal.
[0093] S21, decode the sampled AXI signal, restore the encoded AXI signal, and determine the channel corresponding to the sampled AXI signal according to the preset bit width of the encoded AXI signal;
[0094] Combination Figure 4 Another chip decodes the sampled AXI signal, restores the encoded AXI signal, determines which channel the sampled AXI signal belongs to, and determines the channel corresponding to the AXI signal on the inter-chip signal line based on the preset bit width of the encoded AXI signal.
[0095] S22, the AXI signal of the determined channel is buffered into the corresponding asynchronous FIFO, and after the AXI signal comes out of its respective asynchronous FIFO, the AXI signal is transmitted to the corresponding channel.
[0096] Combination Figure 4 The AXI signal of the determined channel is buffered into the corresponding asynchronous FIFO. After the AXI signal comes out of its respective asynchronous FIFO, the AXI signal from its respective asynchronous FIFO is read and restored to the clock domain of the AXI bus in another chip. This completes the conversion from the clock domain of the inter-chip signal line to the clock domain of the AXI bus in the chip. The AXI signal is then transmitted to the corresponding channel in the chip, restoring the specific AXI signal of each channel of the AXI bus for use within the chip.
[0097] In some embodiments, the sampled AXI signal is decoded to restore the encoded AXI signal, and the channel corresponding to the sampled AXI signal is determined according to the preset bit width of the encoded AXI signal, including:
[0098] The first AXI signal and the second AXI signal of two consecutive cycles on the inter-chip signal line are spliced together to restore the encoded AXI signal.
[0099] Based on the preset bit width of the encoded AXI signal, determine the channels corresponding to the first AXI signal and the second AXI signal.
[0100] Specifically, if the valid line of the inter-chip signal line in the current cycle goes high, it indicates that the AXI signal of the current cycle and the next cycle need to be spliced. For example, two 50-bit AXI signals can be spliced into a 100-bit AXI signal. That is, the two 50-bit AXI signals are recombined to restore the decoded AXI signal. Then, according to the preset bit width of the encoded AXI signal, the channel corresponding to the AXI signal of the two consecutive cycles is determined.
[0101] Optionally, the first AXI signal and the second AXI signal of two consecutive cycles on the inter-chip signal line are spliced together, including:
[0102] If the valid line on the inter-chip signal line of the current cycle goes high, then the current cycle is determined to be the first cycle, the second cycle is the next cycle, and the first cycle and the second cycle are two consecutive cycles.
[0103] The first AXI signal of the first cycle and the second AXI signal of the second cycle are spliced together.
[0104] In some embodiments, the AXI bus-based inter-chip interconnection method further includes:
[0105] The ready signal controls the normal operation or pause of the AXI signal transmission and reception process.
[0106] Specifically, in the original AXI bus protocol, the ready signal needs to be pulled high together with the valid signal to complete the handshake process and begin signal transmission. However, in this design, the ready signal is not directly transmitted. Instead, after both AXI buses begin normal operation, it is used to control the normal operation or pause of signal transmission and reception. It can be understood that the handshake process in this application is encapsulated. For example, the received valid signal will handshake with its own ready signal; the handshake process in this application converts the ready signal into control signals.
[0107] In some embodiments, combined with Figure 3 As shown, the inter-chip interconnection method based on the AXI bus also includes:
[0108] When the first chip is the master and the second chip is the slave, the master sends an AXI signal to the slave through the first inter-chip signal line a, and the slave sends a feedback signal of the AXI signal to the master through the second inter-chip signal line c.
[0109] When the second chip is the master and the first chip is the slave, the master sends an AXI signal to the slave through the third inter-chip signal line d, and the slave sends a feedback signal of the AXI signal to the master through the fourth inter-chip signal line b.
[0110] The AXI signals include: AXI write signals sent through the write address channel and the write data channel, and AXI read signals sent through the read address channel; the feedback signals of the AXI signals include: AXI write signals sent through the write response channel, and AXI read signals sent through the read data channel.
[0111] The sum of the number of the first inter-chip signal line a and the second inter-chip signal line c is less than 50.
[0112] The sum of the number of signal lines d between the third and fourth plates is less than 50.
[0113] The AXI bus consists of five channels: write address channel aw, write data channel w, write response channel b, read address channel ar, and read data channel r. Each channel transmits data independently, and each channel's signal line is only valid when the corresponding valid signal line is pulled high; otherwise, it can be ignored.
[0114] like Figure 5 As shown, aw represents the write address channel of the AXI bus, and awvalid, awaddr, awlen, ..., awready are the AXI signals of the write address channel aw;
[0115] w represents the write data channel of the AXI bus, and wvalid, wdata, wlast, ..., wready are the AXI signals of the write data channel w;
[0116] b represents the write response channel of the AXI bus, and bvalid, bid, bresp, ..., bready are the AXI signals of the write response channel b of the AXI bus.
[0117] ar represents the read address channel of the AXI bus, and arvalid, araddr, arlen, ..., arready are the AXI signals of the read address channel ar of the AXI bus;
[0118] r represents the read data channel of the AXI bus, and rvalid, rdata, rlast, ..., rready are the AXI signals of the read address channel ar of the AXI bus.
[0119] The source of the valid signal and the source of the ready signal are not the same for each channel of the AXI bus. For example, the master sends the valid signal through the write address channel aw, write data channel w, and read address channel ar, and the slave sends the ready signal accordingly through the write address channel aw, write data channel w, and read address channel ar; the slave sends the valid signal through the write response channel b and read data channel r, and the master sends the ready signal accordingly through the write response channel b and read data channel r.
[0120] The first inter-chip signal line a and the second inter-chip signal line c constitute the first group of signal lines; the number of signal lines in the first group is less than 50.
[0121] The third inter-chip signal line d and the fourth inter-chip signal line b constitute the second group of signal lines; the number of signal lines in the second group is less than 50.
[0122] In this embodiment of the application, the first chip and the second chip are interconnected through two sets of inter-chip signal lines. For AXI signal lines, one set is defined in the input / output direction, while for the AXI bus, one set is defined in the master / slave direction. Since the master of the two sets of inter-chip signal lines is different, they have perfect reciprocity, ensuring that the two sets of inter-chip signal lines can perfectly realize the cross-chip interconnection of the two AXI buses.
[0123] Moreover, the number of inter-chip signal lines used is greatly reduced compared to the bit width of all signals within a set of AXI buses. By sending the AXI signals of each channel separately to the inter-chip signal lines in time, the number of inter-chip signal lines is greatly reduced, making circuit routing much easier. The number of inter-chip signal lines in a set is less than 50, which can take into account the design difficulty of modules / hardware circuits within the chip.
[0124] In addition, since the clock on the inter-chip signal lines is asynchronous with the clock of the AXI bus within each chip, the clock frequency setting on the inter-chip signal lines is more flexible and can be set according to hardware and actual bandwidth requirements.
[0125] In some applications, such as LTE testing, an external CPU is used to control the LTE PHY module inside the FPGA. This ensures both the high-speed operation of the CPU and meets the high-speed iteration requirements of the LTE PHY module.
[0126] Figure 6 A schematic diagram of an experimental test structure in which the CPU and SRAM are placed on different FPGAs, as provided in an embodiment of this application; Figure 7 for Figure 6 The diagram illustrates the behavior of the AXI bus in FPGA2 by initiating a write command through the CPU inside FPGA1. Figure 8 for Figure 6 The diagram illustrates how a read command is initiated by the CPU inside FPGA1 to observe the behavior of the AXI bus in FPGA2.
[0127] See Figure 6 The experimental setup shown is a schematic diagram. Read and write commands are initiated by the CPU inside FPGA1 to observe the behavior of the AXI bus within FPGA2. The CPU inside FPGA1 is the master, and the SRAM inside FPGA2 is the slave.
[0128] It should be noted that, Figure 7 and Figure 8 The lines starting with "pad" are signal lines, those ending with "_m" are the master (host) side AXI bus signals, and those ending with "_s" are the slave (slave) side AXI bus signals.
[0129] See Figure 7 For example, when the CPU inside FPGA1 initiates a write operation, although there is a delay of several cycles, the AXI signal is transmitted from the master to the slave. Figure 7 This section only displays some key signals and signal lines within the AXI bus write channel.
[0130] See Figure 8For example, when the CPU inside FPGA1 initiates a read operation, the read address (araddr) signal line is transmitted from the master to the slave. After the slave reads the data (rdata), it is then transmitted back to the master. Figure 8 This only shows some key signals and signal lines within the AXI bus read channel.
[0131] Based on the same inventive concept, participated Figure 3 As shown, this application embodiment provides an inter-chip interconnection system based on the AXI bus, including: a first chip, a second chip, and a verification module; the second chip is disposed inside the verification module, and the first chip is connected to the second chip disposed inside the verification module through an inter-chip signal line; the inter-chip signal line is a signal line between the first chip and the verification module;
[0132] The first chip and the second chip perform the steps of the inter-chip interconnection method based on the AXI bus provided in any of the above embodiments.
[0133] The inter-chip interconnection system based on the AXI bus provided in this application can be implemented and its effects can be referred to the foregoing embodiments, and will not be repeated here.
[0134] Based on the same inventive concept, embodiments of this application provide a computer program product, including a computer program / instructions, which, when executed by a processor, implement the steps of the inter-chip interconnection method based on the AXI bus provided in any of the above embodiments.
[0135] The computer program product provided in this application can be implemented and its effects can be referred to the foregoing embodiments, and will not be repeated here.
[0136] The above embodiments are merely exemplary embodiments of this application and are not intended to limit this application. The scope of protection of this application is defined by the claims. Those skilled in the art can make various modifications or equivalent substitutions to this application within its substance and scope of protection, and such modifications or equivalent substitutions should also be considered to fall within the scope of protection of this application.
Claims
1. A chip interconnection method based on AXI bus, characterized in that, An inter-chip interconnect system based on the AXI bus is provided, the system comprising a first chip, a second chip, and a verification module; the second chip is disposed within the verification module, and the first chip is connected to the second chip disposed within the verification module via an inter-chip signal line; the inter-chip signal line is a signal line between the first chip and the verification module; the method includes: The process of one chip sending an AXI signal to another chip includes: One of the chips sends AXI signals through each channel of the AXI bus in a preset time sequence and buffers them into the asynchronous FIFO corresponding to each channel; After the AXI signal comes out from its respective asynchronous FIFO, the AXI signal of the asynchronous FIFO corresponding to each channel is read, and the preset bit width of the AXI signal of each channel is encoded. The encoded AXI signals of each channel are sent to the inter-chip signal line in a time-division manner; the AXI signal of each channel occupies the inter-chip signal line at different times.
2. The method according to claim 1, characterized in that, The encoded AXI signals of each channel are sequentially sent to the inter-chip signal lines, including: Each channel's AXI signal after encoding is divided into a first AXI signal and a second AXI signal; the first AXI signal and the second AXI signal are AXI signals of the same channel; In the first cycle, the first AXI signal is sent to the inter-chip signal line; In the second cycle, the second AXI signal is sent to the inter-chip signal line; the first cycle and the second cycle are two consecutive cycles.
3. The method according to claim 2, characterized in that, The encoded AXI signal of each channel is divided into a first AXI signal and a second AXI signal, including: Based on the bit width of the encoded AXI signal of each channel, the encoded AXI signal of each channel is divided into a first AXI signal and a second AXI signal with the same bit width.
4. The method according to claim 2, characterized in that, Also includes: The process by which another chip receives an AXI signal sent by one of the chips includes: Another chip receives a clock signal from the inter-chip signal line and samples an AXI signal from the inter-chip signal line according to the clock signal; The sampled AXI signal is decoded to restore the encoded AXI signal, and the channel corresponding to the sampled AXI signal is determined according to the preset bit width of the encoded AXI signal. The AXI signal of the determined channel is buffered into the corresponding asynchronous FIFO. After the AXI signal comes out of its respective asynchronous FIFO, it is transmitted to the corresponding channel.
5. The method according to claim 4, characterized in that, The sampled AXI signal is decoded to restore the encoded AXI signal, and the channel corresponding to the sampled AXI signal is determined according to the preset bit width of the encoded AXI signal, including: The first AXI signal and the second AXI signal of two consecutive cycles on the inter-chip signal line are spliced together to restore the encoded AXI signal; Based on the preset bit width of the encoded AXI signal, determine the channels corresponding to the first AXI signal and the second AXI signal.
6. The method according to claim 5, characterized in that, The first AXI signal and the second AXI signal of two consecutive cycles on the inter-chip signal line are spliced together, including: If the valid line on the inter-chip signal line of the current cycle goes high, then the current cycle is determined to be the first cycle, the second cycle is the next cycle, and the first cycle and the second cycle are two consecutive cycles. The first AXI signal of the first cycle and the second AXI signal of the second cycle are spliced together.
7. The method according to any one of claims 1 to 6, characterized in that, Also includes: The ready signal controls the normal operation or pause of the AXI signal transmission and reception process.
8. The method according to any one of claims 1 to 6, characterized in that, Also includes: When the first chip is the master and the second chip is the slave, the master sends an AXI signal to the slave through the first inter-chip signal line, and the slave sends a feedback signal of the AXI signal to the master through the second inter-chip signal line. When the second chip is the master and the first chip is the slave, the master sends an AXI signal to the slave through the third inter-chip signal line, and the slave sends a feedback signal of the AXI signal to the master through the fourth inter-chip signal line. The AXI signals include: AXI write signals sent through the write address channel and the write data channel, and AXI read signals sent through the read address channel; the feedback signals of the AXI signals include: AXI write signals sent through the write response channel, and AXI read signals sent through the read data channel. The sum of the number of the first inter-chip signal lines and the second inter-chip signal lines is less than 50. The total number of the third inter-piece signal lines and the fourth inter-piece signal lines is less than 50.
9. An inter-chip interconnection system based on the AXI bus, characterized in that, include: The system comprises a first chip, a second chip, and a verification module; the second chip is disposed inside the verification module, and the first chip is connected to the second chip disposed inside the verification module via an inter-chip signal line; the inter-chip signal line is the signal line between the first chip and the verification module. The first chip and the second chip perform the steps of the inter-chip interconnection method based on the AXI bus as described in any one of claims 1 to 8.
10. A computer program product comprising a computer program / instructions that, when executed by a processor, implement the steps of the inter-chip interconnection method based on the AXI bus as described in any one of claims 1 to 8.