Inter-core interconnect system and graphics card device including the same

Abstract

The present disclosure relates to an inter- core interconnect system and a graphics card apparatus including the same. The inter- core interconnect system has at least two cores; and a crossbar matrix bus for connecting the at least two cores, wherein each of the at least two cores includes an on-chip inter- core interconnect interface for inter- core interconnect, the on-chip inter- core interconnect interface having an interface conversion module, wherein the on-chip inter- core interconnect interface converts first data and a first address into a first packet having a first custom packet format using the interface conversion module and transmits the first data and the first address in the first packet onto the crossbar matrix bus, and / or the on-chip inter- core interconnect interface receives a second packet having a second custom packet format from the crossbar matrix bus and converts the second packet into second data and a second address using the interface conversion module.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an inter-core interconnection system and a graphics card device comprising the inter-core interconnection system. Accordingly, the present disclosure also relates to a write operation method for inter-core interconnection and a read operation method for inter-core interconnection. BACKGROUND

[0002] In the field of chip design, inter-core interconnection, especially multi-core interconnection, generally adopts a standard AXI (Advanced eXtensible Interface) bus protocol. The AXI bus protocol is the most important part of the AMBA 3.0 protocol proposed by ARM (Advanced RISC Machines Ltd.), and is an on-chip bus oriented to high performance, high bandwidth and low latency. Its address / control and data phases are separated, supports unaligned data transmission, and only needs the first address in burst transmission. Meanwhile, it supports separate read / write data channels, significant transmission access and out-of-order access, and is easier to achieve timing convergence. AXI is a new high-performance protocol in AMBA (Advanced Microcontroller Bus Architecture). AXI technology enriches the existing AMBA standard content, and meets the needs of super-high-performance and complex SoC (System-on-a-chip) design. The AXI features include: unidirectional channel architecture. Information flow is transmitted in a single direction. Independent data and address channels. The data and address channels are separated, and each channel can be optimized independently. The timing channel can be controlled as needed, the clock frequency can be raised to the highest, and the delay can be reduced to the lowest.

[0003] In the field of chip design, inter-core interconnection, especially multi-core interconnection design, generally adopts a crossbar bus form of wiring. Multiple cores are connected to each other in a star topology through a crossbar bus of related technology.

[0004] The related technology has the following disadvantages: in the case of using a standard AXI3 (AMBA 3.0) bus protocol, the core uses a direct routing method to send data and addresses using the crossbar bus of related technology. Although the efficiency is high, the bus width is large, and the number of lines required by a single core exceeds 220. In the case of multiple cores, the number of lines required will be multiplied. The wiring between the cores will be connected from the positions of different cores to the positions of the crossbar of related technology in the chip physical implementation stage, which will occupy a large number of line resources, and will have a great pressure on the chip back-end layout and wiring, and the timing is difficult to converge and the area is wasted. SUMMARY

[0005] The task based on the present disclosure is to solve the efficiency and area problem of inter-core interconnection, especially multi-core interconnection, in a data packet exchange manner, to reduce the required bus number as much as possible on the basis of maintaining bus efficiency, and to implement the back-end chip.

[0006] According to a first aspect of the present disclosure, in order to solve the above problems, an inter-core interconnection system in a data packet exchange manner is provided, which can have at least two cores, and a crossbar matrix bus for connecting the at least two cores, wherein each of the at least two cores comprises an on-chip inter-core interconnection interface for inter-core interconnection, and the on-chip inter-core interconnection interface has an interface conversion module, wherein the on-chip inter-core interconnection interface converts first data and a first address into a first data packet having a first custom data packet format by using the interface conversion module, and transmits the first data and the first address to the crossbar matrix bus in the first data packet, and / or the on-chip inter-core interconnection interface receives a second data packet having a second custom data packet format from the crossbar matrix bus, and converts the second data packet into second data and a second address by using the interface conversion module.

[0007] The inter-core interconnection system of the present disclosure has the advantage that by equipping the core with an on-chip inter-core interconnection interface with an interface conversion module, and by replacing the crossbar matrix bus of the related art in a direct routing manner with the crossbar matrix bus of the present disclosure in a data packet exchange routing manner, the data and the address can be transmitted in a custom data packet format. In this way, the inter-core interconnection system of the present disclosure can avoid parallel transmission of these data and addresses while maintaining bus efficiency, thereby greatly reducing the required channel width, and further significantly reducing the required bus number, which can be reduced to the number of bytes corresponding to the data packet at most. Compared with the conventional AXI3 bus protocol, this can greatly reduce the number of lines, thereby facilitating back-end layout and wiring.

[0008] In some embodiments, the on-chip inter-core interconnection interface can comprise a FIFO (First In First Out) buffer for buffering the first data packet and / or the second data packet according to the depth of the FIFO buffer.

[0009] In some embodiments, the crossbar matrix bus can have an ID routing function for routing according to the target ID of the first data packet and / or the second data packet.

[0010] In some embodiments, the first data packet and / or the second data packet can contain at least one of the following packet types:

[0011] A write request packet for indicating a write request;

[0012] a write data packet for containing data transmitted for the write request;

[0013] a write return packet for confirming whether a core as a receiver of the data successfully receives the data transmitted for the write request;

[0014] a read request packet for indicating a read request;

[0015] a read data packet for containing data transmitted for the read request; and

[0016] a read return packet for confirming whether a core as a receiver of the data successfully receives the data transmitted for the read request.

[0017] In some embodiments, the write request packet, the write data packet, the write return packet, the read request packet, the read data packet and the read return packet can have the same bit number.

[0018] In some embodiments, a bus width of the crossbar matrix bus connected to each of the at least two cores can be related to the bit number.

[0019] In some embodiments, the bit number can correspond to a bus width of the crossbar matrix bus connected to each of the at least two cores.

[0020] In some embodiments, the bus width can be 48 lines.

[0021] In some embodiments, one of the at least two cores can send one of the write request packet, the write data packet, the write return packet, the read request packet, the read data packet and the read return packet to the crossbar matrix bus in multiple cycles using the on-chip inter-core interconnect interface, wherein a bus width of the crossbar matrix bus connected to each of the at least two cores is related to a bit number of the data packet sent in each cycle.

[0022] In some embodiments, the write request packet can comprise a source ID field for indicating a source ID of the write request packet and a destination ID field for indicating a destination ID of the write request packet.

[0023] In some embodiments, the write request packet can further comprise a type field for indicating a type of data packet, a length field for indicating a number of write data packets belonging to the write request packet, a write request packet ID field for indicating an ID of the write request packet, and an address field for indicating a write address of a write request corresponding to the write request packet.

[0024] In some embodiments, the write data packet can include a source ID field for indicating a source ID of the write data packet, and a destination ID field for indicating a destination ID of the write data packet.

[0025] In some embodiments, the write data packet can further include a type field for indicating a packet type, a write data start bit for indicating a start of a write operation, i.e., a first write data packet of a write request corresponding to the write request packet, a write data end bit for indicating an end of the write operation, i.e., a last write data packet of the write request corresponding to the write request packet, and a data field containing at least a portion of data to be transmitted for performing the write operation, wherein the data is sequentially transmitted through all write data packets belonging to the write request packet of the write operation.

[0026] In some embodiments, the write data packet can further include a mask field for indicating whether the data field of the write data packet is valid, and a reserved field or reserved bit for indicating a field or bit not used in the write data packet.

[0027] In some embodiments, the write return packet can include a write request packet ID field for indicating an ID of a write request packet corresponding to the write return packet, and a destination ID field for indicating a destination ID of the write return packet.

[0028] In some embodiments, the write return packet can further include a type field for indicating a packet type, a count field for indicating a number of write data packets actually received by a core as a receiver of the data for the write request packet, and a receive success bit for indicating whether the data transmitted by a core as a transmitter of the data for the write request packet is successfully received by the core as the receiver of the data.

[0029] In some embodiments, the read request packet can include a source ID field for indicating a source ID of the read request packet, and a destination ID field for indicating a destination ID of the read request packet.

[0030] In some embodiments, the read request packet can further include a type field for indicating a packet type, a length field for indicating a number of read data packets requested by the read request packet, a read request packet ID field for indicating an ID of the read request packet, and an address field for indicating a read address of a read request corresponding to the read request packet.

[0031] In some embodiments, the read data packet can include a source ID field for indicating a source ID of the read data packet, and a destination ID field for indicating a destination ID of the read data packet.

[0032] In some embodiments, the read data packet can further include: a type field, configured to indicate a type of the data packet; a read data packet ID field, configured to indicate an ID of the read data packet; and a data field, configured to contain at least a part of data to be received for performing a read operation, wherein the data is sequentially received through all read data packets belonging to a read request packet of the read operation.

[0033] In some embodiments, the read return packet can include: a read request packet ID field, configured to indicate an ID of a read request packet corresponding to the read return packet; and a target ID field, configured to indicate a target ID of the read return packet.

[0034] In some embodiments, the read return packet can further include: a type field, configured to indicate a type of the data packet; a count field, configured to indicate a number of read data packets actually received by a core as a receiver of the data for the read request packet; and a reception success bit, configured to indicate whether the core as the receiver of the data successfully receives the data transmitted by a core as a sender of the data for the read request packet.

[0035] According to a second aspect of the present disclosure, in order to solve the above problems, a graphics card device is provided, which can include the inter-core interconnection system according to the first aspect of the present disclosure.

[0036] According to a third aspect of the present disclosure, in order to solve the above problems, a write operation method for inter-core interconnection is provided, wherein the write operation method can be executed in the inter-core interconnection system according to the first aspect of the present disclosure,

[0037] wherein the write operation method is designed for a write operation from a first core of the at least two cores to a second core of the at least two cores, and the write operation method can include:

[0038] sending, by an on-chip inter-core interconnection interface of the first core, a write request packet configured to indicate a write request;

[0039] sending, by the on-chip inter-core interconnection interface of the first core, one or more write data packets corresponding to the write request packet, the write data packets being configured to contain data transmitted by the first core for the write request.

[0040] In some embodiments, the write request packet and the one or more write data packets corresponding to the write request packet are sequentially sent in order by the on-chip inter-core interconnection interface of the first core; and / or

[0041] sending, by the on-chip inter-core interconnection interface of the first core, a plurality of write request packets first, and then sending one or more write data packets corresponding to the plurality of write request packets respectively; and / or

[0042] crossingly sending, by an on-chip interconnect interface of the first core, a plurality of write request packets and one or more write data packets corresponding to the plurality of write request packets respectively,

[0043] wherein the order of the plurality of write request packets is consistent with the order of the one or more write data packets corresponding to the plurality of write request packets respectively.

[0044] In some embodiments, the write operation method can further comprise converting, by an interface conversion module of the on-chip interconnect interface of the first core, the first data and the first address into the write request packets and the write data packets.

[0045] In some embodiments, the write operation method can further comprise receiving, by the on-chip interconnect interface of the first core, a write return packet configured for confirming whether the second core successfully receives the data transmitted for the write request.

[0046] In some embodiments, the write operation method can further comprise converting, by an interface conversion module of the on-chip interconnect interface of the first core, the write return packet into the second data and the second address.

[0047] According to a fourth aspect of the present disclosure, in order to solve the above problems, a read operation method for inter-core interconnect is provided, wherein the read operation method can be executed in the inter-core interconnect system according to the first aspect of the present disclosure,

[0048] wherein the read operation method is designed for a read operation from a first core in the at least two cores to a second core in the at least two cores, and the read operation method can comprise:

[0049] sending, by an on-chip interconnect interface of the first core, a read request packet configured for indicating a read request;

[0050] receiving, by the on-chip interconnect interface of the first core, one or more read data packets corresponding to the read request packet, the read data packets being configured for containing data transmitted by the second core for the read request.

[0051] In some embodiments, the read operation method can further comprise sending, by the on-chip interconnect interface of the first core, a read return packet configured for confirming whether the first core successfully receives the data transmitted by the second core for the read request.

[0052] In some embodiments, the read operation method can further include converting, by an interface conversion module of the on-chip NIC interface of the first core, the first data and the first address into the read request packet and the read return packet.

[0053] In some embodiments, the read operation method can further include converting, by an interface conversion module of the on-chip NIC interface of the first core, the read data packet into the second data and the second address.

[0054] The features, details and advantages described for the on-chip NIC interface also correspondingly apply to the graphics card device, the write operation method and the read operation method.

[0055] It is readily understood that the features mentioned above and subsequently set forth can be used not only in the combinations indicated, but also in other combinations or alone, without departing from the scope of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0056] Subsequently, the present disclosure is set forth in greater detail according to embodiments shown in the attached drawings.

[0057] Wherein:

[0058] Figure 1 A schematic diagram of an inter-core interconnect system in the form of a crossbar matrix bus according to the related art is shown;

[0059] Figure 2 A schematic diagram of an inter-core interconnect system in the form of a crossbar matrix bus according to the present disclosure employing a packet-switched approach is shown;

[0060] Figure 3 A schematic diagram of an on-chip NIC interface according to one embodiment of the present disclosure for inter-core interconnect in the form of a crossbar matrix bus employing a packet-switched approach according to the present disclosure is shown;

[0061] Figure 4 A schematic diagram of an on-chip NIC interface according to another embodiment of the present disclosure for inter-core interconnect in the form of a crossbar matrix bus employing a packet-switched approach according to the present disclosure is shown;

[0062] Figure 5 A schematic flow diagram of a method for write operation for inter-core interconnect according to the present disclosure is shown; and

[0063] Figure 6 A schematic flow diagram of a method for read operation for inter-core interconnect according to the present disclosure is shown. DETAILED DESCRIPTION

[0064] Figure 1A schematic diagram of an interconnect system in the form of a crossbar matrix bus for interconnects between cores according to the related art is shown. In Figure 1 the middle, a crossbar matrix is exemplarily connected to 8 cores, namely core 0 to core 7. These cores are connected to each other in a star topology by a crossbar matrix bus according to the related art. In case of a standard AXI3 bus protocol, core 0 to core 7 transmit data and addresses using a direct routing approach with the crossbar matrix bus according to the related art, resulting in a large bus width, with more than 220 lines required for a single core (indicated by bold double arrows in Figure 1 ).

[0065] Figure 2 A schematic diagram of an interconnect system in the form of a crossbar matrix bus for interconnects between cores according to the present disclosure is shown. In Figure 2 the middle, a crossbar matrix according to the present disclosure in the form of a packet switch is exemplarily connected to 8 cores, namely core 0 to core 7. The number of cores can be adjusted according to the specific case. The crossbar matrix can perform a data transfer between any two cores.

[0066] These cores 0 to 7 can each comprise an on-chip interconnect interface 10 to 17 for interconnects between cores, which can have an interface conversion module. The on-chip interconnect interface converts a first data and a first address into a first data packet having a first custom data packet format using the interface conversion module and transmits the first data and the first address as the first data packet onto the crossbar matrix bus, and / or the on-chip interconnect interface receives a second data packet having a second custom data packet format from the crossbar matrix bus and converts the second data packet into a second data and a second address using the interface conversion module. The first address can for example comprise an address of a core as a receiver and additionally an address of a core as a sender. The second address can likewise for example comprise an address of a core as a receiver and additionally an address of a core as a sender. The interconnect system between cores according to the present disclosure can be part of a graphics card device.

[0067] By equipping the cores with on-chip interconnect interfaces having an interface conversion module and by replacing the crossbar matrix bus according to the related art in the form of a direct routing approach with a crossbar matrix bus according to the present disclosure in the form of a packet switch routing approach, data and addresses can be transmitted in the form of a custom data packet format. In this way, the interconnect system between cores according to the present disclosure can avoid parallel transmission of the data while maintaining the bus efficiency, resulting in a significantly reduced channel width and thus a significantly reduced number of buses required (in Figure 2The non-bold double arrow (indicated by the non-bold double arrow) can reduce the data packet to a maximum of the number of bytes corresponding to the data packet.

[0068] In some embodiments, the crossbar matrix bus can have an ID routing function for routing according to a target ID of the first data packet and / or the second data packet. Thus, instead of the first and / or second address described above, the target ID of the data packet itself can be used for routing.

[0069] In some embodiments, the first data packet and / or the second data packet can comprise at least one of the following data packet types:

[0070] A write request packet AW for indicating a write request;

[0071] A write data packet W for containing data transmitted for the write request;

[0072] A write return packet BW for confirming whether a core as a receiver of the data successfully receives the data transmitted for the write request;

[0073] A read request packet AR for indicating a read request;

[0074] A read data packet R for containing data transmitted for the read request; and

[0075] A read return packet BR for confirming whether a core as a receiver of the data successfully receives the data transmitted for the read request.

[0076] In some embodiments, the write request packet AW, the write data packet W, the write return packet BW, the read request packet AR, the read data packet R, and the read return packet BR can have the same number of bits or bytes. In some embodiments, the bus width of the crossbar matrix bus connected to each of the core 0 to core 7 according to the present disclosure can be related to the number of bits or bytes. In particular, the number of bits or bytes can correspond to the bus width of the crossbar matrix bus connected to each of the core 0 to core 7. Thus, the bus width of the crossbar matrix bus connected to each of the core 0 to core 7 is the same. In this way, there is no waste of individual buses due to uneven bus width, while ensuring the maximum efficiency of bus usage.

[0077] In some embodiments, the above-mentioned data packet types can each have 6 bytes, i.e. 48 bits, by way of example. It is also conceivable that these data packet types can each have another number of bytes, which can be adjusted according to the specific circumstances without departing from the scope of protection of the present disclosure. In this case, the bus width can be 48 lines. Compared to the number of lines required for a single core in the related art, which is more than 220, the bus width of the inter-core communication system of the present disclosure can be significantly reduced.

[0078] In some embodiments, further, each of the cores 0 to 7 can send one of the write request packet AW, the write data packet W, the write return packet BW, the read request packet AR, the read data packet R and the read return packet BR in multiple cycles respectively using its on-chip inter-core interconnect interface onto the crossbar matrix bus, wherein the crossbar matrix bus has a bus width associated with each core and the number of bits of the data packet sent in each cycle. Thereby, by setting multiple cycles for sending one data packet, the bus width can be further reduced.

[0079] In some embodiments, the custom format of the write request packet AW can be, for example:

[0080]

[0081] wherein the left column indicates the number of bits corresponding to the field in the packet, for example, [19:0] indicates from the 0th bit to the 19th bit, a total of 20 bits. The right column indicates the meaning of the corresponding field. The other tables below are constructed in the same way, and are not described here.

[0082] The write request packet AW can include a source ID field src id for indicating the source ID of the write request packet, and a destination ID field dst id for indicating the destination ID of the write request packet. Thereby, the crossbar matrix bus using the packet switching mode according to the present disclosure can use the destination ID field dst id to route the write request packet AW.

[0083] In the current embodiment, for the write request packet AW, 3 bits, for example, [35:33], can be used as the source ID field src id. Similarly, 3 bits, for example, [32:30], can be used as the destination ID field dst id. Thereby, the 3-bit width can support at most 2 3 = 8 cores for inter-core interconnection.

[0084] The write request packet AW can further include a type field type for indicating the type of the packet, a length field length for indicating the number of write data packets belonging to the write request packet, a write request packet ID field aw id for indicating the ID of the write request packet, and an address field addr for indicating the write address of the write request corresponding to the write request packet.

[0085] In the current embodiment, there can be 6 types of data packets (write request packet AW, write data packet W, write return packet BW, read request packet AR, read data packet R, and read return packet BR). Thus, for example, 3 bits, e.g., [47:45], can be used to represent the type field type. The encoding format of the type field type can be, for example:

[0086] Encoding Meaning 000 AW 001 W 010 AR 011 R 100 BW 101 BR

[0087] Thus, for the write request packet AW, the encoding of its type field type can be, for example, 000.

[0088] Further, in the current embodiment, for the write request packet AW, the length field length can be, for example, 9 bits, e.g., [44:36], which indicates that one write request packet can correspond to at most 2 9 = 512 write data packets. In the current embodiment, the write request ID field aw_id can be, for example, 10 bits, e.g., [29:20], which indicates that in one write operation, a total of at most 2 10 = 1024 write request packets (i.e., outstanding number = 1024, i.e., the number of write request packets that have been issued but not yet completed or responded). In the current embodiment, the address field addr can be, for example, 20 bits, e.g., [19:0]. Thus, a write address up to 20 bits can be used.

[0089] It is also conceivable that the above fields have other bit numbers, which can be adjusted according to specific circumstances. Similarly, the bit numbers of the fields in other data packet types according to the present disclosure can also be adjusted according to specific circumstances without departing from the scope of protection of the present disclosure.

[0090] In some embodiments, the custom format of the write data packet W can be, for example:

[0091]

[0092] The write data packet W can include a source ID field src_id for indicating the source ID of the write data packet, and a destination ID field dst_id for indicating the destination ID of the write data packet. Similarly, the crossbar matrix bus according to the present disclosure using the packet exchange manner can use the destination ID field dst_id to route the write data packet W.

[0093] In the current embodiment, for the write data packet W, 3 bits, e.g., [38:36], can be used as the source ID field src_id. Similarly, 3 bits, e.g., [44:42], can be used as the destination ID field dst_id. Thus, the bit width of 3 bits can support at most 23 = 8 cores for inter-core interconnection.

[0094] The write data packet W can further comprise a type field type for indicating a packet type, a write data start bit start for indicating a start of a write operation, i.e. a first write data packet of a write request corresponding to the write request packet, a write data end bit end for indicating an end of the write operation, i.e. a last write data packet of the write request corresponding to the write request packet, and a data field data containing at least a part of data to be transmitted for performing the write operation, wherein the data is transmitted sequentially by all write data packets belonging to the write request packet of the write operation.

[0095] In the current embodiment, the type field type of the write data packet W can have the same number of bits as the write request packet AW, e.g. 3 bits, e.g. [47:45], with an encoding of e.g. 001. The write data start bit start can be e.g. 1 bit, e.g.

[40] . The write data end bit end can also be e.g. 1 bit, e.g.

[39] . The data field data can be e.g. 32 bits, e.g. [31:0], i.e. 4 bytes.

[0096] The write data packet can further comprise a mask field mask for indicating whether the data field data of the write data packet is valid or not, and a reserved field or reserved bit reserved for indicating a field or bit not used in the write data packet.

[0097] In the current embodiment, the mask field mask can be e.g. 4 bits, e.g. [35:32], for the write data packet W. Thereby, for a 4 byte data field data, the detection of a conflict can be more fine-grained at byte granularity using the mask field mask. The reserved field or reserved bit reserved can be e.g. at least 1 bit, e.g.

[41] , which is used to ensure that the size of the respective packet is the same, i.e. in the current case 48 bits (6 bytes), and can also be used for future extension of the write data packet W.

[0098] In further embodiments, if the write data packet W has further byte numbers, the write data packet W can comprise a plurality of reserved bits or a reserved field with a plurality of reserved bits, which can be adapted to the specific case. Likewise, the other packet types according to the present disclosure can comprise suitable reserved bits or reserved fields, especially in case these packet types have further byte numbers, for ensuring that the size of the respective packet is the same and also for future extension of the respective packet, respectively.

[0099] In some embodiments, the custom format of the write back packet BW can be e.g.

[0100]

[0101] The write back packet BW can comprise a write request packet ID field aw_id for indicating the ID of the write request packet corresponding to the write back packet, and a destination ID field dst_id for indicating the destination ID of the write back packet. Thus, the crossbar matrix bus in the data packet exchange mode according to the present disclosure can use the destination ID field dst_id to route the write back packet BW. It is worth noting here that the destination ID field dst_id of the write back packet BW can be the source ID field src_id of the write request packet AW and / or the write data packet W corresponding to the write back packet.

[0102] In the current embodiment, for the write back packet BW, 3 bits, for example [44:42], can be used as the destination ID field dst_id. Thus, the bit width of 3 bits can support at most 2 3 =8 cores for inter-core connection. The write request packet ID field aw_id can be 10 bits, for example [41:32].

[0103] The write back packet BW can further comprise a type field type for indicating the type of the packet, a count field count for indicating the number of write data packets actually received by the core as the receiver of the data for the write request packet, and a reception success bit Success for indicating whether the core as the receiver of the data successfully receives the data transmitted by the core as the sender of the data for the write request packet.

[0104] In the current embodiment, the number of bits of the type field type of the write back packet BW can be the same as that of the write request packet AW and the write data packet W, for example 3 bits, for example [47:45], and the encoding is for example 100. The count field count can be for example 9 bits, for example [9:1], which can count at most 2 9 =512 write data packets. Through the count field count, the write back packet BW can return the number information of the write data packets W actually received. The reception success bit Success can be for example 1 bit, for example [0]. If the number of write data packets W received by the core as the receiver for the corresponding write request of the write request packet AW is consistent with the number of write data packets W contained in the corresponding write request, the reception success is indicated through the reception success bit, otherwise the reception failure is indicated through the reception success bit. Through the reception success bit, it can be determined whether the corresponding write operation is successfully completed. Based on this, the core as the sender can decide whether to re-execute the corresponding write operation.

[0105] Additionally, the write back packet BW can further comprise a reserved field or reserved bits reserved for indicating unused fields or bits in the write back packet.

[0106] In the current embodiment, the reserved field or reserved bits reserved can be at least 22 bits, e.g. [31 : 10], for example, which are used to ensure the size of the corresponding data packet is the same, i.e. in the current case to ensure the data packet is 48 bits (6 bytes), and can also be used for future extension of the write back packet BW.

[0107] In some embodiments, the custom format of the read request packet AR can be, for example:

[0108]

[0109] The read request packet AR can comprise a source ID field src id for indicating the source ID of the read request packet, and a destination ID field dst id for indicating the destination ID of the read request packet. Thereby, the crossbar matrix bus of the present disclosure employing data packet switching can use the destination ID field dst id for routing the read request packet AR.

[0110] In the current embodiment, for the read request packet AR, 3 bits, e.g. [35:33], can be used as the source ID field src id. Similarly, 3 bits, e.g. [32:30], can be used as the destination ID field dst id. Thereby, the 3 bits of bit width can support at most 2 3 =8 cores for inter-core interconnection.

[0111] The read request packet AR can further comprise a type field type for indicating the type of the data packet, a length field length for indicating the number of read data packets requested by the read request packet, a read request packet ID field ar id for indicating the ID of the read request packet, and an address field addr for indicating the read address of the read request corresponding to the read request packet.

[0112] In the current embodiment, the type field type of the read request packet AR can be, for example, 3 bits, e.g. [47:45], which is encoded as 010, for example. The length field length can be, for example, 9 bits, e.g. [44:36], which indicates that at most 2 9 =512 read data packets. In the current embodiment, the read request ID field ar id can be, for example, 10 bits, e.g. [29:20], which indicates that at most 2 10= 1024 read request packets (i.e., outstanding number = 1024). In the current embodiment, the address field addr can be, for example, 20 bits, e.g., [19:0]. Thus, up to 20-bit read addresses can be used.

[0113] In some embodiments, the custom format of the read data packet R can be, for example:

[0114]

[0115] The read data packet R can include a source ID field src id to indicate the source ID of the read data packet, and a destination ID field dst id to indicate the destination ID of the read data packet. Also, the crossbar matrix bus of the packet switching type according to the present disclosure can use the destination ID field dst id to route the read data packet R.

[0116] In the current embodiment, for the read data packet R, 3 bits, e.g., [41:39], can be used as the source ID field src id. Similarly, 3 bits, e.g., [44:42], can be used as the destination ID field dst id. Thus, 3-bit width can support up to 2 3 = 8 cores for inter-core interconnection.

[0117] The read data packet R can also include a type field type to indicate the type of the packet, a read data packet ID field r id to indicate the ID of the read data packet, and a data field data containing at least a portion of the data to be received for performing the read operation, wherein the data is sequentially received by all read data packets belonging to the read request packet of the read operation.

[0118] In the current embodiment, the type field type of the read data packet R can be, for example, the same as the read request packet AR, 3 bits, e.g., [47:45], with an encoding of, for example, 011. The read data packet ID field r id can be, for example, 9 bits, e.g., [38:30], indicating that one read request packet can correspond to up to 2 9 = 512 read data packets. The data field data can be, for example, 30 bits, e.g., [29:0].

[0119] In some embodiments, the custom format of the read return packet BR can be, for example:

[0120]

[0121] The read return packet BR can comprise a read request packet ID field ar_id for indicating an ID of the read request packet corresponding to the read return packet, and a destination ID field dst_id for indicating a destination ID of the read return packet. Thus, the crossbar matrix bus in the data packet exchange manner according to the present disclosure can use the destination ID field dst_id to route the read return packet BR. It is worth noting here that the destination ID field dst_id of the read return packet BR can be the destination ID field dst_id of the read request packet AR corresponding to the read return packet.

[0122] In the current embodiment, for the read return packet BR, 3 bits, for example, [44:42], can be used as the destination ID field dst_id. Thus, the bit width of 3 bits can support at most 2 3 =8 cores for inter-core connection. The read request packet ID field ar_id can be, for example, 10 bits, for example, [41:32].

[0123] The read return packet BR can further comprise a type field type for indicating a data packet type, a count field count for indicating a number of read data packets actually received by the core as the receiver of the data for the read request packet, and a reception success bit Success for indicating whether the core as the receiver of the data successfully receives the data transmitted by the core as the sender of the data for the read request packet.

[0124] In the current embodiment, the number of bits of the type field type of the read return packet BR can be the same as that of the read request packet AR and the read data packet R, for example, 3 bits, for example, [47:45], and the encoding is, for example, 101. The count field count can be, for example, 9 bits, for example, [9:1], which can count at most 2 9 =512 read data packets. Through the count field count, the read return packet BR can return the number information of the read data packets R actually received. The reception success bit Success can be, for example, 1 bit, for example, [0]. Similarly to the reception success bit of the write return packet BW, for example, the reception failure can also be indicated through the reception success bit of the read return packet BR. Through the reception success bit, it can be determined whether the corresponding read operation is successfully completed. Based on this, the core as the sender can decide whether to re-execute the corresponding read operation.

[0125] Additionally, the read return packet BR can further comprise a reserved field or reserved bit reserved for indicating a field or bit not used in the read return packet.

[0126] In the current embodiment, the reserved field or reserved bits reserved, for example, can be at least 22 bits, for example, [31:10], which are used to ensure that the size of the corresponding data packet is the same, i.e., in the current case, to ensure that the data packet is 48 bits (6 bytes), and can also be used for future extension of the read back packet BR.

[0127] The meaning of the write back packet BW and / or the read back packet BR is also that they can serve as the basis for whether to continue sending outstanding requests, where the term "outstanding" refers to the ability of the core to initiate multiple read-write operations without receiving a response, and can also represent the number of bursts of read-write requests of the core. That is, through the received write back packet and / or read back packet, the on-chip inter-core interconnection interface can determine whether it can continue to initiate read-write operations. If it can continue to initiate read-write operations, i.e., can continue to send outstanding requests ("outstanding"), the arbitration mechanism of the bus can be set so that the priority of the address packet is higher than the priority of the data packet, and the priority of the write and / or read back packet channel is the lowest.

[0128] Figure 3 A schematic diagram of an on-chip inter-core interconnection interface for an inter-core interconnection in the form of a crossbar matrix bus employing a data packet exchange manner according to one embodiment of the present disclosure is shown. Here, the on-chip inter-core interconnection interface 10 of core 0 is taken as an example for description when it is acting as a sender of a data packet in performing a write operation and / or a read operation. The other on-chip inter-core interconnection interfaces of the other cores have the same structure and function. The on-chip inter-core interconnection interface 10 is designed to convert a first data and a first address into a data packet and send (i.e., represented by UDI_TX) the data packet to the crossbar matrix bus according to the present disclosure. In the current embodiment, the data packet is 48 bits.

[0129] For a write request packet AW, the on-chip interconnect interface 10 can, for example, use its interface conversion module to convert at least the write address aw_addr of the write request and the ID of the write request packet AW, i.e. aw_id, into the corresponding write request packet AW and send it to the crossbar matrix bus. For a write data packet W, the on-chip interconnect interface 10 can, for example, use its interface conversion module to convert at least the data w_data of the write data packet W into the corresponding write data packet W and send it to the crossbar matrix bus. For a read request packet AR, the on-chip interconnect interface 10 can, for example, use its interface conversion module to convert at least the read address ar_addr of the read request and the ID of the read request packet AR, i.e. ar_id, into the corresponding read request packet AR and send it to the crossbar matrix bus. For a read return packet BR, the on-chip interconnect interface 10 can, for example, use its interface conversion module to convert at least the ID of the read request packet AR, i.e. ar_id, to which the read return packet BR corresponds into the corresponding read return packet AR and send it to the crossbar matrix bus.

[0130] Figure 4 A schematic diagram of an on-chip interconnect interface for an interconnect between cores in the form of a crossbar matrix bus in a data packet switching manner according to another embodiment of the present disclosure is shown. Here, the on-chip interconnect interface 10 of core 0 is described as an example for a receiving side of a data packet when performing a write operation and / or a read operation. The other on-chip interconnect interfaces of the other cores have the same structure and functionality. The on-chip interconnect interface 10 is designed to receive, i.e. indicated by UDI_RX, a data packet from the crossbar matrix bus according to the present disclosure and convert the data packet into a second data and a second address. In the current embodiment, the data packet is 48 bits.

[0131] For a write return packet BW, the on-chip interconnect interface 10 can, for example, receive the write return packet BW from the crossbar matrix bus and use its interface conversion module to convert at least the write return packet into the ID of the write request packet AW, i.e. aw_id, to which the write return packet corresponds. For a read data packet R, the on-chip interconnect interface 10 can, for example, receive the read data packet R from the crossbar matrix bus and use its interface conversion module to convert at least the read data packet R into the data r_data of the write data packet R and the ID of the read data packet, i.e. r_id.

[0132] For a write request packet AW, the on-chip interconnect interface 10 can, for example, use its interface conversion module to convert at least the write address aw_addr of the write request and the ID of the write request packet AW, i.e. aw_id, into the corresponding write request packet AW and send it to the crossbar matrix bus. For a write data packet W, the on-chip interconnect interface 10 can, for example, use its interface conversion module to convert at least the data w_data of the write data packet W into the corresponding write data packet W and send it to the crossbar matrix bus. For a read request packet AR, the on-chip interconnect interface 10 can, for example, use its interface conversion module to convert at least the read address ar_addr of the read request and the ID of the read request packet AR, i.e. ar_id, into the corresponding read request packet AR and send it to the crossbar matrix bus. For a read return packet BR, the on-chip interconnect interface 10 can, for example, use its interface conversion module to convert at least the ID of the read request packet AR, i.e. ar_id, to which the read return packet BR corresponds into the corresponding read return packet AR and send it to the crossbar matrix bus. Figure 3 and Figure 4In an embodiment of the on-chip interconnect interface 10 as shown in Fig. 1 1, the on-chip interconnect interface 10 can comprise, for example, a FIFO buffer for the interface conversion module to resolve data latency due to arbitration, where arbitration includes not only arbitration at the interface conversion module but also arbitration in the topology of the crossbar matrix bus. The FIFO buffer can have, for example, the same buffer depth fifo_depth for each of the above custom packet types, or different buffer depths fifo_depth.

[0133] In an embodiment of the on-chip interconnect interface 10 as shown in Fig. 1 1, the buffer depth of the respective FIFO buffer is indicated. The buffer depth of the FIFO buffer for the write request packet AW, the read request packet AR and the read return packet BR can be, for example, fifo_depth = 8 bit each. The buffer depth of the FIFO buffer for the write data packet W can be, for example, fifo_depth = 32 bit. Other buffer depths of the FIFO buffer for the respective packets are also possible. Figure 3 In an embodiment of the on-chip interconnect interface 10 as shown in Fig. 1 1, the buffer depth of the respective FIFO buffer is indicated. The buffer depth of the FIFO buffer for the write request packet AW, the read request packet AR and the read return packet BR can be, for example, fifo_depth = 8 bit each. The buffer depth of the FIFO buffer for the write data packet W can be, for example, fifo_depth = 32 bit. Other buffer depths of the FIFO buffer for the respective packets are also possible.

[0134] Figure 4 In an embodiment of the on-chip interconnect interface 10 as shown in Fig. 1 1, the buffer depth of the respective FIFO buffer is indicated. The buffer depth of the FIFO buffer for the read data packet R can be, for example, fifo_depth = 32 bit. The buffer depth of the FIFO buffer for the write return packet BW can be, for example, fifo_depth = 8 bit. Other buffer depths of the FIFO buffer for the respective packets are also possible.

[0135] The buffer depth of the FIFO buffer generally indicates the backpressure resistance of the overall interconnect bus. Backpressure means that the receiving end informs the sending end (in the current example: the core) to stop sending data. Since the receiving end of the data packet (in the current example: the other core) can temporarily be unable to receive the data packet due to a special situation, this scenario packet can be temporarily stored in the FIFO buffer, so as not to directly backpressure the sending end and not to affect the normal work of the sending end. Generally, the number of data is greater than the number of requests, so the FIFO buffer for buffering data is larger than the FIFO buffer for buffering requests, and the specific value is determined according to different scenarios, and the meaning is to reduce the backpressure on the sending end with as few resources as possible.

[0136] Figure 5 A schematic flow chart of a method for a write operation of an interconnect between cores according to the present disclosure is shown. The write operation method can be performed, for example, in an interconnect system between cores according to the present disclosure. The write operation method can be designed, for example, for a write operation of a first core of at least two cores of the interconnect system to a second core of the at least two cores. The write operation method can comprise, for example, the following steps: ​

[0137] Step 601 : sending a write request packet AW through the on-chip interconnect interface of the first core, the write request packet being configured to indicate a write request;

[0138] Step 602: sending one or more write data packets W corresponding to the write request packet AW through the on-chip interconnect interface of the first core, the write data packets being configured to contain data transmitted by the first core for the write request.

[0139] Additionally, the write operation method may, for example, further comprise in step 601 : converting respective data and addresses into the write request packet by an interface conversion module of the on-chip interconnect interface of the first core. Likewise, the write operation method may, for example, further comprise in step 602: converting respective data and addresses into the write data packet by an interface conversion module of the on-chip interconnect interface of the first core.

[0140] In step 601, the sent write request packet AW of the first core may, for example, be designed to indicate the source and destination of the write request while telling the second core how much data is to be written. In step 602, each write data packet W may, for example, contain the source and destination ID. Each write data packet W may, for example, contain a bit or field indicating whether the write data packet is the first write data packet and / or the last write data packet of the corresponding write request.

[0141] In embodiments of the method, the write request packet and the one or more write data packets belonging to the write request packet are sent in sequence through the on-chip interconnect interface. Alternatively or additionally, a plurality of write request packets can be sent first and the one or more write data packets belonging to the plurality of write request packets can be sent subsequently, wherein the order of the plurality of write request packets is identical to the order of the one or more write data packets belonging to the plurality of write request packets. Alternatively or additionally, a plurality of write request packets and the one or more write data packets belonging to the plurality of write request packets can be sent interleaved, wherein the order of the plurality of write request packets is identical to the order of the one or more write data packets belonging to the plurality of write request packets.

[0142] Additionally, the write operation method may, for example, further comprise:

[0143] Step 603: receiving a write back packet BW from the second core through the on-chip interconnect interface of the first core, the write back packet being configured to acknowledge whether the data transmitted for the write request has been successfully received by the second core.

[0144] Additionally, the write operation method may, for example, further comprise in step 603: converting the write back packet BW into respective data and addresses by an interface conversion module of the on-chip interconnect interface of the first core.

[0145] For a write back packet BW from the second core, the second core determines the origin of the data packet from the source ID field src id of the write request packet AW and starts counting. When receiving the write data packet W with the write data end bit end, the number of write data packets W received in total is compared with the number of write data packets W contained in the corresponding write request. If both numbers are identical, the reception is successful, which is indicated by the reception success bit. If the numbers are not identical, the reception is unsuccessful, which is indicated by the reception success bit. The number of write data packets W actually received is attached as the count field in the write back packet BW. The first core performing the write operation, in particular the on-chip inter-core interface of the first core, can decide whether to re-perform the corresponding write operation.

[0146] Figure 6 A schematic flow chart of a method for a read operation of an inter-core interconnect according to the present disclosure is shown. The read operation method may, for example, be performed in an inter-core interconnect system according to the present disclosure. The read operation method may, for example, be designed for a read operation of a first core of at least two cores of the inter-core interconnect system to a second core of the at least two cores. The read operation method may, for example, comprise the following steps:

[0147] Step 701 : sending a read request packet AR by an on-chip inter-core interconnect interface of the first core, the read request packet being configured for indicating a read request;

[0148] Step 702: receiving one or more read data packets R corresponding to the read request packet AR by the on-chip inter-core interconnect interface of the first core, the read data packets being configured for containing data transmitted by the second core for the read request.

[0149] Additionally, the read operation method may, for example, further comprise in step 701 : converting the respective data and address to the read request packet AR by an interface conversion module of the on-chip inter-core interconnect interface of the first core. Likewise, the read operation method may, for example, further comprise in step 702: converting the respective data and address to the read back packet R by the interface conversion module of the on-chip inter-core interconnect interface of the first core.

[0150] Additionally, the read operation method may, for example, further comprise:

[0151] Step 703: sending a read back packet BR by the on-chip inter-core interconnect interface of the first core, the read back packet being configured for acknowledging whether the first core successfully received the data transmitted by the second core for the read request.

[0152] Additionally, the read operation method may, for example, further comprise in step 703: converting the read back packet BR to the respective data and address by the interface conversion module of the on-chip inter-core interconnect interface of the first core.

[0153] Similarly to Figure 5the write operation method in Figure 6 In the read operation method shown in Fig. 6, for the write return packet BW sent by the first core, the number of read data packets R received for the corresponding read request can be compared with the number of read data packets R requested in the length field of the read request packet AR, for example by the on-chip inter-core interface of the first core, and if they are identical, the reception is successful, and if not, the reception is unsuccessful, indicated by the reception success bit. The number of read data packets R actually received is attached as additional information in the count field of the read return packet BR. The first core performing the read operation, in particular the on-chip inter-core interface of the first core, can decide whether to re-perform the corresponding read operation.

[0154] By the above embodiments, since data and addresses are transmitted in the form of data packet exchange by custom data packets, the number of buses required can be significantly reduced, while the form of data packets is more flexible. Alternatively or additionally, if necessary, a data packet can also be sent in multiple cycles, so as to further reduce the bus width.

[0155] The disclosure is not limited to the embodiments described here and the aspects emphasized therein. Rather, a number of variants are possible within the scope of protection specified by the claims, which are within the scope of a person skilled in the art.

Claims

1. An interconnect system between cores, characterized in that, the interconnect system between cores has: at least two cores; and a crossbar matrix bus for connecting the at least two cores, each of the at least two cores comprises an on-chip interconnect interface for interconnect between cores, the on-chip interconnect interface has an interface conversion module, wherein the on-chip interconnect interface converts first data and a first address into a first data packet having a first custom data packet format by using the interface conversion module, and transmits the first data and the first address on the crossbar matrix bus in the first data packet, and / or the on-chip interconnect interface receives a second data packet having a second custom data packet format from the crossbar matrix bus, and converts the second data packet into second data and a second address by using the interface conversion module.

2. The interconnect system between cores according to claim 1, characterized in that, the on-chip interconnect interface comprises a FIFO buffer for buffering the first data packet and / or the second data packet according to a depth of the FIFO buffer.

3. The interconnect system between cores according to claim 1 or 2, characterized in that, the crossbar matrix bus has an ID routing function for routing according to a target ID of the first data packet and / or the second data packet.

4. The interconnect system between cores according to claim 1 or 2, characterized in that, the first data packet and / or the second data packet contains at least one of the following packet types: a write request packet for indicating a write request; a write data packet for containing data transmitted for the write request; a write return packet for confirming whether a core as a receiver of the data successfully receives the data transmitted for the write request; a read request packet for indicating a read request; a read data packet for containing data transmitted for the read request; and a read return packet for confirming whether a core as a receiver of the data successfully receives the data transmitted for the read request.

5. The interconnect system between cores according to claim 4, characterized in that, the write request packet, the write data packet, the write return packet, the read request packet, the read data packet and the read return packet have the same number of bits. a bus width of the crossbar matrix bus connected to each of the at least two cores is related to the number of bits.

6. The internode interconnect system of claim 5, wherein, 7. The interconnect system between cores according to claim 6, characterized in that, the number of bits corresponds to a bus width of the crossbar matrix bus connected to each of the at least two cores.

8. The interconnect system between cores according to claim 7, characterized in that, the bus width is 48 lines.

9. The interconnect system between cores according to claim 4, characterized in that, ​ One of the at least two cores sends one of the write request packet, the write data packet, the write return packet, the read request packet, the read data packet and the read return packet to the crossbar matrix bus using the on-chip inter-core interconnect interface in multiple cycles, wherein a bus width of the crossbar matrix bus connected to each of the at least two cores is related to a number of bits of the data packet sent in each cycle.

10. The inter-core interconnect system of claim 4, wherein The write request packet comprises a source ID field for indicating a source ID of the write request packet and a destination ID field for indicating a destination ID of the write request packet.

11. The inter-core interconnect system of claim 10, wherein The write request packet further comprises a type field for indicating a type of the data packet, a length field for indicating a number of write data packets belonging to the write request packet, a write request packet ID field for indicating an ID of the write request packet, and an address field for indicating a write address of a write request corresponding to the write request packet.

12. The inter-core interconnect system of claim 4, wherein The write data packet comprises a source ID field for indicating a source ID of the write data packet and a destination ID field for indicating a destination ID of the write data packet.

13. The inter-core interconnect system of claim 12, wherein The write data packet further comprises a type field for indicating a type of the data packet, a write data start bit for indicating a start of a write operation, i.e. a first write data packet of a write request corresponding to the write request packet, a write data end bit for indicating an end of the write operation, i.e. a last write data packet of the write request corresponding to the write request packet, and a data field containing at least a portion of data to be sent for performing the write operation, wherein the data is sent sequentially through all write data packets belonging to the write request packet of the write operation.

14. The inter-core interconnect system of claim 13, wherein The write data packet further comprises a mask field for indicating whether the data field of the write data packet is valid or not, and a reserved field or reserved bit for indicating a field or bit not used in the write data packet.

15. The inter-core interconnect system of claim 4, wherein The write return packet comprises a write request packet ID field for indicating an ID of a write request packet corresponding to the write return packet and a destination ID field for indicating a destination ID of the write return packet.

16. The inter-core interconnect system of claim 15, wherein The write return packet further comprises a type field for indicating a type of the data packet, a count field for indicating a number of write data packets actually received by a core as a receiver of the data for the write request packet, and a receive success bit for indicating whether the data transmitted by a core as a sender of the data for the write request packet is successfully received by the core as the receiver of the data.

17. The inter-processor interconnect system of claim 4, wherein the read request packet further comprises a type field indicating a type of the packet, a length field indicating a number of read data packets requested by the read request packet, a read request packet ID field indicating an ID of the read request packet, and an address field indicating a read address of a read request corresponding to the read request packet.

18. The inter-processor interconnect system of claim 17, wherein the read request packet further comprises a type field indicating a type of the packet, a length field indicating a number of read data packets requested by the read request packet, a read request packet ID field indicating an ID of the read request packet, and an address field indicating a read address of a read request corresponding to the read request packet.

19. The inter-processor interconnect system of claim 4, wherein the read data packet further comprises a type field indicating a type of the packet, a read data packet ID field indicating an ID of the read data packet, and a data field containing at least a portion of data to be received for performing a read operation, wherein the data is sequentially received through all read data packets belonging to a read request packet of the read operation.

20. The inter-processor interconnect system of claim 19, wherein the read data packet further comprises a type field indicating a type of the packet, a read data packet ID field indicating an ID of the read data packet, and a data field containing at least a portion of data to be received for performing a read operation, wherein the data is sequentially received through all read data packets belonging to a read request packet of the read operation.

21. The inter-processor interconnect system of claim 4, wherein the read return packet further comprises a type field indicating a type of the packet, a count field indicating a number of read data packets actually received by a core as a receiver of the data for the read request packet, and a receive success bit indicating whether the core as the receiver of the data successfully received the data transmitted by a core as a sender of the data for the read request packet.

22. The inter-processor interconnect system of claim 21, wherein the read return packet further comprises a type field indicating a type of the packet, a count field indicating a number of read data packets actually received by a core as a receiver of the data for the read request packet, and a receive success bit indicating whether the core as the receiver of the data successfully received the data transmitted by a core as a sender of the data for the read request packet.

23. A graphics card apparatus, comprising the inter-processor interconnect system according to any one of claims 1 to 22.

24. A write operation method for inter-processor interconnect, comprising the write operation method is performed in the inter-processor interconnect system according to any one of claims 1 to 22, wherein the write operation method is designed for a write operation from a first core of the at least two cores to a second core of the at least two cores, and wherein the write operation method comprises: sending, by an on-chip inter-processor interconnect interface of the first core, a write request packet configured to indicate a write request; sending, by the on-chip inter-processor interconnect interface of the first core, one or more write data packets corresponding to the write request packet, the write data packets being configured to contain data transmitted by the first core for the write request.

25. The write operation method of claim 24, wherein sending the write request packet and one or more write data packets corresponding to the write request packet in sequence through the on-chip interconnect interface of the first core; and / or sending a plurality of write request packets first and then one or more write data packets corresponding to the plurality of write request packets respectively through the on-chip interconnect interface of the first core; and / or sending a plurality of write request packets and one or more write data packets corresponding to the plurality of write request packets respectively through the on-chip interconnect interface of the first core in a cross manner, wherein the sequence of the plurality of write request packets is consistent with the sequence of one or more write data packets corresponding to the plurality of write request packets respectively.

26. The write operation method of claim 24 or 25, wherein the write operation method further comprises converting the first data and the first address into the write request packet and the write data packet through an interface conversion module of the on-chip interconnect interface of the first core.

27. The write operation method of claim 24 or 25, wherein the write operation method further comprises receiving a write return packet through the on-chip interconnect interface of the first core, the write return packet being configured for confirming whether the second core successfully receives the data transmitted for the write request.

28. The write operation method of claim 27, wherein the write operation method further comprises converting the write return packet into the second data and the second address through an interface conversion module of the on-chip interconnect interface of the first core.

29. A read operation method for an inter-core interconnect, wherein the read operation method is performed in the inter-core interconnect system according to any one of claims 1 to 22, wherein the read operation method is designed for a read operation from a first core of the at least two cores to a second core of the at least two cores, and wherein the read operation method comprises: sending a read request packet through the on-chip interconnect interface of the first core, the read request packet being configured for indicating a read request; receiving one or more read data packets corresponding to the read request packet through the on-chip interconnect interface of the first core, the read data packet being configured for containing data transmitted by the second core for the read request.

30. The read operation method of claim 29, wherein the read operation method further comprises: sending a read return packet through the on-chip interconnect interface of the first core, the read return packet being configured for confirming whether the first core successfully receives the data transmitted by the second core for the read request.

31. The read operation method of claim 30, wherein the read operation method further comprises converting the first data and the first address into the read request packet and the read return packet through an interface conversion module of the on-chip interconnect interface of the first core.

32. The read operation method of any one of claims 29 to 31, wherein The read operation method further includes converting, by an interface conversion module of the on-chip inter- core interconnection interface of the first core, the read data packet into the second data and the second address.

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