A method of generating receiving substrate for bonding semiconductor die thereto

Abstract

The present application relates to a method of generating a receiving substrate (1) configured to receive one or more dies (3) thereon by hybrid bonding in one or more first landing zones (2a) and / or one or more dies (4) thereon by solder bonding in one or more second landing zones (2b). In both types of landing zones, contact pads (29, 35, 36) embedded in the dielectric layer (37, 50) or the stack of dielectric layers (27, 28) are formed, enabling hybrid bonding in the hybrid bonding landing zone. The contact pad in the solder landing area is configured to receive solder material directly on the contact pad after bonding of the hybrid bonding die without requiring formation of an under bump metal pad. According to a preferred embodiment, at least the solder contact pad comprises two layers (29a, 29b), a bottom layer and a top layer, the bottom layer being formed of a material formed of an intermetallic compound that exhibits slower than the top layer material when reacting with the solder.

Description

Technical Field

[0001] This invention relates to semiconductor processing, and more particularly to a method for bonding individual semiconductor dies to a receiving substrate. Background Technology

[0002] In the semiconductor industry, a typical process involves bonding semiconductor dies—individual semiconductor elements such as integrated circuit chips—to a larger receiving substrate. The substrate can be a processed wafer that itself contains multiple dies. A specific example involves bonding individual dies to a portion of a wafer dedicated to acting as a so-called interposer chip, which is designed to carry and interconnect multiple dies with different functions while being attached to another carrier, such as a printed circuit board. Through-semiconductor via (TSV) connections are created through a substrate such as an interposer used to implement connections from the front to the back of the interposer.

[0003] Die bonding achieves electrical connections between contact pads on the die and corresponding contact pads on the receiving substrate. There are two main bonding methods for achieving these connections: solder bonding and hybrid bonding. Solder bonding involves bonding the die or substrate by applying solder bumps to it prior to the bonding process. The solder has a lower melting point than the metal pads to which it is applied and forms intermetallic compounds with the metal of these pads during a dedicated thermal cycle applied during the bonding process. Solder bonding requires the formation of metal contact pads on the bonding surface, known as under-bump metallization (UBM) pads. These UBM pads have specific compositions designed to prevent the solder from consuming the underlying conductive structure.

[0004] The second widely used bonding technique is called hybrid bonding. Here, the grain and receiving substrate are processed in a certain way to create corresponding dielectric bonding surfaces, in which metal contact pads are embedded. Bonding includes direct dielectric-to-dielectric bonding between the dielectric bonding surfaces under the influence of annealing temperature and possible mechanical stress, and direct metal-to-metal bonding between aligned contact pads on the two surfaces.

[0005] In practice, not all chip types can serve as sources for hybrid bonding or solder bonding dies, thus often requiring the application of different bonding techniques on the same receiving substrate. Since hybrid bonding requires planarization of the entire receiving substrate, this technique is applied first, i.e., one or more hybrid bonding dies are bonded first, followed by one or more solder bonding dies. However, once hybrid bonding dies have been bonded to the receiving substrate, this approach requires processing steps such as plating UBM pads on the substrate, which can lead to processing complexity and potential damage to the hybrid bonding dies. Summary of the Invention

[0006] This invention relates to a method according to the appended claims. According to the invention, a receiving substrate is generated, the receiving substrate being configured to receive one or more dies thereon via hybrid bonding in one or more first landing areas, and / or via solder bonding in one or more second landing areas. In both types of landing areas, contact pads are formed embedded in a dielectric layer or dielectric layer stack, enabling hybrid bonding in the hybrid bonding landing area. The contact pads in the solder landing area are configured to receive solder material directly on the contact pads after the bonding of the hybrid-bonded dies, without requiring the formation of under-bump metal pads.

[0007] According to a preferred embodiment, at least the solder contact pad comprises two layers, a bottom layer and a top layer, wherein the bottom layer is formed of a material that exhibits slower intermetallic compound formation when reacting with solder than the material of the top layer.

[0008] According to the invention, additional contact pads are incorporated into a stack of dielectric material in which mixed and / or solder contact pads are embedded, such that the additional contact pads are exposed after mixed and / or solder bonding. The additional contact pads may be configured to receive electrical testing of one or more bonded dies within the substrate, or for bonding of other dies.

[0009] The present invention particularly relates to a method for generating a receiving substrate adapted to bond a plurality of semiconductor dies to the substrate, thereby electrically connecting the dies to the substrate, the method comprising the following steps:

[0010] A substrate is provided having an upper surface including a plurality of landing areas thereon for receiving the respective grains.

[0011] A dielectric layer is generated on the upper surface and in each of the landing zones.

[0012] A via connection is formed that penetrates the dielectric layer, and the via connection is connected to a circuit within the receiving substrate.

[0013] The dielectric layer and the via are planarized to a common horizontal surface.

[0014] A dielectric layer or dielectric layer stack is formed on the common horizontal surface, wherein contact pads are embedded in the dielectric layer or the dielectric layer stack, and wherein:

[0015] The contact pads are configured such that in each landing zone, a plurality of the contact pads are connected to corresponding via connections within the landing zone.

[0016] The contact pads are configured to enable die bonding to the corresponding landing area via the following:

[0017] Alternatively, by mixing and bonding all grains in the landing zone.

[0018] Alternatively, solder bonding can be achieved by directly applying solder material to the contact pads in all landing areas, thus bonding the grains in all landing areas.

[0019] Alternatively, one or more first grains in one or more first landing regions can be solder-bonded by mixing and bonding, and by directly applying solder material to contact pads in one or more second landing regions.

[0020] The method further includes, after planarizing the first dielectric layer and the via connection to the common horizontal surface, and before generating the contact pads configured for hybrid bonding and / or the contact pads configured for solder bonding:

[0021] In one or more regions of the receiving substrate located outside any landing area, one or more additional contact pads are generated and embedded in an additional dielectric layer formed on the common horizontal surface, and the additional dielectric layer and the one or more additional contact pads are planarized to the common planarization level.

[0022] Furthermore, the contact pads configured for hybrid bonding and / or the contact pads configured for solder bonding are embedded in a stack of dielectric layers, which includes the additional dielectric layer at the bottom of the stack.

[0023] According to one embodiment, the one or more additional contact pads are suitable for testing dies bonded to or contained in a receiving substrate.

[0024] According to one embodiment, the one or more additional contact pads are adapted to bond one or more additional grains to the receiving substrate.

[0025] According to one embodiment, the additional contact pads are generated through the following steps:

[0026] The additional dielectric layer is formed on the common horizontal surface.

[0027] An opening is formed that extends through the entire thickness of the additional dielectric layer, wherein one or more of the via connections are exposed at the bottom of the opening.

[0028] A conductive material layer is conformally deposited in the opening and on the additional dielectric layer, wherein the thickness of the conductive material layer is substantially equal to the thickness of the additional dielectric layer.

[0029] The conductive material layer is patterned to create additional contact pads in the opening, wherein a gap is maintained between the additional contact pads and the sidewall of the opening.

[0030] Deposit another dielectric layer to fill the gap.

[0031] The other dielectric layer is planarized to the level of the upper surface of the additional contact pad.

[0032] According to one embodiment, the conductive material of the additional contact pad is aluminum.

[0033] According to one embodiment, contact pads in the landing area configured to receive a die via solder bonding comprise a stack comprising a bottom layer and a top layer, the top layer being formed of a first material configured to receive the solder material thereon, and the bottom layer being formed of a second material different from the top layer material, the second material being configured to exhibit a slower reaction with the solder material to form an intermetallic compound compared to the first material.

[0034] According to one embodiment, the contact pads in the landing area configured to receive the die via hybrid bonding comprise a stack comprising a bottom layer and a top layer of different materials.

[0035] According to one embodiment, the material of the bottom layer of the stack has a higher coefficient of thermal expansion than the material of the top layer of the stack. Attached Figure Description

[0036] Figure 1a and 1b A receiving substrate applicable to the method of the present invention is shown, the receiving substrate having indications of landing areas for hybrid bonding and solder bonding.

[0037] Figures 2a-2b Figures 6a-6b illustrate a method according to a first embodiment for generating double-layer contact pads in the landing areas of the mixed grain and the solder grain.

[0038] Figures 7a-7b The method according to the second embodiment is shown, in which double-layer contact pads are not included in any landing area.

[0039] Figures 8 to 15 A first method for generating double-layer contact pads embedded in dielectric material is shown.

[0040] Figures 16 to 21 An alternative method for generating double-layer contact pads is shown.

[0041] Figures 22a-22bExamples 28a-28b show an embodiment in which double-layer contact pads are formed in the solder grain landing area, rather than in the mixed grain landing area.

[0042] Figures 29-39 One embodiment is shown in which an additional embedded test pad is generated in a region between the hybrid grain landing region and the solder grain landing region.

[0043] Figures 40-45 A specific method for generating large embedded test pads according to an embodiment of the present invention is shown. Detailed Implementation

[0044] Some embodiments will be described in detail below. All references to materials and dimensions are strictly exemplary and do not limit the scope of the invention, which is determined only by the appended independent claims.

[0045] Figure 1a This is a plan view of the receiving substrate, in this case, a silicon wafer 1, including multiple landing regions 2 for receiving individual semiconductor dies thereon. Two dies 3 and 4 are shown aligned with their respective landing regions 2a and 2b. The wafer 1 has undergone substantial processing steps in the landing regions 2, including at least the formation of interconnect circuits embedded in a dielectric material, also known as back-end process (BEOL) interconnect structures, which are accessible at the surface of the wafer (possibly after the removal of the passivation layer). These interconnect circuits may be connected to active semiconductor devices in the front-end process (FEOL) portion of the integrated circuit dies processed on the wafer, and / or connected to TSV (through-semiconductor via) connections formed partially through the thickness of the wafer, which are later exposed by thinning the wafer from the back side. Dies 3 and 4 can be any of a range of known semiconductor components, such as memory or logic integrated circuit chips.

[0046] exist Figure 1b The cross-sectional view shown illustrates two semiconductor dies 3 and 4 aligned with corresponding landing regions 2a and 2b (i.e., maintained at a certain distance but not yet bonded). Each die may have an in-plane dimension on the order of millimeters and a thickness on the order of tens to hundreds of micrometers. The purpose is to place the dies on the corresponding landing regions 2a and 2b using a pick-and-place tool and to achieve conductive bonding between the dies and the receiving substrate 1 in the corresponding landing regions, wherein the first die 3 will be bonded by hybrid bonding, and the second die 4 will be bonded by solder bonding. The first die 3 is also referred to below as the "hybrid die," and the second die 4 is referred to below as the "solder die."

[0047] The embodiments described below relate to a method for implementing these two different bonding techniques, particularly by method steps for preparing the receiving substrate 1 in the following manner:

[0048] Both of these bonding techniques can be applied when there are no or very few processing steps between the hybrid bonding of the first grain 3 and the solder bonding of the second grain 4.

[0049] - Test pads are incorporated into the receiving substrate for electrical testing of mixed grains and / or solder grains.

[0050] The key feature of this embodiment lies first in the latter feature, namely the merging of the test pads, and secondly in the implementation of two different bonding techniques. This means that the invention can also be applied to embodiments where the receiving substrate is provided with test pads and is configured to receive only mixed grains or only solder grains. Various methods for preparing landing areas for mixed bonding or solder bonding will be described below in the context of embodiments where the two different bonding techniques are applied to the same receiving substrate. However, these methods can also be applied to embodiments where the receiving substrate is configured to receive only mixed grains or only solder grains.

[0051] Figure 2a and 2b It shows in Figure 1b Enlarged views of rectangles 10a and 10b are shown. Each of these views shows a small portion of the corresponding dies 3 and 4 and wafer 1, where dies 3 and 4 are aligned with wafer 1, but prior to the performance of multiple fabrication steps on the wafer. Both dies can be seen to include a substrate portion 5, a FEOL portion 6, and a BEOL portion 7. The hybrid die 3 includes a dielectric bonding layer 8 on the BEOL portion 7, with contact pads 9 embedded therein, which are electrically connected to the respective conductors of the BEOL portion 7. The surface of the dielectric bonding layer 8 and the contact pads 9 are planarized to a common level. However, the contact pads 9 may be slightly recessed relative to the dielectric surface, possibly as a result of the planarization technique applied. The solder die 4 includes under-bump metallization (UBM) pads 15 located on the BEOL portion 7, which are electrically connected to the conductors in the BEOL portion 7, and solder bumps 16 attached to the UBM pads 15.

[0052] In landing regions 2a and 2b, wafer 1 includes a BEOL-type circuit portion 17 and a plurality of TSV connections 18 electrically connected to the BEOL portion 17 and extending partially through the thickness of wafer 1. This portion of the wafer is designed to serve as an interposer substrate and is configured to receive a plurality of dies on its front side, which will be connected to the opposite side of the interposer via TSV connections. The opposite side is processed after the dies on the front side are bonded and the wafer is thinned from the back side to expose the TSVs. This is merely one example of receiving substrate 1. According to other embodiments, the substrate may be configured differently, for example, including FEOL and BEOL portions in each landing region 2, and without TSV connections.

[0053] The upper surface of the BEOL portion 17 of wafer 1 includes electrical conductors embedded in a so-called IMD (intermetallic dielectric) layer. A detailed cross-sectional view shows a possible layout of the upper region of the BEOL portion 17, including conductors 19 and vias 20 embedded in the IMD material 21. The conductors 19' in the upper layer of the BEOL portion are accessible for contact within the upper surface 22 of the BEOL portion 17.

[0054] refer to Figure 3a and 3b A dielectric layer 25 is deposited on the upper surface of the BEOL portion 17, and via connections 26 are formed through the dielectric layer 25 at predetermined locations defined by the layout of the BEOL portion 17. The via connections 26 contact conductors in the upper BEOL surface 22 at the predetermined locations. The via connections 26 can be formed by known methods, including forming cavities of via shape by photolithography and etching, and filling the cavities with a conductive material (e.g., copper), preferably prior to lining the cavities with a suitable barrier layer and possibly a seed layer to achieve Cu electrodeposition, as is known in the art. The upper surface of layer 25 is planarized by known planarization techniques, such as chemical mechanical polishing (CMP), so that the upper surface of the dielectric layer 25 and the via connections 26 reach a common plane level. According to various embodiments of the invention, as... Figure 3a and 3b As shown, the thickness of the dielectric layer 25 with the embedded via connection 26 can be on the order of 500 nm.

[0055] Now for reference Figure 4a and 4b A stack of dielectric layers 27 and 28 is formed on the planarized surface of layer 25, wherein metal contact pads 29 are embedded in the stacks 27 and 28. Various methods for generating contact pads 29 or their equivalents will be further described in this specification. A first array of “hybrid contact pads” 29 is formed in the landing region 2a of the hybrid grain 3. Figure 4aThe second array of "solder contact pads" 29 is formed in the landing area 2b of the solder grain 4. Figure 4b As seen in a plane perpendicular to the plane of the accompanying drawings, all contact pads 29 can have a substantially circular cross-section. In the example shown, the contact pads of the solder grain 4 are slightly larger than the pads of the hybrid grain 3. However, the in-plane dimensions of the contact pads can range from a few micrometers to tens of micrometers, depending on the type of grains to be bonded. The pads 29 are preferably arranged in a rectangular array with a constant pitch. The dimensions and spacing of these contact pad arrays generated according to the invention can correspond to values ​​known in the fields of hybrid and solder bonding applications.

[0056] like Figure 4a and 4b As shown, mixed grains ( Figure 4a ) and solder grains ( Figure 4b The contact pads 29 comprise two layers: a bottom layer 29a and a top layer 29b. The bottom layer 29a is in direct contact with the upper surface of the planarized layer 25, while the upper surface of the top layer 29b is substantially coplanar or slightly recessed relative to the upper surfaces of the stacked dielectric layers 27 and 28. In these two landing regions 2a and 2b (for mixing the die and for soldering the die), at least some of the bottom layer 29a of the contact pads are in direct electrical contact with the corresponding via connections 26 embedded in the dielectric layer 25. As shown, some contact pads 29 may not contact the corresponding via connections 26. These contact pads are dummy pads, which are included, for example, for the mechanical stability of the ultimately bonded die.

[0057] The top layer 29b (simultaneously in the hybrid landing area 2a and the solder landing area 2b) is a layer formed of Cu or another material suitable for forming direct metal-to-metal bonding with corresponding contact pads on the hybrid grains in the hybrid landing area 2a. When the top layer 29b is a Cu layer, the bottom layer 29a is a layer formed, for example, of Ni or Co. Compared to the material of the top layer 29b, the material of the bottom layer 29a exhibits a slower intermetallic reaction rate with the solder material. For example, when the bottom layer 29a is Ni, this Ni layer prevents rapid interaction between the Sn solder bumps applied to the top layer 29b and the Cu of the via connection 26 beneath the Ni layer 29a, thereby preventing the solder from consuming the via connection 26. The Ni layer 29a thus performs a function similar to that of UBM metal pads used in conventional solder bonding. The thicknesses of the two layers 29a and 29b are suitable for this function. For example, for contact pads with in-plane dimensions in the range of approximately 5 to 15 μm, the thicknesses of the two metal layers 29a and 29b can be between 0.5 and 1 μm, such that the overall thickness of the pad 29 (layer 29a + layer 29b) is between 1 and 2 μm.

[0058] The upper surfaces of the dielectric layer stacks 27 and 28 are planarized to a sufficiently flat horizontal plane to allow the hybrid grains 3 to be hybrid-bonded to their dedicated landing regions 2a. The result of the hybrid bonding step is... Figure 5a and 5b The diagram shows that by aligning and bonding the contact pads 9 of the die 3 to the contact pads 29 in the hybrid bonding region 2a, and achieving hybrid dielectric-to-dielectric and metal-to-metal bonding, the hybrid die 3 is bonded and connected to the receiving substrate. Figure 5a Meanwhile, the solder bonding area 2b remains idle. However, the solder bonding area 2b is ready to receive solder dies immediately after the hybrid bonding step, that is, when the hybrid die 3 is already there, there is no need to plate UBM pads or bumps on the solder bonding surface, because the double contact pads 29 are directly suitable for receiving solder connections thereon.

[0059] The latter in Figure 6a and 6b As shown in the image. Figure 6b As shown, solder bump 16 has merged with the top metal layer 29b (Cu) to form solder connection 30, but the formation of the intermetallic compound has not progressed substantially to the underlying Cu via connection 26 due to the presence of the underlying Ni layer 29a, which acts as a barrier layer for intermetallic compound formation (other materials, instead of Ni, can be used here). The representation of the solder connection is merely illustrative. The solder connection does not necessarily consume all the Cu in layer 29b and may consume some of the Ni in layer 29a, but not so much that all the nickel is consumed. Following the solder bonding step is the deposition and curing of an underfill material, which is known in the art and is not shown in the figures.

[0060] Although the function of the double-layer contact pads 29a+29b is primarily related to solder grains, in the illustrated embodiment, the contact pads for receiving the mixed grain 3 also have a double-layer structure. However, this is not generally a limitation of the invention, and other embodiments in which the mixed contact pads do not have a double-layer structure will be described below. However, in the case of mixed grains, the double-layer structure can also be advantageous, depending on the contact pad size and the materials used for the bottom layer 29a and the top layer 29b. This advantage relates to the bulging effect known to occur during mixed bonding. As mentioned above, planarization of the bonding surface typically causes the mixed bonding pads to be slightly recessed relative to the dielectric bonding surface. This can be a beneficial effect because it enables dielectric-to-dielectric bonding first, and then metal-to-metal bonding, which is achieved by the thermal expansion of the metal pads toward each other during the mixed bonding annealing cycle. This thermal expansion is called the bulging effect. The double-layer structure may be advantageous if the metal of the bottom layer 29a has a higher coefficient of thermal expansion than the top layer 29b, further enhancing the bulging effect of the bottom layer.

[0061] A more significant advantage of generating both solder contact pads and hybrid contact pads as a double-layer structure 29a+29b embedded in dielectric layer stacks 27 and 28 is that one or more hybrid dies 3 can be bonded, followed directly by bonding one or more solder dies 4, without any intermediate processing steps, and therefore without the need to prepare landing pads suitable for solder bonding. These landing pads for soldering have been integrated into the same dielectric stacks 27 and 28 as the hybrid contact pads.

[0062] The latter advantage is not actually directly related to such a two-layer structure, but rather to the fact that both hybrid contact pads and solder contact pads are embedded in the dielectric layer stacks 27, 28, and that the solder contact pads, when generated in said stacks, are ready to receive solder bumps thereon, without the need to apply UBM pads on top of the solder bonding surfaces. This is a major advantage of any embodiment of the invention, and this advantage can also be obtained with a two-layer structure without contact pads.

[0063] This is Figure 7a and 7b As shown in the diagram, the hybrid contact pad 35 and the solder contact pad 36 are formed of a single metal (e.g., Cu) and are both embedded in a single dielectric layer 37. This layer and the contact pads are thicker than in the previous embodiment. This increased thickness is applied for the same reason as in the previous embodiment's Ni underlayer 29a, to prevent solder from consuming the Cu via connections 26. This time, there is more Cu in the solder contact pad 36, which ensures that the solder does not consume all the contact pads. However, this solution is not suitable for very small contact pad sizes. On the other hand, the application of the bimetallic structures 29a, 29b of at least the solder contact pads enables the cost-effective fabrication of very small contact pads with fine pitch (e.g., diameters of 5 micrometers or less).

[0064] The double-layer contact pads 29, including the bottom layer 29a and the top layer 29b, can be obtained in different ways, some of which will be referenced below. Figures 8 to 21 The following description is provided. It is obvious that dielectric layers 27 and 28, as well as sublayers 29a and 29b, do not necessarily each consist of a single dielectric or metal layer.

[0065] Reference Figures 8 to 15 A first method for generating double-layer embedded contact pads 29 is described. In the first step ( Figure 8 In this process, the first dielectric layer 27a is deposited on the planarized surface of layer 25, i.e., the dielectric layer 25 in which the contact vias 26 are embedded is located directly on the upper surface of the BEOL portion 17 (which is not on the upper surface of the BEOL portion 17). Figure 8-21(As shown in the diagram). Layer 27a can be, for example, a silicon oxide layer about 0.6 μm thick, which can be obtained by a known deposition method, such as CVD (chemical vapor deposition). A SiCN layer 27b, about 100 nm thick, is then deposited on layer 27a, which serves as a CMP stop layer in the later stages of the process. Figure 9 As shown, via opening 40 is formed in the stack of layers 27a and 27b by standard photolithography and etching. Opening 40 can be formed by timed etching, which stops when the upper surface of via connection 26 is exposed (slight over-etching is allowed here). Alternatively, layer 25 can be a stack of dielectric layers including, for example, a SiCN layer on top, which can then be used as an etch stop layer in the etching process used to form opening 40.

[0066] Then( Figure 10 The barrier layer (not shown) and Cu seed layer 41 are conformally deposited one after the other, i.e., following the morphology of the surface of the SiCN layer 27b and the bottom and sidewalls of the opening 40. The barrier layer can be a TaN layer of approximately 10 nm thickness. The seed layer 41 can be approximately 150 nm thick. (Refer to...) Figure 11 Then, Ni or an equivalent material is formed on the seed layer 41 by electrodeposition, i.e., Ni grows upward from the seed layer, thereby filling the opening 40 with Ni. This is followed by a planarization step using standard grinding and / or CMP, stopping at the SiCN layer 27b, to obtain... Figure 11 The image shown shows a planarized Ni layer 42 filling the via opening to act as a barrier layer for the formation of intermetallic compounds during welding, as described above. Alternatively, the Ni layer can be formed using techniques other than electrodeposition (e.g., PVD physical vapor deposition). In this case, only the TaN barrier layer is deposited, while the Ni layer is deposited directly on the barrier layer and then planarized to the level of the SiCN layer 27b.

[0067] Reference Figure 12 A second dielectric layer 28a, possibly another silicon oxide layer approximately 0.6 μm thick, is deposited on the planarized surface of the first SiCN layer 27a, and a second SiCN layer 28b is deposited on the second dielectric layer 28a. See also Figure 13 The second via opening 43 is formed using standard photolithography and etching. The second opening is formed on top of and aligned with the first opening 40, and has substantially the same in-plane dimensions as the first opening. This allows for small overlap errors, such as a slight misalignment of the second via opening 43 relative to the first via opening 40. Figure 14 As shown, another seed layer 44 is conformally deposited in the second opening 43 and on the second SiCN layer 28b. Subsequently, Cu is electrodeposited on the second seed layer 44 and planarized to the level of the second SiCN layer 28b, resulting in the desired shape. Figure 15The structure shown includes a planarized top Cu layer 45. Therefore, this is one embodiment of the aforementioned double-layer contact pad 29: the first layer 29a includes a first seed layer 41 and a Ni layer 42 formed thereon, while the second layer 29b includes a second seed layer 44 and a Cu layer 45 formed thereon. Layers 29a and 29b are embedded in a stack of dielectric layers 27 and 28, each dielectric layer including a silicon oxide layer (27a, 28a) and a SiCN layer (27b, 28b). The surface of the SiCN layer 28b is then the dielectric bonding surface to be bonded to the mixed grains, preferably also the SiCN bonding surface. The advantage of this approach is that SiCN-SiCN bonding provides stronger bonding than oxide-oxide bonding.

[0068] Reference Figures 16 to 20 Another method for generating the double-layer contact pad 29 is shown. A first dielectric layer 50, such as a silicon dioxide layer, is deposited on the planarized surface of layer 25, which includes the via connection 26, followed by the deposition of a SiCN layer 51. The dielectric layer 50 has approximately twice the thickness of layers 27a and 28a in the previous embodiment. The SiCN layer 51 can again have a thickness of approximately 100 nm. (Reference) Figure 17 A via opening 52 is formed through the stack of layers 50 and 51. A barrier layer (not shown), such as 10 nm TaN, is conformally deposited, followed by ( Figure 18 Ni is deposited directly on the barrier layer via physical vapor deposition. A Ni layer 53 is conformally formed in the via opening 52, i.e., the Ni layer is formed on the bottom and sidewalls of the opening 52 (the barrier layer within it) and on the horizontal surface of the substrate. The thickness of the Ni layer 53 is approximately 0.5 μm. Then, as... Figure 19 As shown, the Ni layer 53 was planarized to the level of the SiCN layer 51, followed by another Cu layer deposition via PVD. Copper filled the remaining approximately 0.5 μm high cavity left by the conformal Ni deposition. The second planarization resulted in… Figure 20 The structure shown is as follows: the Cu top layer 29b is laterally sealed by upright Ni sidewalls extending upwards from the Ni bottom layer 29a. This is another embodiment of the double-layer contact pads 29 generated according to the present invention.

[0069] In an alternative to the final processing step, a Cu layer 54 may also be deposited on the conformal Ni layer 53 before planarizing the Ni layer. This is as follows: Figure 21 As shown. Subsequently, Cu and Ni were planarized to the level of SiCN layer 51, resulting in... Figure 20The same bilayer structure is shown. One advantage will be the oxide-free interface between layers 53 and 54, because these layers can be deposited in a single deposition step (i.e., there is no need to remove the substrate from the processing chamber between the deposition of layers 53 and 54). An embodiment is now described in which bilayer metal contact pads 29 are applied to receive solder-bonded grains 4, rather than mixed-bonded grains 3. Reference Figure 22a and 22b The stack of dielectric layers 27 and 28 is again formed on the surface of the planarized layer 25, but the double-layer metal pads 29 are formed only in the bonding regions 2b of the solder grains. Figure 22b ), but not in the bonding region 2a of the mixed grains ( Figure 22a ).

[0070] Then, on the planarized surface of the layer stack 27+28, a thin protective layer 60 is deposited and patterned (see...). Figure 23a and 23b This layer 60 covers the landing region 2b of the solder grains but not the landing region 2a of the mixed grains. Layer 60 can be, for example, a TiN layer with a thickness of 10 nm. See also... Figure 24a and 24b Another dielectric layer 61 (e.g., SiO2) is deposited and planarized to obtain a horizontal surface across the entire wafer 1. The thickness of layer 61 can be comparable to the thickness of layers 27 and 28. Afterwards ( Figure 25a and 25b In the hybrid landing region 2a, contact pads 62 are formed in the stack of dielectric layers 27, 28, and 61, and the stack 27, 28, and 61 are planarized. Then, hybrid bonding of the hybrid die 3 to these contact pads 62 is performed. Figure 26a and 26b Subsequently, dielectric layer 61 and TiN layer 60 were locally removed from solder landing area 2b. Figure 27a and 27b Subsequently, solder grain 4 was bonded to solder landing region 2b. Figure 28a and 28b The partial removal of dielectric layer 61 and TiN layer 60 can be performed by photolithography and etching, wherein the hybrid die 3 is protected by a mask layer that can be peeled off after photolithography and etching without the risk of damaging the hybrid die. Therefore, this embodiment is also advantageous because steps that could potentially damage the hybrid-bonded die are not required after hybrid bonding.

[0071] Now for reference Figures 29 to 36This illustration shows an embodiment of the invention in which additional embedded contact pads are incorporated into a dielectric stack comprising the aforementioned hybrid bonding pads and / or solder bonding pads. These additional contact pads are suitable as test pads for electrical testing of dies incorporated into the receiving substrate and / or for testing dies bonded to the substrate by hybrid bonding or solder bonding. The additional pads may also be adapted to bond additional dies to the receiving substrate.

[0072] As described above, the incorporation of additional contact pads, i.e., by integrating the mixed and / or solder dies into dielectric layer 37 or dielectric layer stack 27+28, can be applied to receiving substrates configured to receive only mixed bonding dies, only solder bonding dies, or both types of dies simultaneously. One embodiment is described below, wherein additional contact pads are generated on a receiving substrate configured to receive both mixed dies and solder dies. However, the following description also applies to receiving substrates configured to receive only mixed dies or only solder dies.

[0073] Figure 29 The hybrid die 3 and solder die 4, aligned with the receiving substrate 1 before bonding to the wafer 1, are shown again. The area between and partially overlapping the respective landing areas 2a and 2b is represented by rectangle 69, and... Figures 30-36 This is shown in more detail below. For example... Figure 30 As shown, a dielectric layer 25 including via connections 26 is formed, as described with respect to the preceding embodiments. On this layer 25, another dielectric layer 70, for example formed of SiO2, is deposited. The thickness of layer 70 is on the same order of magnitude as the thickness of layer 25, for example, between 300 and 500 nm. (Reference) Figure 31 Large aluminum test contact pads 71 ​​are then formed embedded in the dielectric layer 70. These test pads are much larger than the previously described mixed contact pads and solder contact pads 29, 35, and 36. The test pads can be, for example, squares with side lengths of approximately 50 to 100 μm. The test pads 71 ​​are electrically connected to the circuitry of the BEOL section 17 via via connections 26 in layer 25. The actual via connections connecting the pads 71 ​​to the BEOL section 17 are located outside the plane of the figures.

[0074] The preferred method for generating test pads 71 ​​will be further described in this specification, but the description of the fabrication process after generating these test pads will be completed first. This fabrication process is substantially similar to the fabrication process described earlier in this specification for generating hybrid and solder-bonded embedded contact pads.

[0075] In that particular example, and as Figure 32As shown, a double-layer solder bonding pad 29 (i.e., comprising layers 29a+29b) is formed in the solder landing area 2b. For this purpose, another dielectric layer 72 with a similar thickness to layer 70 is formed on layer 70, and the double-layer bonding pad 29 is formed in the stack 70+72, which can be referenced. Figure 8-15 This is accomplished using any of the described embodiments. The solder landing area 2b is covered by a TiN protective layer 60. Figure 33 ), and then an additional dielectric layer 61 is formed. Figure 34 ) and hybrid bonding pads 62 embedded in the stack of layers 70, 72, and 61 ( Figure 35 This enables the hybrid bonding step, such as flattening the stack. Figure 36 As shown, the opening of solder bonding region 2b follows ( Figure 37 Solder bonding of solder grains 4 and application of underfill material 72 Figure 38 ).

[0076] As described, hybrid bonding pad 62 is embedded in the stack of dielectric layers 70, 72, and 61, while solder bonding pad 29 is embedded in the stack of dielectric layers 70 and 72. Therefore, hybrid bonding pads and / or solder bonding pads are embedded at the bottom of the stack of dielectric layers having layer 70, wherein buried pad 71 is embedded in layer 70.

[0077] like Figure 39 As shown, dielectric layers 72 and 61 can then be partially opened to allow access to test pads 71 ​​for electrical testing of mixed grains 3 and / or solder grains 4.

[0078] Aluminum test pads 71 ​​are embedded in the stack of dielectric layers 70, 72, and 61, as are hybrid contact pads 62 in hybrid landing region 2a and solder contact pads 29 in solder landing region. This allows for simple testing of bonded dies 3 and 4 by opening the stack after die bonding. This contrasts with current applications where test pads are electroplated onto the receiving substrate after the dies are bonded by hybrid or solder bonding.

[0079] Using aluminum for test pads is merely exemplary; other materials can also be applied. These large contact pads can be used not only as test pads for electrical testing but also as contact pads for wire bonding. In the latter case, Al contact pads can be generated in separate dedicated landing areas of the wire-bonded grains, for example, after bonding multiple grains 3 by hybrid bonding and additional grains 4 by solder bonding, and then bonding the Al contact pads to a receiving substrate. In addition to wire bonding, Al pads can also be used as substrates on which microbumps are received for bonding to another substrate.

[0080] Reference Figures 40 to 45 A detailed description of a possible method according to the invention for generating, in particular, aluminum test or wire bonding pads is provided. Figure 40 A portion of wafer 1, BEOL portion 17, dielectric layer 25, and planarized dielectric layer 70 formed thereon are shown. Figure 41 The opening 80 is shown to be formed by photolithography and etching through layer 70. At the bottom of the opening 80, one or more via connections 26 (located outside the plane of the figure) are exposed and can be used for contact via Al bonding pads 71.

[0081] Then Al is deposited to fill the opening 80 and form a conformal layer 81 of Al on layer 70. Figure 42 The thickness of Al layer 81 is equal to or as close as possible to the thickness of dielectric layer 70.

[0082] In the case of Al, two preliminary depositions (not shown) are performed before depositing the Al layer 81: first, a thin AlN layer is deposited to prevent Cu from diffusing from the Cu vias 26. Then, TiN is deposited to improve the adhesion of Al. Both of these preparatory layers can be approximately 10 nm thick.

[0083] Layer 81 can be thinned by grinding and / or CMP, but this is difficult and time-consuming in the case of Al due to the large Al pad size. Figure 43 Another method is shown: patterning the Al layer by photolithography and dry etching, so that Al is retained only in the opening 80 except for a small gap 82 around the opening 80 (e.g., with a width of about 1 μm, depending on the overlap accuracy of the photolithography tool).

[0084] Then another dielectric layer 83 was deposited. Figure 44 The dielectric layer 83 fills the gap 82 and forms on the surface of layer 70. This dielectric layer 83 can be a standard PECVD (plasma-enhanced chemical vapor deposition) oxide layer or a spin-coated glass-type oxide layer. The dielectric layer conformally fills the gap 82, thereby forming a recess 84 at the gap location. The thickness of layer 83 is sufficient such that the bottom of the recess 84 is located above the upper surface of the Al pad 71. Planarization ultimately results in... Figure 45 The image shown shows that the Al test pad 71 is fully embedded in the dielectric material layer 70+83.

[0085] Although the invention has been described and illustrated in detail in the accompanying drawings and the foregoing description, such description and illustration are intended to be illustrative or exemplary, and not restrictive. By studying the drawings, this disclosure, and the appended claims, those skilled in the art can understand and practice other variations of the disclosed embodiments in the practice of the claimed invention. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite articles "a" or "an" do not exclude a plural. The mere fact that certain measures are stated in mutually different dependent claims does not imply that combinations of these measures cannot be advantageously used. Any reference numerals in the claims should not be construed as limiting the scope.

Claims

1. A method for generating a receiving substrate, the receiving substrate being adapted to bond a plurality of semiconductor dies (3, 4) to the substrate, thereby electrically connecting the dies to the substrate, the method comprising the steps of: A substrate (1) is provided, the substrate having an upper surface including a plurality of landing regions (2a, 2b) for receiving the respective grains (3, 4) thereon. A first dielectric layer (25) is generated on the upper surface and in each of the landing areas. A via connection (26) is generated through the first dielectric layer, and the via connection is connected to a circuit within the receiving substrate (1). The first dielectric layer (25) and the via connection (26) are planarized to a common horizontal surface. A second dielectric layer (37, 50) or a dielectric layer (27, 28) is formed on the common horizontal surface; A stack of 70, 72, 61; 70, 72), wherein contact pads (29, 35, 36) are embedded in the dielectric layer or the stack of the dielectric layers, and wherein: The contact pads are configured such that in each landing zone (2a, 2b), a plurality of the contact pads are connected to corresponding via connections (26) within the landing zone. The contact pads are configured to bond the dies (3, 4) to the corresponding bonding regions (2a, 2b) by means of the following: Alternatively, the grains can be bonded together in all bonding regions. Alternatively, solder bonding of the grains in all landing areas can be achieved by directly applying solder material to the contact pads in all landing areas. Alternatively, one or more first grains in one or more first landing regions (2a) can be solder-bonded by mixing and bonding, and by applying solder material directly to contact pads in one or more second landing regions (2b). And the method further includes: after planarizing the first dielectric layer (25) and the via connection (26) to the common horizontal surface, and before generating the contact pads configured for hybrid bonding and / or the contact pads configured for solder bonding: In one or more regions of the receiving substrate located outside any landing area, one or more additional contact pads (71) are generated and embedded in an additional dielectric layer (70) formed on the common horizontal surface. The additional dielectric layer (70) and the one or more additional contact pads (71) are planarized to a common planarized level. And the contact pads configured for hybrid bonding and / or the contact pads configured for solder bonding are embedded in a stack of dielectric layers (70, 72, 61; 70, 72), the stack including the additional dielectric layer (70) at the bottom of the stack.

2. The method according to claim 1, characterized in that, The one or more additional contact pads (71) are suitable for testing the grains (3, 4) that are bonded to the receiving substrate (1) or contained in the receiving substrate (1).

3. The method according to claim 1 or 2, characterized in that, The one or more additional contact pads (71) are adapted to bond one or more additional grains to the receiving substrate (1).

4. The method according to any one of claims 1 to 3, characterized in that, The additional contact pads are generated through the following steps: The additional dielectric layer (70) is formed on the common horizontal surface. An opening (80) is formed through the entire thickness of the additional dielectric layer (70), wherein one or more of the via connections (26) are exposed at the bottom of the opening (80). A conductive material layer (81) is conformally deposited in the opening (80) and on the additional dielectric layer (70), wherein the thickness of the conductive material layer (81) is substantially equal to the thickness of the additional dielectric layer (70). The conductive material layer (81) is patterned to create additional contact pads (71) in the opening (80), wherein a gap (84) is maintained between the additional contact pads (71) and the sidewalls of the opening (80). Another dielectric layer (83) is deposited to fill the gap (84). The other dielectric layer (83) is planarized to the level of the upper surface of the additional contact pad (71).

5. The method according to any one of the preceding claims, characterized in that, The conductive material of the additional contact pad (71) is aluminum.

6. The method according to any one of the preceding claims, characterized in that, The contact pads (29) in the landing area (2b) configured to receive the die via solder bonding comprise a stack including a bottom layer (29a) and a top layer (29b), the top layer being formed of a first material configured to receive the solder material thereon, and the bottom layer being formed of a second material different from the top layer material, the second material being configured to exhibit a slower reaction with the intermetallic compound of the solder material compared to the first material.

7. The method according to any one of the preceding claims, characterized in that, The contact pads (29) configured in the landing area (2a) to receive the die by hybrid bonding comprise a stack of a bottom layer (29a) and a top layer (29b) containing different materials.

8. The method according to claim 6 or 7, characterized in that, The material of the bottom layer (29a) of the stack has a higher coefficient of thermal expansion than the material of the top layer (29b) of the stack.

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