Double-balanced mixer
By adding FETs and optimizing the bias function in the GaAs HEMT process, the high power consumption and large area problem of double-balanced mixers is solved, realizing a low-power, small-size mixer suitable for high-frequency applications.
Patent Information
- Application Number
- CN202511001029.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-21
- Publication Date
- 2025-11-14
AI Technical Summary
Existing dual-balanced mixers based on GaAs HEMT technology struggle to achieve both low power consumption and small size, and traditional architectures require large local oscillator power and large chip area.
By adding a set of FET transistors to the source stage of the FET ring mixer core and using appropriate bias design to replace the bias function, the local oscillator power requirement is reduced. At the same time, a FET transistor is connected in series in the intermediate frequency output stage to provide gain for the chip and reduce the DC blocking capacitor and filter capacitor.
It achieves a low-power, small-size mixer with power consumption reduced to 20mA and chip area reduced to 1/3, and has strong linearity and anti-interference capabilities, making it suitable for high-frequency application scenarios.
Smart Images
Figure CN120956218A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of microwave and millimeter-wave circuit technology, and in particular to a double-balanced mixer. Background Technology
[0002] Mixers are an indispensable component in radio frequency and microwave circuit systems. Whether it is microwave communication, radar, remote control, remote sensing, reconnaissance and electronic warfare, or microwave measurement systems, microwave signals must be downsampled to medium and low frequencies using mixers for processing.
[0003] From a circuit structure perspective, existing mixers mainly include single-ended mixers, single-balanced mixers, and double-balanced mixers. Considering practical operating conditions, double-balanced mixers have become the mainstream circuit structure due to their excellent spurious suppression characteristics and port isolation.
[0004] Traditional double-balanced mixers use diodes as their core functional components. This architecture often requires a large voltage swing from the local oscillator power to drive the diode, thus typically necessitating an amplifier at the local oscillator terminal. This architecture introduces significant power consumption and requires more chip area. Double-balanced structures are also widely used in CMOS circuit architectures, with MOSFETs as the mixing device. This type of architecture amplifies and shapes the local oscillator signal to drive the MOSFET gate in square wave form. However, it still requires a sufficiently large swing in the local oscillator square wave signal to effectively drive the MOSFET. However, due to differences in material properties and device performance, CMOS circuits typically employ active balun designs. Furthermore, the narrow bandgap of MOSFETs and advanced manufacturing processes allow CMOS mixers to often achieve lower power consumption and smaller size. Compared to CMOS processes, GaAs (gallium arsenide) materials offer superior linearity, strong anti-interference capabilities, and excellent radiation resistance, demonstrating broad application prospects in rapidly developing emerging fields such as low-altitude economy and inter-satellite communication. How to realize a mixer with both low power consumption and small size based on GaAs HEMT (High Electron Mobility Transistor) technology has become a key technical problem that urgently needs to be solved in this field. Summary of the Invention
[0005] This invention provides a dual-balanced mixer to address the problem that current GaAs HEMT-based mixers struggle to achieve both low power consumption and small size.
[0006] In a first aspect, embodiments of the present invention provide a dual-balanced mixer, comprising: a radio frequency planar balun, a local oscillator planar balun, a FET ring mixer core, a first FET transistor, and a second FET transistor; The input terminal of the local oscillator plane balun is used to receive the local oscillator signal; the two output terminals of the local oscillator plane balun are connected to the drain of the FET in the FET ring mixer core; The input terminal of the RF plane balun is used to receive RF input signals; the two output terminals of the RF plane balun are respectively connected to the gates of the first FET and the second FET, the sources of the first FET and the second FET are grounded, and the drains of the first FET and the second FET are connected to the source of the FET in the FET ring mixer core. In the FET ring mixer core, the drain of the FET transistor is connected to the intermediate frequency signal output terminal.
[0007] In one possible implementation, the FET ring mixer core includes a third FET, a fourth FET, a fifth FET, and a sixth FET. One output terminal of the local oscillator plane balun is connected to the gates of the third FET and the sixth FET, and the other output terminal is connected to the gates of the fourth FET and the fifth FET. The drain of the first FET is connected to the source of the third FET and the fourth FET, and the drain of the second FET is connected to the source of the fifth FET and the sixth FET. The drains of the third, fourth, fifth, and sixth FETs are connected to the intermediate frequency signal output terminal.
[0008] In one possible implementation, the two outputs of the local oscillator planar balun are connected to a first bias voltage; the two outputs of the radio frequency planar balun are connected to a second bias voltage.
[0009] In one possible implementation, the drains of the third and fifth FETs are grounded, and the drains of the fourth and sixth FETs are connected to the intermediate frequency signal output terminal via an amplifier.
[0010] In one possible implementation, the amplifier includes: a seventh FET and a third bias power supply; the drains of the fourth FET and the sixth FET are connected to the gate of the seventh FET; the gate and drain of the seventh FET are connected to the third bias power supply, and the source is connected to the intermediate frequency signal output terminal.
[0011] In one possible implementation, the double-balanced mixer further includes: an eighth FET; the drains of the third FET and the fifth FET are connected to the gate of the eighth FET; the gate and drain of the eighth FET are connected to the third bias power supply, and the source is grounded.
[0012] In one possible implementation, the source of the seventh FET is connected to the intermediate frequency signal output terminal in one path and grounded through a resistor in the other.
[0013] In one possible implementation, the source of the eighth FET is grounded through an inductor and a resistor, and also through a resistor.
[0014] In one possible implementation, the sources of the first FET and the second FET are grounded through an inductor and a resistor.
[0015] In one possible implementation, the FETs in the FET ring mixer core are all gallium arsenide-high electron mobility transistors (GaAs-high electron mobility transistors).
[0016] This application provides a dual-balanced mixer. The two outputs of an RF planar balun are connected to the gates of a first FET and a second FET, respectively. The sources of both FETs are grounded, and their drains are connected to the sources of the FETs in the FET ring mixer core. Essentially, a set of FETs (first and second FETs) is added to the source stage of the FET ring mixer core. By applying a suitable bias voltage to this set of FETs, the source stage potential of the FET ring mixer core can be determined without degrading the RF input power, thus replacing the bias function and effectively reducing the chip area. The entire mixer requires only a very small local oscillator power to operate, effectively reducing device power consumption. Attached Figure Description
[0017] Figure 1 This is a schematic diagram of the single-ended mixer topology provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of the single-balanced mixer topology provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the structure of a conventional double-balanced mixer topology provided in an embodiment of the present invention; Figure 4 This is a schematic diagram of the dual-balanced mixer topology provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of a conventional double-balanced mixer with its local oscillator connected to a driver amplifier, provided in an embodiment of the present invention. Figure 6 This is a schematic diagram of the structure of the double-balanced mixer provided in an embodiment of the present invention; Figure 7 This is a schematic diagram of the amplifier provided in an embodiment of the present invention. Detailed Implementation
[0018] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.
[0019] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.
[0020] First, let's explain the terms used in this application: A field-effect transistor (FET) is a semiconductor device that controls the movement of charge carriers (electrons or holes) in a semiconductor by applying an external electric field, thereby regulating the current. Its core characteristic is voltage-controlled current. Compared to bipolar junction transistors (BJTs), it offers advantages such as high input impedance, low noise, and low power consumption, and is widely used in electronic circuits for amplification, switching, and oscillation. The FET structure revolves around a source (S), drain (D), and gate (G), with the gate voltage controlling the conductivity of the channel between the source and drain. When a voltage is applied to the gate, an electric field is generated in the channel, changing its conductivity (turning on / off or changing resistance), thus regulating the output current.
[0021] GaAs HEMT: HEMT is a type of FET, a semiconductor device that controls current through an electric field effect. HEMT is a special type, also known as a modulation-doped field-effect transistor. It operates using a two-dimensional electron gas with very high mobility, enabling it to operate in ultra-high frequency and ultra-high speed applications. GaAs is a commonly used material for making HEMTs. GaAs has a high electron mobility, 5.7 times higher than silicon, making it ideal for high-frequency circuits. HEMTs based on GaAs can leverage its high electron mobility to achieve excellent performance such as high speed and low noise, and are commonly used in high-frequency applications such as satellite communication systems, wireless communication systems, and radar systems.
[0022] For ease of understanding of the inventive points of this application, see the following: Figures 1 to 5 This section introduces existing mixers: Mixers use nonlinear devices as the core mixing unit, and their circuit implementation mainly includes the following four types (excluding functional mixers, such as image rejection mixers): single-ended mixers, where the intermediate frequency (IF) is mixed and output through a low-pass filter (e.g., ...). Figure 1 A single-balanced mixer, with the local oscillator input via a balun and the intermediate frequency output via a low-pass filter (e.g., ...). Figure 2 A double-balanced mixer, with RF and local oscillator inputs via a balun, and intermediate frequency outputs via a low-pass filter (e.g., ...). Figure 3 ); Dual-balanced mixers, RF, local oscillator, and intermediate frequency signals are transmitted through a balun (e.g., Figure 4 ). Figures 1 to 4 In this context, RF represents radio frequency signal, LO represents local oscillator signal, DC represents bias voltage, and IF represents intermediate frequency output.
[0023] Among them, the double-balanced mixer is the mainstream circuit structure because it has high spurious suppression characteristics and port isolation characteristics.
[0024] Traditional double-balanced mixers often require a large voltage swing from the local oscillator power to drive the diodes; therefore, an amplifier is usually needed at the local oscillator terminal. (See [link]). Figure 5 As shown, this architecture introduces significant power consumption and requires more chip area. Therefore, achieving a low-power, small-size double-balanced mixer in GaAs HEMT technology is crucial.
[0025] To address this issue, this application proposes a dual-balanced mixer structure, aiming to overcome the problem of high power consumption in traditional GaAs HEMT dual-balanced mixers. By optimizing the mixer circuit architecture, the dual-balanced mixer achieves low power consumption and small size, greatly expanding the application range of mixer chips.
[0026] The implementation of the present invention will be described in detail below with reference to the accompanying drawings: Figure 6 This is a schematic diagram of a double-balanced mixer provided in an embodiment of the present invention. (Refer to...) Figure 6 The double-balanced mixer includes: Local oscillator plane balun k1, radio frequency plane balun k2, FET ring mixer core, first FET (FET1) and second FET (FET2).
[0027] The input terminal of the local oscillator plane balun k1 is used to receive the local oscillator signal LO; the two output terminals of the local oscillator plane balun k1 are connected to the drain of the FET in the FET ring mixer core; the input terminal of the radio frequency plane balun k2 is used to receive the radio frequency input signal RF; the two output terminals of the radio frequency plane balun k2 are respectively connected to the gate of the first FET (FET1) and the second FET (FET2), and the source of the first FET (FET1) and the second FET (FET2) is grounded through an inductor and a resistor; the drain of the first FET (FET1) and the second FET (FET2) is connected to the source of the FET in the FET ring mixer core; the drain of the FET in the FET ring mixer core is connected to the intermediate frequency signal output terminal IF.
[0028] In one possible implementation, the FET ring mixer core of this embodiment may include: a third FET (FET3), a fourth FET (FET4), a fifth FET (FET5), and a sixth FET (FET6).
[0029] In the dual-balanced mixer of this embodiment, the radio frequency signal RF is generated into two radio frequency differential signals by the radio frequency plane balun k2. One of the radio frequency differential signals passes through the first FET (FET1) and is connected to the source of the third FET (FET3) and the fourth FET (FET4) in the FET ring mixer core. The other radio frequency differential signal passes through the second FET (FET2) and is connected to the source of the fifth FET (FET5) and the sixth FET (FET6) in the FET ring mixer core.
[0030] The local oscillator signal LO is generated into two local oscillator differential signals by the local oscillator plane balun k1. One local oscillator differential signal is connected to the gates of the third FET (FET3) and the sixth FET (FET6), and the other output is connected to the gates of the fourth FET (FET4) and the fifth FET (FET5). Finally, the drains of the third FET (FET3), the fourth FET (FET4), the fifth FET (FET5), and the sixth FET (FET6) are connected to the intermediate frequency signal output terminal IF.
[0031] The dual-balanced mixer of this embodiment connects the gates of a first FET and a second FET respectively to the two output terminals of the RF planar balun. The sources of the first and second FETs are grounded, and their drains are connected to the sources of the FETs in the FET ring mixer core. This adds a set of FETs (the first and second FETs) to the source level of the FET ring mixer core. By applying a suitable bias voltage to this set of FETs, the source level potential of the FET ring mixer core can be determined without degrading the RF input power, thus replacing the bias function and effectively reducing the chip area. The entire mixer requires only a very small local oscillator power to operate, effectively reducing device power consumption.
[0032] See Figure 6 As shown, in some embodiments, the two outputs of the local oscillator planar balun k1 can be connected to a first bias voltage V1 via resistors; the two outputs of the RF planar balun can be connected to a second bias voltage V2 via resistors. By increasing the active bias, the FET can be operated in a near-pinch-off position, so that the local oscillator power can be driven with only a very small voltage swing, and the local oscillator power is as low as -5dBm, which greatly reduces the chip power consumption.
[0033] See Figure 6 As shown, in some embodiments, the drains of the third FET (FET3) and the fifth FET (FET5) are grounded. The drains of the fourth FET (FET4) and the sixth FET (FET6) are connected to the intermediate frequency signal output via an amplifier.
[0034] For amplifiers, the traditional GaAs amplifier structure is as follows: Figure 7 As shown, due to the low intermediate frequency (IF), the amplifier's DC blocking capacitor, filter capacitor, and choke inductor are extremely large, failing to effectively reduce chip area. The amplifier in this embodiment includes: a seventh FET (FET7) and a third bias power supply V3; the drains of the fourth FET (FET4) and the sixth FET (FET6) are connected to the gate of the seventh FET (FET7); the gate and drain of the seventh FET (FET7) are connected to the third bias power supply V3, and its source is connected to the IF signal output terminal in one path and grounded through a resistor in the other. This embodiment provides a certain gain to the chip by connecting a single FET in series in the IF output stage. By raising the RF potential through the single FET, power network, and negative feedback resistor, the input DC blocking capacitor and source-level filter capacitor are effectively eliminated, reducing chip area and power consumption.
[0035] In this embodiment, the drains of the third FET (FET3) and the fifth FET (FET5) are connected to the gate of the eighth FET (FET8); the gate and drain of the eighth FET (FET8) are connected to the third bias power supply V3, and the source is grounded through an inductor and a resistor, and through a resistor. A grounded load is designed at the differential output stage to match the circuit balance.
[0036] In some embodiments, the first FET (FET1), second FET (FET2), third FET (FET3), fourth FET (FET4), fifth FET (FET5), sixth FET (FET6), seventh FET (FET7), and eighth FET (FET8) can all be GaAs-high electron mobility transistor (HEMT) process structures. This embodiment achieves a low-power, small-size mixer in GaAs HEMT technology, and the entire device exhibits high linearity, strong anti-interference capability, and strong radiation resistance.
[0037] After testing, the mixer designed in this embodiment of the application has a power consumption of only 20mA, which is much lower than that of other mixers. Figure 5 The conventional mixer shown is... and compared to... Figure 5 The mixer shown is reduced to one-third the size, significantly lowering costs. Furthermore, the mixer of this application can change its operating frequency by adjusting the local oscillator and RF balun operating bands, for example, operating in the L-band or the lower P-band. The passive balun can also be replaced with an active balun, achieving a smaller chip area at the expense of power consumption.
[0038] The main inventive points of this application include: (1) By increasing the active bias, the FET is made to operate in a position close to pinch-off, so that the local oscillator power only needs a very small voltage swing to drive it. The local oscillator power is as low as -5dBm, which greatly reduces the chip power consumption.
[0039] (2) The reason why the -5dBm local oscillator power can work is that a set of FETs is added to the source of the FET ring mixer core, and a suitable bias voltage is added to the FETs so that the RF input power is not degraded, and the source potential of the mixer FET is determined, thus replacing the bias function.
[0040] (3) By connecting a FET in series in the intermediate frequency output stage, a certain gain is provided to the chip. The RF potential is raised by the FET, power network and negative feedback resistor, which effectively reduces the input DC blocking capacitor and source-level filter capacitor.
[0041] In actual fabrication, a GaAs pHEMT process with high transconductance can be selected. By optimizing the FET contact resistance and designing an air bridge, FET parasitics can be reduced, and the Process Design Kit (PDK) model can be extracted as simulation input. Through design such as... Figure 6 The diagram shows a FET stack and its source circuit, with different bias conditions for the FETs achieved through resistor voltage division. A single-stage amplifier circuit with RF potential boost is designed at the output stage to reduce input DC blocking by raising the RF potential, and the traditional choke filtering function is replaced by resistor voltage division. A grounded load is designed at the differential terminal of the output stage to match the circuit balance. A reasonable filter circuit can also be designed to reduce crosstalk between different potentials.
[0042] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A double-balanced mixer, characterized in that, include: RF planar balun, local oscillator planar balun, FET ring mixer core, first FET and second FET; The input terminal of the local oscillator plane balun is used to receive the local oscillator signal; the two output terminals of the local oscillator plane balun are connected to the drain of the FET in the FET ring mixer core; The input terminal of the radio frequency plane balun is used to receive radio frequency input signals; The two output terminals of the radio frequency planar balun are respectively connected to the gates of the first FET and the second FET, the sources of the first FET and the second FET are grounded, and the drains of the first FET and the second FET are connected to the source of the FET in the FET ring mixer core. In the FET ring mixer core, the drain of the FET transistor is connected to the intermediate frequency signal output terminal.
2. The double-balanced mixer as described in claim 1, characterized in that, The FET ring mixer core includes a third FET, a fourth FET, a fifth FET, and a sixth FET; One output terminal of the local oscillator plane balun is connected to the gates of the third FET and the sixth FET, and the other output terminal is connected to the gates of the fourth FET and the fifth FET. The drain of the first FET is connected to the source of the third FET and the fourth FET, and the drain of the second FET is connected to the source of the fifth FET and the sixth FET. The drains of the third, fourth, fifth, and sixth FETs are connected to the intermediate frequency signal output terminal.
3. The double-balanced mixer as described in claim 1 or 2, characterized in that, The two output terminals of the local oscillator planar balun are connected to the first bias voltage. The two outputs of the RF planar balun are connected to a second bias voltage.
4. The double-balanced mixer as described in claim 2, characterized in that, The drains of the third and fifth FETs are grounded, and the drains of the fourth and sixth FETs are connected to the intermediate frequency signal output terminal through an amplifier.
5. The double-balanced mixer as described in claim 4, characterized in that, The amplifier includes: a seventh FET and a third bias power supply; The drains of the fourth FET and the sixth FET are connected to the gate of the seventh FET; the gate and drain of the seventh FET are connected to the third bias power supply, and the source is connected to the intermediate frequency signal output terminal.
6. The double-balanced mixer as described in claim 4, characterized in that, Also includes: Eighth FET; The drains of the third FET and the fifth FET are connected to the gate of the eighth FET; The gate and drain of the eighth FET are connected to the third bias power supply, and the source is grounded.
7. The double-balanced mixer as described in claim 5, characterized in that, The source of the seventh FET is connected to the intermediate frequency signal output terminal in one way, and grounded through a resistor in the other way.
8. The double-balanced mixer as described in claim 6, characterized in that, The source of the eighth FET is grounded through an inductor and a resistor in one path, and through a resistor in the other path.
9. The double-balanced mixer as described in claim 1, characterized in that, The sources of the first FET and the second FET are grounded through an inductor and a resistor.
10. The double-balanced mixer as described in claim 1, characterized in that, The FET transistors in the FET ring mixer core are all of gallium arsenide-high electron mobility transistor technology.