Rapid detection system, method and equipment for process level switch of intelligent substation

Abstract

The invention relates to the technical field of intelligent substations, in particular to a rapid detection system, method and equipment for a process level switch of an intelligent substation, and aims to solve the problem that existing detection only depends on network transmission performance indexes and cannot comprehensively evaluate the business function correctness and operation reliability of the switch. The system, the method and the equipment comprise a power system fault scene modeling and message generation unit, a high-precision synchronous message injection and capture unit, a multi-dimensional state association and comprehensive judgment unit and a diagnosis report generation unit. According to the scheme, comprehensive detection, high-fidelity scene and deep diagnosis are realized, and service reliability determinacy evaluation is provided.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of intelligent substation, and in particular, relates to an intelligent substation process layer switch rapid detection system, method and device. BACKGROUND

[0002] With the rapid development of modern power systems and the profound changes in energy structure, the intelligentization, automation and informatization of power grids have become an irreversible trend of the times. As the core physical node of building a strong smart grid, the safe, stable and efficient operation of the intelligent substation is the cornerstone of ensuring the reliability of the entire power system. Compared with traditional substations, the intelligent substation takes the IEC 61850 series standards published by the International Electrotechnical Commission (IEC) as the technical framework, and through the deployment of advanced sensors, intelligent electronic devices (IEDs) and high-speed optical fiber communication networks, it realizes the overall digitization of station information, the standardization of device functions and the unification of communication protocols. In this new architecture, the process layer is in a pivotal position connecting primary devices and secondary devices, responsible for collecting real-time state quantities from mutual inductors, circuit breakers and other primary devices, and converting them into standard sampling value (SV) messages and general object-oriented substation event (GOOSE) messages, which are transmitted to the protection and control devices in the bay layer through the process layer network. Therefore, the stability and correctness of the performance of the industrial Ethernet switch, which is the core of data exchange in the process layer, directly determines whether the protection and control logic of the entire substation can be accurately and timely triggered and executed.

[0003] In the practice of intelligent substation construction, acceptance and post-operation maintenance, comprehensive and accurate detection of the process layer switch is a key link to ensure system safety. Currently, the mainstream detection method for this type of switch in the field is usually to draw lessons from the network device testing paradigm in the traditional information technology (IT) field, and to use professional network test instruments to build an isolated test environment in the laboratory or on site. Specifically, the tester will connect the switch under test with the test instrument, simulate the generation of SV and GOOSE message flows in accordance with the IEC 61850 standard format, and set different network load conditions, such as full load flow, burst flow or background flow, etc. In this process, the core purpose of the test is to quantitatively evaluate the key performance indicators (KPIs) of the switch in the data forwarding layer, mainly including message throughput, end-to-end forwarding delay, delay jitter and frame loss rate, etc. This performance parameter-based testing method has indeed effectively solved the verification problem of the basic forwarding capability of the switch in the early stage of the development of intelligent substations, providing an important quantitative basis for device selection and network access permission, and to some extent, ensuring the physical basis of process layer network communication.

[0004] With the deepening of the application scenarios of smart substations and the increasing requirements for system reliability under extreme conditions, the above detection methods, which follow the ideas of the IT field and simply focus on network transmission performance, gradually show their inherent limitations at the principle level. The reason for this is that this testing paradigm regards the process layer switch as a single-function "black box" data pipeline, and its evaluation dimension is only limited to whether the data can be "fast" and "lossless" forwarded, but it seriously ignores the specific business logic and functional correctness that the switch as an organic part of the smart substation must meet. This deep-seated contradiction is reflected in that a switch that performs well in performance indicator testing may still have hidden functional defects under the complex electromagnetic environment and specific business logic in actual operation. For example, this testing method cannot effectively verify whether the switch's guarantee capability for GOOSE message priority (QoS) is always effective under various abnormal traffic impacts, and it is also difficult to deeply detect the robustness of its key functions such as processing of virtual local area network (VLAN) tags, multicast address filtering, and accurate coordination with station clock synchronization protocols (such as PTP). These functional correctness is exactly the fundamental that determines whether the protection action can be reliably linked within microseconds. Although the existing test instruments can generate a large number of messages, the content and timing relationship of the messages are often mechanical and homogeneous, and cannot truly simulate the complex message storm scenario of multiple IEDs in short time under the condition of power system fault. Therefore, the switch tested by this "performance standard" test may delay or lose the key protection message due to its inability to correctly process specific message sequences or priority relationships when a real fault occurs, thus causing protection rejection or misoperation, which poses a great threat to the safety of the power grid. The "fault" between the detection result and the actual operation reliability makes the existing detection method provide a "false sense of security", and its rapidity is at the expense of the depth and comprehensiveness of the detection.

[0005] How to go beyond the current single detection dimension that only focuses on the performance indicators of the network physical layer and the data link layer, and build a multi-dimensional comprehensive criterion system that can deeply integrate network performance evaluation and substation-specific business logic verification, so as to realize the rapid, accurate and comprehensive detection and evaluation of the process layer switch at both functional and performance levels, and truly ensure its operation reliability under various complex conditions, has become a key challenge and technical problem to be solved for those skilled in the art. SUMMARY

[0006] The technical problem to be solved by the present application is to overcome the limitation of the prior art that only relies on network transmission performance indicators to detect the process layer switch of the intelligent substation, which leads to the inability to comprehensively evaluate the correctness of the service function and the operation reliability of the switch under real power system faults. To this end, the present application provides a kind of intelligent substation process layer switch fast detection system, method and equipment, which aims to build a comprehensive evaluation system deeply integrating specific business logic of power system and network performance test, and realize comprehensive, accurate and automatic detection of the function and performance of the measured switch under complex working conditions.

[0007] To achieve the above-mentioned application purpose, a technical solution provided by the present application is: a kind of intelligent substation process layer switch fast detection system, system includes: power system fault scene modeling and message generation unit, high-precision synchronous message injection and capture unit, multi-dimensional state association and comprehensive decision unit and diagnostic report generation unit.

[0008] The power system fault scene modeling and message generation unit is used to generate a group of IEC 61850 standard message sequences with high fidelity that completely reproduce the real power system fault scene in time, content and logic according to the preset power system model and fault parameters. The input end of the unit receives power grid topology data, protection device setting configuration data and fault event definition parameters; the output end generates sample value (SV) message stream conforming to IEC 61850-9-2 standard and general object-oriented substation event (GOOSE) message stream conforming to IEC 61850-8-1 standard containing accurate time stamps, and transmits the message sequence data to the high-precision synchronous message injection and capture unit.

[0009] The high-precision synchronous message injection and capture unit is used to connect the measured switch (SUT) to a precisely controllable test environment, and strictly according to the time stamp of the message sequence generated by the power system fault scene modeling and message generation unit, inject the message from the specified port to the measured switch, and capture all output messages with high precision at all output ports of the measured switch. The unit includes a plurality of test ports physically connected to the ports of the measured switch, and is internally provided with a local high-precision clock that maintains nanosecond-level synchronization with an external time synchronization source (such as PTP master clock), to ensure the absolute accuracy and consistency of the message injection and capture time stamp. The injected message sequence constitutes a test stimulus for the measured switch, and the captured message sequence constitutes an original response record of the behavior of the measured switch.

[0010] The multi-dimensional state correlation and comprehensive decision unit is the core of the application. Its function is to receive the original injection message sequence (as a reference) and the captured message sequence (as a response) from the high-precision synchronous message injection and capture unit, and combine the active detection data of the internal running state of the measured switch, to comprehensively analyze and judge the behavior of the measured switch from four dimensions of transmission integrity, functional logic correctness, causal timing consistency and internal state stability. The output of the unit is a set of structured and quantitative decision result data, which represents the specific behavior of the measured switch under the simulated fault scenario.

[0011] The diagnosis report generation unit integrates, analyzes and visualizes the decision result data output by the multi-dimensional state correlation and comprehensive decision unit, and generates a detailed detection report that can be interpreted by technical personnel. The report not only contains traditional performance index statistics, but more importantly, clearly points out any functional defects or performance bottlenecks exposed by the measured switch in the simulated fault scenario, and provides the exact time point, associated messages and state data that cause the defect for deep fault tracing.

[0012] Further, the power system fault scenario modeling and message generation unit specifically includes: a power grid topology and device model database, a fault event parameterization configuration module, an electro-mechanical-electromagnetic transient joint simulation engine, and an IEC 61850 message encoding and timing generation module.

[0013] The power grid topology and device model database is used to store the intelligent substation full-station configuration description file (SCD) conforming to the Common Information Model (CIM) standard, which solidifies the primary device wiring relationship of the substation, the functional logic configuration of the secondary device IED, the data set definition, and the control block parameters of GOOSE and SV.

[0014] The fault event parameterization configuration module provides a man-machine interactive interface, allowing test personnel to set specific fault scenarios, including but not limited to: fault type (such as single-phase grounding, three-phase short circuit, oscillation, etc.), fault occurrence location (accurate to a specific line or bus), fault start time, fault duration and transition resistance value.

[0015] The electro-mechanical-electromagnetic transient joint simulation engine is the physical basis for generating message content. The engine receives fault event parameters and calls the power grid model in the database to calculate the voltage and current instantaneous waveforms of each electrical node in the station during the fault period by solving the power system differential algebraic equation set. The simulation step of the simulation engine is set to no more than 10 microseconds to ensure accurate capture of high-frequency transient processes.

[0016] IEC 61850 message encoding and timing generation module, receives the instantaneous waveform data from the simulation engine, and according to the merging unit (MU) configuration defined in the SCD file, the simulated voltage and current waveforms are sampled and encoded according to the IEC 61850-9-2 LE specification to generate a series of SV messages with continuous sampling count values (smpCnt) and accurate time stamps. At the same time, according to the protection IED logic defined in the SCD file (such as overcurrent protection, differential protection), the simulation waveform is judged in real time whether it triggers the protection setting value, and once it is triggered, the logic processing delay of the IED is simulated, and the GOOSE message conforming to the IEC 61850-8-1 specification is generated. The content (such as the change of stNum, sqNum, and trip signal setting) and the publishing timing of the message strictly follow the behavior mode of the real IED. Finally, all generated SV and GOOSE messages are integrated into a unified message sequence file based on absolute time, which constitutes the "script" of the subsequent injection test.

[0017] As a preferred embodiment of the application, the high-precision synchronous message injection and capture unit is implemented based on a field programmable gate array (FPGA) platform to eliminate the time uncertainty caused by general operating systems and processors. The unit specifically includes a central clock synchronization module, a multi-channel optical transceiver interface module, a DMA-based message injection scheduler, and a line-speed capture and hardware timestamp module.

[0018] The central clock synchronization module is connected to an external IEEE 1588 (PTP) master clock through a dedicated network interface and implements a PTP slave clock protocol stack. The module generates a local high-precision reference clock within the FPGA with a synchronization deviation of less than 10 nanoseconds from the master clock, which is distributed to all logic modules within the unit that require a time reference.

[0019] The multi-channel optical transceiver interface module is configured with multiple pluggable optical modules (SFP / SFP+) cages, supporting 100 / 1000Mbps rates, for physical connection with the fiber ports of the measured switch.

[0020] The DMA-based message injection scheduler first loads the message sequence file into the FPGA on-chip or on-board dedicated SDRAM through a high-speed bus. Then, a hardware state machine continuously compares the count value of the current local high-precision clock with the timestamp of the next message to be sent stored in the SDRAM. When the two are equal, the scheduler sends the message data from the SDRAM to the MAC controller of the specified port for transmission through direct memory access (DMA) technology without CPU intervention, ensuring that the message injection time error is within tens of nanoseconds.

[0021] Line-speed capture and hardware timestamp module, real-time monitoring of physical layer (PHY) received data of all test ports. Once the start delimiter (SFD) of a valid data frame is detected, a dedicated hardware timestamp logic unit latches the 64-bit count value of the current local high-precision clock and stores the timestamp together with the captured complete packet frame data in a large-capacity FIFO capture buffer. This hardware timestamp mechanism below the data link layer avoids any delay and jitter caused by upper protocol stack processing, ensuring the highest fidelity of the captured timestamp.

[0022] Specifically, the multi-dimensional state correlation and comprehensive decision unit is the technical core of the application, which internally integrates a series of analysis engines to cooperatively complete the in-depth analysis of the behavior of the measured switch. The unit includes: a switch internal state active detection module, a transmission performance quantization analysis engine, a service function logic consistency verification engine, a power system causal time sequence correlation analysis engine, and a cross-domain data correlation and fault diagnosis engine.

[0023] The switch internal state active detection module is connected to the management port of the measured switch through a separate management network interface. During the test, the module periodically sends a simple network management protocol (SNMP) GET request packet to the measured switch according to a preset strategy, or executes a state query command through a command line interface (CLI). The objects of its query are key parameters that can reflect the internal resource usage and function state of the switch, including but not limited to: the input / output queue depth of each port, the packet count and packet loss count of each priority queue, the bandwidth utilization of the port, the CPU occupancy, the memory usage, the VLAN forwarding table item, the multicast group forwarding table item, and the PTP clock synchronization state parameters (such as the offset from the master clock, the path delay, etc.). All the queried state data are attached with accurate timestamps to form a time sequence of the internal state of the switch parallel to the packet capture data.

[0024] The transmission performance quantization analysis engine performs basic network performance evaluation. It compares the original injected packet sequence with the captured packet sequence one by one, and for each successfully forwarded packet, it calculates the end-to-end forwarding delay by calculating the difference between its capture timestamp and injection timestamp. By analyzing the delay variation of a group of key packets (such as consecutive GOOSE trip packets), the delay jitter is calculated. By counting the missing injected packets in the captured sequence, the frame loss rate is calculated. Unlike existing technologies, the analysis of the application is based on specific fault scenarios, which can quantify the performance indicators of key packets (rather than general traffic) under service impact.

[0025] Business function logic consistency check engine, which focuses on verifying whether the switch correctly implements the key network functions required by IEC 61850. The engine performs the following check logic: Quality of service (QoS) priority guarantee check: In the simulated fault scenario, there will be a time when high-priority GOOSE messages and a large number of low-priority SV messages are transmitted concurrently. This engine identifies these concurrent events and checks whether the tested switch preferentially forwards GOOSE messages with high-priority tags (such as PCP values of 6 or 7 in the VLAN header). The basis for the decision is that the forwarding delay of the GOOSE message must be significantly lower than the forwarding delay of the lower-priority SV message injected at the same time, and must be within an absolute low-delay threshold (such as less than 5 microseconds).

[0026] Virtual local area network (VLAN) isolation check: This engine extracts the VLAN IDs of all messages from the injected message sequence and determines, according to the standard definition, that messages carrying a specific VLAN ID should only appear on certain specific egress ports of the tested switch. Subsequently, the engine checks the captured message sequence to verify whether messages of the VLAN ID have been captured on unauthorized ports. Any such event is considered a failure of the VLAN isolation function.

[0027] Multicast filtering correctness check: Both GOOSE and SV messages use layer 2 multicast for transmission. This engine analyzes the destination MAC address (which is a multicast address) of the injected messages and determines, according to IGMP Snooping or static multicast table configuration, the set of ports through which the multicast stream should be forwarded. The engine verifies whether the multicast stream is accurately forwarded only to the above-mentioned port set by analyzing the captured data. Any forwarding to non-subscription ports (i.e., multicast flooding) is considered a functional defect.

[0028] The power system causal time sequence correlation analysis engine is a key innovation of the application. It promotes the detection from the network level to the power system business logic level. The engine first constructs an expected event causal graph according to the physical process and protection logic of the fault scene. The nodes in the graph are key events, such as 'fault occurs', 'protection IED detects fault', 'protection IED sends trip GOOSE', 'circuit breaker intelligent terminal receives trip GOOSE', 'circuit breaker acts', and 'circuit breaker intelligent terminal sends position GOOSE'. The directed edges in the graph represent the causal relationship and the maximum allowed time interval between events. For example, the weight of the edge from 'protection IED sends trip GOOSE' to 'circuit breaker intelligent terminal receives trip GOOSE' is the maximum transmission time specified in the IEC 61850 standard. The engine then maps the timestamps of all captured key messages to the corresponding nodes of the causal graph, and checks whether the time difference between all adjacent nodes meets the timing constraints defined in the graph. Any violation of the causal timing constraints, such as a trip message transmission timeout or a state feedback message arriving before the trip instruction, will be identified as a serious logic processing error.

[0029] The cross-domain data correlation and fault diagnosis engine is responsible for integrating the outputs of all the above analysis engines. It aligns external message events (injection and capture), switch internal states (SNMP data), and logic decision results (function and timing verification) on a unified time axis. When an abnormal event is detected (such as a GOOSE message delay that is too large), the engine automatically traces back all dimensions of data before and after the time point to find the root cause. For example, it can find that the delay of the GOOSE message is highly correlated in time with the instantaneous filling of the output queue of the port detected by SNMP and the injection of a large amount of SV background traffic at the same time. This correlation analysis capability improves the diagnosis from 'what happened' to 'why it happened', providing direct evidence for the positioning of switch defects.

[0030] To achieve the above application purposes, another technical solution provided by the application is a multi-dimensional criterion-based intelligent substation process layer switch rapid detection method. The method corresponds to the above system and includes the following steps: Step S1: Establish a test environment. Connect the switch under test to the test port of the high-precision synchronous message injection and capture unit through an optical fiber, and connect its management port to the multi-dimensional state correlation and comprehensive decision unit. Establish time synchronization between the system and the PTP master clock.

[0031] Step S2: configuring and generating fault scenarios. Through the power system fault scenario modeling and message generation unit, set the fault type, location and other parameters, generate a message sequence file containing high-fidelity SV and GOOSE messages with accurate time stamps that reproduce the fault scenario.

[0032] Step S3: performing synchronous injection and capture. The high-precision synchronous message injection and capture unit loads the message sequence file and strictly follows the time stamps in the file to inject a message stream through a specified port to the measured switch; at the same time, all output messages are captured at nanosecond level accuracy on all output ports of the measured switch, and each captured message is stamped with a hardware timestamp.

[0033] Step S4: performing state synchronization detection. While injecting and capturing messages, the multi-dimensional state association and comprehensive decision unit actively detects and records the internal key operating state parameters of the measured switch through protocols such as SNMP, forming a state time sequence.

[0034] Step S5: performing multi-dimensional association decision. After the test is completed, the multi-dimensional state association and comprehensive decision unit performs comprehensive and automated analysis on the collected injection message sequence, captured message sequence and internal state time sequence, including: calculating the transmission performance indicators of key messages; checking the logical correctness of QoS, VLAN, multicast and other functions; verifying whether the cause-effect sequence of power system business events is maintained; and associating and analyzing the external message behavior and internal state changes.

[0035] Step S6: generating a diagnostic report. The diagnostic report generation unit generates a structured comprehensive test report by summarizing all decision results, detailing the performance of the measured switch under simulated faults, and highlighting and presenting in-depth diagnostic data for any detected abnormalities.

[0036] The application also provides an intelligent substation process layer switch rapid detection device based on multi-dimensional criteria, which integrates all or part of the functional units of the aforementioned system to form a test instrument that can operate independently. The device includes a processor, a memory, and a plurality of network interfaces in communication with the processor. The memory stores a computer program that, when executed by the processor, implements all steps of the aforementioned method.

[0037] Compared with the prior art, the application has the following beneficial effects: Comprehensiveness of detection dimensions: The application breaks through the limitations of traditional methods that only focus on network forwarding performance, creatively introduces multiple detection dimensions such as functional logic correctness, cause-effect sequence consistency and internal state stability, and builds a comprehensive evaluation system.

[0038] High fidelity of test scenario: through the fault scenario generation mechanism based on the electromechanical-electromagnetic transient simulation, the application can generate the message flow highly consistent with the real power system fault, the content, timing and logical correlation of which are far beyond the mechanical flow generated by the traditional test instrument, ensuring the effectiveness and pertinence of the test.

[0039] Deepening of diagnostic capability: the application realizes the "white box" perspective of the switch behavior by synchronously detecting and correlatively analyzing the external message behavior and the internal state of the switch, can deeply go from the "what" level to the "why" level, and provides unprecedented depth for the device defect positioning.

[0040] Determinacy of evaluation result: through the strict checking of the cause-effect timing of the power system business logic, the application can directly judge whether the processing behavior of the switch will endanger the safe and stable operation of the power system, the conclusion provided by the application is no longer the fuzzy performance index, but the determinacy evaluation of the business reliability, thereby truly eliminating the "false sense of security" caused by the existing detection method. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 is a functional module block diagram of the intelligent substation process layer switch rapid detection system in an embodiment of the application.

[0042] Figure 2 is Figure 1 a specific structure block diagram of the power system fault scenario modeling and message generation unit.

[0043] Figure 3 is Figure 1 a specific structure block diagram of the high-precision synchronous message injection and capture unit.

[0044] Figure 4 is Figure 1 a specific structure block diagram of the multi-dimensional state correlation and comprehensive decision unit.

[0045] Figure 5 is a physical connection schematic diagram of the detection system in an embodiment of the application.

[0046] Figure 6 is a flowchart of the intelligent substation process layer switch rapid detection method based on multi-dimensional criteria in an embodiment of the application.

[0047] Figure 7 is a schematic diagram of the power system cause-effect timing correlation analysis in an embodiment of the application.

[0048] The reference signs are as follows: 10, power system fault scenario modeling and message generation unit; 11, power grid topology and equipment model database; 12, fault event parameterization configuration module; 13, electromechanical-electromagnetic transient joint simulation engine; 14, IEC61850 message coding and timing generation module; 20, high-precision synchronous message injection and capture unit; 21, central clock synchronization module; 22, multi-channel optoelectronic transceiver interface module; 23, DMA-based message injection scheduler; 24, line-speed capture and hardware timestamp module; 30, multi-dimensional state association and comprehensive decision unit; 31, switch internal state active detection module; 32, transmission performance quantitative analysis engine; 33, service function logic consistency verification engine; 34, power system causal timing association analysis engine; 35, cross-domain data association and fault diagnosis engine; 40, diagnosis report generation unit; S100, establishing a test environment step; S200, configuring and generating a fault scenario step; S300, executing synchronous injection and capture step; S400, executing state synchronization detection step; S500, executing multi-dimensional association decision step; S600, generating a diagnosis report step. DETAILED DESCRIPTION

[0049] To make the objectives, technical solutions, and advantages of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of protection of the present application.

[0050] Please refer to Figure 1 The intelligent substation process layer switch rapid detection system provided by the present application aims to overcome the limitation of the prior art that only relies on general network performance indicators for evaluation, and through constructing a comprehensive evaluation system that deeply integrates power system specific service logic and network performance testing, the function correctness, performance stability, and service reliability of the measured switch under simulated real power system fault working conditions are comprehensively, accurately, and automatically detected. The system logically includes a power system fault scenario modeling and message generation unit 10, a high-precision synchronous message injection and capture unit 20, a multi-dimensional state association and comprehensive decision unit 30, and a diagnosis report generation unit 40. The four units work cooperatively to constitute a complete closed-loop test and diagnosis process.

[0051] Specifically, the core function of the power system fault scenario modeling and message generation unit 10 is to build the source of test stimulus. Instead of generating indiscriminate general network traffic, it generates a set of IEC 61850 standard message sequences with extremely high fidelity in terms of time, content and logic, which can completely reproduce the dynamic process of the real power system according to the pre-set power system model and specific fault parameters. The input of this unit is the configuration data defining the physical structure and logical relationship of the power grid and the parameters describing the specific disturbance event, and its output is an integrated message sequence file containing the sampling value (SV) message stream and the general object-oriented substation event (GOOSE) message stream with precise nanosecond-level timestamps, which is then submitted to the high-precision synchronous message injection and capture unit 20.

[0052] The function of the high-precision synchronous message injection and capture unit 20 is to create an accurately controllable and repeatable physical test environment. It accesses the measured switch (SUT) as the core test object, and strictly according to the time stamp defined in the message sequence file generated by the power system fault scenario modeling and message generation unit 10, injects specific messages from the specified port into the measured switch. At the same time, the unit captures all output messages with the same high precision on all or specified output ports of the measured switch. The internal integrated local high-precision clock and external authoritative time synchronization source (such as PTP master clock based on IEEE 1588 protocol) maintain nanosecond-level synchronization, which is the technical basis for ensuring the accuracy of message injection time and the absolute accuracy and global consistency of capture timestamp. The injected message sequence constitutes the test stimulus for the measured switch, while the captured message sequence constitutes the original, unprocessed response record of its behavior.

[0053] The multi-dimensional state correlation and comprehensive decision unit 30 is the core of the technical solution of the present application, which is responsible for in-depth analysis and intelligent decision of the massive data collected during the test. The unit receives the original injection message sequence (as the ideal benchmark) and all captured message sequences (as the actual response) from the high-precision synchronous message injection and capture unit 20, and innovatively combines the data obtained by actively detecting the internal running state of the measured switch through independent management channels. The unit comprehensively analyzes the behavior of the measured switch from four mutually orthogonal dimensions, namely transmission integrity, functional logic correctness, causal timing consistency and internal state stability. The output of this unit is no longer a single performance indicator, but a set of structured, quantitative, multi-dimensional decision result data, which fully and meticulously represents the specific behavior and potential defects of the measured switch under the simulated specific fault scenario.

[0054] Finally, the function of the diagnosis report generation unit 40 is to systematically integrate and correlate the multi-dimensional state association with the complex decision result data output by the comprehensive decision unit 30, and finally generate a comprehensive detection report that is detailed, clear and directly interpretable by engineering technicians. The report not only contains statistical data such as traditional network performance indicators such as time delay, jitter, and packet loss rate, but more importantly, it can clearly point out any functional defects (such as QoS policy failure, VLAN isolation destruction) or performance bottlenecks (such as specific business flow congestion) exposed by the measured switch in the simulated fault scenario, and can provide the exact time point that caused the defect, the key message details associated with it, and the internal state data snapshot of the switch at that time, thereby providing direct and strong evidence for subsequent fault tracing and device improvement.

[0055] Further, in order to realize the above functions, the internal structure and working mechanism of each unit are designed to be more specific and fine. Please refer to Figure 2 which shows the specific composition of the power system fault scenario modeling and message generation unit 10. The unit internally integrates the power grid topology and device model database 11, the fault event parameterization configuration module 12, the electro-mechanical-electromagnetic transient joint simulation engine 13, and the IEC 61850 message encoding and timing generation module 14.

[0056] The power grid topology and device model database 11 is the basis of the entire scenario generation. Its core is to store the intelligent substation full station configuration description file (SCD) conforming to the IEC61850 standard system based on the Common Information Model (CIM). This SCD file in standardized XML format solidifies all the key information of the simulated substation, including the electrical wiring relationship of primary main devices (such as transformers, circuit breakers, disconnectors), the functional logic configuration of secondary intelligent electronic devices (IED), such as the detailed setting and logic equations of overcurrent, differential, distance, etc. protection elements in the protection IED. In addition, the file also precisely defines the content of the data set (DataSet), as well as all the parameters of the control block (SVCB and GOCB) for transmitting sampled values (SV) and general object-oriented substation events (GOOSE), such as APPID, VLAN ID, priority (PCP) and target multicast MAC address, etc.

[0057] The fault event parameterization configuration module 12 provides a graphical or command-line interface for the test engineers to precisely set up the power system fault scenarios to be simulated. The parameters that can be set by the user are very rich, covering all kinds of disturbances that can occur in real power grids. These parameters include but are not limited to: fault type, such as single-phase-to-ground, phase-to-phase short circuit, three-phase short circuit, and more complex system oscillation or asymmetric operation conditions; fault location, which can be accurately set to a specific percentage of a transmission line or a specific phase of a bus; fault start time, which can be set as an absolute time or a relative time with respect to the start of the simulation; fault duration, for example, 100 milliseconds; and fault transition resistance value, to simulate faults of different severity.

[0058] The electro-magnetic transient simulation engine 13 is the physical core that generates high-fidelity message content. The engine receives the fault disturbance defined by the fault event parameterization configuration module 12 and retrieves the complete power grid model and device parameters from the database 11. Inside, it simulates the dynamic response of the power system in the entire time range before and after the fault occurs by solving large-scale nonlinear differential algebraic equations. In order to accurately capture the voltage and current waveform distortion caused by traveling waves, high-order harmonics, etc. in the initial stage of the fault, the numerical integration step size of the simulation engine is set to a very small value, specifically, its simulation step size is not greater than 10 microseconds. This high time resolution simulation capability is the key to ensuring that the generated SV messages can truly reflect the physical nature of the fault transient process.

[0059] IEC 61850 message encoding and timing generation module 14 is responsible for converting the physical world simulation data output by the simulation engine into IEC 61850 standard messages in the digital world. It receives the voltage and current instantaneous waveform data sequences of all the key measurement points in the station from the simulation engine 13. According to the merging unit (MU) configuration defined in the SCD file, this module digitizes and encodes the simulated voltage and current waveforms according to the IEC 61850-9-2 LE (light edition) specification, generating a series of SV messages with continuously increasing sample count values (smpCnt) and accurate injection timestamps. At the same time, a logical simulator is also running in parallel inside this module, which monitors the simulation waveform data in real time according to the logic of the protection IED defined in the SCD file (e.g., the setting value of a three-phase overcurrent protection). Once the calculated current effective value exceeds the setting value of a certain protection and meets the delay requirement, the logical simulator will trigger and simulate the logical processing delay (usually a few milliseconds) inside the real IED, and then generate a GOOSE message that complies with the IEC 61850-8-1 specification. The content of this GOOSE message, such as the jump of the state number (stNum) and sequence number (sqNum), the setting of the tripping signal Boolean (from 0 to 1), and the time stamp of its publication, all strictly follow the behavior pattern of the real IED when it acts on protection. Finally, all the generated SV and GOOSE messages are integrated into a time-ordered message sequence file with absolute time as the only reference, which constitutes the accurate "script" for subsequent injection testing.

[0060] As a preferred embodiment of the present application, to completely eliminate the time uncertainties such as interrupts and scheduling delays inherent in general-purpose computer operating systems (such as Windows or Linux) and standard CPU architectures when handling real-time tasks, the high-precision synchronous message injection and capture unit 20 is implemented in hardware based on a field programmable gate array (FPGA) platform. Please refer to Figure 3 This unit specifically includes a central clock synchronization module 21, a multi-channel optoelectronic transceiver interface module 22, a DMA-based message injection scheduler 23, and a line-speed capture and hardware timestamp module 24.

[0061] The central clock synchronization module 21 is the time reference core of the whole unit. It connects to an external, high-precision IEEE 1588 (PTP) master clock through a dedicated physical network interface (such as RJ45 or SFP). Inside the FPGA, a complete PTP slave clock protocol stack hardware logic is implemented, which generates a local high-precision reference clock (for example, a 64-bit nanosecond counter) with a synchronization deviation of less than 10 nanoseconds from the master clock through continuous message exchange and algorithm calculation with the master clock. This highly stable and accurate reference clock is then distributed to all logic modules inside the FPGA that require accurate time reference, including the injection scheduler and capture timestamp unit, with extremely low delay wiring resources, ensuring the time consistency of the whole unit and even the entire test system.

[0062] The multi-channel optical transceiver interface module 22 provides physical connection with the measured switch. It is configured with multiple pluggable optical module cages on the hardware board, such as SFP or SFP+ specifications, allowing users to flexibly configure test interfaces according to the port type and rate of the measured switch. These interfaces support rates such as 100Mbps, 1000Mbps, and even 10Gbps, and are compatible with multi-mode or single-mode optical fibers, thus having the ability to seamlessly interface with current mainstream intelligent substation process layer network devices.

[0063] The DMA-based message injection scheduler 23 is the key to achieving nanosecond-level accurate message injection. Before the test starts, the controller loads the aforementioned generated message sequence file from the host memory into the FPGA's on-board dedicated large-capacity SDRAM through a high-speed bus (such as PCIe). After the test starts, a specially designed hardware state machine begins to work. The state machine continuously compares the current count value of the local high-precision clock with the target timestamp of the next message to be sent stored in the SDRAM in each clock cycle. Once they are exactly equal, the scheduler immediately triggers a direct memory access (DMA) controller. The DMA controller, without any CPU software intervention, directly reads the complete data of the message from the SDRAM and sends it to the media access control (MAC) layer's transmit FIFO of the target port at high speed, and the MAC controller completes the frame transmission. The entire process is completely automated by hardware logic, thus controlling the injection time error of the message to within tens of nanoseconds, far beyond the reach of software methods.

[0064] The line-speed capture and hardware timestamping module 24 is responsible for recording the responses of the measured switch with high fidelity. It monitors the receive data stream of the physical layer interface (PHY) of all test ports configured in capture mode in real time. Once the hardware logic detects the start of frame (SFD) byte of a valid Ethernet frame passing through, a dedicated hardware timestamping logic unit will immediately latch the 64-bit count value of the current local high-precision clock. This timestamp is then written into a large-capacity, high-speed FIFO capture buffer as a data unit together with the captured Ethernet frame data. Since the generation of the timestamp is done at the physical layer signal level below the data link layer, it completely avoids the delay and jitter caused by upper-layer protocol stack processing, memory copying or operating system interrupts, thus ensuring the highest fidelity and accuracy of the captured timestamp.

[0065] Specifically, the multi-dimensional state correlation and comprehensive decision unit 30, as the technical core of the present application, integrates a series of collaborative analysis engines inside to complete the deep and multi-dimensional analysis of the behavior of the measured switch. Please refer to Figure 4 The unit includes a switch internal state active detection module 31, a transmission performance quantization analysis engine 32, a service function logic consistency verification engine 33, a power system causal time sequence correlation analysis engine 34, and a cross-domain data correlation and fault diagnosis engine 35.

[0066] The switch internal state active probing module 31 connects to the out-of-band or in-band management port of the tested switch through a management network interface independent of the service test plane. During the entire message injection and capture test process, the module periodically sends a simple network management protocol (SNMP) GET request message to the tested switch according to a pre-set strategy (such as polling once every 100 milliseconds), or logs in to the switch through Telnet / SSH and executes a command line interface (CLI) state query command. The object of the query is those key parameters that can directly or indirectly reflect the internal resource usage and function running state of the switch, including but not limited to: the current depth of the input / output queue of each physical port, the message count and packet loss count of each priority queue (CoS 0 to 7), the real-time bandwidth utilization of the port, the CPU occupancy rate of the switch core processor, the system memory usage, the dynamically learned VLAN forwarding table (MAC-VLAN-Port), the multicast group forwarding table (MAC-Port List), and the synchronization state parameters when the switch is a PTP slave clock, such as the current offset from master (offsetFromMaster) and the average path delay (meanPathDelay). All the queried state data is attached with an accurate timestamp (homogeneous with the message capture timestamp) to form a switch internal state time series data parallel to the external message event stream.

[0067] The transmission performance quantitative analysis engine 32 performs basic but crucial network performance evaluation. It first associates and compares the original injection message sequence with the captured message sequence, and matches them through the unique identifier of the message (such as the stNum and sqNum of the GOOSE message, or the smpCnt of the SV message). For each successfully forwarded message, it obtains the end-to-end forwarding delay of the message traversing the tested switch by calculating the difference between the hardware timestamp recorded at the capture end and the original timestamp recorded at the injection end. By analyzing the delay sequence of a group of key messages with inherent correlation (for example, continuously issued GOOSE trip messages with increasing sqNum), the jitter can be calculated. By counting the number of messages that exist in the injection sequence but are missing in the capture sequence, the frame loss rate can be accurately calculated. Unlike existing technologies that simply use general traffic for testing, the analysis of the present application is based on specific power system fault scenarios, so it can quantify the real performance indicators of those messages that are crucial to system safety (rather than meaningless background traffic) under real service impact.

[0068] The business function logic consistency verification engine 33 focuses on verifying whether the tested switch correctly and efficiently performs the key network functions required by the smart substation process level network, which are the basis for ensuring the correct operation of the power system business. The engine specifically performs the following core verification logic: First, quality of service (QoS) priority guarantee verification. In the simulated fault scenario, there will be a time when high-priority GOOSE messages (for example, the PCP value in the VLAN header is usually set to 6 or 7) and a large number of low-priority SV messages (the PCP value is usually set to 4) are injected concurrently. The engine automatically identifies these key concurrent events and checks whether the tested switch complies with the IEEE 802.1p standard to prioritize and forward high-priority GOOSE messages. The basis for its decision is twofold: first, the forwarding delay of the GOOSE message must be significantly lower than the average forwarding delay of the lower-priority SV message injected in the same microsecond or millisecond time window; second, the absolute forwarding delay of the GOOSE message must be within a very low hard threshold (for example, according to the IEC 61850-5 standard requirement, less than 5 microseconds). Second, virtual local area network (VLAN) isolation verification. The engine extracts the VLAN ID of all messages from the injected message sequence and determines, according to the substation network plan, that messages carrying a specific VLAN ID should only appear on certain specific out ports of the tested switch. Subsequently, the engine traverses all captured message sequences to verify whether messages belonging to the VLAN ID are captured on unallowed ports. Any such event will be judged as a failure of the VLAN isolation function, which is a serious safety hazard in the substation environment. Third, multicast filtering correctness verification. GOOSE and SV messages are transmitted using layer 2 multicast. The engine parses the multicast address in the injected message as the destination MAC address and determines, according to the IGMP Snooping or static multicast table settings in the network configuration, the set of target ports to which the multicast stream should be forwarded. The engine verifies whether the multicast stream is accurately and only forwarded to the above-mentioned expected port set by analyzing the captured data of all out ports. Any unnecessary forwarding (i.e., multicast flooding) of the multicast stream to ports that do not subscribe to the multicast is considered a functional defect, as it unnecessarily occupies the bandwidth and processing resources of other ports.

[0069] The power system causal timing correlation analysis engine 34 is a key innovation of the present application compared to traditional network testers, which raises the detection dimension from the isolated network level to the tightly coupled power system business logic level. Please refer to Figure 7The engine first automatically builds an expected event causal graph before the test starts, according to the physical processes and protection and control logic of the fault scenario used for the test. The nodes in the graph represent a series of key events that occur during the fault in the power system, such as "T0: Metallic short circuit occurs on line F1", "T1: Protection IED A on line F1 detects overcurrent", "T2: Protection IED A sends trip GOOSE message G1", "T3: Intelligent terminal of circuit breaker CB1 receives trip GOOSE message G1", "T4: Physical tripping action of circuit breaker CB1 is completed", and "T5: Intelligent terminal of circuit breaker CB1 sends position GOOSE message G2 to feedback the status". The directed edges in the graph represent the necessary causal relationship between the events and the maximum allowed time interval. For example, the weight of the edge from event T2 to T3 is the maximum allowed network transmission time (e.g. 3 milliseconds) for this type of GOOSE message as specified in the IEC 61850 standard. After the test is completed, the engine maps the precise timestamps of all the key messages (such as G1 and G2) captured during the test to the corresponding nodes in the causal graph, forming the actual event occurrence time sequence. Then, the engine strictly checks whether the actual time difference between all adjacent nodes meets the predefined timing constraints in the graph. Any violation of the causal timing constraints, such as the transmission time of trip message G1 exceeding 3 milliseconds, or more seriously, the status feedback message G2 that should be sent after the circuit breaker action arriving earlier than the trip command message G1, will be identified as a serious logic processing error that directly threatens the safety of the power system.

[0070] The cross-domain data correlation and fault diagnosis engine 35, which plays the role of "chief diagnostic officer", is responsible for the final synthesis and deep mining of the outputs of all the above analysis engines. It accurately aligns external message events (time and content of injection and capture), internal switch states (CPU, memory, queue depth data from SNMP probes), and upper-layer logical decision results (such as function verification failure or timing violation) on a unified and high-precision time axis. When an abnormal event is detected, for example, the power system causal timing correlation analysis engine 34 reports that the transmission delay of a certain key GOOSE message has reached an abnormal 20 microseconds, the engine will immediately automatically backtrack all dimensions of data before and after the abnormal event occurrence time point (for example, within a range of 500 microseconds before and after), to find potential root causes. For example, it may find that: the delay of the GOOSE message is highly correlated in time with the phenomenon that the high-priority output queue depth of its out-port detected by SNMP probe instantaneously fills from 5% to 98%, and the CPU utilization of the switch increases from 10% to 85%. Further correlation of the injected message data finds that at this moment, a sudden burst of large-flow SV background message storm is injected into other ports of the switch. Through such automatic correlation analysis of cross-domain data, the engine can draw a highly accurate diagnosis conclusion: "the GOOSE message transmission timeout is caused by the instantaneous bottleneck of internal processing resources (queue cache or CPU) of the switch under the impact of large-flow SV background traffic, resulting in the failure of QoS strategy to fully guarantee the priority passing of high-priority messages." This powerful correlation analysis capability deepens the diagnosis from the surface level of "what abnormality has occurred" to the root cause level of "why it has occurred", providing unprecedented direct evidence for the positioning and optimization of switch hardware and software defects.

[0071] To achieve the above object, the application provides another technical scheme: a multi-dimensional criterion-based intelligent substation process layer switch rapid detection method. Please refer to Figure 6 The method corresponds to the above system and includes the following steps: Step S100: Establish a test environment. This step physically connects the service ports of the switch under test (SUT) to the multiple test ports of the high-precision synchronous message injection and capture unit 20 through optical fibers. At the same time, the management ports of the switch under test are connected to the control network interface of the multi-dimensional state correlation and comprehensive decision unit 30 through a separate network cable. Finally, ensure that the entire test system and the external PTP master clock establish stable and reliable time synchronization, so that all time stamps in the system are based on the same time reference.

[0072] Step S200: Configuration and generation of fault scenarios. The tester sets a specific test scenario through the interactive interface of the power system fault scenario modeling and message generation unit 10. For example, set as "220 kV substation II bus B phase grounding fault, fault start time is 2 seconds after the simulation starts, lasts for 120 milliseconds, transition resistance is 5 ohms". The unit then calls the corresponding power grid model, performs transient calculation through the simulation engine 13, and generates a message sequence file that reproduces the complete fault scenario, contains high-fidelity SV and GOOSE messages, and has nanosecond-level accurate time stamps.

[0073] Step S300: Perform synchronous injection and capture. The high-precision synchronous message injection and capture unit 20 loads the message sequence file generated in the previous step. After the test starts, its internal injection scheduler 23 strictly follows the time stamp of each message in the file and injects the message stream into the tested switch through the specified port. At the same time, its line-speed capture and hardware timestamp module 24 captures all output messages with nanosecond-level precision on all output ports of the tested switch, and applies accurate hardware timestamps to each successfully captured message frame, and stores them in the capture buffer.

[0074] Step S400: Perform state synchronization detection. While the message injection and capture process of step S300 is ongoing, the switch internal state active detection module 31 in the multi-dimensional state correlation and comprehensive decision unit 30 works in parallel. It actively detects and records a series of internal key running state parameters of the tested switch, such as CPU occupancy, memory usage, and port queue state, through the management network, periodically (e.g. every 50 milliseconds), and timestamps each set of collected data to form an internal state time sequence that is accurately aligned in time with the message capture data.

[0075] Step S500: Perform multi-dimensional correlation decision. After the test is completed, the multi-dimensional state correlation and comprehensive decision unit 30 starts all its internal analysis engines to perform comprehensive and automated offline or online analysis on all the data collected during the test - namely the original injection message sequence, the captured message sequence with timestamps, and the internal state time sequence with timestamps. The specific analysis content is as described above, including calculating the transmission performance indicators (delay, jitter, packet loss) of key messages; verifying the logical correctness of network functions such as QoS, VLAN, and multicast; verifying whether the cause-and-effect timing of power system protection and control business events is strictly maintained; and performing deep correlation analysis between external message behavior abnormalities (if any) and internal state changes to find the root cause.

[0076] Step S600: generating a diagnosis report. Finally, the diagnosis report generating unit 40 aggregates the decision results of all analysis engines to generate a structured and illustrated comprehensive detection report. The report clearly lists the performance of the measured switch under the simulated specific fault scenario, highlights all detected functional defects, performance bottlenecks or timing violation events, and provides detailed diagnosis data, including the time point of the problem, the relevant message content, the internal state snapshot of the switch at that time, etc., for the user to make the final evaluation and decision.

[0077] The present application also provides a multi-dimensional criterion-based intelligent substation process layer switch rapid detection device, which physically integrates all or part of the functional units of the aforementioned system to form a portable or rack-mounted, independently-operable test instrument. The device includes a high-performance processor (such as a multi-core CPU), a large-capacity memory (RAM and SSD), and a plurality of high-speed network interfaces (for service testing and management control) in communication connection with the processor. The memory stores a computer program, which, when executed by the processor, can completely implement all steps of the aforementioned detection method, providing a one-stop test solution for users.

[0078] Embodiment To more specifically illustrate the technical effects brought by the technical solutions of the present application, a specific embodiment is given below.

[0079] Test object and environment Measured switch (SUT): a certain brand of industrial process layer switch, model SW-PL24G, with 24 1Gbps fiber SFP ports, supporting IEEE 802.1p / Q, IGMP Snooping v2, IEEE 1588v2 PTP, etc.

[0080] Test system: the intelligent substation process layer switch rapid detection system of the present application.

[0081] Time synchronization: the test system and the SUT are connected to the same high-precision PTP master clock (Meinberg LANTIMEM1000), with a synchronization accuracy better than ±50ns.

[0082] Physical connection: the four injection ports of the test system are connected to Port1 to Port4 of the SUT; all 24 ports of the SUT are connected to the capture ports of the test system; the management port of the test system is connected to the management port of the SUT.

[0083] Fault scenario setting (step S200) Power grid model: a typical 220kV double-bus wiring substation SCD file.

[0084] Fault event: A B, C phase metallic short circuit fault is set at T = 10.000000000 seconds, at 80% of the distance from the bus to one of the outgoing lines L1, with a fault duration of 150 ms.

[0085] Expected behavior: This fault will trigger the distance protection I segment of line L1 to act. The protection IED (logical node LN: PDIS1) installed on the side of line L1 should send a trip GOOSE message within about 20 ms after the fault occurs, with a VLAN ID of 101, a PCP of 6, and a target multicast MAC of 01-0C-CD-01-00-10. This GOOSE message should be forwarded by the SUT to the intelligent terminal connected to circuit breaker CB1 (connected to Port 10 of the SUT). At the same time, all merging units (MUs) in the station will continuously send SV message streams, and during the fault period, the current sampling value in the SV message related to the fault line will increase sharply.

[0086] Test execution and analysis (steps S300-S500) Injection and capture: The system injects SV and GOOSE mixed traffic containing the above fault information from Ports 1-4 to the SUT according to the generated script file. The total background SV traffic is about 3.2 Gbps.

[0087] State detection: The system polls the CPU utilization, memory occupation, and queue depth of each port of the SUT at an interval of 50 ms.

[0088] Multi-dimensional decision: Transmission performance analysis: After analysis, the key trip GOOSE message (stNum changes from 1 to 2) is injected from Port 2 at T_inject = 10.020150000 s and captured at Port 10 at T_capture = 10.020153850 s. The calculated end-to-end forwarding delay is 3.85 µs.

[0089] Business function logic verification: QoS verification: In the time window around T = 10.020150 s, the average delay of the background SV message (PCP = 4) injected simultaneously with the GOOSE message (PCP = 6) is 22.5 µs. The GOOSE delay is much lower than the SV delay, and the absolute value is less than 5 µs, so the QoS priority guarantee function verification is passed.

[0090] Multicast Check: Analyzing the data of all capturing ports, it is found that the GOOSE message with destination MAC 01-0C-CD-01-00-10 is only captured at Port 10 (which is configured as a member of this multicast group) and does not appear on any other non-subscribed port. The multicast filtering function check is passed.

[0091] Causal Timing Correlation Analysis: The established causal graph requires that the time interval from "Protection IED sends trip GOOSE" to "Circuit Breaker Intelligent Terminal receives trip GOOSE" be less than 3 ms.

[0092] The actual detected network transmission delay is 3.85 µs, which is much smaller than the standard requirement of 3 ms. The causal timing consistency check is passed.

[0093] Cross-domain Data Correlation Diagnosis: At time T = 10.100000000 s, a sudden, 5 ms long, 4 Gbps rate SV traffic impact is simulated. The analysis engine detects that during this period, a regular GOOSE heartbeat message injected has its delay increased to 18.6 µs. The cross-domain diagnosis engine immediately correlates to the internal state data at this time point and finds that the CPU utilization of the SUT instantaneously rises from 15% to 92%, and the priority 6 queue depth of Port 10 reaches the maximum value of 95%. The diagnosis conclusion is: When facing an extreme traffic impact that exceeds its line speed processing capability, the internal processing capability of the SUT appears bottlenecked, causing high-priority queue congestion and temporary decline in QoS guarantee capability.

[0094] Comparative Example The same SUT is tested using a traditional network performance tester (such as a tester based on the RFC 2544 standard).

[0095] Test Method: The tester injects Ethernet frames of a fixed size (such as 128 bytes) into the SUT at Port 1 and receives them at Port 10. By gradually increasing the injection rate, the throughput, delay, and packet loss rate are tested.

[0096] Test Results: The tester reports that under a 95% 1 Gbps line speed load, the average forwarding delay of the SUT is 4.5 µs, and the packet loss rate is 0. According to the RFC 2544 standard, the performance of the SUT is "excellent", and the test is "passed".

[0097] By the contrast of the above examples and the comparative examples, it can be clearly seen that the system and method proposed in the application can discover deep functional defects and performance bottlenecks closely related to the safe operation of the power system which cannot be touched by the traditional testing methods by introducing multi-dimensional and deeply fused service logic criteria, thereby providing the network access acceptance and operation and maintenance of the process layer network equipment of the intelligent substation with unprecedented, more comprehensive and reliable technical support.

Claims

1. A rapid detection system for process layer switches in intelligent substations, characterized in that, include: The power system fault scenario modeling and message generation unit (10) is used to generate a message sequence that reproduces the real power system fault scenario in terms of content, timing and logic, based on the preset power system model and fault event definition parameters. It includes sampled value (SV) message stream with precise timestamp and general object-oriented substation event (GOOSE) message stream. The high-precision synchronous message injection and capture unit (20) is connected to the port of the switch under test. It is used to receive message sequences and inject messages into the designated input port of the switch under test according to the precise timestamp of each message in the message sequence. At the same time, it captures all output messages at the output port of the switch under test with high precision and adds a capture timestamp to each captured message, thereby generating the original injected message sequence and the captured message sequence. The multidimensional state association and comprehensive decision unit (30) is used to receive the original injected message sequence and the captured message sequence, and combine the active detection data of the internal operating state of the switch under test to comprehensively analyze and decide the behavior of the switch under test from four dimensions: transmission integrity, functional logic correctness, causal timing consistency and internal state stability, and output structured decision result data. The diagnostic report generation unit (40) is used to receive the judgment result data, integrate and visualize it, and generate a test report that points out the functional defects or performance bottlenecks exposed by the switch under test in the simulated fault scenario.

2. The system according to claim 1, characterized in that, The power system fault scenario modeling and message generation unit (10) specifically includes: The power grid topology and equipment model database (11) is used to store the smart substation full-station configuration description file (SCD) containing the wiring relationship of primary equipment, functional logic configuration of secondary equipment, dataset definition, and GOOSE and SV control block parameters of the substation. The fault event parameterization configuration module (12) is used to provide a human-machine interaction interface for setting fault scenario parameters including fault type, fault location, fault start time, fault duration and transition resistance value. The electromechanical-electromagnetic transient joint simulation engine (13) is used to receive fault scenario parameters and call the power grid model in the database (11). By solving the differential algebraic equations of the power system, it can accurately calculate the voltage and current instantaneous waveforms of each electrical node in the entire station during the fault. The IEC 61850 message encoding and timing generation module (14) is used to receive instantaneous waveform data and, according to the configuration in the SCD file, encode the waveform data into an SV message with a sample count value (smpCnt) and a precise timestamp, and generate a GOOSE message whose content and timing conform to the behavior mode of the real device based on whether the simulated waveform triggers the protection setting.

3. The system according to claim 2, characterized in that, When generating GOOSE messages, the IEC 61850 message encoding and timing generation module (14) is also configured to: determine in real time whether the simulated waveform triggers the protection setting based on the protection IED logic defined in the SCD file; when it is determined to be triggered, the internal logic processing of the simulated protection IED is delayed, and then a GOOSE message conforming to the IEC 61850-8-1 standard is generated. The content of the GOOSE message accurately reflects the transition of the status number (stNum) and sequence number (sqNum) and the setting of the trip signal Boolean value.

4. The system according to claim 1, characterized in that, The high-precision synchronization message injection and capture unit (20) is implemented based on a field-programmable gate array (FPGA) platform and specifically includes: The central clock synchronization module (21) is used to connect to an external IEEE 1588 (PTP) master clock and implement the PTP slave clock protocol stack to generate a local high-precision reference clock that is synchronized with the master clock at the nanosecond level inside the FPGA. A multi-channel optoelectronic transceiver interface module (22) is used to provide a pluggable optical module interface for physical connection with the port of the switch under test; The DMA-based message injection scheduler (23) is used to load the message sequence into the memory and continuously compare the current value of the local high-precision reference clock with the timestamp of the next message to be sent through the hardware state machine. When the two are equal, the message data is sent to the specified port for transmission through direct memory access (DMA) technology. The line-rate capture and hardware timestamp module (24) is used to monitor the physical layer received data of all test ports in real time, and latch the current count value of the local high-precision reference clock as the capture timestamp when the start delimiter (SFD) of a valid data frame is detected.

5. The system according to claim 4, characterized in that, The DMA-based message injection scheduler (23) is configured to load the message sequence file into the dedicated SDRAM on the FPGA board via a high-speed bus. Its hardware state machine is configured to perform comparison and DMA triggering operations without the intervention of the central processing unit (CPU) to ensure that the message injection time error is on the order of tens of nanoseconds. Furthermore, the line-speed capture and hardware timestamp module (24) is configured to store the capture timestamp and the captured complete message frame data together in a FIFO capture buffer to avoid the delay and jitter caused by the upper-layer protocol stack processing.

6. The system according to claim 1, characterized in that, The multidimensional state association and comprehensive decision unit (30) specifically includes: The switch internal status active detection module (31) is used to periodically send Simple Network Management Protocol (SNMP) requests or execute command line interface (CLI) commands to the switch under test through an independent management network interface during the test process, so as to obtain and record key parameters with precise timestamps that reflect the internal resource usage and functional status of the switch, forming an internal status time series. The transmission performance quantification analysis engine (32) is used to calculate the end-to-end forwarding delay, delay jitter and frame loss rate of key messages by comparing the original injected message sequence with the captured message sequence; Business function logic consistency verification engine (33); Power system causal time-series correlation analysis engine (34); and cross-domain data correlation and fault diagnosis engine (35).

7. The system according to claim 6, characterized in that, The business function logic consistency verification engine (33) is configured to perform at least one of the following verification logics: Quality of Service (QoS) Priority Guarantee Verification: In fault scenarios, identify the moment when high-priority GOOSE packets and low-priority SV packets occur concurrently, and determine whether the forwarding latency of the GOOSE packets is significantly lower than the forwarding latency of the concurrent SV packets and is within a preset absolute low latency threshold. Virtual LAN (VLAN) isolation verification: Extract the VLAN ID of the packet from the injected packet sequence, determine the set of outgoing ports that it is allowed to appear on based on the network configuration, and then verify whether the packet with that VLAN ID appears on a port outside the set in the captured packet sequence; or Multicast filtering correctness verification: Parse the destination multicast MAC address of the injected packet, and determine the set of ports that should be forwarded according to the preset multicast forwarding table entries. Then verify whether the multicast stream was accurately forwarded to the port set in the captured data, and was not flooded to non-subscribed ports.

8. The system according to claim 6, characterized in that, The power system causal time-series correlation analysis engine (34) is configured as follows: First, based on the physical process and protection logic of the fault scenario, an event causal relationship graph is constructed, which includes multiple key event nodes and directed edges that define the causal relationships between nodes and the maximum allowable time interval. Key event nodes include fault occurrence, protection IED issuing trip GOOSE, circuit breaker smart terminal receiving trip GOOSE, circuit breaker action, and circuit breaker smart terminal issuing change GOOSE. Then, the capture timestamps of all key messages in the captured message sequence are mapped to the corresponding nodes in the event causal relationship graph; Finally, check whether the actual time difference between all adjacent nodes satisfies the timing constraints on the directed edges defined in the graph, and mark any violation of the constraints as a logical processing error. The cross-domain data association and fault diagnosis engine (35) is configured as follows: On a unified timeline, align the external message events represented by the original injected message sequence and the captured message sequence, the internal state of the switch represented by the internal state time sequence, and the logical decision results generated by the business function logic consistency verification engine (33) and the power system causal time sequence correlation analysis engine (34); Furthermore, when an abnormal event is detected, such as a message transmission timeout or a function verification failure, the system automatically traces back all data before and after the time of the abnormal event to analyze and locate the root cause of the abnormal event. The root cause includes resource bottlenecks within the switch, such as a full port output queue or excessive CPU utilization.

9. A rapid detection method for a rapid detection system for a process layer switch in an intelligent substation according to any one of claims 1-8, characterized in that, Includes the following steps: Establish a test environment (S100), connect the service port of the switch under test to the high-precision synchronous message injection and capture unit (20), and connect its management port to the multi-dimensional state association and comprehensive decision unit (30). Configure and generate fault scenarios (S200). Through the power system fault scenario modeling and message generation unit (10), set fault parameters and generate a message sequence file with precise timestamps that reproduces the fault scenario. Execute synchronous injection and capture (S300), load the message sequence file by the high-precision synchronous message injection and capture unit (20), and inject the message stream into the switch under test strictly according to the timestamp in the file. At the same time, capture all output messages on all outgoing ports of the switch under test and attach hardware timestamps. The execution state synchronization detection (S400) is performed simultaneously with packet injection and capture. The multi-dimensional state association and comprehensive decision unit (30) periodically and actively detects and records the internal key operating state parameters of the switch under test, forming a state time series. After the test is completed, the multidimensional association decision (S500) is executed. The multidimensional state association and comprehensive decision unit (30) performs a comprehensive analysis on the collected injection message sequence, capture message sequence and internal state time sequence. The analysis includes: calculating the transmission performance indicators of key messages, verifying the logical correctness of the quality of service (QoS), virtual local area network (VLAN) and multicast functions, verifying whether the causal timing of power system business events is maintained, and performing correlation analysis between external message behavior and internal state changes. A diagnostic report (S600) is generated. The diagnostic report generation unit (40) summarizes all the judgment results and generates a detailed comprehensive test report.

10. A detection device for a rapid detection system for intelligent substation process layer switches according to any one of claims 1-8, characterized in that, This device integrates all or part of the functional units of the aforementioned system, forming a test instrument that can operate independently; The device includes a processor, memory, and multiple network interfaces that communicate with the processor; The memory contains computer programs.

Images