Data transmission method and device, electronic equipment and storage medium

Abstract

The invention discloses a data transmission method and device, electronic equipment and a storage medium, and belongs to the technical field of communication. The method comprises the steps that a first data frame is sent to a coprocessor through a main processor, the first data frame is used for controlling the main processor to write or read data to the coprocessor, the first data frame carries an address increasing identifier, and the address increasing identifier is used for indicating the coprocessor to start writing or reading data from a starting register in N registers, n is an integer greater than 1; and writing or reading data in the N registers from the starting register based on the address increase identification through the coprocessor.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of communication, and particularly relates to a data transmission method and device, electronic equipment and storage medium. BACKGROUND

[0002] At present, with the development of communication technology, the data volume of data transmission of electronic equipment is also increasing, in order to ensure the real-time of data transmission, the electronic equipment can transmit data through I3C bus protocol.

[0003] In the related art, the I3C bus protocol requires that each data transmission must start with a start signal (START), followed by a slave address and a target address, such as a register, and a read-write bit, terminated with a stop signal (STOP). If multiple target addresses need to be accessed, multiple communication processes must be repeatedly initiated.

[0004] However, in the above method, the repeatedly initiated multiple communication processes generate redundant start signals or stop signals and slave addresses, and the repeated start signals / stop signals increase the idle time of the I3C bus, so that the efficiency of data transmission of the electronic equipment is low. SUMMARY

[0005] The embodiments of the present application provide a data transmission method, device, electronic equipment and storage medium, which can improve the efficiency of data transmission of the electronic equipment.

[0006] In a first aspect, the embodiments of the present application provide a data transmission method, executed by an electronic equipment, the electronic equipment comprising a host processor and a coprocessor, the coprocessor comprising N registers, the data transmission method comprising: sending, by the host processor, a first data frame to the coprocessor, the first data frame being used to control the host processor to write or read data to the coprocessor, the first data frame carrying an address increase identifier, the address increase identifier being used to instruct the coprocessor to start writing or reading data from a starting register in the N registers, N being an integer greater than 1; based on the address increase identifier, writing or reading, by the coprocessor, data in the N registers starting from the starting register.

[0007] In a second aspect, an embodiment of the present application provides a data transmission apparatus, executed by an electronic device, the electronic device comprising a main processor and a coprocessor, the coprocessor comprising N registers, the data transmission apparatus comprising: a sending module and a processing module. The sending module is configured to send a first data frame to the coprocessor through the main processor, the first data frame being used to control the main processor to write or read data to or from the coprocessor, the first data frame carrying an address increase identifier, the address increase identifier being used to instruct the coprocessor to write or read data from a starting register in the N registers, N being an integer greater than 1. The processing module is configured to write or read data in the N registers starting from the starting register based on the address increase identifier through the coprocessor.

[0008] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, the memory storing a program or instructions executable on the processor, and the program or instructions, when executed by the processor, implement the steps of the method according to the first aspect.

[0009] In a fourth aspect, an embodiment of the present application provides a readable storage medium, the readable storage medium storing a program or instructions, and the program or instructions, when executed by a processor, implement the steps of the method according to the first aspect.

[0010] In a fifth aspect, an embodiment of the present application provides a chip, the chip comprising a processor and a communication interface, the communication interface and the processor being coupled, and the processor being configured to run a program or instructions to implement the method according to the first aspect.

[0011] In a sixth aspect, an embodiment of the present application provides a computer program product, the program product being stored in a storage medium, and the program product being executed by at least one processor to implement the method according to the first aspect.

[0012] In the embodiment of the present application, the main processor sends a first data frame to the coprocessor, the first data frame is used to control the main processor to write or read data to the coprocessor, the first data frame carries an address increase identifier, the address increase identifier is used to instruct the coprocessor to write or read data from a starting register in N registers, N is an integer greater than 1; then, the coprocessor writes or reads data in the N registers starting from the starting register based on the address increase identifier. In this scheme, by carrying the address increase identifier in the first data frame, the coprocessor can automatically increase the address of the register starting from the address of the starting register in the N registers according to the address increase identifier, and write or read data in the register corresponding to the increased address, that is, the coprocessor can write or read data in the N registers starting from the starting register in batches according to the address increase identifier in the first data frame; that is, if the main processor needs to access multiple target addresses, it only needs to initiate a communication process once, avoiding the increase of bus idle time caused by redundant start signals or stop signals generated by repeated initiation of multiple communication processes, thereby improving the efficiency of data transmission of the electronic device. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a multimedia architecture schematic diagram of a related art I2C bus;

[0014] Figure 2 is a multimedia architecture schematic diagram of a related art I3C bus;

[0015] Figure 3 is one of the flowcharts of a data transmission method provided by the embodiment of the present application;

[0016] Figure 4 is one of the schematic diagrams of the data structure of a data frame provided by the embodiment of the present application;

[0017] Figure 5 is the second schematic diagram of the data structure of a data frame provided by the embodiment of the present application;

[0018] Figure 6 is the third schematic diagram of the data structure of a data frame provided by the embodiment of the present application;

[0019] Figure 7 is the fourth schematic diagram of the data structure of a data frame provided by the embodiment of the present application;

[0020] Figure 8 is the fifth schematic diagram of the data structure of a data frame provided by the embodiment of the present application;

[0021] Figure 9 is the sixth schematic diagram of the data structure of a data frame provided by the embodiment of the present application;

[0022] Figure 10 Figure 2 is a flowchart of a data transmission method according to an embodiment of the present application;

[0023] Figure 11 Figure 3 is a schematic diagram of a data transmission according to an embodiment of the present application;

[0024] Figure 12 Figure 4 is a flowchart of a data transmission method according to an embodiment of the present application;

[0025] Figure 13 Figure 5 is a schematic diagram of a data transmission according to an embodiment of the present application;

[0026] Figure 14 Figure 6 is a flowchart of a data transmission method according to an embodiment of the present application;

[0027] Figure 15 Figure 7 is a schematic diagram of a data transmission according to an embodiment of the present application;

[0028] Figure 16 Figure 8 is a flowchart of a data transmission method according to an embodiment of the present application;

[0029] Figure 17 Figure 9 is a schematic diagram of a data frame data structure according to an embodiment of the present application;

[0030] Figure 18 Figure 10 is a schematic diagram of a data frame data structure according to an embodiment of the present application;

[0031] Figure 19 Figure 11 is a schematic diagram of a data frame data structure according to an embodiment of the present application;

[0032] Figure 20 Figure 12 is a schematic diagram of a data frame data structure according to an embodiment of the present application;

[0033] Figure 21 Figure 13 is a flowchart of a data transmission method according to an embodiment of the present application;

[0034] Figure 22 Figure 14 is a flowchart of a data transmission method according to an embodiment of the present application;

[0035] Figure 23 Figure 15 is a structural schematic diagram of a data transmission device according to an embodiment of the present application;

[0036] Figure 24 Figure 16 is a hardware structural schematic diagram of an electronic device according to an embodiment of the present application;

[0037] Figure 25Fig. 2 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present application. DETAILED DESCRIPTION

[0038] The technical solutions in the embodiments of the present application will be clearly described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art belong to the scope of protection of the present application.

[0039] The terms "first", "second", and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than that illustrated or described herein, and the objects distinguished by "first", "second", and the like are generally of a kind and are not limited in number, for example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally represents an "or" relationship between the objects before and after it.

[0040] The terms "at least one", "at least one of", and the like in the specification and claims of the present application mean any one of the objects, a combination of any two or more of the objects. For example, at least one of a, b, and c can mean "a", "b", "c", "a and b", "a and c", "b and c", and "a, b, and c", where a, b, and c can be single or multiple. Similarly, "at least two" means two or more, and has a similar meaning to "at least one".

[0041] The data transmission method provided by the embodiments of the present application will be described in detail below in combination with the drawings and specific embodiments and application scenarios.

[0042] The data transmission method provided by the embodiments of the present application can be applied in an image transmission scenario; or, is suitable for a multi-chip configuration bus interconnection scenario. In a multi-chip data transmission rate and hardware overhead balance, an acceleration sensor can be added to a mobile terminal shooting device carrying a multimedia system on chip (SOC) to interconnect on the bus to correct picture jitter, or more image sensors can be added to meet multi-focus coverage scenarios.

[0043] It should be noted that the above image can include a picture or a video.

[0044] In recent years, with the continuous improvement of video shooting specifications from 1080P to 4K, 6K and even 8K, higher requirements are put forward for electronic devices. In electronic devices equipped with multimedia SOC, the interconnection of main processors, coprocessors and image sensors generally uses high-speed buses such as Mobile Industry Processor Interface (MIPI), Camera Serial Interface (CSI), Display Serial Interface (DSI), Peripheral Component Interconnect Express (PCIE) and the like for high-bandwidth picture or video transmission, i.e. data sources such as image sensors are connected to main processors or coprocessors through CSI buses, and coprocessors are connected to main processors through PCIE or DSI. In addition to the image data interconnection path, the main processor needs a set of configuration buses to interconnect the entire chip system in order to ensure pre-configuration before shooting, real-time modification of configuration by the user during shooting and processing configuration after shooting. Usually, the above configuration buses can be connected through low-speed buses such as Serial Peripheral Interface (SPI), Secure Digital Input and Output (SDIO) and Inter-Integrated Circuit (I2C). With the increasing complexity of the system, higher requirements are put forward for efficient control of the system.

[0045] The traditional multimedia chip system configuration bus uses 4-wire SPI or 9-wire SDIO to ensure the rate and delay. When connecting multiple chips, the number of interfaces (pins) required increases exponentially, which puts great pressure on the input / output (I / O) pins of the main processor and the board-level wiring between chips. In addition, the packaged image sensor usually only provides a configuration port compatible with the I2C protocol, which further aggravates the above interconnection complexity. Figure 1 A traditional multimedia chip system configuration interconnection architecture is shown, which includes a main processor 10, a coprocessor 11, an image processor 13 and an image processor 14; the main processor 10 is connected to the coprocessor 11 and the coprocessor 12 through a 4-wire SPI, Figure 1 indicated by CS, CLK, MISO and MOSI, and the main processor 10 can be connected to the coprocessor 12 through an I2C bus, Figure 1The I3C bus is represented by a serial clock line (SCL) and a serial data line (SDA), which are connected to the image sensor 13 and the image sensor 14; the SCL bus provides a clock signal, and the SDA bus provides transmission data. Since the maximum rate supported by the I2C protocol is only 3.4 Mbps, using only the I2C as the configuration bus cannot meet the bandwidth and delay requirements during burst configuration.

[0046] To solve the above problems, the electronic device can perform data transmission through the I3C protocol, which requires that each data transmission must start with a start condition (START) followed by a slave address and a read / write bit. If multiple target addresses, such as registers or devices, need to be accessed, multiple communication processes must be repeatedly initiated, which generates redundant start / stop conditions (START / STOP) and address frames, and the repeated start / stop signals increase the idle time of the bus, which may cause arbitration conflicts or priority competition in a multi-device system.

[0047] Exemplarily, Figure 2 An I3C protocol-based multimedia chip system configuration architecture is shown, which includes a host processor 10, a co-processor 11, an image sensor 13, and an image sensor 14 connected to the host processor 10 through an I3C bus; the host processor 10 can be connected to the co-processor 11, the image sensor 13, and the image sensor 14 through the SCL bus and the SDA bus in the I3C bus; the co-processor 11 can include multiple registers, the SCL bus provides a clock signal, and the SDA bus provides transmission data. The host controller serves as a controller to control other chips in the system. The co-processor serves as a target to accept shooting parameter configuration from the host controller, and can serve as a secondary controller to wake up or configure the image sensor when the host controller is in sleep mode. The image sensor serves as a target to accept configuration issued from the controller or the secondary controller.

[0048] Generally, when an electronic device performs multi-address data transmission through the I3C bus protocol, the electronic device can perform data transmission for each address, each data transmission must start with a start signal (START) followed by a slave address and a target address, such as a register, and a read / write bit, and end with a stop signal (STOP). Therefore, when performing multi-address data transmission, the electronic device must repeatedly initiate multiple communication processes. However, the repeatedly initiated multiple communication processes generate redundant start signals or stop signals and slave addresses, and the repeated start / stop signals increase the idle time of the I3C bus, which reduces the efficiency of data transmission of the electronic device.

[0049] In addition, in a multi-chip system, the main processor usually occupies the main power consumption in the whole system. In order to meet the endurance requirement of mobile terminal devices, the main processor needs to be put to sleep to enter a low-power mode when the system load is small or idle, at which time the system control right needs to be handed over to the coprocessor, and the coprocessor and the image sensor need to communicate with each other. The current system interconnection cannot guarantee seamless switching of the main coprocessor to control the image sensor.

[0050] In the data transmission method provided in the embodiments of the present application, by carrying the address increase identifier in the first data frame, the coprocessor can automatically increase the address of the register starting from the address of the starting register in the N registers and write or read data in the register corresponding to the increased address, that is, the coprocessor can write or read data in batches in the N registers starting from the starting register according to the address increase identifier in the first data frame. That is, if the main processor needs to access multiple target addresses, it only needs to initiate a communication process once, avoiding the increase of bus idle time caused by redundant start signals or stop signals generated by repeated initiation of multiple communication processes, thereby improving the efficiency of data transmission of the electronic device.

[0051] The execution subject of the data transmission method provided in the embodiments of the present application can be a data transmission device, which can be an electronic device or a functional module in an electronic device. The technical solutions provided in the embodiments of the present application are described below with the electronic device as an example.

[0052] The embodiments of the present application provide a data transmission method, Figure 3 A flowchart of a data transmission method provided in the embodiments of the present application is shown, which can be applied to an electronic device including a main processor and a coprocessor, and the coprocessor includes N registers. As shown in Figure 3 The data transmission method provided in the embodiments of the present application can include the following steps 201 and 202.

[0053] Step 201, the electronic device sends a first data frame to the coprocessor through the main processor.

[0054] In the embodiments of the present application, the first data frame is used to control the main processor to write or read data to the coprocessor, the first data frame carries an address increase identifier, and the address increase identifier is used to instruct the coprocessor to write or read data starting from a starting register in the N registers, and N is an integer greater than 1.

[0055] Optionally, the address increasing identifier can be any one of a numerical identifier, a character identifier, or a special symbol identifier, etc. The actual use requirement can be considered, and the embodiments of the present application are not limited thereto.

[0056] Preferably, the address increasing identifier can be a numerical identifier.

[0057] Optionally, the main processor can send the first data frame to the coprocessor when receiving the first command.

[0058] Optionally, the first command can be sent by a first application in the electronic device, or the first command can be sent by a kernel layer in the system architecture of the electronic device. The actual use requirement can be considered, and the embodiments of the present application are not limited thereto.

[0059] Optionally, the first application can be any application program in the electronic device. For example, the first application can be a shooting application, a chat application, a video playing application, etc.

[0060] Optionally, the first command can include a data transmission type identifier and data information.

[0061] Optionally, the data transmission type can be write data or read data.

[0062] Optionally, the data transmission type identifier can be any one of a numerical identifier, a character identifier, or a special symbol identifier, etc. The actual use requirement can be considered, and the embodiments of the present application are not limited thereto.

[0063] Optionally, when the data transmission type is write data, the data information can be the first data to be written. When the data transmission type is read data, the data information can include a data identifier and a data type to be read.

[0064] Optionally, the data identifier can be any one of a numerical identifier, a character identifier, or a special symbol identifier, etc. The actual use requirement can be considered, and the embodiments of the present application are not limited thereto.

[0065] Optionally, the data type can be any one of video data, picture data, or document data, etc. The actual use requirement can be considered, and the embodiments of the present application are not limited thereto.

[0066] Optionally, the first data frame further includes a command segment and an address segment.

[0067] In this embodiment of the application, the command segment includes a data transfer type, and the address segment includes the address of the start register. The command segment is used to control the main processor to write or read data from the coprocessor.

[0068] For example, when the data transmission type is write data, the data structure of the first data frame may include: a first data segment, a second data segment, and a third data segment. The first data segment includes a write data command, i.e., the command segment, which may include an address increment identifier. The second data segment includes the address of the start register, i.e., the address segment. The third data segment includes the first data.

[0069] Optionally, in this embodiment, the size of each data segment in the first data frame can be preset; or, it can be user-defined. The specific size can be determined according to actual usage requirements, and this embodiment does not impose any limitations.

[0070] For example, the size of each data segment in the first data frame described above can be any of the following: 8 bits, 16 bits, or 32 bits, etc. The specific size can be determined according to actual usage requirements, and this application embodiment does not impose any limitations.

[0071] Preferably, the size of each data segment in the first data frame can be 32 bits.

[0072] For example, such as Figure 4 As shown, when the data transmission type is write data, the data structure of the first data frame may include: a first data segment 15. Figure 4 The first data segment 15, denoted by "command," includes a write data command and an address increment identifier; the second data segment 16... Figure 4 The second data segment 16, denoted by "address," includes the address of the start register; X third data segments 17... Figure 4 The data segment in the X third data segments 17 is used to store the first data; wherein the size of each of the first data segment, the second data segment and the X third data segments is 32 bits.

[0073] It should be noted that a maximum of 32 third data segments are transmitted in each first video frame.

[0074] For example, combined Figure 4 ,like Figure 5 As shown, Figure 5 To map the data structure of the first data frame corresponding to the written data to the specific data structure in the I3C bus protocol; the I3C bus protocol includes: a start segment,Figure 5 start, the coprocessor address segment, Figure 5 coprocess addr; write operation segment, Figure 5 wr; response segment, Figure 5 ack; 32-bit command segment, i.e. the first data segment, Figure 5 command; each 8 bits in the 32-bit command segment corresponds to a check bit, Figure 5 T; 32-bit start register address segment, i.e. the second data segment, Figure 5 address; each 8 bits in the 32-bit start register address segment corresponds to a check bit, Figure 5 T; 32 data segments, Figure 5 data; each data segment is 32 bits, each 32-bit data segment corresponds to a 32-bit register in the coprocessor, and each 8 bits in each 32-bit data segment corresponds to a check bit, Figure 5 T; stop segment, Figure 5 P.

[0075] Optionally, in the case of reading data in the data transmission type, the data structure of the first data frame can include a fourth data segment, i.e. the command segment, and a fifth data segment, i.e. the address segment, the fourth data segment includes a read data command and an address increase identifier, and the fifth data segment can include the address of the start register.

[0076] Optionally, before step 202, the data transmission method provided in the embodiment of the application further includes the following step 301.

[0077] In the case of reading operation in the data transmission type, the first message is sent to the coprocessor by the host processor after a preset time length.

[0078] In the embodiment of the application, the first message is used to instruct the coprocessor to read data.

[0079] It can be understood that after the host processor sends the first data frame to the coprocessor, the host processor needs to wait until the coprocessor acquires the data to be read, and then the host processor performs the read operation.

[0080] Exemplarily, after the main processor sends the first data frame to the coprocessor, the main processor can send a first message to the coprocessor every preset time length, the first message being used to indicate whether the coprocessor has obtained all the data to be read, and after the coprocessor accurately completes the data to be read, the coprocessor can transmit an ack message in the I3C bus protocol, and after the main processor detects the ack message, the main processor starts reading the data.

[0081] It should be noted that, since the I3C bus naturally has an ack mechanism, the coprocessor and the main processor do not need to perform a data preparation completion handshake, and when the coprocessor is not ready for the data to be read, the coprocessor will not transmit an ack message in the I3C bus protocol, so the main processor will not perform a reading operation.

[0082] Exemplarily, as shown in Figure 5 , in the case where the above data transmission type is reading data, the data structure of the first data frame can include: a fourth data segment 18, Figure 6 indicated by command, the fourth data segment 18 includes a read data command, and the read data command can include an address increase identifier; a second data segment 19, Figure 6 indicated by address, the second data segment 19 includes the address of a starting register and the address of a terminal register, and the process is stage 1; after the coprocessor obtains the data to be read by the main processor according to the address increase identifier, Figure 6 indicated by “idle”, the main processor can perform a reading operation in the coprocessor according to the address increase identifier and the address of the starting register, Figure 6 indicated by rdata, and the process is stage 2.

[0083] Exemplarily, in combination with Figure 6 , as shown in Figure 6 , Figure 7 , the data structure of the first data frame corresponding to the above reading data is mapped to a specific data structure in the I3C bus protocol; stage 1: the first data frame includes: a start (start) segment, Figure 7 indicated by start, a coprocessor address segment, Figure 7 indicated by coprocess addr; a write operation segment, Figure 7 indicated by wr; a response segment, Figure 7 indicated by ack; a 32-bit command segment, that is, the fourth data segment, Figure 7 indicated by command, each 8 bits of the 32-bit command segment correspond to a check bit, Figure 7 indicated by T; a 32-bit starting register address segment, that is, the fifth data segment, Figure 7The address segment of the 32-bit start register corresponds to one check bit every 8 bits, denoted by address, Figure 5 denoted by T; stop segment, Figure 7 denoted by P.

[0084] Stage 2 includes a start segment, Figure 7 denoted by start, coprocessor address segment, Figure 7 denoted by coprocess addr; read operation segment, Figure 7 denoted by rd; response segment, Figure 7 denoted by ack; 32 data segments, Figure 7 denoted by data, each data segment being 32 bits, each 32-bit data segment corresponding to a 32-bit register in the coprocessor, and each 8 bits in each 32-bit data segment corresponding to a response segment, Figure 7 denoted by ack; stop segment, Figure 7 denoted by P.

[0085] Exemplarily, the above-mentioned main processor can be a central processing unit (CPU) in the electronic device.

[0086] Exemplarily, the above-mentioned coprocessor can be a graphics processing unit (GPU) in the electronic device.

[0087] Optionally, in the embodiment of the present application, the main processor can receive the first command through the IO interface.

[0088] Optionally, in the embodiment of the present application, the main processor can send the first data frame to the coprocessor through the bus.

[0089] Optionally, in the embodiment of the present application, the above-mentioned bus can be any one of an I2C bus or an I3C bus. It can be determined according to actual use requirements, and the embodiment of the present application does not limit it.

[0090] Optionally, in the embodiment of the present application, before the above-mentioned step 201, the main processor in the electronic device can perform an initialization operation on the coprocessor to determine the address of the coprocessor and the address of the register in the coprocessor.

[0091] Exemplarily, as Figure 8As shown, the SOC is powered on, the main processor executes the system initialization process, and the main processor assigns the address 0x71 to the coprocessor through the dynamic address allocation command in the I3C protocol. Frame structure of assigning dynamic address. The main processor outputs the start bit start, 7'h7E, the read command rd, and the coprocessor replies ack at the same time, and then the host sends the ENTDAA CCC command, the check bit T, the restart bit Sr, 7'h7E, the write command wr in turn, and the coprocessor replies ack. The coprocessor sends its own information coprocess 1info, and the main processor gives the address of the coprocessor coprocess addr, the check bit PAR, and the coprocessor replies ack. The main processor sends the restart bit Sr, 7'h7E, the write command wr again, and the coprocessor does not reply nack. The main processor gives the end bit P, and completes the dynamic address allocation.

[0092] Exemplarily, in combination with Figure 8 As shown, Figure 9 As shown, Figure 9 To map the data structure of the above initialization process to the specific data structure in the I3C bus protocol; the data structure of the initialization process includes: start (start) section, Figure 9 indicated by start, broadcast address section, Figure 9 indicated by 7'h7E, read command section, Figure 9 indicated by rd, response section, Figure 9 indicated by ack; command section, Figure 9 indicated by ENTDAA CCC; check bit section, Figure 9 indicated by T; restart bit section, Figure 9 indicated by Sr, broadcast address section, Figure 9 indicated by 7'h7E; write command section, Figure 9 indicated by wr; response section, Figure 9 indicated by ack; coprocessor information section, Figure 9 indicated by coprocess 1info; the main processor gives the address of the coprocessor section, Figure 9 indicated by coprocess addr; check bit section, Figure 9 indicated by PAR, response section, Figure 9 indicated by ack; restart bit section, Figure 9 indicated by Sr; broadcast address section, Figure 9 indicated by 7'h7E; write command section, Figure 9 indicated by wr; no response section, Figure 3 indicated by nack; end section, Figure 10 indicated by P.

[0093] Optionally, before step 202, the data transmission method provided in the embodiment of the present application further includes step 401.

[0094] In step 401, the electronic device receives the first data frame through the coprocessor.

[0095] In the embodiment of the present application, after receiving the first data frame, the coprocessor can parse the first data frame to parse the data transmission type and the address increase identifier from the first data frame, so that the coprocessor can perform data transmission according to the data transmission type and the address increase identifier.

[0096] For example, the coprocessor can parse the first data frame through a state machine.

[0097] For example, the coprocessor can synchronize the frame header: byte-by-byte comparison until 0xAA55 is detected, then extract the metadata: read the command code and data length field. Next, collect data: read N bytes continuously to the buffer according to the length field. Finally, check: calculate the Cyclic Redundancy Check (CRC) and compare it with the frame tail field, and discard the frame if it fails.

[0098] In step 202, the electronic device writes or reads data in N registers starting from the start register based on the address increase identifier through the coprocessor.

[0099] Optionally, in the case where the data type in the first data frame is write data, the coprocessor can write or read data in N registers starting from the start register based on the first data stored in the first data frame.

[0100] It should be noted that in the case where the data type in the first data frame is write data, the address of the start register can be randomly selected by the host processor.

[0101] Optionally, in the case where the data type in the first data frame is read data, the coprocessor can read data in N registers starting from the start register until the end register in the N registers is read.

[0102] It should be noted that in the case where the data type in the first data frame is read data, the address of the start register is determined by the host processor according to the data identifier.

[0103] Optionally, in the embodiment of the present application, after reading the data, the coprocessor in the electronic device can transmit the read data to the host processor through the I3C bus.

[0104] This application provides a data transmission method in which a main processor sends a first data frame to a coprocessor. This first command controls the main processor to write or read data from the coprocessor. The first data frame carries an address increment flag, which instructs the coprocessor to write or read data from a start register among N registers, where N is an integer greater than 1. Then, the coprocessor writes or reads data from the start register into the N registers based on the address increment flag. In this scheme, by carrying an address increment flag in the first data frame, the coprocessor can automatically increment the register address based on the address increment flag, starting from the address of the start register among the N registers, and write or read data into the register corresponding to the incremented address. That is, the coprocessor can batch write or read data from the start register into the N registers based on the address increment flag in the first data frame. In other words, if the main processor needs to access multiple target addresses, it only needs to initiate one communication process, avoiding redundant start or stop signals from multiple repeatedly initiated communication processes, which increases bus idle time and thus improves the efficiency of data transmission in electronic devices.

[0105] Optionally, in this embodiment of the application, the above-mentioned address addition identifier includes a first address addition identifier.

[0106] In this embodiment of the application, the first address is marked with an identifier to instruct the coprocessor to write or read data into N registers in sequence with a step size of 1.

[0107] For example, the first address above can be incremented by 1.

[0108] For example, combined Figure 11 ,like Figure 11 As shown, step 202 above can be specifically implemented through step 202a below.

[0109] Step 202a: The electronic device, through the coprocessor, adds an identifier based on the first address and sequentially writes or reads data into N registers starting from the start register.

[0110] Optionally, in this embodiment of the application, taking the data type command included in the first data frame as writing data as an example, the coprocessor can add an identifier through the first address, starting from the start register, and after the start register is full of data, it automatically jumps to the next adjacent register of the start register (hereinafter referred to as the first register) and stores data in the first register, and so on, until all the first data is written into the coprocessor's register.

[0111] For example, taking writing data as an example, such as Figure 3As shown, the first data frame corresponding to the write data includes a write command, a start register address and 32 first data, and the coprocessor can write the first data in the 32 registers in the N registers in sequence from the first register in the register table, Figure 12 In the coprocessor internal register map, the first data is written in the 32 registers in the N registers in sequence from the first register in the register table according to the order of the registers.

[0112] Optionally, in the embodiment of the present application, taking the data type command included in the first data frame as an example of reading data, the coprocessor can automatically jump to the next adjacent register (hereinafter referred to as the second register) of the start register and read data in the second register after reading data in the start register through the first address increment identifier. In this way, the reading process is repeated until the end register is reached.

[0113] In the embodiment of the present application, the coprocessor in the electronic device can write or read data in the N registers in sequence from the start register in the coprocessor according to the first address increment identifier, thereby improving the efficiency of data transmission of the electronic device.

[0114] Optionally, in the embodiment of the present application, the address increment identifier includes a second address increment identifier.

[0115] In the embodiment of the present application, the second address increment identifier is used to instruct the coprocessor to write or read data in the registers at intervals of the step size of the second address increment identifier.

[0116] For example, the second address increment identifier can be 2.

[0117] For example, in combination with Figure 11 As shown, the step 202 can be implemented by the following step 202b. Figure 13

[0118] In step 202b, the electronic device selects a first register in the N registers at intervals of a second step size corresponding to the second address increment identifier from the start register based on the second address increment identifier through the coprocessor, and writes or reads data.

[0119] Optionally, in the embodiment of the present application, the second step size can be a preset step size, for example, 2, 3, 4, etc. The specific value can be determined according to actual use requirements, and the present application is not limited in this embodiment.

[0120] ​Optionally, in the embodiment of the present application, taking the data type command included in the first data frame as an example, the coprocessor can automatically jump to the next register (hereinafter referred to as a third register) with a second step interval after storing data in the starting register and storing full data in the starting register, and store data in the third register, and so on, until all the first data is written into the registers of the coprocessor.

[0121] For example, assuming that the coprocessor includes 5 registers and the step corresponding to the second address increment identifier is 2, the coprocessor can write data in the third register after storing full data in the first register, i.e., the starting register, and write the remaining data in the first data in the fifth register after storing full data in the third register, at this time, all the data in the first data has been written into the registers of the coprocessor.

[0122] For example, taking writing data as an example, in combination with Figure 13 As shown in Figure 3 , the first data frame corresponding to the writing data includes a write command, a starting register address and 32 first data, the coprocessor can write the first data in the register table Figure 14 , which is represented as coprocesserinteranalregister map, and write the first data in the first register in the register table according to the order of the registers, and continue to write the first data in the third register after storing full data in the first register, and so on, until the first data is completely written into the registers of the coprocessor.

[0123] Optionally, in the embodiment of the present application, taking the data type command included in the first data frame as an example, the coprocessor can automatically jump to the next register (hereinafter referred to as a third register) with a second step interval after storing data in the starting register and storing full data in the starting register, and store data in the third register, and so on, until all the first data is written into the registers of the coprocessor.

[0124] For example, assuming that the coprocessor includes 5 registers and the step corresponding to the second address increment identifier is 2, the coprocessor can write data in the third register after storing full data in the first register, i.e., the starting register, and write the remaining data in the first data in the fifth register after storing full data in the third register, at this time, all the data in the first data has been written into the registers of the coprocessor.

[0125] In the embodiment of the present application, the coprocessor in the electronic device can use different address increment methods according to different address increment identifiers, which improves the flexibility of the electronic device in address increment.

[0126] Optionally, in the embodiments of the present application, the address increase identifier includes a third address increase identifier.

[0127] In the embodiments of the present application, the third address increase identifier is used to instruct the coprocessor to write or read data in the M registers in the N registers in turn in a ring manner starting from the start register.

[0128] For example, the third address increase identifier can be 3.

[0129] For example, in combination with Figure 11 As shown in Figure 15 The step 202 can be implemented by the following step 202c.

[0130] In the step 202c, the electronic device writes or reads data in the M registers in the N registers in turn in a ring manner starting from the start register based on the third address increase identifier, and M is less than or equal to N.

[0131] Optionally, in the embodiments of the present application, taking the data type command included in the first data frame as write data as an example, the coprocessor can write data in the start register based on the third address increase identifier, jump to the next adjacent register (hereinafter referred to as the first register) of the start register automatically after the start register is full of data, write data in the first register, and then write data in the start register after the first register is full of data, and so on, until all the first data is written into the registers of the coprocessor.

[0132] For example, taking N as 5 registers as an example, and taking the data type command included in the first data frame as write data as an example, the coprocessor can write data in the first register, i.e., the start register, based on the third address increase identifier, jump to the second register automatically after the first register is full of data, write data in the second register, and then write data in the first register after the second register is full of data, and so on, until all the first data is written into the registers of the coprocessor.

[0133] For example, taking write data as an example, in combination with Figure 15 As shown in Figure 3 As shown in Figure 16The coprocessor internal register map is represented as follows: according to the order of the registers, the first data is written into the first register in the register table, and after the first register is filled with data, the first data is continuously written into the second register, and after the fifth register is filled with data, the first data is continuously written into the first register in the register table, and so on, until the first data is completely written into the registers in the coprocessor.

[0134] Optionally, in the embodiment of the application, taking the data type command included in the first data frame as an example, the coprocessor can automatically jump to the next adjacent register (hereinafter referred to as the first register) of the starting register and read data in the first register after reading data in the starting register, and then automatically jump to the starting register to read data, and so on, until the end register is read.

[0135] Exemplarily, taking N as 5 registers as an example, and taking the data type command included in the first data frame as an example, the coprocessor can read data from the first register, i.e., the starting register, and then automatically jump to the second register to read data, and then automatically jump to the first register to read data after reading data in the second register, and so on, until the end register is read.

[0136] In the embodiment of the application, the coprocessor in the electronic device can use different address increasing methods according to different address increasing identifiers, thereby improving the flexibility of address increasing of the electronic device.

[0137] Optionally, in the embodiment of the application, the first data frame carries the first data, the first data is stored in X data segments in the first data frame, each data segment in the X data segments corresponds to a CRC check bit, and X is an integer less than or equal to N.

[0138] Optionally, in the embodiment of the application, the size of the CRC check bit can be any one of the following: 5 Bits, 8 Bits, 16 Bits, and 32 Bits.

[0139] Optionally, in the embodiment of the application, the size of the CRC check bit can be preset by the electronic device, or the size of the CRC check bit can be determined by the electronic device according to the load of the main processor.

[0140] For example, when the load of the main processor is greater than or equal to a first threshold, the electronic device may determine the size of the CRC check bit to be 5 bits; or, when the load of the main processor is greater than or equal to a second threshold, the electronic device may determine the size of the CRC check bit to be 8 bits; or, when the load of the main processor is less than the second threshold, the electronic device may determine the size of the CRC check bit to be 32 bits; wherein the first preset is greater than the second threshold.

[0141] It should be noted that the size of the CRC check bit corresponding to each of the above X data segments is the same.

[0142] For example, combined Figure 4 ,like Figure 17 As shown, step 202 above can be specifically implemented through step 501 below.

[0143] Step 501: The electronic device, through the coprocessor, adds an identifier based on the address, writes the first data into N registers starting from the start register, and verifies the first data written in the corresponding register based on the CRC check bit corresponding to each of the X data segments.

[0144] In this embodiment of the application, the data in each of the above X data segments is written into a register.

[0145] For example, combined Figure 17 ,like Figure 17 As shown, the data structure of the first data frame may include: a first data segment 15, Figure 17 The first data segment 15, denoted by "command," includes a write data command and an address increment identifier; the second data segment 16... Figure 17 The second data segment 16, denoted by "address," includes the address of the start register; X third data segments 17... Figure 17 In this context, "data" represents the data segment, and each third data segment is followed by a CRC checksum bit after 17. Figure 18 It is represented by CRC.

[0146] For example, combined Figure 18 ,like Figure 18 As shown, Figure 18 To map the data structure of the first data frame, which includes CRC check bits, to the specific data structure in the I3C bus protocol; the I3C bus protocol includes: the start segment, Figure 18 The term "start" indicates the coprocessor address range. Figure 18 The `coprocess addr;` directive is used to write the operation segment. Figure 5 The response section is represented by wr. Figure 5The 'ack' symbol represents the 32-bit command segment, which is the first data segment mentioned above. Figure 5 In this 32-bit command segment, each 8 bits correspond to a check bit. Figure 5 The T in the text represents the address segment of the 32-bit start register, which is the second data segment mentioned above. Figure 18 The address field of this 32-bit start register is represented by an address bit, with each 8 bits corresponding to a check bit. Figure 18 The 'T' indicates the number of data segments; 32 data segments. Figure 18 In this context, "data" represents a segment of data, each segment being 32 bits long. Each 32-bit data segment corresponds to a 32-bit register in the coprocessor, and every 8 bits within each 32-bit data segment constitute a check bit. Figure 18 The 'T' indicates the 'T'; each data segment corresponds to a CRC checksum bit segment. Figure 18 In this context, CRC is used, where each CRC check bit field corresponds to a check bit. Figure 19 The terminator is represented by T; it signifies the stop segment. Figure 19 The Chinese character is represented by P.

[0147] In this embodiment, due to the configuration of register tables for consecutive addresses of the coprocessor, and considering the significant impact of errors during register configuration on overall system performance, a CRC check mechanism is introduced. CRC checks are added to the transmitted data to ensure the robustness of the electronic device.

[0148] Optionally, in the embodiments of this application, the data transmission method provided in the embodiments of this application further includes the following steps 402 and 403.

[0149] Step 402: When the load of the main processor is less than or equal to a preset threshold, the electronic device sends a second data frame to the coprocessor through the main processor.

[0150] In this embodiment of the application, the second data frame is used to instruct the main processor to allocate control of the main processor to the coprocessor.

[0151] Optionally, in this embodiment of the application, the aforementioned preset threshold can be preset by the electronic device or user-defined.

[0152] Optionally, in this embodiment, the aforementioned load may include at least one of the following: user space process load, multi-threaded / multi-process task, kernel space load, interrupt handling, kernel task, and I / O wait load, etc. The specific load can be determined according to actual usage requirements, and this embodiment does not impose any limitations.

[0153] It should be noted that the above-mentioned main processor load being less than the preset threshold can mean that the load of each of the above-mentioned components is less than or equal to the corresponding preset threshold.

[0154] It can be understood that the load of the main processor is less than or equal to the preset threshold, which indicates that the main processor requires to enter the low-power mode.

[0155] Exemplarily, the second data frame can be a low-power frame.

[0156] Exemplarily, as shown in the following table, the data structure of the low-power frame can include a low-power command segment, denoted as command, and a low-power information segment, denoted as low-power info. Figure 19 Figure 20 Figure 20

[0157] Exemplarily, as shown in the following table, the low-power frame is mapped to a specific data structure in the I3C bus protocol; the I3C bus protocol corresponding to the low-power frame includes a start segment, denoted as start, a coprocessor address segment, denoted as coprocess addr, a write operation segment, denoted as wr, an acknowledgement segment, denoted as ack, a 32-bit command segment, i.e., the low-power command segment, denoted as command, a 32-bit low-power information segment, denoted as T, and a stop segment, denoted as P. Figure 20 Figure 20 Figure 20 Figure 20 Figure 20 Figure 20 Figure 20 Figure 21 Figure 22 Figure 2

[0158] It can be understood that the low-power information can be a permission that the main processor wants to assign to the coprocessor.

[0159] Optionally, in the embodiment of the present application, the main processor in the electronic device can send the second data frame to the coprocessor through the bus between the main processor and the coprocessor.

[0160] In step 403, the electronic device exercises control right through the coprocessor in the case that the bus between the main processor and the coprocessor is in an idle state.

[0161] In the embodiment of the present application, the idle state of the bus means that there is no data transmission between the main processor and the coprocessor.

[0162] ​​​​​​​​​​​​​It should be noted that after the main processor sends the second data frame to the coprocessor, if the bus between the main processor and the coprocessor is not in an idle state, the coprocessor cannot exercise control at this time, and the coprocessor can only wait until the bus between the main processor and the coprocessor is in an idle state, and the coprocessor can exercise control at this time.

[0163] Exemplarily, as shown in the following, the coprocessor exercises control in the case that the main processor is in a low-power mode is explained and described through specific examples. The specific implementation can be achieved through the following steps 1 to step 5. Figure 23

[0164] Step 1, the software in the electronic device commands the main processor to enter a low-power mode.

[0165] Step 2, the main processor in the electronic device selects to transfer control to the coprocessor.

[0166] Step 3, the main processor in the electronic device sends a low-power frame to the coprocessor.

[0167] Step 4, the coprocessor in the electronic device receives and parses the low-power frame.

[0168] Step 5, the coprocessor in the electronic device waits for the bus to be idle and then starts to exercise control.

[0169] In the embodiment of the application, the coprocessor in the electronic device can exercise control in the case that the bus is idle, thereby avoiding the phenomenon of lag caused by switching control in the process of data transmission.

[0170] Optionally, after the step 303, the data transmission method provided in the embodiment of the application further includes the following steps 601 and 602.

[0171] Step 601, in the case that the main processor receives a second command and the bus is in an idle state, the electronic device sends a third data frame to the coprocessor through the main processor.

[0172] In the embodiment of the application, the third data frame is used to instruct the coprocessor to transfer control to the main processor.

[0173] In the embodiment of the application, the second command is used to wake up the main processor.

[0174] Optionally, in the embodiment of the application, the main processor in the electronic device can send the third data frame to the coprocessor through the bus between the main processor and the coprocessor.

[0175] ​Step 602, the main processor exercises the control right in the case that the coprocessor completes the unfinished data operation and the bus is in the idle state.

[0176] It should be noted that, after the main processor sends the third data frame to the coprocessor, if the bus between the main processor and the coprocessor is not in the idle state and the coprocessor does not complete the current data operation, the main processor cannot exercise the control right at this time, and the main processor can only wait until the bus between the main processor and the coprocessor is in the idle state and the coprocessor completes the current data operation, and then the main processor exercises the control right.

[0177] Exemplarily, as shown in Figure 23 , the following is explained by a specific example. The following steps 6 to 9 can be implemented.

[0178] Step 6, the main processor in the electronic device is woken up by software to exit low power consumption.

[0179] Step 7, the main processor in the electronic device sends a third data frame to the coprocessor when the bus is idle.

[0180] Step 8, the coprocessor in the electronic device remains silent after completing the unfinished task after receiving the third data frame.

[0181] Step 9, the main processor in the electronic device waits for the bus to be idle and then starts to exercise the control right.

[0182] In the embodiment of the application, the main processor in the electronic device can exercise the control right in the case that the bus is idle and the coprocessor completes the unfinished data operation, thereby avoiding the phenomenon of lag caused by switching the control right in the process of data transmission.

[0183] Optionally, in the embodiment of the application, in combination with Figure 24 , the electronic device includes a first processor 13 connected with the main processor 10 and the coprocessor 11.

[0184] Exemplarily, the first processor can be a chip or a system with processing function in the electronic device.

[0185] For example, the first processor can be an image sensor.

[0186] Exemplarily, the data transmission method provided by the embodiment of the application further includes the following steps 701 or 702.

[0187] Step 701, in the case that the load of the main processor is greater than a preset threshold, the electronic device sends a first data frame to the first processor through the main processor.

[0188] At 702, in response to the main processor load being less than or equal to the preset threshold, the electronic device sends, by the coprocessor, the first data frame to the first processor.

[0189] It should be noted that the specific process in which the electronic device sends the first data frame to the first processor by the main processor or sends the first data frame to the first processor by the coprocessor can be found in the above embodiments, and to avoid repetition, it will not be repeated here.

[0190] It should be noted that the operation performed by the first processor after receiving the first data frame can be found in the above embodiments, and to avoid repetition, it will not be repeated here.

[0191] In the embodiments of the present application, the electronic device can select the main processor or the coprocessor to send the first data frame to the first processor according to the load of the main processor, thereby improving the flexibility of the electronic device in sending the first data frame.

[0192] The above-mentioned various method embodiments, or various possible implementation manners in each method embodiment, can be executed individually, or, in the absence of contradictions, can also be executed in combination, and the specific execution can be determined according to actual use requirements, and the embodiments of the present application do not limit this.

[0193] It should be noted that the data transmission method provided in the embodiments of the present application can be executed by a data transmission device. In the embodiments of the present application, the data transmission device executing the data transmission method is taken as an example to illustrate the data transmission device provided in the embodiments of the present application.

[0194] Figure 25 A possible structure schematic diagram of the data transmission device involved in the embodiments of the present application is shown. As shown in the figure, Figure 25 The data transmission device 70 can include a sending module 71 and a processing module 72.

[0195] The sending module 71 is configured to send, by the main processor, a first data frame to the coprocessor, the first data frame being used to control the main processor to write or read data to the coprocessor, the first data frame carrying an address increase identifier, the address increase identifier being used to instruct the coprocessor to write or read data from a starting register in N registers, N being an integer greater than 1. The processing module 72 is configured to write or read data in the N registers starting from the starting register based on the address increase identifier by the coprocessor.

[0196] In a possible implementation manner, the above-mentioned first data frame further includes a command segment and an address segment, the command segment including a data transmission type, and the address segment including an address of the starting register, the command segment being used to control the main processor to write or read data to the coprocessor.

[0197] In a possible implementation, the sending module 71 is further configured to, before reading data from the starting register in the N registers based on the address increase identifier, send, by the main processor (10) to the coprocessor (11), a first message after a preset time length in a case where the data transmission type is a read operation, the first message being used to instruct the coprocessor (11) to read data.

[0198] In a possible implementation, the address increase identifier includes a first address increase identifier. The processing module 72 is specifically configured to, based on the first address increase identifier, write or read data from the starting register in the N registers in sequence by the coprocessor.

[0199] In a possible implementation, the address increase identifier includes a second address increase identifier. The processing module is specifically configured to, based on the second address increase identifier, select a first register in the N registers with a second step corresponding to the second address increase identifier as an interval, and write or read data from the starting register by the coprocessor.

[0200] In a possible implementation, the address increase identifier includes a third address increase identifier. The processing module 72 is specifically configured to, based on the third address increase identifier, write or read data in M registers in the N registers in a loop from the starting register in sequence by the coprocessor, where M is less than or equal to N.

[0201] In a possible implementation, the first data frame carries first data, the first data is stored in X data segments in the first data frame, each data segment corresponds to a cyclic redundancy check (CRC) check bit, and X is an integer less than or equal to N. The processing module 72 is specifically configured to, based on the address increase identifier, write the first data in the N registers from the starting register by the coprocessor, data in each data segment is written into a register, and the first data written in the corresponding register is checked based on the CRC check bit corresponding to each data segment.

[0202] In a possible implementation, the sending module 71 is further configured to, in a case where a load of the main processor is less than or equal to a preset threshold, send, by the main processor to the coprocessor, a second data frame, the second data frame being used to instruct the main processor to allocate control of the main processor to the coprocessor. The processing module 72 is further configured to, in a case where a bus between the main processor and the coprocessor is in an idle state, exercise the control by the coprocessor.

[0203] In a possible implementation, the sending module 71 is further configured to send, by the main processor, a third data frame to the coprocessor, where the third data frame is used to instruct the coprocessor to transfer the control right to the main processor, after the coprocessor exercises the control right, the main processor receives the second command, and the bus is in an idle state.

[0204] In a possible implementation, the electronic device includes a first processor 12 connected with the main processor and the coprocessor. The sending module 71 is further configured to send, by the main processor 10, a first data frame to the first processor 12, when the load of the main processor 10 is greater than a preset threshold; or send, by the coprocessor 11, the first data frame to the first processor 12, when the load of the main processor 10 is less than or equal to the preset threshold.

[0205] The embodiment of the present application provides a data transmission device. By carrying the address increase identifier in the first data frame, the coprocessor can automatically increase the address of the register from the address of the starting register in the N registers according to the address increase identifier, and write or read data in the register corresponding to the increased address. That is, the coprocessor can write or read data in the N registers in batches from the starting register according to the address increase identifier in the first data frame. In other words, if the main processor needs to access multiple target addresses, it only needs to initiate a communication process once, avoiding the increase of the bus idle time caused by the redundant start signal or stop signal generated by the repeated initiation of multiple communication processes, thereby improving the data transmission efficiency of the data transmission device.

[0206] The data transmission device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, a mobile electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the device.

[0207] The data transmission device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0208] The data transmission device provided in this application can implement the various processes implemented in the above embodiments. To avoid repetition, it will not be described again here.

[0209] Optionally, such as ​ As shown, this application embodiment also provides an electronic device 90, including a processor 91 and a memory 92. The memory 92 stores a program or instructions that can run on the processor 91. When the program or instructions are executed by the processor 91, they implement the various steps of the above-described data transmission method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0210] It should be noted that the electronic devices in the embodiments of this application include the mobile electronic devices and non-mobile electronic devices described above.

[0211] ​ A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0212] The electronic device 100 includes, but is not limited to, a radio frequency unit 101, a network module 102, an audio output unit 103, an input unit 104, a sensor 105, a display unit 106, a user input unit 107, an interface unit 108, a memory 109, and a processor 110, etc.

[0213] As can be appreciated by those skilled in the art, the electronic device 100 can further include a power supply (such as a battery) that supplies power to each of the components, and the power supply can be logically connected to the processor 110 through a power management system, so that the power management system can realize functions such as management of charging, discharging, and power consumption management. ​ The electronic device structure shown in the figure does not constitute a limitation on the electronic device, and the electronic device can include more or fewer components than shown, or combine certain components, or different component arrangements, which will not be described here.

[0214] The processor 110 is configured to send, by the main processor, a first data frame to the coprocessor, the first data frame being used to control the main processor to write or read data to or from the coprocessor, the first data frame carrying an address increase identifier, the address increase identifier being used to instruct the coprocessor to write or read data from a starting register in N registers, N being an integer greater than 1. And based on the address increase identifier, the coprocessor writes or reads data in the N registers starting from the starting register.

[0215] Optionally, in the embodiment of the present application, the processor 110 is further configured to, before reading data in the N registers starting from the starting register based on the address increase identifier, in the case of a read operation, send, by the main processor (10), a first message to the coprocessor (11) after a preset time period, the first message being used to instruct the coprocessor (11) to read data.

[0216] Optionally, in the embodiment of the present application, the address increase identifier includes a first address increase identifier. The processor 110 is specifically configured to, based on the first address increase identifier, write or read data in the N registers starting from the starting register in turn by the coprocessor.

[0217] Optionally, in the embodiment of the present application, the address increase identifier includes a second address increase identifier. The processor 110 is specifically configured to, based on the second address increase identifier, select a first register in the N registers with a second step corresponding to the second address increase identifier as an interval, and write or read data by the coprocessor starting from the starting register.

[0218] Optionally, in the embodiments of the present application, the address increase identifier comprises a third address increase identifier. The processor 110 is specifically configured to write or read data in the M registers in the N registers in a loop, starting from the start register, based on the third address increase identifier by the coprocessor, where M is less than or equal to N.

[0219] Optionally, in the embodiments of the present application, the first data frame carries first data, the first data is stored in X data segments in the first data frame, each data segment in the X data segments corresponds to a cyclic redundancy check (CRC) check bit, and X is an integer less than or equal to N. The processor 110 is specifically configured to write the first data in the N registers, starting from the start register, based on the address increase identifier by the coprocessor, and the data in each data segment is written in a register, and the first data written in the corresponding register is checked based on the CRC check bit corresponding to each data segment.

[0220] Optionally, in the embodiments of the present application, the processor 110 is further configured to, when the load of the main processor is less than or equal to a preset threshold, send, by the main processor, a second data frame to the coprocessor, the second data frame being used to indicate that the main processor allocates control right of the main processor to the coprocessor; and when the bus between the main processor and the coprocessor is in an idle state, exercise the control right by the coprocessor.

[0221] Optionally, in the embodiments of the present application, the processor 110 is further configured to, after the control right is exercised by the coprocessor, when the main processor receives a second command and the bus is in an idle state, send, by the main processor, a third data frame to the coprocessor, the third data frame being used to indicate that the coprocessor transfers the control right to the main processor; and when the coprocessor completes an unfinished data operation and the bus is in an idle state, exercise the control right by the main processor.

[0222] Optionally, in the embodiments of the present application, the electronic device comprises a first processor connected with the main processor and the coprocessor. The processor 110 is further configured to, when the load of the main processor is greater than a preset threshold, send, by the main processor, a first data frame to the first processor; or, when the load of the main processor is less than or equal to the preset threshold, send, by the coprocessor, the first data frame to the first processor.

[0223] The electronic device provided in the embodiments of the present application can increase the address of the starting register in the N registers according to the address increase identifier, and write or read data in the register corresponding to the increased address, that is, the coprocessor can write or read data in the N registers starting from the starting register according to the address increase identifier in the first data frame, so that the efficiency of data transmission of the electronic device is improved.

[0224] The electronic device provided in the embodiments of the present application can realize each process realized by the method embodiments, and achieve the same technical effects. To avoid repetition, details are not described herein.

[0225] The beneficial effects of various implementation manners in the embodiments can refer to the beneficial effects of the corresponding implementation manners in the method embodiments, and details are not described herein to avoid repetition.

[0226] It should be understood that, in the embodiments of the present application, the input unit 104 can include a graphics processor (GPU) 1041 and a microphone 1042. The graphics processor 1041 processes image data of a still picture or a video obtained by an image capture device (such as a camera) in a video capture mode or an image capture mode. The display unit 106 can include a display panel 1061, which can be configured in the form of a liquid crystal display, an organic light-emitting diode, etc. The user input unit 107 includes at least one of a touch panel 1071 and other input devices 1072. The touch panel 1071 is also called a touch screen. The touch panel 1071 can include a touch detection device and a touch controller. The other input devices 1072 can include, but are not limited to, a physical keyboard, function keys (such as volume control keys, on-off keys, etc.), a trackball, a mouse, a joystick, and the like, which are not described herein.

[0227] The memory 109 can be used to store software programs and various data. The memory 109 can mainly include a first storage area storing programs or instructions and a second storage area storing data, wherein the first storage area can store an operating system, application programs or instructions required by at least one function (such as a sound playing function, an image playing function, etc.), and the like. In addition, the memory 109 can include a volatile memory or a non-volatile memory, or the memory 109 can include both a volatile memory and a non-volatile memory. The non-volatile memory can be a Read-Only Memory (ROM), a Programmable ROM (PROM), an Erasable PROM (EPROM), an Electrically EPROM (EEPROM), or a flash memory. The volatile memory can be a Random Access Memory (RAM), a Static RAM (SRAM), a Dynamic RAM (DRAM), a Synchronous DRAM (SDRAM), a Double Data Rate SDRAM (DDR SDRAM), an Enhanced SDRAM (ESDRAM), a Synch link DRAM (SLDRAM), and a Direct Rambus RAM (DRRAM). The memory 109 in the embodiments of the present application includes but is not limited to these and any other suitable types of memory.

[0228] The processor 110 can include one or more processing units; optionally, the processor 110 integrates an application processor and a modem processor, wherein the application processor mainly processes operations related to an operating system, a user interface, and an application program, and the modem processor mainly processes wireless communication signals, such as a baseband processor. It can be understood that the above-mentioned modem processor can also not be integrated into the processor 110.

[0229] The embodiments of the present application also provide a readable storage medium, the readable storage medium stores programs or instructions, the programs or instructions are executed by a processor to realize various processes of the above-mentioned method embodiments, and the same technical effects can be achieved. To avoid repetition, details are not described here.

[0230] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes a computer readable storage medium, such as a computer readable only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0231] The embodiment of the present application further provides a chip, which comprises a processor and a communication interface, the communication interface is coupled with the processor, the processor is used for running programs or instructions, realizes various processes of the above method embodiments, and can achieve the same technical effects. To avoid repetition, details are not described here.

[0232] It should be understood that the chip mentioned in the embodiment of the present application can also be referred to as a system level chip, a system chip, a chip system or a system on chip, etc.

[0233] The embodiment of the present application provides a computer program product, which is stored in a storage medium, and is executed by at least one processor to realize various processes of the above data transmission method embodiments, and can achieve the same technical effects. To avoid repetition, details are not described here.

[0234] It should be noted that in this paper, the term "includes", "contains" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or includes elements inherent to such process, method, article or device. Without more limitations, the element defined by the statement "includes a" does not exclude the presence of another identical element in the process, method, article or device including the element. In addition, it should be pointed out that the scope of the method and device in the embodiment of the present application is not limited to the order of the functions shown or discussed, but can also include the functions performed in a substantially simultaneous manner or in the opposite order according to the functions involved, for example, the described method can be performed in an order different from the described order, and various steps can also be added, omitted or combined. In addition, the features described with reference to some examples can be combined in other examples.

[0235] Through the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned example methods can be realized by means of software and a necessary general hardware platform, and of course, can also be realized by hardware, but in many cases, the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a computer software product in essence or in the form of a part that contributes to the prior art, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, or an optical disk) and includes a plurality of instructions for causing a terminal (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application.

[0236] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above-mentioned specific embodiments, and the above-mentioned specific embodiments are only illustrative and not restrictive. Those skilled in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A data transmission method, characterized in that, Performed by an electronic device, the electronic device including a main processor and a coprocessor, the coprocessor including N registers, the method includes: The main processor sends a first data frame to the coprocessor. The first data frame is used to control the main processor to write or read data to the coprocessor. The first data frame carries an address increment flag, which is used to instruct the coprocessor to write or read data from the start register among the N registers, where N is an integer greater than 1. The coprocessor, based on the address and an identifier, writes or reads data from the N registers, starting from the start register.

2. The method according to claim 1, characterized in that, The first data frame further includes a command segment and an address segment. The command segment includes a data transfer type, and the address segment includes the address of the start register. The command segment is used to control the main processor to write or read data from the coprocessor.

3. The method according to claim 2, characterized in that, Before the step of adding an identifier based on the address via the coprocessor and reading data from the N registers starting from the start register, the method further includes: When the data transfer type is a read operation, after a preset time period, the main processor sends a first message to the coprocessor, the first message being used to instruct the coprocessor to read the data.

4. The method according to claim 1, characterized in that, The address increment identifier includes a first address increment identifier; The step of writing or reading data from the N registers, starting from the start register, based on the address incremented by the coprocessor, includes: The coprocessor adds an identifier based on the first address and sequentially writes or reads data from the N registers, starting from the start register.

5. The method according to claim 1, characterized in that, The address increment identifier includes a second address increment identifier; The step of writing or reading data from the N registers, starting from the start register, based on the address incremented by the coprocessor, includes: Using the coprocessor, based on the second address, an identifier is added. Starting from the start register, with the second step size corresponding to the second address being added as an interval, the first register is selected from the N registers to write or read data.

6. The method according to claim 1, characterized in that, The address increment identifier includes a third address increment identifier; The step of writing or reading data from the N registers, starting from the start register, based on the address incremented by the coprocessor, includes: The coprocessor adds an identifier based on the third address and, starting from the start register, sequentially writes or reads data in M ​​of the N registers in a loop, where M is less than or equal to N.

7. The method according to any one of claims 1 to 6, characterized in that, The first data frame carries first data, which is stored in X data segments in the first data frame. Each data segment corresponds to a cyclic redundancy check (CRC) bit, where X is an integer less than or equal to N. The step of writing data into the N registers starting from the start register by adding an identifier based on the address through the coprocessor includes: The coprocessor adds an identifier based on the address and writes the first data into the N registers starting from the start register. Data in each data segment is written into one register, and the first data written into the corresponding register is verified based on the CRC check bit corresponding to each data segment.

8. The method according to claim 1, characterized in that, The method further includes: When the load on the main processor is less than or equal to a preset threshold, the main processor sends a second data frame to the coprocessor. The second data frame is used to instruct the main processor to allocate control of the main processor to the coprocessor. When the bus between the main processor and the coprocessor is idle, the control is exercised through the coprocessor.

9. The method according to claim 8, characterized in that, After exercising the control through the coprocessor, the method further includes: When the main processor receives the second command and the bus is idle, the main processor sends a third data frame to the coprocessor. The third data frame is used to instruct the coprocessor to transfer control to the main processor. When the coprocessor completes unfinished data operations and the bus is idle, the main processor exercises the control.

10. The method according to claim 1, characterized in that, The electronic device includes a first processor connected to the main processor and the coprocessor; the method further includes: If the main processor load exceeds the preset threshold, the first data frame is sent from the main processor to the first processor; or... When the load on the main processor is less than or equal to the preset threshold, the first data frame is sent to the first processor through the coprocessor.

11. A data transmission device, characterized in that, The data transmission device is executed by an electronic device, which includes a main processor and a coprocessor, the coprocessor including N registers, and the data transmission device includes a sending module and a processing module. The sending module is used to send a first data frame to the coprocessor through the main processor. The first data frame is used to control the main processor to write or read data to the coprocessor. The first data frame carries an address increment identifier, which is used to instruct the coprocessor to write or read data from the start register among the N registers, where N is an integer greater than 1. The processing module is used to write or read data from the N registers starting from the start register by adding an identifier based on the address through the coprocessor.

12. An electronic device, characterized in that, It includes a processor, a memory, and a program or instructions stored in the memory and executable on the processor, wherein the program or instructions, when executed by the processor, implement the steps of the data transmission method as described in any one of claims 1 to 10.

13. A readable storage medium, characterized in that, The readable storage medium stores a program or instructions that, when executed by a processor, implement the steps of the data transmission method as described in any one of claims 1 to 10.

Images