Network card adapter plate and server system

Abstract

The invention discloses a network card adapter plate and a server system, and relates to the technical field of computers, the network card adapter plate comprises a power supply connector, a plurality of node connectors, a power supply and time sequence signal processing module and a plurality of network card connectors, the power supply connector is connected to a power supply board, the plurality of node connectors are respectively connected with different server nodes, and the power supply and time sequence signal processing module is connected with the network card connectors. The plurality of network card connectors are respectively configured to be connected with different interfaces of a network card; the power supply and time sequence signal processing module comprises a power supply enabling control unit, an electronic fuse and a main power supply time sequence signal generating unit; the power supply enabling control unit enables the electronic fuse to supply power to the network card when the hot plug-in condition is met and no hot pull-out operation exists; the power supply normal signal output end of the electronic fuse outputs an auxiliary power supply time sequence signal to the network card; and the main power supply time sequence signal generation unit outputs a main power supply time sequence signal to the network card when receiving the network card power supply normal signal and having no hot pull-out operation. According to the invention, hot plugging of the network card is realized in a multi-node sharing environment.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, more particularly, to a network card adapter plate and a server system. BACKGROUND

[0002] In the related art, the hot plug scheme of the network card is mostly designed for a single node, and the power supply and signal timing are controlled through a complex programmable logic device (CPLD) or an extender on a single server mainboard, which cannot adapt to the scenario of connecting two independent nodes with the network card. When the hot plug operation is performed, the two nodes need to be coordinated to complete the link establishment or disconnection synchronously, and the related art lacks hardware support for the cooperative management of the two nodes, resulting in that the PCIe (Peripheral Component Interconnect Express) link cannot be reliably powered on and established after hot insertion, or data is lost and the device is damaged when hot pulled out.

[0003] Therefore, how to realize the hot plug of the network card in a multi-node sharing environment is a technical problem to be solved by those skilled in the art. SUMMARY

[0004] The present application aims to provide a network card adapter plate and a server system, which realize the hot plug of the network card in a multi-node sharing environment.

[0005] To achieve the above-mentioned purpose, the present application provides a network card adapter plate, comprising a power connector, a plurality of node connectors, a power supply and timing signal processing module, a plurality of network card connectors, the power connector is connected to a power board, the plurality of node connectors are respectively connected to different server nodes, the plurality of network card connectors are respectively configured to connect different interfaces of the network card, and the power supply and timing signal processing module is respectively connected to the power connector, the plurality of node connectors and the plurality of network card connectors; the power supply and timing signal processing module comprises a power enable control unit, an electronic fuse and a main power timing signal generation unit; the power enable control unit is configured to enable the electronic fuse to supply power to the network card when the hot insertion condition is met and there is no hot pull-out operation; the power input end of the electronic fuse is connected to the power connector, the power output end of the electronic fuse is connected to each network card connector, and the power normal signal output end of the electronic fuse is connected to the main network card connector to output an auxiliary power timing signal to the network card, thereby controlling the power-on or power-off of the auxiliary power of the network card; wherein the network card returns the network card power normal signal through the main network card connector after the power-on of the auxiliary power is completed; the main power timing signal generation unit is configured to output the main power timing signal to the network card through the main network card connector to control the power-on or power-off of the main power of the network card when the network card power normal signal is received and there is no hot pull-out operation.

[0006] To achieve the above object, the application provides a server system, which comprises a power board, a plurality of server nodes and a network card adapter plate as mentioned above, the power board supplies power for the network card through the network card adapter plate, and the plurality of server nodes are connected with the network card through the network card adapter plate.

[0007] The application sets the power connector, the plurality of node connectors, the plurality of network card connectors and the power and timing signal processing module connecting the three, constructs a switching control architecture independent of any server node, namely the network card adapter plate, so that the power management and the key timing signal in the hot plug process no longer depend on the independent control of any node, but are uniformly scheduled by the special module on the adapter plate. When the hot insertion operation occurs, the power and timing signal processing module can actively control the power supply sequence of the network card, ensuring the power-on timing conforming to the network card specification; when hot plugging out, it can power off and reset in sequence to avoid abnormal state. Since the power and timing signal processing module is connected with the plurality of node connectors at the same time, it can send state indication or receive feedback to each node before / after the power action, realizing the synchronization and coordination of the plurality of nodes on the link establishment and disconnection. As can be seen, the application realizes the hot plug of the network card in the multi-node sharing environment. The application also discloses a server system, which can also realize the above technical effects.

[0008] It should be understood that the above general description and the following detailed description are only exemplary and cannot limit the application. BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the application, the drawings needed in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor.

[0010] Figure 1 A structure diagram of a network card adapter plate according to an exemplary embodiment is shown.

[0011] Figure 2 A structure diagram of a server system according to an exemplary embodiment is shown.

[0012] Figure 3 A structure diagram of a dual-node DSFF network card hot plug implementation in an application embodiment provided by the application is shown.

[0013] Figure 4 A circuit diagram of a dual-node DSFF network card hot plug implementation in an application embodiment provided by the application is shown.

[0014] Figure 5 A flowchart of a hot insertion implementation method in an application embodiment provided by the application is shown.

[0015] Figure 6 Figure 1 is a flow chart of a hot plug implementation method according to an application embodiment of the present application.

[0016] Figure 1 is a flow chart of a hot plug implementation method according to an application embodiment of the present application. DETAILED DESCRIPTION

[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, any other embodiments obtained by those skilled in the art without creative work fall within the protection scope of the present application.

[0018] It should be noted that, in the description of the present application, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or device. The terms "first", "second" and the like in the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0019] In order for those skilled in the art to better understand the technical solutions of the present application, the present application will be further described in detail below with reference to the drawings and specific embodiments.

[0020] The present embodiment provides a network card adapter board, as shown in Figure 1 The power connector 301 is connected to the power board, the plurality of node connectors 302 are respectively connected to different server nodes, the plurality of network card connectors 304 are respectively configured to connect different interfaces of the network cards, and the power and timing signal processing module 303 is respectively connected to the power connector 301, the plurality of node connectors 302 and the plurality of network card connectors 304.

[0021] The power and timing signal processing module 303 is configured to control the power-on of the power supply of the network card and process the power-on timing signal according to the hot plug operation, or control the power-off of the power supply of the network card and process the power-off timing signal according to the hot plug operation.

[0022] In the embodiment, the network card adapter board includes a power connector, a plurality of node connectors, a power and timing signal processing module, and a plurality of network card connectors. The power connector is used to connect an external power board to obtain standby power required by the system; the plurality of node connectors are respectively connected to different server nodes to realize control signal and data communication with the nodes; the plurality of network card connectors are used to connect different interfaces on the network cards; and the power and timing signal processing module is a core control unit of the adapter board, which is connected to the power connector, the node connector, and the network card connector, and is used to coordinate power management and timing control between the plurality of nodes and the network cards during hot plug operation.

[0023] In the hot plug operation, after the network card is physically inserted and the hot plug key is triggered, the power and timing signal processing module detects the hot plug signal and the network card in-place signal, then controls the power circuit to power on the network card according to a preset timing, sequentially enables the auxiliary power and the main power enable signals, and manages the reset signals sent by the plurality of nodes to ensure that the network card completes the power-on and link establishment process according to the specification in the plurality of node environment. In the hot pull-out operation, the module receives the hot pull-out signal, notifies the plurality of nodes to disconnect the link connection with the network card, sequentially turns off the main power, the auxiliary power, and the standby power according to the power-off timing, and controls the reset signal state to ensure that the network card is safely powered off and does not affect subsequent reinsertion.

[0024] The network card adapter board in the embodiment supports shared access of a plurality of server nodes to the same network card, and the nodes are independent of each other, so that failure of any node does not affect normal connection of other nodes to the network card. Timing control and power management realized by hardware can adapt to hot plug requirements of the plurality of nodes of different specifications.

[0025] The power and timing signal processing module 303 includes a power enable control unit, an electronic fuse, and a main power timing signal generation unit.

[0026] The power enable control unit is configured to enable the electronic fuse to power the network card when the hot plug condition is met and there is no hot pull-out operation.

[0027] The power input end of the electronic fuse is connected to the power connector, the power output end of the electronic fuse is connected to the network card connector, and the power normal signal output end of the electronic fuse is connected to the main network card connector to output the auxiliary power timing signal to the network card to control power-on or power-off of the auxiliary power of the network card; wherein the network card returns the network card power normal signal through the main network card connector after the auxiliary power is powered on.

[0028] The main power timing signal generation unit is configured to output the main power timing signal to the network card through the main network card connector to control power-on or power-off of the main power of the network card when the network card power normal signal is received and there is no hot pull-out operation.

[0029] In order to achieve independent and reliable control of the hot plug process of the network card, the power supply and timing signal processing module 303 adopts a phased and sequenced power management architecture. The core of the module includes a power enable control unit, an electronic fuse and a main power timing signal generation unit. Among them, the power enable control unit is responsible for the preliminary judgment of the hot plug operation and the start of the basic power supply. It receives in real time the present signal (PRSNTB#) from each network card connector, the hot insertion signal generated by the hot insertion operation and the hot pull-out signal generated by the hot pull-out operation, and performs logical synthesis on these signals. Only when the network card is physically present, the user has performed a hot insertion operation and has not triggered a hot pull-out operation, the power enable control unit will output a valid signal, thereby enabling the electronic fuse.

[0030] The electronic fuse, as the key execution device of the power supply on-off, has its power input end connected to the power connector to obtain power (such as P12V_STBY, P3V3_STBY) from the external power board. After being enabled, the electronic fuse outputs power to each network card connector to provide basic power supply for the network card. At the same time, the power good signal (PowerGood, PG) generated inside the electronic fuse is directly used as an auxiliary power timing signal (AUX_PWR_EN) and transmitted to the network card through the main network card connector. After receiving the signal, the network card starts to power on the internal auxiliary power domain. After the auxiliary power is stable, the network card returns a high-level valid network card power good signal (NIC_PWR_GOOD) to the network card adapter board through the main network card connector, indicating that it is ready for the next stage.

[0031] The main power timing signal generation unit is responsible for the final main power control. Under the premise that the network card auxiliary power is ready (i.e. receiving the NIC_PWR_GOOD signal) and no hot pull-out operation, the main power timing signal generation unit outputs a valid main power timing signal (MAIN_PWR_EN) which is also sent to the network card through the main network card connector. The network card starts the power-on process of its main power domain according to this signal. In the hot pull-out scenario, the process is executed in reverse: first, the main power timing signal is withdrawn, and after the main power is turned off, the electronic fuse is turned off through the power enable control unit, cutting off the basic power supply, so as to ensure that the whole power-on and power-off process strictly follows the standard timing, avoiding hardware damage or data loss caused by timing disorder.

[0032] The power supply connector, the plurality of node connectors, the plurality of network card connectors and the power supply and timing signal processing module are arranged, a switching control architecture independent of any server node, namely a network card switching board, is constructed, so that power management and key timing signals in the hot plug process no longer depend on independent control of any node, but are uniformly scheduled by the special module on the switching board. When the hot insertion operation occurs, the power supply and timing signal processing module can actively control the power supply sequence of the network card, and ensure that the power-on timing conforms to the network card specification; when hot extraction occurs, power-off and reset can be performed in sequence to avoid abnormal states. Since the power supply and timing signal processing module is connected to the plurality of node connectors at the same time, state indication can be sent to each node before / after the power supply is operated or feedback is received, and synchronization and coordination of multiple nodes in link establishment and disconnection are realized. As can be seen, the hot plug of the network card is realized in the multi-node sharing environment according to the embodiment of the application.

[0033] On the basis of the above embodiment, as a feasible implementation manner, the power supply enable control unit comprises: a first AND logic implementation unit, a first inverting circuit, a second AND logic implementation unit and a second inverting circuit; the input end of the first AND logic implementation unit is connected to the in-place signal output by each network card connector, and the output end of the first AND logic implementation unit is connected to the input end of the first inverting circuit; the input end of the second AND logic implementation unit is connected to the hot insertion signal generated by the hot insertion operation, the output end of the first inverting circuit and the output end of the second inverting circuit, respectively, and the output end of the second AND logic implementation unit is connected to the enable end of the electronic fuse; the input end of the second inverting circuit is connected to the hot extraction signal generated by the hot extraction operation; the main power supply timing signal generation unit comprises a third AND logic implementation unit; the input end of the third AND logic implementation unit is connected to the network card power supply normal signal and the output end of the second inverting circuit, respectively, and the output end of the third AND logic implementation unit is configured to output the main power supply timing signal to the network card through the main network card connector; wherein the network card is configured to control the main power supply to be powered on or powered off according to the received main power supply timing signal.

[0034] In a specific implementation, the AND logic implementation unit can be an AND gate circuit made of MOS transistors, or an AND logic chip, which is not specifically limited herein. The input end of the first AND logic implementation unit is connected to the in-place signal (such as the PRSNTB# signal) output by each network card connector, for comprehensively judging whether the network card is physically in place on all interfaces; the output signal of the first AND logic implementation unit is inverted by the first inverting circuit to generate a high-level valid network card in-place status indication signal. The input end of the second AND logic implementation unit receives the hot plug signal generated by the hot plug operation, the network card in-place status signal output by the first inverting circuit, and the hot unplug signal inverted by the second inverting circuit, respectively. The second AND logic implementation unit performs logical AND operation on the three conditions, and the output is valid only when the hot plug is valid, the network card is in place, and there is no hot unplug operation. The output signal directly controls the enable end of the electronic fuse (EFUSE).

[0035] The power input end of the electronic fuse is connected to the power connector of the adapter board to obtain standby power therefrom; when the enable end is valid, the electronic fuse outputs power to each network card connector to provide basic power supply for the network card. At the same time, the power good signal (PG) generated by the electronic fuse is used as an auxiliary power timing signal (such as AUX_PWR_EN) of the network card, which is output to the network card through the main network card connector. After receiving the valid auxiliary power timing signal, the network card controls the power-on of the internal auxiliary power supply, and returns a network card power good signal (such as NIC_PWR_GOOD) to the adapter board through the main network card connector after the power-on is completed.

[0036] The network card power good signal and the hot unplug signal inverted by the second inverting circuit (i.e., the signal indicating no hot unplug state) are input to the third AND logic implementation unit. The output of the third AND logic implementation unit is used as a main power timing signal (such as MAIN_PWR_EN) and is sent to the network card through the main network card connector. The network card controls the power-on or power-off of the internal main power supply according to the main power timing signal. Through this hierarchical enablement, the module strictly follows the power-on sequence of the auxiliary power supply first and the main power supply second, and the power-off sequence of the main power supply first and the auxiliary power supply second when hot unplug, thereby ensuring the safety and reliability of the network card power management and providing a key hardware guarantee for the hot plug operation in a multi-node environment.

[0037] As a feasible implementation, the power enablement control unit further includes a first delay circuit, and the output end of the second inverting circuit is connected to the input end of the second AND logic implementation unit through the first delay circuit.

[0038] The delay line can be a simple RC (Resistor, Capacitor) delay circuit, the length of which is set by adjusting the values of the resistor and the capacitor, or a more complex digital delay circuit that uses a counter or a register to achieve precise time control. In a specific implementation, the hot plug signal generated by the hot plug operation is first input to the second inverting circuit for inversion, and the output signal is then connected to the newly added first delay line and then connected to the input end of the second AND logic implementation unit through the delay line.

[0039] When the operator triggers the hot plug operation, the first delay line will delay for a period of time after the hot plug signal is inverted and then pass the invalidation signal (indicating that the hot plug action has started) to the second AND logic implementation unit. This delay creates a critical time window: before the hot plug instruction is issued and the network card basic power is not immediately cut off, the system has enough time to preferentially perform the standard power-off process of the main power supply and the auxiliary power supply. Specifically, during this period, the hot plug signal will first pull down the main power supply timing signal through the third AND logic implementation unit, causing the network card main power supply to power off and notifying each node to disconnect the link. Only after the delay time set by the first delay line ends, the second AND logic implementation unit will output a low level due to the change in the input end condition, thereby closing the electronic fuse and cutting off the power supply to the network card. This "delayed power-off" mechanism realized by the first delay line strictly specifies the sequence of power-off, effectively preventing data loss or hardware stress problems that may occur due to instantaneous power-off, thereby making the power timing control of the entire hot plug process more accurate and reliable, fully meeting the high-standard hot plug specification requirements.

[0040] As a feasible implementation, the electronic fuse includes a first electronic fuse and a second electronic fuse, the power input end of the first electronic fuse is connected to a 12V power supply through a power connector, and the power input end of the second electronic fuse is connected to a 3.3V power supply through a power connector; the power and timing signal processing module further includes: a fourth AND logic implementation unit, the input end of the fourth AND logic implementation unit is connected to the power normal signal output end of the first electronic fuse and the second electronic fuse, respectively, and the output end of the fourth AND logic implementation unit is configured to output an auxiliary power timing signal to the network card through the main network card connector.

[0041] In a specific implementation, the electronic fuse includes a first electronic fuse and a second electronic fuse, which are respectively responsible for different voltage domains: the power input end of the first electronic fuse is connected to a 12V power supply through a power connector, which is specifically used to generate and control the 12V standby power (P12V_STBY_OCP) required by the network card; and the power input end of the second electronic fuse is connected to a 3.3V power supply, which is responsible for providing a 3.3V standby power (P3V3_STBY_OCP). The input end of the fourth logical implementation unit is connected to the power good (PG) output end of the first electronic fuse and the second electronic fuse. This means that only when the 12V and 3.3V standby power are stable output and the respective electronic fuses report that the power is normal, the fourth logical implementation unit will output a high level. This output signal is directly configured as an auxiliary power timing signal (such as AUX_PWR_EN) sent to the network card through the main network card connector. This "double confirmation" mechanism is crucial, which ensures that the auxiliary power inside the network card is only allowed to be powered on when both the two-way basic power supply is completely ready, thereby strictly following the integrity and safety requirements of the power timing, effectively preventing the risk of network card initialization failure or damage due to unstable single power supply, and further enhancing the robustness of hot plug operation in complex multi-node environment.

[0042] As a feasible implementation, the main power timing signal generation unit further includes a second delay line, the output end of the third logical implementation unit is connected to the input end of the second delay line, and the output end of the second delay line is connected to the main network card connector. The third logical implementation unit is configured to output the main power timing signal to the network card through the main network card connector through the second delay line.

[0043] In a specific implementation, the output end of the third logical implementation unit is first connected to the input end of the second delay line, and then finally connected to the main network card connector via the output end of the second delay line. This means that the original main power timing signal generated by the third logical implementation unit must be delayed for a preset time by the second delay line before it can be output as an effective main power timing signal to the network card. When the auxiliary power of the network card is powered on and returns the power normal signal, the third logical implementation unit will immediately respond and output a high level, but the signal needs to be delayed by the second delay line before it finally takes effect. That is, a controllable time interval is forcibly inserted before the main power is enabled. This delay ensures that the auxiliary power inside the network card has enough time to reach a fully stable state, power the core logic and complete the initial initialization, and then allow the main power to be powered on. In this way, the second delay line strictly establishes the time sequence between the two key events of auxiliary power readiness and main power opening, thereby reliably implementing the key step of "stabilizing the auxiliary power before turning on the main power" required in the network card power timing specification, effectively preventing problems such as power surge, logic competition or initialization failure that may be caused by the main power turning on too early, and ensuring the reliability and stability of the network card hot insertion process.

[0044] As a feasible implementation, the power and timing signal processing module further includes a bandwidth configuration signal processing unit connected to the bandwidth allocation pins of the network card through each network card connector. The bandwidth configuration signal processing unit is configured to output a preset bandwidth configuration level signal to the network card to configure the network card into a mode of sharing bandwidth among multiple server nodes.

[0045] In a specific implementation, the bandwidth configuration signal processing unit is responsible for initializing and allocating the PCIe (Peripheral Component Interconnect Express) channel resources of the network card to adapt to the application scenario of multi-node sharing. The bandwidth configuration signal processing unit is physically connected to the specific pins for bandwidth allocation on the network card through the network card connector, that is, the BIF (Bandwidth Indication Function) pins. The core function of the bandwidth configuration signal processing unit is to output a set of pre-set and fixed level signal combinations to these pins. This set of pre-set level signals is equivalent to issuing an explicit configuration instruction to the network card hardware, which tells the network card how to divide its internal PCIe channel resources. For example, in a typical dual-node scenario, the unit can divide the total bandwidth (such as 32 PCIe channels) of the network card into two independent X16 channel groups by configuring the level signal to a specific mode, and assign them to two server nodes respectively, thereby realizing the hard partitioning and sharing of bandwidth. This configuration is completed at the initial power-on of the network card before the link with the node is established, ensuring that the network card can start in the correct hardware mode and laying the foundation for subsequent identification and access by multiple server nodes. Through this hardware-level static configuration method, the bandwidth configuration signal processing unit realizes the flexible and reliable division of a single network card into multiple logical endpoints, enabling it to be identified and shared by multiple server nodes, thereby fully utilizing the resource utilization and flexibility advantages of high-performance network cards in a multi-node server architecture.

[0046] As a feasible implementation, the power and timing signal processing module further includes a plurality of bus switches, the first signal end of the bus switch is configured to receive the reset signal sent by the corresponding node connector, the second signal end of the bus switch is connected to the reset pin of the network card through the corresponding network card connector, and the enable end of the bus switch is connected to the output end of the third and logic implementation unit.

[0047] In a specific implementation, the power and timing signal processing module further includes a plurality of bus switches (BUS SWITCH) for safe isolation and control on the reset signal path between the network card and the server node. The first signal end (input side) of each bus switch is configured to receive the reset signal (such as the HOST_PERST# signal) sent by the server node from the corresponding node connector. The second signal end (output side) is connected to the corresponding reset pin of the network card through the corresponding network card connector. The enable ends (OE) of all bus switches are not independently controlled, but are uniformly connected to the output end of the third and logic implementation unit, which is the generation point of the main power timing signal (MAIN_PWR_EN).

[0048] By this embodiment, the reset state of the network card is forced to synchronize with the power-on and power-off timing of the main power supply. When the main power supply is not on (i.e. MAIN_PWR_EN is invalid), the enable terminal of the bus switch is in the disabled state, at this time the switch is off, and the reset signal sent by the node cannot be transmitted to the network card. At the same time, the reset pin of the network card is internally maintained at a valid reset level by a pull-down resistor, ensuring that the network card will not enter the working state when not fully powered in any unexpected situation, thereby avoiding potential bus conflicts or logic errors. Only when the main power supply timing signal is valid (MAIN_PWR_EN is valid), the bus switch is synchronously enabled, thereby connecting the reset signal generated by each server node to the network card, at this time the node can manage the network card reset operation by controlling these reset signals, thereby realizing safe and reliable hot plug.

[0049] As a feasible implementation, the power supply and timing signal processing module further comprises a second delay circuit and a third delay circuit, the input end of the second delay circuit is connected to the output end of the third AND logic implementation unit, the output end of the second delay circuit is connected to the input end of the third delay circuit, and the output end of the third delay circuit is connected to the enable terminals of the plurality of bus switches.

[0050] In a specific implementation, the input end of the second delay circuit is directly connected to the output end of the third AND logic implementation unit to receive the generated main power supply timing signal; the output end of the second delay circuit is connected to the input end of the third delay circuit, and the final output end of the third delay circuit is connected to the enable terminals of all bus switches. After the main power supply timing signal is valid, the bus switch is not immediately turned on, but a controlled and phased waiting time is forced to be inserted. The main power supply timing signal first passes through the second delay circuit, and this delay ensures that the main power supply enable command has taken full effect and provides an initial stable time for the power-on of the network card main power supply domain; then, the signal further passes through the third delay circuit for further delay, which ensures that the network card internal main power supply has enough time to reach a fully stable working state. Finally, when the signal after two levels of delay reaches the bus switch enable terminal, the power supply environment of the network card is in a stable and reliable state, and at this time the bus switch is allowed to be turned on to transmit the reset signal of the server node to the network card. This design strictly follows the basic principle of "stabilize the power supply before processing the reset" of the hardware operation, effectively prevents the network card logic error or link training failure that may be caused by the reset operation when the power supply is not stable, and significantly improves the success rate and reliability of the hot insertion process.

[0051] As a feasible implementation, the hot plug interaction module further comprises: a hot plug-in key configured to receive a hot plug-in operation and generate a hot plug-in key signal; a hot plug-in key signal processing unit configured to generate a hot plug-in signal based on the hot plug-in key signal; a hot plug-out key configured to receive a hot plug-out operation and generate a hot plug-out key signal; and a hot plug-out key signal processing unit configured to generate a hot plug-out signal based on the hot plug-out key signal.

[0052] In a specific implementation, the hot plug interaction module is a key interface between the operator and the hardware system for safe operation, and its core function is to receive the operator's instructions and convert them into stable control signals recognizable by the system. The hot plug interaction module specifically includes four main parts: first, a hot plug-in key, which is physically configured to receive the operator's hot plug-in operation (such as a pressing action) and generate a raw hot plug-in key electrical signal accordingly; second, a hot plug-in key signal processing unit connected to the hot plug-in key, responsible for shaping and confirming the received raw hot plug-in key signal, ultimately generating a stable hot plug-in signal and distributing it to the core control logic of the system. Correspondingly, the hot plug interaction module also includes a hot plug-out key for receiving the operator's hot plug-out operation and generating a raw hot plug-out key signal, and a hot plug-out key signal processing unit that generates a stable hot plug-out signal based on the key signal. Through this modular design, unstable mechanical key actions are converted into reliable digital control commands, providing a clear and error-proof starting mechanism for the entire hot plug process.

[0053] As a feasible implementation, the hot plug-in key signal processing unit includes a first debounce circuit and a first flip-flop, the hot plug-in key is connected to the first debounce circuit, the first debounce circuit is connected to the first flip-flop, and the first flip-flop is connected to the signal connector corresponding to each node; the hot plug-out key signal processing unit includes a second debounce circuit and a second flip-flop, the hot plug-out key is connected to the second debounce circuit, the second debounce circuit is connected to the second flip-flop, and the second flip-flop is connected to the signal connector corresponding to each node.

[0054] In a specific implementation, the electrical output end of the hot plug-in key is directly connected to the input end of the first anti-jitter circuit, which effectively filters out the millisecond-level level jitter generated when the key contact is closed or opened through hardware RC filtering or a dedicated anti-jitter chip, and outputs a preliminarily smoothed level signal; this signal is then sent to the clock or data input end of the first flip-flop, which samples and latches at the next clock edge, finally outputting a clean, jitter-free and system clock-synchronized stable hot plug-in signal, which is then connected to the corresponding signal connector of each node, thereby reliably informing all server nodes of the occurrence of the hot plug-in event. Similarly, the hot pull-out key is connected to the second anti-jitter circuit and the second flip-flop in turn, and the second flip-flop generates a stable hot pull-out signal and sends it to each node. This cascaded design of "anti-jitter circuit + flip-flop" fundamentally eliminates multiple false triggers caused by mechanical jitter, ensuring the accuracy of the hot plug-in command and the reliability of system operation.

[0055] As a feasible implementation, the hot plug interaction module further comprises a hot plug-in indicator light and a hot pull-out indicator light; the output end of the third AND logic implementation unit is connected to the hot plug-in indicator light and the hot pull-out indicator light, so as to control the hot plug-in indicator light and the hot pull-out indicator light according to the main power timing signal output by the third AND logic implementation unit.

[0056] In a specific implementation, the hot plug interaction module also integrates a visual feedback unit, specifically including a hot plug-in indicator light and a hot pull-out indicator light, for directly displaying the current power state of the network card and the result of the hot plug operation to the operator. The output end of the third AND logic implementation unit, i.e., the generated main power timing signal (MAIN_PWR_EN), is connected to the control end of the hot plug-in indicator light and the hot pull-out indicator light. Its control mechanism is that the main power timing signal is the final sign of the completion of the power-on of the network card core power supply, when the main power timing signal is at a valid level, it indicates that the main power supply domain of the network card has been successfully established and stabilized, and the entire hot plug-in process has been substantially completed; when the main power timing signal is at an invalid level, it indicates that the main power supply of the network card has been disconnected, and the hot pull-out process has been executed in place. Therefore, by driving the indicator light with the main power timing signal, the core running state of the network card can be truly reflected. For example, when the main power timing signal is valid, the hot plug-in indicator light can be lit (e.g., green), informing the operator that the network card is ready and can be used normally; when the main power timing signal is invalid, the hot pull-out indicator light is lit (e.g., red), prompting the operator that the network card has been safely powered off and can be physically removed. This design provides the operator with clear, accurate and strictly synchronized state indication with the internal power state, greatly improving the safety and user experience of hot plug operation.

[0057] As a feasible implementation, the power supply and timing signal processing module further comprises a second delay line, a third delay line and a fourth delay line, the input end of the second delay line is connected to the output end of the third and logical implementation unit, the output end of the second delay line is connected to the input end of the third delay line, the output end of the third delay line is connected to the input end of the fourth delay line, and the output end of the fourth delay line is connected to the hot insertion indicator light and the hot extraction indicator light.

[0058] In a specific implementation, the input end of the second delay line is connected to the output end of the third and logical implementation unit to receive the original main power supply timing signal, the output end of the second delay line is connected to the input end of the third delay line, the output end of the third delay line is further connected to the input end of the fourth delay line, and the final output end of the fourth delay line is connected to the control end of the hot insertion indicator light and the hot extraction indicator light.

[0059] It can be seen that the main power supply timing signal is fully delayed and shaped in the embodiment, and the indicator light is driven. The delay of the second delay line can be used to ensure the stability of the main power supply timing signal itself; the signal then passes through the third delay line, which can ensure that the main power supply has been completely established and the subsequent key operations (such as the opening of the bus switch and the release of the reset signal) have been performed; finally, the signal passes through the delay of the fourth delay line, which can be intentionally set to a relatively long time, and the purpose is to ensure that before the indicator light is lit, the network card not only completes the power-on, but also successfully establishes a stable PCIe link with the server node and enters a normal working state. Therefore, when the indicator light is finally lit, it conveys to the operator not only "the power supply has been turned on", but also "the network card is completely ready for business use", thereby providing a higher level and more reliable operation completion confirmation, effectively preventing the operator from misjudging that the operation has been completed when the link has not been successfully established, and greatly improving the usability and safety of the system.

[0060] The embodiment provides a server system, as shown in the figure, comprising a power board 10, a plurality of server nodes 20 and a network card adapter board 30 provided by the above embodiment, the power board 10 supplies power to the network card 40 through the network card adapter board 30, and the plurality of server nodes 20 are connected to the network card 40 through the network card adapter board 30. Figure 2

[0061] Among them, the power board 10 serves as the centralized power supply unit of the system, and is connected to the power connector of the network card adapter board 30 to provide stable and reliable 12V and 3.3V standby power input for the entire hot plug operation. The plurality of server nodes 20 represent the computing units of the system, and are interconnected through respective signal interfaces and corresponding node connectors on the network card adapter board 30.

[0062] ​In the server system, one end of the network card adapter board 30 is connected to the power board 10 to obtain power, and the other end is connected to multiple server nodes 20 to interact with signals, and the network card connector thereon is used to plug in the network card 40. The core workflow is: when the network card 40 is physically inserted into the adapter board and triggers the hot plug operation, the power supply and timing signal processing module inside the adapter board will strictly follow the standard sequence to control the power provided by the power board to be applied to the network card in an orderly manner, and manage the power-on and power-off timing. At the same time, the adapter board coordinates the reset signal on-off and PCIe link establishment / disconnection process between each server node 20 and the network card 40.

[0063] As a feasible implementation, the server node includes an intra-node signal processing module configured to send a reset signal to the network card through the network card adapter board after receiving a hot plug-in signal to establish a communication link with the network card, or to disconnect the communication link with the network card after receiving a hot plug-out signal.

[0064] In specific implementation, an intra-node signal processing module is integrated in each server node, and the core function of the intra-node signal processing module is to receive global control signals from the network card adapter board and perform corresponding link operations. Specifically, when the intra-node signal processing module receives a valid hot plug-in signal through the network card adapter board, it does not immediately act, but cooperates to monitor the power-on and reset timing state of the network card. After confirming that the network card power is stable and the reset condition is met, the module sends a reset signal to the network card through the bus switch on the network card adapter board, and then triggers the PCIe link training process between the node and the network card, and finally establishes a stable and reliable communication link. Conversely, when the module receives a hot plug-out signal, it will immediately start the link disconnection process: first ensure that all ongoing data services have been safely stopped or migrated, then actively disconnect the PCIe logical connection with the network card, and finally make the network card enter the reset state. By deploying this dedicated signal processing module inside each server node, it ensures that multiple nodes can independently, orderly and safely manage and share the connection of the network card, and realizes multi-node hot plug-in cooperation.

[0065] As a feasible implementation, the server system includes a first server node and a second server node, and the network card is a double-slot network card.

[0066] In a specific implementation, the server system is specifically a dual-node application scenario, and the architecture thereof includes a first server node and a second server node. The two nodes are logically independent of each other and each assumes a computing task, but work cooperatively through a network and system management. To match the architecture, the network card used in the system is a specific dual-slot network card, such as a DSFF (Dual Small Form Factor) network card or a TDSFF (Tall Dual Small Form Factor) network card. The physical characteristic of such a network card is that it is designed with two independent hardware interfaces (such as two 4C+ connectors), which enables it to establish a physical connection with the first server node and the second server node through a network card adapter board at the same time.

[0067] It can be seen that, by introducing a dedicated network card adapter board, the embodiment realizes safe sharing and independent thermal management of a single high-performance network card by multiple nodes of a server. The failure or maintenance of any server node will not affect the other nodes to continue accessing the network card through the adapter board, and the controlled power supply provided by the power board through the adapter board also ensures that the hot plug process will not impact the stability of the system.

[0068] On the basis of the above embodiment, as a preferred implementation, the server system further includes a dynamic arbitration module connected with the plurality of server nodes and configured to, before performing a hot plug operation, acquire health state information of each node in the plurality of server nodes; if at least one node is in an unhealthy state, delay or prohibit the execution of the hot plug operation and send an alarm signal; and if all nodes are in a healthy state, allow the hot plug operation to be executed in a normal process.

[0069] In a specific implementation, the dynamic arbitration module acquires the health state of each server node in real time, such as the node power state, temperature, PCIe link stability, and the like. When a user triggers a hot plug operation (such as pressing a hot plug-in or hot plug-out button), the initial signal generated by the hot plug interaction module will not be immediately responded by the power and timing signal processing module, but will be first sent to the dynamic arbitration module for decision-making. The arbitration module will check the health state of all related nodes: if it is found that one of the nodes is in an unhealthy state such as failure, overload, high temperature, or PCIe training failure, the arbitration module will output a control signal to temporarily delay or completely prohibit the execution process of the current hot plug operation, and send a detailed alarm to prompt the operation and maintenance personnel to handle the node exception in priority; only when all nodes are determined to be healthy, the arbitration module allows the hot plug control signal to pass, thereby triggering the subsequent standard power-on / power-off timing process.

[0070] As can be seen, this implementation effectively prevents risks such as link establishment failure, data loss, or even system downtime that may occur when hot-swapping is performed during node anomalies, greatly improving the system's robustness and reliability. Through a proactive alarm mechanism, potential system problems are exposed to maintenance personnel before the hot-swapping operation, realizing a shift from a reactive fault response to a proactive fault prevention maintenance model, thus improving system maintainability. Simultaneously, it enhances the overall collaborative management capabilities of this complex multi-node server system, ensuring that the high-risk hot-swapping operation is only performed under stable and secure conditions, thereby guaranteeing the continuity of critical business operations and data integrity.

[0071] The following describes an application embodiment provided by the present invention, such as... Figure 3 As shown, the system includes a hot-plug interaction module, a power and timing signal processing module, and an intra-node signal processing module. The hot-plug interaction module includes a hot-plug button, a hot-plug button, and hot-plug / hot-plug indicator lights for interaction with hot-plug operators. The power and timing module powers on the DSFF network card and processes related timing signals after a hot-plug operation, ensuring the power-on timing conforms to specifications and thus guaranteeing normal operation. It also powers off the DSFF network card and processes related timing signals after a hot-plug operation, ensuring proper power-off. The intra-node signal processing module ensures that when two server nodes receive a hot-plug signal from the DSFF network card, they send a PCIe reset signal to the network card and establish a link connection; or, upon receiving a hot-plug signal, they disconnect the link, ensuring the integrity of service data and preventing data loss.

[0072] like Figure 4As shown, the common power board provides P12V_STBY and P3V3_STBY power for the DSFF adapter board, and the two powers are respectively converted to P12V_STBY_OCP and P3V3_STBY_OCP electricity through the EFUSE chip, and are connected to the DSFF Primary 4C+ connector (main network card connector) and the Second 4C+ connector (secondary network card connector) to provide power for the DSFF network card. The corresponding timing management signals of DSFF / TDSFF are AUX_PWR_EN0 (auxiliary power timing signal), MAIN_PWR_EN0 (main power timing signal), and NIC_PWR_GOOD0 (network card power normal signal) on the Primary connector, and AUX_PWR_EN1, MAIN_PWR_EN1, and NIC_PWR_GOOD1 signals on the Second connector are only reserved. After the DSFF network card is hot inserted, the hot insertion button is pressed. DSFF_HOT_IN_BTN# (hot insertion button signal) will generate a low-level pulse signal, and after the pulse signal passes through the debouncing circuit and the flip-flop, a stable DSFF_HOT_IN (hot insertion signal) high-level signal is generated, indicating that the hot insertion action is performed. After the DSFF network card is inserted into the DSFF adapter board, PRSNTB#[0, 1, 2, 3] and PRSNTB#[4, 5, 6, 7] signals will change, and some PRSNTB# signals (bit signals) will be pulled low. PRSNTB#[0, 1, 2, 3] and PRSNTB#[4, 5, 6, 7] pass through AND1 (AND gate 1) and the inverting circuit to generate the DSFF in-place signal. When the DSFF_HOT_IN signal and the DSFF in-place signal are enabled at the same time, and no hot pull-out action is triggered, AND2 gate circuit outputs high level, enabling P12V_STBY_OCP EFUSE (12V power signal) and P3V3_STBY_OCPEFUSE (3.3V power signal), generating P12V_STBY_OCP and P3V3_STBY_OCP power to power the DSFF network card.

[0073] After the P12V_STBY_OCP and P3V3_STBY_OCP power supplies are powered on, the PG signals of the two power supplies are logically ANDed by AND3 (AND gate 3) and are used as the AUX_PWR_EN0 timing signal of the DSFF network card and are connected to the DSFF network card. At the same time, the BIF (bandwidth indication signal) is in a fixed pull-up / pull-down mode on the DSFF adapter board, and the bandwidth of the DSFF network card is allocated as X16+X16, and each node corresponds to an X16 PCIE. After the network card receives the AUX_PWR_EN0, the internal AUX power of the network card is powered on, and after the power-on is completed, the network card actively sends the NIC_PWR_GOOD0 signal to the two nodes. At the same time, when no hot plug action is triggered, the NIC_PWR_GOOD0 signal on the DSFF adapter board is logically ANDed by AND4 (AND gate 4) and a delay line 1 to generate the MAIN_PWR_EN0 signal to the Primary main connector, and the network card starts to power on the internal MAIN power.

[0074] After the MAIN_PWR_EN0 signal is valid, it is connected to the enable signal OE of the two BUS SWITCHs (bus switches) through a delay line 2. When the OE enable signal of the two BUS SWITCHs is low, the BUS SWITCH is closed, and the PERST#[0, 1, 2, 3] and PERST#[4, 5, 6, 7] (reset signals) connected to the DSFF network card on the DSFF adapter board are pulled low by default, and the network card is always in a reset state. After the MAIN_PWR_EN0 signal is valid, the OE enable signal of the two BUS SWITCHs is pulled high through the delay line 2, and the BUS SWITCH is opened, and the HOST_PERST#[0, 1, 2, 3] and HOST_PERST#[4, 5, 6, 7] (reset signals) sent by the two nodes can be normally connected to the DSFF Primary 4C+ connector and the Second 4C+ connector. The node provides a 100M reference clock signal to the DSFF network card, which can be provided by the CPU (Central Processing Unit, central processor) in the node or by a clock generator / clock buffer in the node. The CPU of each node is connected to the network card through PCIE X16, and after the node receives the DSFF_HOT_IN signal, it sends HOST_PERST#[0, 1, 2, 3] and HOST_PERST#[4, 5, 6, 7], and after the BUS SWITCH is opened, it is connected to the DSFF network card, and the network card is reset, and the DSFF / TDSFF network card can work normally. In addition, after the MAIN_PWR_EN0 signal is valid, the hot plug indicator light is lit through the delay line 2 and the delay line 3, indicating that the DSFF network card hot plug action is completed.

[0075] When the DSFF hot removal action is needed, the hot pull-out button needs to be pressed. DSFF HOT REMOVE BTN# (hot pull-out button signal) generates a low-level pulse signal, which, after passing through the debouncing circuit and flip-flop, generates a stable DSFF HOT REMOVE (hot pull-out signal) high-level signal, indicating that the hot removal action will be performed. The DSFF HOT REMOVE signal is connected to two nodes, informing the two nodes that the DSFF network card will perform hot removal, and after the two nodes receive the signal, the link connection between the CPU and the DSFF network card of the node is disconnected. In addition, DSFF HOT REMOVE, after passing through the inverter circuit, AND4 (AND gate 4) and delay circuit 1, pulls down the MAIN PWR EN0 signal, and the MAIN power of the DSFF network card is powered off. The MAIN PWR EN0 signal synchronously passes through delay circuit 2 to pull down the enable signal OE of the two BUS SWITCHes, and the BUS SWITCH is disconnected, and PERST#[0, 1, 2, 3] and PERST#[4, 5, 6, 7] return to the default low state, and the DSFF network card is reset.

[0076] In addition, the DSFF HOT REMOVE signal, after passing through the inverter circuit and delay circuit 4, is connected to AND2 (AND gate 2) to pull down the AND2 output, pull down the enable signal of P12V_STBY_OCP and P3V3_STBY_OCP power EFUSE, and power off P12V_STBY_OCP and P3V3_STBY_OCP power, and synchronously pull down AUX PWR EN0 signal. The DSFF network card is powered off, the MAIN PWR EN0 signal, after passing through delay circuit 2 and delay circuit 3, lights up the hot pull-out indicator, indicating that the DSFF network card hot pull-out action is completed, and the network card can be physically removed.

[0077] As Figure 5As shown, after the DSFF network card is hot-inserted and the hot-insertion button is pressed, the DSFF_HOT_IN signal is generated through the debouncing circuit and trigger to inform the two nodes. This signal is then connected to the enable control P12V_STBY_OCP and P3V3_STBY_OCP of the power supply EFUSE via an AND gate to power on. After power-on, the AUX_PWR_EN0 and MAIN_PWR_EN0 timing signals of the DSFF network card are pulled high in sequence, and the two BUS SWITCH switches are turned on. The HOST_PERST#[0,1,2,3] and HOST_PERST#[4,5,6,7] signals of the two nodes are connected to the DSFF Primary 4C+ connector and Second 4C+ connector, respectively. After the network card is reset, the DSFF network card can work normally. In addition, the MAIN_PWR_EN0 signal also passes through delay lines 2 and 3 to illuminate the network card hot-insertion indicator light, indicating that the network card hot-insertion operation is complete.

[0078] like Figure 6 As shown, after the DSFF network card presses the hot-remove button, it generates a DSFF_HOT_REMOVE signal through a debouncing circuit and a trigger to inform the two nodes. Upon receiving the signal, the two nodes disconnect the PCIe link from the network card. Furthermore, the DSFF_HOT_REMOVE signal, after passing through an inverting circuit, an AND4 gate, and delay circuit 1, pulls the MAIN_PWR_EN0 signal low. The MAIN_PWR_EN0 signal, after passing through delay circuit 2, turns off the two BUS SWITCH switches, pulling the DSFF network card's PERST#[0,1,2,3] and PERST#[4,5,6,7] signals low, resetting the network card. The DSFF_HOT_REMOVE signal also passes through an inverting circuit, delay circuit 4, and an AND2 gate, pulling down the power supply EFUSE enable control P12V_STBY_OCP and P3V3_STBY_OCP, powering down the DSFF network card. After MAIN_PWR_EN0 passes through delay line 2 and delay line 4, the hot-pull indicator light illuminates, indicating that the DSFF network card hot-pull operation is complete and the network card can be physically removed.

[0079] The embodiment provides a double-node DSFF network card hot plug implementation method, interacts with a server through a hot insertion button or a hot pull-out button, informs two server nodes to establish or disconnect a PCIE Link with the network card, and simultaneously passes through a series of reasonable hardware lines on a DSFF adapter plate to ensure that power supply, timing signals, reset signals and the like are sequentially enabled according to a power-on timing sequence in the DSFF specification after the DSFF network card is hot inserted, so that the DSFF network card normally runs and establishes a connection with the two server nodes after being powered on, and when the DSFF network card is hot pulled out, timing signals, reset signals, electrical signals and the like are sequentially released according to the specification, the DSFF network card is normally disconnected from the two nodes and powered off, and the next network card hot insertion action is not affected.

[0080] The network card adapter plate and the server system provided by the application are described in detail above. The principles and implementation manners of the application are described by applying specific examples in this paper, and the above embodiment description is only used to help understand the method of the application and the core idea thereof. It should be pointed out that, for those skilled in the art, some improvements and modifications can be made to the application without departing from the principles of the application, and these improvements and modifications also fall within the protection scope of the application.

Claims

1. A network card adapter plate, characterized by, The power supply connector is connected to a power supply board, the plurality of node connectors are respectively connected to different server nodes, and the plurality of network card connectors are respectively configured to connect different interfaces of network cards. The power supply and timing signal processing module includes a power supply enable control unit, an electronic fuse, and a main power supply timing signal generation unit. The power supply enable control unit is configured to enable the electronic fuse to supply power to the network card when the hot insertion condition is met and there is no hot removal operation. The power supply input end of the electronic fuse is connected to the power supply connector, the power supply output end of the electronic fuse is connected to each network card connector, and the power supply normal signal output end of the electronic fuse is connected to the main network card connector to output an auxiliary power supply timing signal to the network card to control the power-on or power-off of the auxiliary power supply of the network card. The main power supply timing signal generation unit is configured to output a main power supply timing signal to the network card through the main network card connector to control the power-on or power-off of the main power supply of the network card when the network card power normal signal is received and there is no hot removal operation.

2. The net card adapter plate of claim 1, wherein, The power supply enable control unit includes a first AND logic implementation unit, a first inversion circuit, a second AND logic implementation unit, and a second inversion circuit. The input end of the first AND logic implementation unit is connected to the in-place signal output by each network card connector, and the output end of the first AND logic implementation unit is connected to the input end of the first inversion circuit. The input end of the second AND logic implementation unit is respectively connected to the hot insertion signal generated by the hot insertion operation, the output end of the first inversion circuit, and the output end of the second inversion circuit, and the output end of the second AND logic implementation unit is connected to the enable end of the electronic fuse. The input end of the second inversion circuit is connected to the hot removal signal generated by the hot removal operation. The main power supply timing signal generation unit includes a third AND logic implementation unit. The input end of the third AND logic implementation unit is respectively connected to the network card power normal signal and the output end of the second inversion circuit, and the output end of the third AND logic implementation unit is configured to output a main power supply timing signal to the network card through the main network card connector.

3. The net card adapter plate of claim 2, wherein, The power supply enable control unit further includes a first delay circuit, and the output end of the second inversion circuit is connected to the input end of the second AND logic implementation unit through the first delay circuit.

4. The net card adapter plate of claim 2, wherein, The electronic fuse includes a first electronic fuse and a second electronic fuse, the power supply input end of the first electronic fuse is connected to a 12V power supply through the power supply connector, and the power supply input end of the second electronic fuse is connected to a 3.3V power supply through the power supply connector. The power supply and timing signal processing module further comprises a fourth AND logic implementation unit, input ends of the fourth AND logic implementation unit are connected to power normal signal output ends of the first electronic fuse and the second electronic fuse respectively, and an output end of the fourth AND logic implementation unit is configured to output the auxiliary power supply timing signal to the network card through the main network card connector.

5. The net card adapter plate of claim 2, wherein, The main power supply timing signal generation unit further comprises a second delay line, an output end of the third AND logic implementation unit is connected to an input end of the second delay line, and an output end of the second delay line is connected to the main network card connector, and the third AND logic implementation unit is configured to output the main power supply timing signal to the network card through the main network card connector through the second delay line.

6. The net card adapter plate of claim 2, wherein, The power supply and timing signal processing module further comprises a bandwidth configuration signal processing unit, the bandwidth configuration signal processing unit is connected to bandwidth distribution pins of the network card through each network card connector, and the bandwidth configuration signal processing unit is configured to output a preset bandwidth configuration level signal to the network card to configure the network card in a mode of sharing bandwidth by multiple server nodes.

7. The net card adapter plate of claim 2, wherein, The power supply and timing signal processing module further comprises a plurality of bus switches, a first signal end of each bus switch is configured to receive a reset signal sent by a corresponding node connector, a second signal end of each bus switch is connected to a reset pin of the network card through a corresponding network card connector, and an enable end of each bus switch is connected to an output end of the third AND logic implementation unit.

8. The net card adapter plate of claim 7, wherein, The power supply and timing signal processing module further comprises a second delay line and a third delay line, an input end of the second delay line is connected to an output end of the third AND logic implementation unit, an output end of the second delay line is connected to an input end of the third delay line, and an output end of the third delay line is connected to enable ends of the plurality of bus switches.

9. The net card adapter plate of claim 2, wherein, Further comprising a hot plug interaction module, the hot plug interaction module comprises: A hot plug-in key configured to receive a hot plug-in operation and generate a hot plug-in key signal; A hot plug-in key signal processing unit configured to generate a hot plug-in signal based on the hot plug-in key signal; A hot plug-out key configured to receive a hot plug-out operation and generate a hot plug-out key signal; A hot plug-out key signal processing unit configured to generate a hot plug-out signal based on the hot plug-out key signal.

10. The net card adapter plate of claim 9, wherein, The hot plug-in key signal processing unit comprises a first debounce circuit and a first flip-flop, the hot plug-in key is connected to the first debounce circuit, the first debounce circuit is connected to the first flip-flop, and the first flip-flop is connected to a signal connector corresponding to each node; The hot plug-out key signal processing unit comprises a second debounce circuit and a second flip-flop, the hot plug-out key is connected to the second debounce circuit, the second debounce circuit is connected to the second flip-flop, and the second flip-flop is connected to a signal connector corresponding to each node.

11. The net card adapter plate of claim 9, wherein, The hot plug interaction module further comprises a hot plug-in indicator light and a hot plug-out indicator light; The output end of the third and logic implementation unit is connected to the hot plug indicator light and the hot unplug indicator light, so as to control the hot plug indicator light and the hot unplug indicator light according to the main power supply timing signal output by the third and logic implementation unit.

12. The net card adapter plate of claim 11, wherein, The power supply and timing signal processing module further comprises a second delay circuit, a third delay circuit and a fourth delay circuit, the input end of the second delay circuit is connected to the output end of the third and logic implementation unit, the output end of the second delay circuit is connected to the input end of the third delay circuit, the output end of the third delay circuit is connected to the input end of the fourth delay circuit, and the output end of the fourth delay circuit is connected to the hot plug indicator light and the hot unplug indicator light.

13. A server system, characterized by The server system comprises a power board, a plurality of server nodes and the network card adapter board as claimed in any one of claims 1 to 12, the power board supplies power for the network card through the network card adapter board, and the plurality of server nodes are connected to the network card through the network card adapter board.

14. The server system of claim 13, wherein, The server node comprises an intra-node signal processing module, which is configured to send a reset signal to the network card through the network card adapter board to establish a communication link with the network card after receiving a hot plug signal, or to disconnect the communication link with the network card after receiving a hot unplug signal.

15. The server system of claim 13, wherein, The server system comprises a first server node and a second server node, and the network card is a double-slot network card. The server system comprises a first server node and a second server node, and the network card is a double-slot network card.

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