Cascade amplification circuit module based on complementary parameter amplifier

Abstract

A cascade amplification circuit module based on complementary parameter amplifiers belongs to the technical field of integrated circuit amplifiers and comprises a first-stage complementary parameter amplifier (CPA) and a second-stage amplifier (floating inverting type or transconductance resistance type). The first-stage CPA adopts an NMOS and PMOS complementary structure, passive amplification is achieved through grid multiplexing, a grid capacitor is used for storing signals in the sampling stage, a depletion layer capacitor is switched to improve gain in the amplification stage, common-mode voltage is stabilized through complementary design, and an extra feedback circuit is not needed. And the second-stage amplifier provides driving capability and is combined with passive gain to suppress noise. The cascade structure does not need frequency compensation, the design is simplified, the problem of balancing gain, noise and power consumption of a traditional amplifier is solved, and the cascade amplifier has the advantages of being high in energy efficiency and low in complexity.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit amplifier technology, specifically relating to a cascaded amplifier circuit module based on complementary parameter amplifiers. Background Technology

[0002] With the rapid development of communication technologies, sensor design, computing power, and healthcare applications, the Internet of Things (IoT) devices will experience unprecedented growth in the coming years. This rapid evolution places higher demands on analog-to-digital converters (ADCs), especially in terms of high resolution and low power consumption, in order to efficiently digitize the outputs of high dynamic range (DR) sensors within a limited power budget. As a crucial part of the signal chain, the accuracy, speed, and power consumption of ADCs have become determinants of signal processing accuracy, speed, and power consumption.

[0003] In the design of high-efficiency, high-precision ADCs, the energy efficiency of components such as comparators and amplifiers is often a key factor determining the overall system performance. Traditional cascode amplifiers can achieve high gain, but their swing is limited, and their energy efficiency is low due to their static operation. A floating inverter amplifier proposed in recent literature [X. Tang et al., "An Energy-Efficient Comparator With Dynamic Floating Inverter Amplifier," in IEEE Journal of Solid-State Circuits, vol.55, no.4, pp.1011-1022, April 2020, doi:10.1109 / JSSC.2019.2960485.] achieves dynamic operation and does not require additional common-mode feedback circuitry; however, its gain is typically low, and its noise is relatively high, making it difficult to meet the requirements of high energy efficiency and high performance. The parametric amplifier proposed in the literature [S. Ranganathan and Y. Tsividis, "Discrete-time parametric amplification based on a three-terminal MOS variable: analysis and experimental results," in IEEE Journal of Solid-State Circuits, vol. 38, no. 12, pp. 2087-2093, Dec. 2003, doi: 10.1109 / JSSC.2003.819162.] is a passive amplifier that achieves amplification by changing the transistor capacitance through bias transistors. It boasts advantages such as ultra-low power consumption and only sampling noise without flicker noise. However, it cannot actively drive loads and has relatively low gain. In existing amplifier designs, there is a trade-off between power consumption, area, and noise, and cascaded amplifiers typically require frequency compensation to meet stability requirements, increasing complexity. Therefore, at this stage, we need amplifier circuits with higher gain and higher energy efficiency. Summary of the Invention

[0004] In view of the above, this invention proposes a compensation-free two-stage cascaded amplifier based on a complementary parametric amplifier (CPA). Utilizing a low-power, low-noise CPA as the preamplifier stage and employing a transconductance resistance (GmR) amplifier or a floating inverting amplifier as the driver stage, high gain is achieved while the first stage provides passive amplification. The CPA reduces the noise requirements of the second-stage amplifier, and the second-stage amplifier provides the necessary driving capability. This invention combines passive and active amplification, eliminating the need for compensation resistors and capacitors, and offers the overall advantages of high gain, high energy efficiency, and low noise.

[0005] The first-stage amplifier is a complementary parametric amplifier. Based on a traditional parametric amplifier, it uses both NMOS and PMOS transistors at the same input. This complementary structure reduces gate voltage variations, achieving common-mode voltage stability and enhanced linearity. The size ratio of the PMOS and NMOS transistors can be adjusted to regulate the output common-mode voltage, facilitating multi-stage cascading without requiring additional common-mode feedback circuitry. Furthermore, by using the transistor gates as both input and output terminals, any channel current and noise are avoided, achieving purely passive amplification. The second-stage amplifier can use a transconductance-resistance amplifier and a floating inverting amplifier to drive the load capacitor.

[0006] The technical solution of the present invention is as follows:

[0007] A cascaded amplifier circuit module based on a complementary parameter amplifier is characterized in that it includes: a first-stage amplifier and a second-stage amplifier, wherein the first-stage amplifier is a complementary parameter amplifier (CPA) and the second-stage amplifier is a transconductance resistance amplifier (GmR) or a floating inverting amplifier.

[0008] The first stage amplifier includes:

[0009] The inverting and non-inverting input terminals are connected to the inverting input terminal (V) of the differential input signal via the first sampling switch (S1) and the second sampling switch (S2), respectively. ip ) and negative input (V in );

[0010] The system comprises a first NMOS transistor (M1) and a second NMOS transistor (M2), a first PMOS transistor (M3) and a second PMOS transistor (M4), wherein: the gates of the first NMOS transistor (M1) and the first PMOS transistor (M3) are connected to the inverting input terminal and serve as the inverting output terminal of the first stage amplifier; the gates of the second NMOS transistor (M2) and the second PMOS transistor (M4) are connected to the non-inverting input terminal and serve as the non-inverting output terminal of the first stage amplifier; the source and drain of the first NMOS transistor (M1) and the second NMOS transistor (M2) are switched to the power supply voltage (VDD) or ground (GND) via a third switch (S3); the source and drain of the first PMOS transistor (M3) and the second PMOS transistor (M4) are switched to the power supply voltage (VDD) or ground (GND) via a fourth switch (S4).

[0011] The input of the second-stage amplifier is directly connected to the non-inverting and inverting outputs of the first-stage amplifier; the first-stage amplifier passively amplifies the input signal through the gate capacitor during the sampling phase, and achieves gain enhancement through the depletion layer capacitor during the amplification phase, and the cascaded structure does not require a frequency compensation circuit; the first sampling switch (S1), the second sampling switch (S2), the third switch (S3), and the fourth switch (S4) are connected by a non-overlapping clock signal (Φ). SAMP , Φ EN ) control, where Φ SAMP For the sampling clock, Φ EN To amplify the enable clock, both clocks have the same frequency and no phase overlap.

[0012] Furthermore, the second-stage amplifier is a floating inverting amplifier, including a third NMOS transistor (M5), a fourth NMOS transistor (M6), a third PMOS transistor (M7), and a fourth PMOS transistor (M8). The gates of the third NMOS transistor (M5) and the third PMOS transistor (M7) are connected to the inverting output terminal of the first-stage amplifier, and the gates of the fourth NMOS transistor (M6) and the fourth PMOS transistor (M8) are connected to the non-inverting output terminal of the first-stage amplifier. The source of the third NMOS transistor (M5) and the drain of the third PMOS transistor (M7) are connected to the common-mode voltage (VCM) through a seventh switch (S7), and the source of the fourth NMOS transistor (M6) and the drain of the fourth PMOS transistor (M8) are connected to the common-mode voltage (VCM) through an eighth switch (S8).

[0013] The reset capacitor (C) res One end of the circuit is connected to the source of the M7 via the ninth switch (S9), and the other end is connected to the source of the M7 via the tenth switch (S1). 10) is connected to the source of the third NMOS transistor (M5);

[0014] The fifth switch (S5), sixth switch (S6), seventh switch (S7), eighth switch (S8), ninth switch (S9), and tenth switch (S1) 10 ) by clock signal Φ EN and its reverse signal Control is used to dynamically supply power during the amplification phase and reset the output node during the reset phase.

[0015] Furthermore, the second-stage amplifier is a transconductance-resistance amplifier, including: a fifth PMOS transistor (M9) and a sixth PMOS transistor (M... 10 ), the seventh PMOS transistor (M 11 ), first load resistor (R1) and second load resistor (R2);

[0016] The gate of the fifth PMOS transistor (M9) is connected to the non-inverting output terminal of the first stage amplifier, and the gate of the sixth PMOS transistor (M...) is connected to the non-inverting output terminal of the first stage amplifier. 10 The gate of the fifth PMOS transistor (M9) is connected to the inverting output terminal of the first stage amplifier; the drain of the fifth PMOS transistor (M9) is connected to one end of the first load resistor (R1) and serves as the inverting output terminal (Voutn); the gate of the sixth PMOS transistor (M1 .... 10 The drain of the fifth PMOS transistor (M9) is connected to one end of the second load resistor (R2) and serves as the positive output terminal (Voutp); the fifth PMOS transistor (M9) and the sixth PMOS transistor (M1) 10 The source of the transistor is connected to the seventh PMOS transistor (M). 11 The drain of the seventh PMOS transistor (M) 11 The gate of the first load resistor (R1) is connected to the bias voltage (Vb), and its source is grounded; the other ends of the first load resistor (R1) and the second load resistor (R2) are both grounded.

[0017] Furthermore, in the first stage amplifier, the width-to-length ratio (W / L) of the first NMOS transistor (M1) and the second NMOS transistor (M2) is 1:2 to 1:3 with respect to the width-to-length ratio of the first PMOS transistor (M3) and the second PMOS transistor (M4), which is used to regulate the output common-mode voltage through charge conservation and suppress common-mode drift.

[0018] Furthermore, the gain A of the first-stage amplifier v The formula is as follows:

[0019]

[0020] In the formula, This refers to the gate oxide capacitance per unit area of ​​an NMOS transistor. W is the gate oxide capacitance per unit area of ​​a PMOS transistor. p The width L represents the width of the second PMOS transistor (M4) and the width of the first PMOS transistor (M3). p The lengths of the second PMOS transistor (M4) and the first PMOS transistor (M3), W n L represents the width of the first NMOS transistor (M1) and the second NMOS transistor (M2). n The lengths of the first NMOS transistor (M1) and the second NMOS transistor (M2) are given. The depletion layer capacitances of the first NMOS transistor (M1) and the second NMOS transistor (M2) are shown. This refers to the depletion layer capacitance of the second PMOS transistor (M4) and the first PMOS transistor (M3).

[0021] Furthermore, the output common-mode voltage of the first-stage amplifier The formula is as follows:

[0022]

[0023] In the formula, C is the common-mode input voltage of the first-stage amplifier. G1 C is the sum of the gate capacitances of the first NMOS transistor (M1) and the first PMOS transistor (M3) during sampling. G2 This represents the sum of the gate capacitances of the first NMOS transistor (M1) and the first PMOS transistor (M3) during amplification. This refers to the overlapping capacitance of the first NMOS transistor (M1) and the second NMOS transistor (M2). This represents the gate capacitance of the first PMOS transistor (M3) during sampling. This is the gate capacitance of the first PMOS transistor (M3) during amplification.

[0024] Furthermore, the complementary parameter amplifier achieves passive gain during the amplification stage by introducing a depletion layer capacitor, and the noise of the second stage amplifier is suppressed by the first stage gain, so that the noise power of the overall circuit is dominated by the first stage.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0026] 1) Common-mode voltage stability: By integrating NMOS and PMOS at the same input terminal, the complementary structure is used to cancel gate voltage changes and stabilize the common-mode voltage without the need for an additional common-mode feedback circuit.

[0027] 2) Passive gain and dynamic control: The transistor gate is reused as the input / output terminal to achieve pure passive amplification. Combined with clock control, the working mode is dynamically switched, which significantly reduces static power consumption.

[0028] 3) Combination of passive and active amplifiers: The first-stage CPA suppresses noise in the second stage through passive amplification, while the second-stage amplifier (floating inverting or transconductance type) focuses on driving capability, eliminating the need for frequency compensation circuitry. This allows for flexible performance optimization by adjusting the transistor size ratio, overcoming the limitations of traditional parametric amplifiers such as low gain and insufficient driving capability.

[0029] 4) It can be applied in ADCs, filters, switched capacitors, and sensing amplifiers. As a residual amplifier, it can provide high gain, high linearity, low power consumption, and low noise performance. Attached Figure Description

[0030] Figure 1 This is a structural block diagram of the two-stage cascaded amplifier of the present invention.

[0031] Figure 2 This is a schematic diagram of the first-stage complementary parameter amplifier circuit structure of the present invention.

[0032] Figure 3 This is a schematic diagram of the circuit structure of the first complementary parameter amplifier cascaded with a floating inverting amplifier according to the present invention.

[0033] Figure 4 This is a schematic diagram of the circuit structure of the second type of complementary parameter amplifier cascaded transconductance resistance amplifier of the present invention.

[0034] Figure 5 This is a schematic diagram of the clock signal used in the amplifier structure of this invention. Detailed Implementation

[0035] To describe the present invention in more detail, the technical solution of the present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0036] like Figure 1 As shown, the cascaded amplifier circuit based on complementary parameter amplifiers of this invention consists of a first-stage amplifier and a second-stage amplifier cascaded together. The first-stage amplifier uses a passive, low-power, low-noise complementary parameter amplifier as the main source of noise, while simultaneously reducing the noise requirements of the second-stage amplifier. The second stage uses a transconductance resistance (GmR) amplifier or a floating inverting amplifier as the driver stage, while also providing the necessary driving capability. Furthermore, due to the passive amplification characteristics of the complementary parameter amplifier, no phase margin compensation scheme needs to be considered when cascading.

[0037] The complementary parameter amplifier has only four transistors, such as Figure 2As shown, the amplifier includes two PMOS transistors M3 and M4, two NMOS transistors M1 and M2, and four switches S1, S2, S3, and S4. One end of switches S1 and S2 is connected to the input signal, and the other end is connected to the gates of M1 and M3, and M2 and M4, respectively. The gates of M1 and M3 are connected, serving as both the inverting input and output of the amplifier. The gates of M2 and M4 are connected, serving as both the non-inverting input and output of the amplifier. The source and drain of M1 and M2 are connected, and connected to the power supply voltage VDD or the chip's ground GND via switch S3; the source and drain of M3 and M4 are connected, and connected to the power supply voltage VDD or the chip's ground GND via switch S4. The control terminals of switches S1 and S2 are connected to the clock signal Φ. SAMP The control electrodes of switches S3 and S4 are connected to the clock signal Φ. EN .

[0038] In the first cascaded architecture, the first-stage amplifier is a complementary parameter amplifier, and the second stage is a floating inverting amplifier. The floating inverting amplifier circuit includes four transistors, such as... Figure 3 As shown, there are two PMOS transistors M7 and M8, two NMOS transistors M5 and M6, six switches S5, S6, S7, S8, S9, and S10, and one capacitor C. res One end of S5 is connected to the power supply voltage VDD, and the other end of S5 is connected to one end of S9 and C. res One end of S5 is connected to the source of M7, and the other end of S9 is connected to the source of M7. The gate of M7 is connected to the gate of M5 and serves as the inverting voltage input of the second-stage amplifier. The gate of M8 is connected to the gate of M6 and serves as the non-inverting voltage input of the second-stage amplifier. The drain of M7 is connected to the source of M5. One end of S7 is connected to the source of M5, and the drain of M8 is connected to the source of M6. One end of S8 is connected to the other end of S7 and S8, which are connected to VCM to provide bias. The control terminals of switches S5, S6, S7, and S8 are connected to the clock signal Φ. EN The control electrodes of switches S9 and S10 are connected to the clock signal.

[0039] In the second cascaded architecture, the first stage amplifier is a complementary parameter amplifier, and the second stage is a transconductance resistance amplifier, such as... Figure 4 The transconductance amplifier shown includes three PMOS transistors M9, M10, and M11, and two resistors R1 and R2.

[0040] In this stage, the gate of M9 serves as the non-inverting input, and the gate of M10 serves as the inverting input. The drains of M9 and M10 are connected to resistors R1 and R2, respectively, and also serve as the inverting and non-inverting outputs. The other ends of the resistors are connected to GND. The sources of M9 and M10 are connected to the drain of M11. The gate of M11 is connected to the bias potential Vb.

[0041] The clock signal Φ SAMP For sampling clock, clock signal Φ EN Clock signal used to close the switch during the system amplification phase. For Φ EN The inverse signal. Φ SAMP and Φ EN Intervals with the same frequency and no overlap Figure 5 .

[0042] The first two-stage cascaded amplifier architecture in this embodiment operates as follows:

[0043] During the sampling phase, the corresponding clock control signal Φ SAMP In the first-stage complementary parametric amplifier, the input signal has a common-mode voltage (VCM). Vin is sampled on the gates of transistors M1 and M3 through switch S1, and Vip is sampled on the gates of transistors M2 and M4 through switch S2. At this time, the source and drain of NMOS transistors M1 and M2 are grounded, and the source and drain of PMOS transistors M3 and M4 are connected to the power supply voltage VDD. Under this voltage bias, all MOS transistors are in the strong inversion region. Due to the presence of the inversion layer, the depletion layer capacitance is shielded. At this time, the capacitance from the gate to ground at the non-inverting and inverting input terminals is only the gate oxide capacitance WLC of the PMOS and NMOS transistors. ox The sum of C G1 Where W is the width of the transistor, L is the length of the transistor, and C ox The capacitance of the gate oxide layer per unit area.

[0044] During the amplification stage, the corresponding clock control signal Φ EN With switches S1 and S2 open, the sources and drains of NMOS transistors M1 and M2 are connected to the power supply voltage VDD, while the sources and drains of PMOS transistors M3 and M4 are grounded. Under this voltage bias, both PMOS transistors M3 and M4, and both NMOS transistors M1 and M2, are in the depletion region. The inversion layer disappears, and the depletion layer capacitance re-emerges. At this point, the capacitance from the gate to ground at the non-inverting and inverting input terminals is the gate oxide capacitance WLC of the PMOS and NMOS transistors, respectively. ox With depletion layer capacitance C dep The sum of series C G2 During the two region transitions, the total gate charge of transistors M1 and M3 remains conserved, and the total gate charge of transistors M2 and M4 remains conserved; therefore, the gain can be expressed as...

[0045]

[0046] The gain is related to process parameters and can typically be 5-8 times. Furthermore, compared to traditional parametric amplifiers, the complementary structure proposed in this invention avoids significant common-mode voltage drift caused by capacitance reduction due to charge conservation. By combining PMOS M3 and NMOS M1 at the same input, common-mode voltage neutralization is achieved, thus realizing a wider input range and more stable output common-mode voltage. Simultaneously, the output common-mode voltage can be calculated based on charge conservation.

[0047]

[0048] The formula shows that any stable output common-mode voltage can be obtained by changing the dimensions of transistors M1 / M3 and M2 / M4. This characteristic gives CPA a significant advantage in cascaded amplifier structures, eliminating the need for additional common-mode feedback circuitry. Simultaneously, the passive amplification characteristic allows the output voltage to rise rapidly to the expected value, with speed and clock signal Φ... EN The rise rate is basically the same, saving the settling time when using active amplifier cascade.

[0049] Similarly, during the amplification stage, when Φ EN When the voltage is high, the gate input voltages of M5 and M7 are negative input signals amplified by CPA, and the gate input voltages of M6 and M8 are positive input signals amplified by CPA. These generate a small-signal output current gm*vin through their transconductance gm. This current flows through the loads M5, M7, M6, and M8. Simultaneously, switches S5 and S6 are open, and S9 and S10 are closed. res The upper and lower plates are connected to the sources of M7 and M8, and the sources of M5 and M6, respectively, providing power supply current for the second-stage amplifier. With C... res As the charge on the transistors decreases, the source voltages of M7 and M8 decrease, while the source voltages of M5 and M6 gradually increase, causing the four transistors to gradually enter the cutoff region. The time-varying gm current is converted into an output voltage at the output terminal through the output impedance.

[0050] The third stage is the reset stage. Switches S7 and S8 are closed, and the drains of M5 and M7, and the drains of M6 and M8 are connected to the bias voltage VCM, resetting the output and providing a bias point for the next stable common-mode output. Simultaneously, switches S5 and S6 are closed, and S9 and S10 are open, C... res The upper and lower plates are connected to the power supply VDD and ground GND respectively, and are charged to meet the needs of the next cycle.

[0051] In the total noise of the cascaded system, the complementary parameter amplifier dominates, and the pre-amplifier passive gain suppresses the noise of the second stage, allowing the capacitance of the floating inverting amplifier in the second stage to be significantly reduced. The complementary parameter amplifier itself only consumes energy to charge its own parasitic capacitance, and the cascaded structure achieves improved energy efficiency.

[0052] The second two-stage cascaded amplifier architecture in this embodiment operates as follows: During the sampling and amplification stages, the workflow of the first-stage amplifier's complementary parameter amplifier is exactly the same as the first architecture. The difference lies in the amplification stage, when Φ... EN When the voltage is high, the gate input voltage of M10 is already a negative input signal amplified by CPA, and the gate input voltage of M9 is a positive input signal amplified by CPA. M11 applies a bias voltage through its gate to provide the current required by the second-stage amplifier. M9 and M10 generate a small-signal output current gm*vin through their transconductance gm. At this time, the load is resistors R1 and R2. The time-constant gm current is converted into an output voltage at the output terminal through the output impedance.

[0053] Taking this structure as an example, to calculate the amplifier's quality factor (FoM), for a typical transconductance-resistance amplifier, the transistor operates in a static state. However, in a cascaded structure, since the first-stage complementary parameter amplifier is a dynamic amplifier with no quiescent current, the quality factor of the cascaded structure is approximately greater than that of a single transconductance-resistance amplifier.

[0054]

[0055] By using a complementary parametric amplifier as a preamplifier, the current requirement of the second stage is reduced. The passive gain, low noise, and dynamic power consumption of the complementary parametric amplifier itself allow the cascaded structure to improve the gain of the complementary parametric amplifier by approximately 10 times in terms of quality factor.

[0056] The above description of the embodiments is provided to enable those skilled in the art to understand and apply the present invention. Those skilled in the art can readily make various modifications to the above embodiments, such as other cascaded configurations based on complementary parametric amplifiers, three-stage or four-stage structures, and apply the general principles described herein to other embodiments without inventive effort. Therefore, the present invention is not limited to the above embodiments, and any improvements and modifications made to the present invention by those skilled in the art based on the disclosure thereof should be within the scope of protection of the present invention.

Claims

1. A cascaded amplifier circuit module based on a complementary parameter amplifier, characterized in that, include: The first stage amplifier is a complementary parameter amplifier (CPA), and the second stage amplifier is a transconductance resistance amplifier (GmR) or a floating inverting amplifier. The first stage amplifier includes: The inverting and non-inverting input terminals are connected to the inverting input terminal (V) of the differential input signal via the first sampling switch (S1) and the second sampling switch (S2), respectively. ip ) and negative input (V in ); The system comprises a first NMOS transistor (M1) and a second NMOS transistor (M2), a first PMOS transistor (M3) and a second PMOS transistor (M4), wherein: the gates of the first NMOS transistor (M1) and the first PMOS transistor (M3) are connected to the inverting input terminal and serve as the inverting output terminal of the first stage amplifier; the gates of the second NMOS transistor (M2) and the second PMOS transistor (M4) are connected to the non-inverting input terminal and serve as the non-inverting output terminal of the first stage amplifier; the source and drain of the first NMOS transistor (M1) and the second NMOS transistor (M2) are switched to the power supply voltage (VDD) or ground (GND) via a third switch (S3); the source and drain of the first PMOS transistor (M3) and the second PMOS transistor (M4) are switched to the power supply voltage (VDD) or ground (GND) via a fourth switch (S4). The input of the second-stage amplifier is directly connected to the non-inverting and inverting outputs of the first-stage amplifier; the first-stage amplifier passively amplifies the input signal through the gate capacitor during the sampling phase, and achieves gain enhancement through the depletion layer capacitor during the amplification phase, and the cascaded structure does not require a frequency compensation circuit; the first sampling switch (S1), the second sampling switch (S2), the third switch (S3), and the fourth switch (S4) are connected by a non-overlapping clock signal (Φ). SAMP , Φ EN ) control, where Φ SAMP For the sampling clock, Φ EN To amplify the enable clock, both clocks have the same frequency and no phase overlap.

2. The cascaded amplifier circuit module based on complementary parameter amplifiers according to claim 1, characterized in that, The second-stage amplifier is a floating inverting amplifier, including a third NMOS transistor (M5), a fourth NMOS transistor (M6), a third PMOS transistor (M7), and a fourth PMOS transistor (M8). The gates of the third NMOS transistor (M5) and the third PMOS transistor (M7) are connected to the inverting output terminal of the first-stage amplifier, and the gates of the fourth NMOS transistor (M6) and the fourth PMOS transistor (M8) are connected to the non-inverting output terminal of the first-stage amplifier. The source of the third NMOS transistor (M5) and the drain of the third PMOS transistor (M7) are connected to the common-mode voltage (VCM) through a seventh switch (S7), and the source of the fourth NMOS transistor (M6) and the drain of the fourth PMOS transistor (M8) are connected to the common-mode voltage (VCM) through an eighth switch (S8). The reset capacitor (C) res One end of the circuit is connected to the source of the M7 via the ninth switch (S9), and the other end is connected to the source of the M7 via the tenth switch (S1). 10 ) is connected to the source of the third NMOS transistor (M5); The fifth switch (S5), sixth switch (S6), seventh switch (S7), eighth switch (S8), ninth switch (S9), and tenth switch (S1) 10 ) by clock signal Φ EN and its reverse signal Control is used to dynamically supply power during the amplification phase and reset the output node during the reset phase.

3. The cascaded amplifier circuit module according to claim 1, characterized in that, The second-stage amplifier is a transconductance-resistance amplifier, including: a fifth PMOS transistor (M9) and a sixth PMOS transistor (M... 10 ), the seventh PMOS transistor (M) 11 ), first load resistor (R1) and second load resistor (R2); The gate of the fifth PMOS transistor (M9) is connected to the non-inverting output terminal of the first stage amplifier, and the gate of the sixth PMOS transistor (M...) is connected to the non-inverting output terminal of the first stage amplifier. 10 The gate of the fifth PMOS transistor (M9) is connected to the inverting output terminal of the first stage amplifier; the drain of the fifth PMOS transistor (M9) is connected to one end of the first load resistor (R1) and serves as the inverting output terminal (Voutn); the gate of the sixth PMOS transistor (M1 .... 10 The drain of the fifth PMOS transistor (M9) is connected to one end of the second load resistor (R2) and serves as the positive output terminal (Voutp); the fifth PMOS transistor (M9) and the sixth PMOS transistor (M1) 10 The source of the transistor is connected to the seventh PMOS transistor (M). 11 The drain of the seventh PMOS transistor (M) 11 The gate of the first load resistor (R1) is connected to the bias voltage (Vb), and its source is grounded; the other ends of the first load resistor (R1) and the second load resistor (R2) are both grounded.

4. The cascaded amplifier circuit module according to claim 1, characterized in that, In the first stage amplifier: the width-to-length ratio (W / L) of the first NMOS transistor (M1) and the second NMOS transistor (M2) is 1:2 to 1:3 with the width-to-length ratio of the first PMOS transistor (M3) and the second PMOS transistor (M4), which is used to regulate the output common-mode voltage through charge conservation and suppress common-mode drift.

5. The cascaded amplifier circuit module according to claim 1, characterized in that, The gain A of the first stage amplifier v The formula is as follows: In the formula, This refers to the gate oxide capacitance per unit area of ​​an NMOS transistor. W is the gate oxide capacitance per unit area of ​​a PMOS transistor. p The width L represents the width of the second PMOS transistor (M4) and the width of the first PMOS transistor (M3). p The lengths of the second PMOS transistor (M4) and the first PMOS transistor (M3), W n L represents the width of the first NMOS transistor (M1) and the second NMOS transistor (M2). n The lengths of the first NMOS transistor (M1) and the second NMOS transistor (M2) are given. The depletion layer capacitances of the first NMOS transistor (M1) and the second NMOS transistor (M2) are shown. This refers to the depletion layer capacitance of the second PMOS transistor (M4) and the first PMOS transistor (M3).

6. The cascaded amplifier circuit module according to claim 1, characterized in that, The common-mode voltage of the first stage amplifier The formula is as follows: In the formula, C is the common-mode input voltage of the first-stage amplifier. G1 C is the sum of the gate capacitances of the first NMOS transistor (M1) and the first PMOS transistor (M3) during sampling. G2 This represents the sum of the gate capacitances of the first NMOS transistor (M1) and the first PMOS transistor (M3) during amplification. This refers to the overlapping capacitance of the first NMOS transistor (M1) and the second NMOS transistor (M2). This represents the gate capacitance of the first PMOS transistor (M3) during sampling. This is the gate capacitance of the first PMOS transistor (M3) during amplification.

7. The cascaded amplifier circuit module according to claim 1, characterized in that, The complementary parameter amplifier achieves passive gain during the amplification stage by introducing a depletion layer capacitor, and the noise of the second stage amplifier is suppressed by the first stage gain, so that the noise power of the overall circuit is dominated by the first stage.

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