Data processing method, device and system

Abstract

The embodiment of the invention discloses a data processing method, which can be applied to a cascade FEC (Forward Error Correction) scheme in a 1.6 T high-speed transmission scene, and the scheme comprises the following steps: p: q symbol demultiplexing, alignment identifier locking and de-skewing are carried out on p first data streams subjected to Reed-Solomon RS (Reed-Solomon Reed-Solomon) coding to obtain q second data streams, p is an integer greater than or equal to 1, q is an integer greater than or equal to 1, and q is an integer greater than or equal to 1; q is equal to 2 * p; and performing data processing including inner code coding and dual-polarization symbol mapping on the q second data streams to obtain one dual-polarization data stream. According to the scheme, a four-symbol boundary is provided before the inner code is coded, so that the error correction performance of a cascade FEC scheme can be improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a data processing method, apparatus and system. Background Technology

[0002] Driven by technologies such as 5G, cloud computing, big data, and artificial intelligence, high-speed optical transmission networks are developing towards high capacity, packetization, and intelligence. Optical communication systems utilize the amplitude, phase, polarization, or frequency of light waves to carry information. Forward error correction (FEC) coding is used to correct transmission errors, allowing the receiver to recover the original data sent by the transmitter from the received data. A cascaded FEC transmission scheme is proposed, where the transmitting device and the transmitting processing module are connected via a connection unit interface. The transmitting device performs a first FEC encoding on the data to be transmitted and sends the first FEC-encoded data to the transmitting processing module. The transmitting processing module then performs a second FEC encoding on the first FEC-encoded data, modulates the bit sequence resulting from the second FEC encoding to generate a corresponding modulation symbol sequence, and finally generates an optical signal based on the modulation symbol sequence, which is transmitted to the receiver via optical fiber. The first FEC encoding is also called external code encoding, and the second FEC encoding is also called internal code encoding. The modulation mapping is also called symbol mapping.

[0003] Typically, the transmitting processing module performs interleaving before the second FEC encoding to shuffle the data order, thereby enhancing the error correction performance of the cascaded FEC scheme. For the data received by the transmitting processing module after the first FEC encoding, it needs to obtain the symbol boundaries of the first FEC encoding in the received data. Using the obtained symbol boundaries, the interleaving can be processed at the granularity of multiple first FEC encoded symbols, thus enabling the cascaded FEC scheme to have better error correction performance.

[0004] For coherent transmission scenarios, existing technical solutions provide cascaded FEC schemes for 800G transmission scenarios, but not for 1.6T transmission scenarios. Existing cascaded FEC schemes for 800G transmission scenarios cannot be directly applied to 1.6T transmission scenarios. More specifically, the client sublayer is a 1.6TBASE-R 8:8 Physical Media Attachment (PMA) layer based on symbol-multiplexing (SM), also known as 1.6TBASE-R 8:8SM-PMA. This lack of symbol boundaries affects the error correction performance of the overall cascaded FEC scheme. Furthermore, the skew of the eight data streams output by 1.6TBASE-R 8:8SM-PMA also impacts the error correction performance of the overall cascaded FEC scheme. For a solution with a customer sublayer of 1.6TBASE-R 8:16SM-PMA, the 16 data streams output by 1.6TBASE-R 8:16SM-PMA exhibit skewness, which also affects the error correction performance of the overall cascaded FEC solution. How to obtain symbol boundaries and remove skewness is a pressing issue that needs to be addressed in the next-generation 1.6T coherent transmission solution using internal code encoding. Summary of the Invention

[0005] This application provides a data processing method, apparatus, and system that enables the outer code symbol boundary to be obtained before the inner code is encoded, thereby achieving better cascaded FEC error correction performance and being applicable to a wide range of transmission scenarios.

[0006] In a first aspect, embodiments of this application provide a data processing method, comprising: performing p:q symbol demultiplexing, alignment identifier locking, and deskewing on p first data streams encoded by Reed-Solomon RS to obtain q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 × p; performing data processing on the q second data streams including internal code encoding and dual polarization symbol mapping to obtain 1 dual polarization data stream.

[0007] In the above embodiments of this application, before performing internal code encoding, a four-symbol boundary is obtained, and the four-symbol boundary is used to ensure that the information bits in the internal code encoding contain an integer number of RS symbols. Moreover, after deskewing, the cascaded FEC scheme has good error correction performance and can be applied to a wide range of transmission scenarios.

[0008] In conjunction with the first aspect, in a first possible implementation of the first aspect, the step of performing p:q symbol demultiplexing, alignment identifier locking, and deskewing on p first data streams encoded by Reed-Solomon RS to obtain q second data streams specifically includes: performing p:q symbol demultiplexing on the p first data streams encoded by Reed-Solomon RS to obtain q fourth data streams; and performing alignment identifier locking and deskewing on each of the q fourth data streams to obtain the q second data streams. The fourth data streams can also be referred to as demultiplexed data streams.

[0009] In conjunction with the first possible implementation of the first aspect, in the second possible implementation of the first aspect, by performing alignment identifier locking on the q fourth data streams respectively, four symbol boundaries will also be obtained, wherein there are p four symbol boundaries, each corresponding to one of the p first data streams.

[0010] In conjunction with the first aspect and the above possible implementations, in the third possible implementation of the first aspect, the p:q symbol demultiplexing includes p 1:2 symbol demultiplexings, wherein each of the p 1:2 symbol demultiplexings corresponds one-to-one with a p first data stream. This embodiment provides a specific implementation method for demultiplexing, which is simple to implement.

[0011] In conjunction with the third possible implementation of the first aspect, in the fourth possible implementation of the first aspect, the 1:2 symbol demultiplexing employs a round-robin method of distributing 40 bits at a time to demultiplex the corresponding first data stream to obtain two fourth data streams. It should be understood that using a 40-bit round-robin method can match the four-symbol boundaries, which is used to lock the alignment identifier for each fourth data stream, thereby obtaining the four-symbol boundaries of the corresponding first data stream.

[0012] In conjunction with the fourth possible implementation of the first aspect, in the fifth possible implementation of the first aspect, both of the second fourth data streams implement alignment identifier locking, and the boundary of the distributed 40 bits is a four-symbol boundary.

[0013] In conjunction with the fourth possible implementation of the first aspect, in the sixth possible implementation of the first aspect, if at least one of the two fourth data streams fails to achieve alignment identifier locking within a threshold time interval, the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is shifted, and 1:2 symbol demultiplexing is performed again to obtain two new fourth data streams; alignment identifier locking is then applied to each of the two newly obtained fourth data streams. This embodiment provides a complete process for obtaining four-symbol boundaries; only when all fourth data streams achieve alignment identifier locking can the correct four-symbol boundaries be obtained.

[0014] In conjunction with the sixth possible implementation of the first aspect, in the seventh possible implementation of the first aspect, the granularity of shifting the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is 1 bit; or, the granularity of shifting the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is 40×m+1 bits, where m is an integer greater than 0. This application provides various shift granularities, which can be matched to the specific hardware implementation processing bit width, making implementation relatively simple and with low complexity.

[0015] In conjunction with the first aspect and the above possible implementations, in the eighth possible implementation of the first aspect, data processing including internal code encoding and dual polarization symbol mapping is performed on the q second data streams to obtain 1 dual polarization data stream, specifically including: performing q:p symbol multiplexing on the q second data streams to obtain p third data streams; and performing data processing including internal code encoding and dual polarization symbol mapping on the p third data streams to obtain the 1 dual polarization data stream.

[0016] In conjunction with the first aspect and the above possible implementations, in the ninth possible implementation of the first aspect, p = 8 and q = 16.

[0017] In conjunction with the first aspect and the above possible implementations, in the tenth possible implementation of the first aspect, the codeword length of the internal code is 126 bits, wherein the information bits are 110 bits and the parity bits are 16 bits; or, the codeword length of the internal code is 128 bits, wherein the information bits are 120 bits and the parity bits are 8 bits.

[0018] In conjunction with the first aspect and the above possible implementations, in the eleventh possible implementation of the first aspect, the codeword length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits. The four symbols include 40 bits.

[0019] In conjunction with the eleventh possible implementation of the first aspect, in the twelfth possible implementation of the first aspect, each of the first data streams is further subjected to convolutional interleaving before being encoded by the internal code. The convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, and the delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, and each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

[0020] In conjunction with the twelfth possible implementation of the first aspect, in the thirteenth possible implementation of the first aspect, each delay line receives 40 bits as input and outputs 40 bits as output, and the continuous r×40 bits in the output data stream after convolutional interleaving include the 40 bits output by each delay line.

[0021] In conjunction with the eleventh possible implementation of the above aspects, in the fourteenth possible implementation of the above aspects, the 40 bits stored in each storage unit in the convolutional interleaving are 4 RS symbols. In this case, it can be guaranteed that the 12 consecutive RS symbols output by the convolutional interleaving unit come from 12 different RS codewords, thus enabling the cascaded FEC to have better decoding performance.

[0022] In conjunction with the first aspect and the aforementioned possible implementations, in the fourteenth possible implementation of the first aspect, the q fourth data streams locked by the alignment identifier are de-skewed, so that there is no skew between the q second data streams after de-skewing. This de-skewing method can be used to support accurate calculation of possible path data delay. This de-skewing is called full deskew.

[0023] In conjunction with the first aspect and the above possible implementations, in the fifteenth possible implementation of the first aspect, the q fourth data streams locked by the alignment identifier are de-skewed, such that there is a d-value between the de-skewed q second data streams. skew The skewness of bits, where d skew It must be an integer multiple of 40. In this case, the deskewing is called 40-bit deskewing.

[0024] In conjunction with the first aspect and the above possible implementations, in the sixteenth possible implementation of the first aspect, the dual polarization symbol mapping is any one of DP-16QAM symbol mapping, DP-8QAM symbol mapping, or DP-QPSK symbol mapping.

[0025] Secondly, embodiments of this application provide a data processing method, including: performing p:q symbol demultiplexing, alignment identifier locking, and deskewing on p first data streams encoded by Reed-Solomon RS to obtain q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 4 × p; performing data processing on the q second data streams including internal code encoding and dual polarization symbol mapping to obtain 1 dual polarization data stream.

[0026] In the above embodiments of this application, before performing internal code encoding, a four-symbol boundary is obtained, and the four-symbol boundary is used to ensure that the information bits in the internal code encoding contain an integer number of RS symbols. Moreover, after deskewing, the cascaded FEC scheme has good error correction performance and can be applied to a wide range of transmission scenarios.

[0027] In conjunction with the second aspect, in a first possible implementation of the second aspect, the step of performing p:q symbol demultiplexing, alignment identifier locking, and deskewing on p first data streams encoded by Reed-Solomon RS to obtain q second data streams specifically includes: performing p:q symbol demultiplexing on p first data streams encoded by Reed-Solomon RS to obtain q fourth data streams; and performing alignment identifier locking and deskewing on each of the q fourth data streams to obtain the q second data streams.

[0028] In conjunction with the first possible implementation of the second aspect, in the second possible implementation of the second aspect, alignment identifier locking is performed on the q fourth data streams respectively, and four symbol boundaries will also be obtained, wherein there are p four symbol boundaries, which correspond one-to-one with the p first data streams.

[0029] In conjunction with the second aspect and the above possible implementations, in a third possible implementation of the second aspect, the p:q symbol demultiplexing includes p 1:4 symbol demultiplexings, wherein each of the p 1:4 symbol demultiplexings corresponds one-to-one with a p first data stream. This embodiment provides a specific implementation method for demultiplexing, which is simple to implement.

[0030] In conjunction with the third possible implementation of the second aspect, in the fourth possible implementation of the second aspect, the 1:4 symbol demultiplexing employs a round-robin method distributing 40 bits at a time to demultiplex the corresponding first data stream to obtain four fourth data streams. It should be understood that using a 40-bit round-robin method can match the four-symbol boundaries, which is used to lock the alignment identifier for each fourth data stream, thereby obtaining the four-symbol boundaries of the corresponding first data stream.

[0031] In conjunction with the fourth possible implementation of the second aspect, in the fifth possible implementation of the second aspect, all four fourth data streams implement alignment identifier locking, and the boundary of the distributed 40 bits is a four-symbol boundary.

[0032] In conjunction with the fourth possible implementation of the second aspect, in the sixth possible implementation of the second aspect, if at least one of the four fourth data streams fails to achieve alignment identifier locking within a threshold time interval, the boundary of the 40 bits distributed in the 1:4 symbol demultiplexing is shifted, and 1:4 symbol demultiplexing is performed again to re-obtain the four fourth data streams; alignment identifier locking is then performed on each of the four re-obtained fourth data streams. This embodiment provides a complete process for obtaining the four-symbol boundaries; only when all fourth data streams achieve alignment identifier locking can the correct four-symbol boundaries be obtained.

[0033] In conjunction with the sixth possible implementation of the second aspect, in the seventh possible implementation of the second aspect, the granularity of shifting the boundary of the 40 bits distributed in the 1:4 symbol demultiplexing is 1 bit; or, the granularity of shifting the boundary of the 40 bits distributed in the 1:4 symbol demultiplexing is 40×m+1 bits, where m is an integer greater than 0. This application provides various shift granularities, which can be matched to the specific hardware implementation processing bit width, making implementation relatively simple and with low complexity.

[0034] In conjunction with the second aspect and the above possible implementations, in the eighth possible implementation of the second aspect, data processing including internal code encoding and dual polarization symbol mapping is performed on the q second data streams to obtain one dual polarization data stream. Specifically, this includes: performing q:p symbol multiplexing on the q second data streams to obtain p third data streams; and performing data processing including internal code encoding and dual polarization symbol mapping on the p third data streams to obtain the one dual polarization data stream.

[0035] In conjunction with the second aspect and the above possible implementations, in the ninth possible implementation of the second aspect, p = 4 and q = 16.

[0036] In conjunction with the second aspect and the above possible implementations, in the tenth possible implementation of the second aspect, the codeword length of the internal code is 126 bits, of which 110 bits are information bits and 16 bits are parity bits; or, the codeword length of the internal code is 128 bits, of which 120 bits are information bits and 8 bits are parity bits.

[0037] In conjunction with the second aspect and the above possible implementations, in the eleventh possible implementation of the second aspect, the codeword length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits. The four symbols include 40 bits.

[0038] In conjunction with the eleventh possible implementation of the second aspect, in the twelfth possible implementation of the second aspect, each of the first data streams is further subjected to convolutional interleaving before being encoded by the internal code. The convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, with the delay line having the fewest storage units including 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, and each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

[0039] In conjunction with the twelfth possible implementation of the second aspect, in the thirteenth possible implementation of the second aspect, each delay line inputs 40 bits at a time and outputs 40 bits at a time, and the continuous r×40 bits in the output data stream after convolutional interleaving include the 40 bits output by each delay line.

[0040] In conjunction with the eleventh possible implementation of the above aspects, in the fourteenth possible implementation of the above aspects, the 40 bits stored in each storage unit in the convolutional interleaving are 4 RS symbols. In this case, it can be guaranteed that the 12 consecutive RS symbols output by the convolutional interleaving unit come from 12 different RS codewords, thus enabling the cascaded FEC to have better decoding performance.

[0041] In conjunction with the second aspect and the above possible implementations, in the fourteenth possible implementation of the second aspect, the q fourth data streams locked by the alignment identifier are de-skewed, so that there is no skew between the q second data streams after de-skewing. This de-skewing method can be used to support accurate calculation of possible path data delay. This de-skewing is called full de-skew.

[0042] In conjunction with the first aspect and the above possible implementations, in the fifteenth possible implementation of the first aspect, the q fourth data streams locked by the alignment identifier are de-skewed, such that there is a d-value between the de-skewed q second data streams. skew The skewness of bits, where d skew It must be an integer multiple of 40. In this case, the deskewing is called 40-bit deskewing.

[0043] In conjunction with the second aspect and the above possible implementations, in the sixteenth possible implementation of the second aspect, the dual polarization symbol mapping is any one of DP-16QAM symbol mapping, DP-8QAM symbol mapping, or DP-QPSK symbol mapping.

[0044] Thirdly, embodiments of this application provide a data processing apparatus, including: a first processing unit and a second processing unit; the first processing unit is configured to perform p:q symbol demultiplexing, alignment identifier locking, and deskewing on p first data streams encoded by Reed-Solomon RS to obtain q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 2 × p; the second processing unit is configured to perform data processing including internal code encoding and dual polarization symbol mapping on the q second data streams to obtain 1 dual polarization data stream.

[0045] In the above embodiments of this application, before performing internal code encoding, a four-symbol boundary is obtained, and the four-symbol boundary is used to ensure that the information bits in the internal code encoding contain an integer number of RS symbols. Moreover, after deskewing, the cascaded FEC scheme has good error correction performance and can be applied to a wide range of transmission scenarios.

[0046] In conjunction with the third aspect, in a first possible implementation of the third aspect, the first processing unit is specifically used to: perform p:q symbol demultiplexing on p first data streams encoded by Reed-Solomon RS to obtain q fourth data streams; and perform alignment identifier locking and deskewing on the q fourth data streams respectively to obtain the q second data streams.

[0047] In conjunction with the first possible implementation of the third aspect, in the second possible implementation of the third aspect, the first processing unit performs alignment identifier locking on the q fourth data streams respectively, and also obtains four symbol boundaries, wherein there are p four symbol boundaries, which correspond one-to-one with the p first data streams.

[0048] In conjunction with the first possible implementation of the third aspect, in the third possible implementation of the third aspect, the p:q symbol demultiplexing includes p 1:2 symbol demultiplexings, wherein each of the p 1:2 symbol demultiplexings corresponds one-to-one with a p first data stream. This embodiment provides a specific implementation method for demultiplexing, which is simple to implement.

[0049] In conjunction with the third aspect and the aforementioned possible implementations, in a fourth possible implementation of the third aspect, the 1:2 symbol demultiplexing employs a polling method that distributes 40 bits at a time to demultiplex the corresponding first data stream to obtain two fourth data streams. It should be understood that using a 40-bit polling method can match the four-symbol boundaries, which is used to lock the alignment identifier for each fourth data stream, thereby obtaining the four-symbol boundaries of the corresponding first data stream.

[0050] In conjunction with the fourth possible implementation of the third aspect, in the fifth possible implementation of the third aspect, both of the second fourth data streams implement alignment identifier locking, and the boundary of the distributed 40 bits is a four-symbol boundary.

[0051] In conjunction with the fourth possible implementation of the third aspect, in the sixth possible implementation of the third aspect, if at least one of the two fourth data streams fails to achieve alignment identifier locking within a threshold time interval, the first processing unit is further configured to shift the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing, and re-perform 1:2 symbol demultiplexing to obtain two fourth data streams again; and perform alignment identifier locking on the two re-obtained fourth data streams respectively. This embodiment provides a complete process for obtaining the four-symbol boundary; only when all fourth data streams achieve alignment identifier locking can the correct four-symbol boundary be obtained.

[0052] In conjunction with the sixth possible implementation of the third aspect, in the seventh possible implementation of the third aspect, the granularity of shifting the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is 1 bit; or, the granularity of shifting the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is 40×m+1 bits, where m is an integer greater than 0. This application provides various shift granularities, which can be matched to the specific hardware implementation processing bit width, making implementation relatively simple and with low complexity.

[0053] In conjunction with the third aspect and the above possible implementations, in the eighth possible implementation of the third aspect, the second processing unit is specifically used to: perform q:p symbol multiplexing on the q second data streams to obtain p third data streams; and perform data processing on the p third data streams including internal code encoding and dual polarization symbol mapping to obtain the 1 dual polarization data stream.

[0054] In conjunction with the third aspect and the above possible implementations, in the ninth possible implementation of the third aspect, p = 8 and q = 16.

[0055] In conjunction with the third aspect and the above possible implementations, in the tenth possible implementation of the third aspect, the codeword length of the internal code is 126 bits, wherein the information bits are 110 bits and the parity bits are 16 bits. Alternatively, the codeword length of the internal code is 128 bits, wherein the information bits are 120 bits and the parity bits are 8 bits.

[0056] In conjunction with the third aspect and the above possible implementations, in the eleventh possible implementation of the third aspect, the codeword length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits. The four symbols include 40 bits.

[0057] In conjunction with the eleventh possible implementation of the third aspect, in the twelfth possible implementation of the third aspect, the second processing unit is further configured to perform convolutional interleaving on the received data stream, the convolutional interleaving including delaying the input data stream according to r delay lines, where r is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

[0058] In conjunction with the twelfth possible implementation of the third aspect, in the thirteenth possible implementation of the third aspect, each delay line receives 40 bits as input and outputs 40 bits as output, and the continuous r×40 bits in the output data stream after convolutional interleaving include the 40 bits output by each delay line.

[0059] In conjunction with the eleventh possible implementation of the above aspects, in the fourteenth possible implementation of the above aspects, the 40 bits stored in each storage unit in the convolutional interleaving are 4 RS symbols. In this case, it can be guaranteed that the 12 consecutive RS symbols output by the convolutional interleaving unit come from 12 different RS codewords, thus enabling the cascaded FEC to have better decoding performance.

[0060] In conjunction with the third aspect and the above possible implementations, in the fourteenth possible implementation of the third aspect, the q fourth data streams locked by the alignment identifier are de-skewed, so that there is no skew between the q second data streams after de-skewing. This de-skewing method can be used to support accurate calculation of possible path data delay. This de-skewing is called full de-skew.

[0061] In conjunction with the first aspect and the above possible implementations, in the fifteenth possible implementation of the first aspect, the q fourth data streams locked by the alignment identifier are de-skewed, such that there is a d-value between the de-skewed q second data streams. skew The skewness of bits, where d skew It must be an integer multiple of 40. In this case, the deskewing is called 40-bit deskewing. s kew).

[0062] In conjunction with the third aspect and the above possible implementations, in the sixteenth possible implementation of the third aspect, the dual polarization symbol mapping is any one of DP-16QAM symbol mapping, DP-8QAM symbol mapping, or DP-QPSK symbol mapping.

[0063] Fourthly, embodiments of this application provide a data processing apparatus, including: a first processing unit and a second processing unit; the first processing unit is configured to perform p:q symbol demultiplexing, alignment identifier locking, and deskewing on p first data streams encoded by Reed-Solomon RS to obtain q second data streams, wherein p is an integer greater than or equal to 1, q is an integer, and q = 4 × p; the second processing unit is configured to perform data processing including internal code encoding and dual polarization symbol mapping on the q second data streams to obtain 1 dual polarization data stream.

[0064] In the above embodiments of this application, before performing internal code encoding, a four-symbol boundary is obtained, and the four-symbol boundary is used to ensure that the information bits in the internal code encoding contain an integer number of RS symbols. Moreover, after deskewing, the cascaded FEC scheme has good error correction performance and can be applied to a wide range of transmission scenarios.

[0065] In conjunction with the fourth aspect, in a first possible implementation of the fourth aspect, the first processing unit is specifically configured to: perform p:q symbol demultiplexing on p first data streams encoded by Reed-Solomon RS to obtain q fourth data streams; and perform alignment identifier locking and deskewing on the q fourth data streams respectively to obtain the q second data streams.

[0066] In conjunction with the first possible implementation of the fourth aspect, in the second possible implementation of the fourth aspect, the first processing unit performs alignment identifier locking on the q fourth data streams respectively, and also obtains four symbol boundaries, wherein there are p four symbol boundaries, which correspond one-to-one with the p first data streams.

[0067] In conjunction with the first possible implementation of the fourth aspect, in the third possible implementation of the fourth aspect, the p:q symbol demultiplexing includes p 1:4 symbol demultiplexings, wherein each of the p 1:4 symbol demultiplexings corresponds one-to-one with a p first data stream. This embodiment provides a specific implementation method for demultiplexing, which is simple to implement.

[0068] In conjunction with the fourth aspect and the above possible implementations, in the fourth possible implementation of the fourth aspect, the 1:4 symbol demultiplexing adopts a polling method that distributes 40 bits at a time to demultiplex the corresponding first data stream to obtain four fourth data streams. It should be understood that using a 40-bit polling method can match the four-symbol boundaries, which is used to lock the alignment identifier for each fourth data stream, thereby obtaining the four-symbol boundaries of the corresponding first data stream.

[0069] In conjunction with the fourth possible implementation of the fourth aspect, in the fifth possible implementation of the fourth aspect, all four fourth data streams implement alignment identifier locking, and the boundary of the distributed 40 bits is a four-symbol boundary.

[0070] In conjunction with the fourth possible implementation of the fourth aspect, in the sixth possible implementation of the fourth aspect, if at least one of the four fourth data streams fails to achieve alignment identifier locking within a threshold time interval, the first processing unit is further configured to shift the boundary of the 40 bits distributed in the 1:4 symbol demultiplexing, and re-perform 1:4 symbol demultiplexing to obtain four fourth data streams again; and perform alignment identifier locking on each of the four re-obtained fourth data streams. This embodiment provides a complete process for obtaining the four symbol boundaries; only when all fourth data streams achieve alignment identifier locking can the correct four symbol boundaries be obtained.

[0071] In conjunction with the sixth possible implementation of the fourth aspect, in the seventh possible implementation of the fourth aspect, the granularity of shifting the boundary of the 40 bits distributed in the 1:4 symbol demultiplexing is 1 bit; or, the granularity of shifting the boundary of the 40 bits distributed in the 1:4 symbol demultiplexing is 40×m+1 bits, where m is an integer greater than 0. This application provides various shift granularities, which can be matched to the specific hardware implementation processing bit width, making implementation relatively simple and with low complexity.

[0072] In conjunction with the fourth aspect and the above possible implementations, in the eighth possible implementation of the fourth aspect, the second processing unit is specifically used to: perform q:p symbol multiplexing on the q second data streams to obtain p third data streams; and perform data processing on the p third data streams including internal code encoding and dual polarization symbol mapping to obtain the 1 dual polarization data stream.

[0073] In conjunction with the fourth aspect and the above possible implementations, in the ninth possible implementation of the fourth aspect, p = 4 and q = 16.

[0074] In conjunction with the fourth aspect and the above possible implementations, in the tenth possible implementation of the fourth aspect, the codeword length of the internal code is 126 bits, of which 110 bits are information bits and 16 bits are parity bits; or, the codeword length of the internal code is 128 bits, of which 120 bits are information bits and 8 bits are parity bits.

[0075] In conjunction with the fourth aspect and the above possible implementations, in the eleventh possible implementation of the fourth aspect, the codeword length of the RS is 544 symbols, wherein the information length is 514 symbols, and each symbol contains 10 bits. The four symbols include 40 bits.

[0076] In conjunction with the eleventh possible implementation of the fourth aspect, in the twelfth possible implementation of the fourth aspect, the second processing unit is further configured to perform convolutional interleaving on the received data stream, the convolutional interleaving including delaying the input data stream according to r delay lines, where r is an integer greater than 1, each delay line includes a different number of storage units, the delay line with the smallest number of storage units includes 0 storage units, the difference in the number of storage units between any two adjacent delay lines is Q, each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

[0077] In conjunction with the twelfth possible implementation of the fourth aspect, in the thirteenth possible implementation of the fourth aspect, each delay line receives 40 bits as input and outputs 40 bits as output, and the continuous r×40 bits in the output data stream after convolutional interleaving include the 40 bits output by each delay line.

[0078] In conjunction with the eleventh possible implementation of the above aspects, in the fourteenth possible implementation of the above aspects, the 40 bits stored in each storage unit in the convolutional interleaving are 4 RS symbols. In this case, it can be guaranteed that the 12 consecutive RS symbols output by the convolutional interleaving unit come from 12 different RS codewords, thus enabling the cascaded FEC to have better decoding performance.

[0079] In conjunction with the fourth aspect and the above-described possible implementations, in the fourteenth possible implementation of the fourth aspect,

[0080] The q fourth data streams, locked by alignment markers, are de-skewed so that there is no skew between the q second data streams after de-skewing. This de-skewing method can be used to support accurate calculation of possible path data delays. This de-skewing is called full deskew.

[0081] In conjunction with the first aspect and the above possible implementations, in the fifteenth possible implementation of the first aspect, the q fourth data streams locked by the alignment identifier are de-skewed, such that there is a d-value between the de-skewed q second data streams. skew The skewness of bits, where d skew It must be an integer multiple of 40. In this case, the deskewing is called 40-bit deskewing.

[0082] In conjunction with the fourth aspect and the above possible implementations, in the sixteenth possible implementation of the fourth aspect, the dual polarization symbol mapping is any one of DP-16QAM symbol mapping, DP-8QAM symbol mapping, or DP-QPSK symbol mapping.

[0083] In some possible implementations, the data processing apparatus provided in this application is used in scenarios including Ethernet, optical transport networks, and space optical communication.

[0084] Fifthly, embodiments of this application provide a chip for performing the methods described in any of the first or second aspects.

[0085] Sixthly, embodiments of this application provide an optical module. The optical module includes a processor and an interface. The processor is used to execute the methods described in any of the first or second aspects and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor.

[0086] In a seventh aspect, embodiments of this application provide a communication device. The communication device includes a host-side device and an optical module as described in any embodiment of the sixth aspect, the optical module being connected to the host-side device.

[0087] Eighthly, embodiments of this application provide another device. This device includes a processor and an interface. The processor is used to perform the methods described in any of the embodiments of the first or second aspect, and to transmit signals through the interface. For example, the interface is used to transmit signals from the processor or to transmit received signals to the processor. The device may be a router, switch, server, or optical transport network equipment, etc.

[0088] Ninthly, embodiments of this application provide a communication system including a first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is a communication device as described in any embodiment of the seventh aspect, and the first communication device and the second communication device are connected.

[0089] In a tenth aspect, this application provides a computer-readable storage medium storing instructions that, when executed by a computer, cause the method described in any of the embodiments of the first or second aspect to be implemented.

[0090] In the eleventh aspect, this application provides a computer program product including program instructions that, when executed, implement the method described in any of the embodiments of the first or second aspect above. Attached Figure Description

[0091] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application;

[0092] Figure 2 for Figure 1 A schematic diagram of a data transmission process in the communication system shown.

[0093] Figure 3 This is a schematic diagram of another communication system used in an embodiment of this application;

[0094] Figure 4 A flowchart of a data processing method provided in an embodiment of this application;

[0095] Figure 5(a) is a flowchart of an embodiment of this application for obtaining multiple de-skewed data streams;

[0096] Figure 5(b) is a flowchart illustrating a specific method for acquiring multiple de-skewed data streams according to an embodiment of this application.

[0097] Figure 5(c) is a flowchart of another specific process for obtaining multiple de-skewed data streams provided in an embodiment of this application;

[0098] Figure 6(a) is a schematic diagram of a convolutional interleaving process provided in an embodiment of this application;

[0099] Figure 6(b) is a schematic diagram of another convolutional interleaving process provided in an embodiment of this application;

[0100] Figure 7 A schematic diagram of a data processing architecture provided in this application;

[0101] Figure 8 A schematic diagram of another data processing architecture provided in this application;

[0102] Figure 9 A schematic diagram of another data processing architecture provided in this application;

[0103] Figure 10 A schematic diagram of another data processing architecture provided in this application;

[0104] Figure 11 A schematic diagram of another data processing architecture provided in this application;

[0105] Figure 12 A schematic diagram of another data processing architecture provided in this application;

[0106] Figure 13 A schematic diagram of another data processing architecture provided in this application;

[0107] Figure 14 A schematic diagram of the structure of a data processing device provided in this application;

[0108] Figure 15 A schematic diagram of the structure of an optical module provided in this application;

[0109] Figure 16 This is a schematic diagram of the structure of a communication device provided in this application. Detailed Implementation

[0110] This application provides a data processing method, apparatus, and system that enables the outer code symbol boundary to be obtained before the inner code is encoded, thereby achieving better cascaded FEC error correction performance and being applicable to a wide range of transmission scenarios.

[0111] It should be noted that the terms "first," "second," etc., in this application specification, claims, and the accompanying drawings are used to distinguish similar objects, not to limit a specific order or sequence. It should be understood that the above terms can be used interchangeably where appropriate so that the embodiments described in this application can be implemented in a sequence other than that described in this application. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or devices.

[0112] Figure 1 This is a schematic diagram of a communication system used in an embodiment of this application. Figure 1As shown, the communication system includes a transmitting device 01, a transmitting processing module 02, a channel transmission medium 03, a receiving processing module 04, and a receiving device 05. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also called a client device at the transmitting end, and the receiving device 05 is also called a client device at the receiving end. The channel transmission medium 03 can be optical fiber. The client device is sometimes also called a host device. The client device includes a client chip and an interface. The client chip is also called a host chip. The connection interface between the transmitting device 01 and the transmitting processing module 02 can be connected through an attachment unit interface (AUI), and the connection interface between the receiving device 05 and the receiving processing module 04 can also be connected through an AUI. The transmitting processing module 02 and the receiving processing module 04 can be optical modules, electrical modules, connectors, or other modules that process data during data transmission. For example, the processing module can be a ZR optical module, FR optical module, or LR optical module, such as a 1.6T FR1 coherent optical module (referred to as a 1.6T FR coherent optical module), a 1.6T TLR1 coherent optical module (referred to as a 1.6T LR coherent optical module), or a 1.6T ZR coherent optical module. Furthermore, the transmitting device 01, transmitting processing module 02, channel transmission medium 03, receiving processing module 04, and receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here.

[0113] Figure 2 for Figure 1 The diagram illustrates a data transmission process in the communication system shown. Figure 2 As shown, during the data transmission process from transmitting device 01 to receiving device 05, transmitting device 01 performs external code encoding on the data and then transmits the externally encoded data to transmitting processing module 02. Transmitting processing module 02 performs internal code encoding on the externally encoded data to obtain data with both external and internal code encoding, and transmits this encoded data to channel transmission medium 03. Channel transmission medium 03 transmits the externally and internally encoded data to receiving processing module 04. Receiving processing module 04 performs internal code decoding on the externally and internally encoded data and transmits the internally decoded data to receiving device 05. Receiving device 05 performs external code decoding on the internally decoded data.

[0114] It should be understood that the distinction between "internal" in "internal code" and "external" in "external code" is based solely on the distance between the entity performing the data operation and the channel transmission medium 03. The entity operating on the internal code is closer to the channel transmission medium, while the entity operating on the external code is farther away. In this embodiment, after data is sent from the transmitting device 01, it is transmitted to the channel transmission medium 03 via the transmitting processing module 02, and then from the channel transmission medium 03 via the receiving processing module 04 to the receiving device 05. The data encoded by the transmitting device 01 is farther from the channel transmission medium 03 than the data encoded by the transmitting processing module 02, and the data decoded by the receiving device 05 is farther from the channel transmission medium 03 than the data decoded by the receiving processing module 04. Therefore, the data encoded by the transmitting device 01 is called data encoded with the external code, the data encoded by the transmitting processing module 02 is called data encoded with the internal code, the data decoded by the receiving device 05 is called data decoded with the external code, and the data decoded by the receiving processing module 04 is called data decoded with the internal code. In one possible implementation, both the internal and external encoding methods described above employ FEC encoding, thus forming a cascaded FEC transmission scheme. For example, the transmitting device 01 can use Reed-Solomon (RS) code for external encoding, and the transmitting processing module 02 can use Hamming code for internal encoding. Alternatively, the transmitting device 01 can use RS code for external encoding, and the transmitting processing module 02 can use Bose-Chaudhuri-Hocquenghem (BCH) code for internal encoding. A BCH code correcting a single error is equivalent to a Hamming code. Another example is that the transmitting device 01 can use RS code for external encoding, and the transmitting processing module 02 can also use Polar code for internal encoding. In some specific application scenarios, the transmitting device 01 can use RS(544,514) code, also known as KP4 code, for external encoding.

[0115] Figure 3 This is a schematic diagram of another communication system used in an embodiment of this application. For example... Figure 3As shown, the communication system includes a transmitting device 01, a channel transmission medium 03, and a receiving device 05. The transmitting device 01 performs external code encoding and internal code encoding on the data. The encoded data is then sent to the transmission medium 03. The receiving device 05 decodes the data received from the transmission medium 03, performing internal code decoding and external code decoding. Taking a data center network as an example, the transmitting device 01 and the receiving device 05 can be devices such as switches, routers, or servers. The transmitting device 01 is also referred to as a client-side device or host-side device located at the transmitting end, and the receiving device 05 is also referred to as a client-side chip located at the receiving end. The channel transmission medium 03 can be optical fiber. The client-side device includes a client-side chip and an interface. The client-side chip is also referred to as a host-side chip. The transmitting device 01, channel transmission medium 03, and receiving device 05 in this communication system can all support bidirectional transmission or unidirectional transmission; specific limitations are not specified here. That is to say, Figure 3 The transmitting device 01 shown also integrates Figure 2 The function of the sending processing module 02 shown is as follows: Figure 3 The receiving device 05 shown also integrates Figure 2 The receiving end processing module 04 is shown to have the following functions. At this time, the transmitting end device 01 may also employ linear pluggable optics (LPO), co-packaged optics (CPO), or near packaged optics (NPO) technology.

[0116] It should also be noted that the above content is an exemplary description of the application scenarios of the data processing method provided in the embodiments of this application, and does not constitute a limitation on the application scenarios of the data processing method. As those skilled in the art will know, as business needs change, the application scenarios can be adjusted according to the application needs, and the embodiments of this application do not list them one by one.

[0117] Figure 4 This is a schematic flowchart illustrating a data processing method provided in an embodiment of this application. It should be understood that this data processing method is applied at the sending end, for example, it can be specifically implemented through the methods described above. Figure 2 The shown origin processing module 02 can be implemented in this way, or for example, it can be implemented through the above-mentioned... Figure 3 The shown transmitting device 01 is implemented.

[0118] 101. Perform p:q symbol demultiplexing, alignment identifier locking, and deskewing on the p first data streams encoded by RS to obtain q second data streams, where p is an integer greater than or equal to 1, q is an integer, and q = 2 × p or q = 4 × p.

[0119] In this embodiment, all p first data streams are data streams encoded with external codes. For ease of explanation, the following description uses RS encoding as an example of external code encoding. In practical applications, other encoding methods can also be used for external code encoding. The data stream after RS ​​encoding can include multiple RS codewords. In this embodiment, the code length of the RS code is counted in units of symbols. The symbols in the RS code can be called RS symbols. For example, the RS code uses RS(544,514) code, also known as KP4 code. The code length of the RS code is 544 RS symbols, that is, the codeword of the RS code includes 544 RS symbols, and one RS symbol contains 10 bits. Each a in each first data stream RS The adjacent RS symbols are respectively from a RS 1 RS codeword, where a RS An integer power greater than or equal to 4 and equal to 2.

[0120] In some specific applications, targeting 1.6T transmission scenarios, such as 1.6TBASE-R transmission, consider p=8. The nominal rate of each of the p=8 first data streams is 212.5 Gbits per second (b / s). In some specific applications, the p=8 first data streams are obtained by demodulating 8 AUI data streams of 1.6TBASE-8 using 4-Level Pulse Amplitude Modulation (PAM4). This PAM4 demodulation is also called PAM4 decoding. The 8 AUI data streams of 1.6TBASE-8 are obtained by processing 16 Physical Coding Sublayer lane (PCSL) data streams using 1.6TBASE-R16:8SM-PMA. In each of the 16 PCSL data streams, every four adjacent RS symbols come from four different RS codewords.

[0121] In other specific applications, targeting 1.6T transmission scenarios, such as 1.6TBASE-R transmission, consider p=4. The nominal rate of each of the p=4 first data streams is 212.5 Gbits per second (b / s). In some specific applications, the p=4 first data streams are obtained by demodulating four AUI data streams of 1.6TBASE-4 using four-level pulse amplitude modulation (PAM4). This PAM4 demodulation is also called PAM4 decoding. The four AUI data streams of 1.6TBASE-4 are obtained by processing 16 PCSL data streams using 1.6TBASE-R16:4SM-PMA. In each of the 16 PCSL data streams, every four adjacent RS symbols come from four different RS codewords.

[0122] As shown in Figure 5(a), p:q symbol demultiplexing is performed on the p first data streams to obtain q demultiplexed data streams. The cases of q = 2 × p and q = 4 × p are described below.

[0123] 1) For the case where q = 2 × p:

[0124] As shown in Figure 5(b), the p:q symbol demultiplexing includes p 1:2 symbol demultiplexings, and each of the p 1:2 symbol demultiplexings corresponds one-to-one with a p first data stream. Each 1:2 symbol demultiplexing uses a round-robin method, distributing 40 bits at a time, to demultiplex its input first data stream to obtain two output demultiplexed data streams.

[0125] The q-strip demultiplexed data streams are each subjected to alignment marker lock processing. Here, alignment marker lock is also simply referred to as alignment lock. The alignment marker lock operation utilizes the known alignment marker (AM) in the PCSL data stream.

[0126] Alignment identifier locking can only be achieved in the two output demultiplexed data streams if and only when 40 bits are distributed in the 1:2 symbol demultiplexing process, corresponding to 4 symbols (i.e., 4 foreign code RS symbols), that is, the 40-bit boundary corresponds to 4 symbol boundaries. Here, achieving alignment identifier locking means that the alignment identifier is correctly locked. In this case, the boundary of the 40 distributed bits is a four-symbol boundary. It should be understood that the number of four-symbol boundaries is equal to the number of first data streams, that is, p four-symbol boundaries correspond to p first data streams.

[0127] Within a certain time interval (also called a threshold time interval) or a certain bit interval (e.g., 222, 822, 400 bits), when the two output demultiplexed data streams do not achieve alignment flag locking, the 40-bit boundary distributed in the above 1:2 symbol demultiplexing is shifted. This shift is also called slipping. In some specific applications, the 40-bit boundary distributed in the above 1:2 symbol demultiplexing is slipped by 1 bit. In other specific applications, the 40-bit boundary distributed in the above 1:2 symbol demultiplexing is slipped by a bit greater than 1. In this case, it is necessary to ensure that all possible boundaries are evaluated. A slip of 40 × m + 1 bits can be made, where m is a positive integer, for example, 41 bits or 81 bits. When the shift interval matches the specific hardware implementation's processing bit width, the implementation is relatively simple and has low complexity. The above shift operation continues until the alignment flag locking is achieved for all two output demultiplexed data streams. When both demultiplexed data streams of the 1:2 symbol demultiplexing output achieve alignment identifier locking, four-symbol locking is achieved, and the four-symbol boundary corresponding to the first data stream is obtained. Then, a deskewing operation is performed on the locked data stream.

[0128] The deskewing process is also called offset removal. In some specific applications, deskewing is performed on the q locked data streams to ensure that there is no skew between the q deskewed data streams, thus supporting accurate calculation of possible path data delay. In this case, the deskewing is also called full deskewing. In other specific applications, the deskewing is based on 40-bit deskewing, which means that there are allowed d-bit differences between the q deskewed data streams. skew The skewness of bits, where d skew When the value is a multiple of 40, the deskewing is also called 40-bit deskewing.

[0129] 2) For the case where q = 4 × p:

[0130] As shown in Figure 5(c), the p:q symbol demultiplexing includes p 1:4 symbol demultiplexings, and each of the p 1:4 symbol demultiplexings corresponds one-to-one with a p first data stream. Each 1:4 symbol demultiplexing uses a round-robin method, distributing 40 bits at a time, to demultiplex the input first data stream into four output demultiplexed data streams.

[0131] The q-strip demultiplexed data streams are each subjected to alignment marker lock processing. Here, alignment marker lock is also simply referred to as alignment lock. The alignment marker lock operation utilizes the known alignment marker (AM) in the PCSL data stream.

[0132] Alignment identifier locking can only be achieved in the four output demultiplexed data streams if and only if, in the aforementioned 1:4 symbol demultiplexing, 40 bits are distributed corresponding to 4 symbols (i.e., 4 foreign code RS symbols), that is, the 40-bit boundary corresponds to 4 symbol boundaries. Here, achieving alignment identifier locking means that the alignment identifier is correctly locked. In this case, the boundary of the 40 distributed bits is a four-symbol boundary. It should be understood that the number of four-symbol boundaries is equal to the number of first data streams, that is, p four-symbol boundaries correspond to p first data streams.

[0133] Within a certain time interval (also called a threshold time interval) or a certain bit interval (e.g., 222, 822, 400 bits), when the alignment flag locking is not achieved in the four output demultiplexed data streams, 40-bit boundaries in the above 1:4 symbol demultiplexing are shifted (also called slips). In some specific applications, the 40-bit boundaries in the above 1:4 symbol demultiplexing are shifted by 1 bit. In other specific applications, the 40-bit boundaries in the above 1:4 symbol demultiplexing are shifted by a bit greater than 1. In this case, it is necessary to ensure that all possible boundaries are evaluated. A slip of 40 × m + 1 bits can be made, where m is a positive integer, for example, 41 bits or 81 bits. When the shift interval matches the specific hardware implementation's bit width, the implementation is relatively simple and has low complexity. The above shift operation continues until the alignment flag locking is achieved in all four output demultiplexed data streams. When the alignment identifier locking is achieved in all four demultiplexed data streams of the 1:4 symbol demultiplexing output, four-symbol locking is achieved, and the four-symbol boundary corresponding to the first data stream is also obtained. Then, a deskewing operation is performed on the locked data stream.

[0134] The deskewing process is also called offset removal. In some specific applications, deskewing is performed on the q locked data streams to ensure that there is no skew between the q deskewed data streams, thus supporting accurate calculation of possible path data delay. In this case, the deskewing is also called full deskewing. In other specific applications, the deskewing is based on 40-bit deskewing, which means that there are allowed d-bit differences between the q deskewed data streams. skew The skewness of bits, where d skew When the value is a multiple of 40, the deskewing is also called 40-bit deskewing.

[0135] For the cases q = 2 × p and q = 4 × p, when all q demultiplexed data streams achieve alignment identifier locking, symbol-quartet locking is also achieved, and the four outer code symbol boundaries corresponding to each first data stream are also obtained. These four outer code symbol boundaries are also called symbol-quartet boundaries, or simply symbol boundaries. In this case, the q demultiplexed data streams are q PCSL data streams. The four adjacent RS symbols in the q demultiplexed data streams come from four different RS codewords. More specifically, for a demultiplexed data stream, starting from the alignment identifier, the symbols in the data stream are represented in the form A, B, C, D, A, B, C, D… etc., where A, B, C, and D represent one RS symbol from the four different codewords.

[0136] It should be noted that for 1.6T transmission scenarios, such as 1.6TBASE-R transmission, q=16.

[0137] It should be noted that in each of the first data streams, every four adjacent RS symbols come from four different RS codewords. By obtaining the four-symbol boundary corresponding to a first data stream, the four adjacent RS symbols in the first data stream can also be obtained.

[0138] 102. Perform data processing on the q second data streams, including internal code encoding and dual-polarization symbol mapping, to obtain one dual-polarization data stream.

[0139] Based on the acquired four symbols, 40 adjacent (also known as consecutive) bits in each first data stream can be obtained, corresponding to 4 RS symbols. More specifically, the 4 RS symbols come from 4 different RS codewords. The 4 RS symbols are also called RSFEC symbol quartets.

[0140] The following uses a first data stream as an example to illustrate the internal code encoding method. Specifically, every K information bits in the first data stream are internally encoded to generate NK check bits, thereby obtaining an internal codeword consisting of N bits, where 1 < K < N. In this application, K is considered to be a multiple of 10. Combining the obtained symbol boundaries, the K information bits in each internal codeword can correspond to K / 10 external code RS symbols.

[0141] In some specific applications, the K information bits in each inner codeword correspond to K / 10 outer code RS symbols, and the corresponding K / 10 outer code RS symbols come from K / 10 different outer code RS codewords. This allows the FEC concatenation scheme, which includes RS encoding and inner code encoding, to achieve optimal performance. For example, the inner code encoding uses BCH(126,110), where K=110 information bits in each inner codeword correspond to K / 10=11 outer code symbols, and the corresponding K / 10=11 outer code symbols come from K / 10=11 different outer code RS codewords. Another example is the inner code encoding using a linear block code of N=128 and K=120, where K=120 information bits in each inner codeword correspond to K / 10=12 outer code symbols, and the corresponding K / 10=12 outer code symbols come from K / 10=12 different outer code RS codewords. To ensure that the K information bits in each internal codeword correspond to K / 10 different external codewords (RS codes), the first data stream undergoes convolutional interleaving before internal code encoding. The convolutional interleaving process is described in detail below.

[0142] Specifically, the convolutional interleaver (CIE) performing the convolutional interleaving process includes r delay lines, each with a different number of storage units. The delay line with the fewest storage units has 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q, where r is an integer greater than 1 and Q is an integer greater than or equal to 1. Each storage unit stores d bits, where d is an integer greater than or equal to 1. The bits in the input data stream of the CIE are sequentially input to the r delay lines according to their numbers, with d bits input and output from each delay line at a time. In some applications, the CIE outputs d bits at a time. In other applications, the CIE outputs r × d bits at a time, where r × d bits come from the r delay lines and include the d bits output from each delay line. The consecutive r × d bits in the output data stream of the CIE include the d bits output from each delay line.

[0143] It should be understood that the r delay lines each comprise 0, Q, 2Q, ..., (r-1)Q storage units, with each unit storing d bits. The r delay lines correspond to r delay values, which include 0 bits, Q×d bits, 2Q×d bits, ..., (r-1)Q×d bits. The more bits a delay line includes in its delay values, the longer the delay (also called latency) of that delay line to the data stream. It should be understood that when a delay line contains no storage units, the delay is 0 bits, which is called zero-latency pass-through. It should be understood that the aforementioned storage units are also called delay elements.

[0144] Figure 6(a) is a schematic diagram of the first structure of convolutional interleaving in an embodiment of this application. As shown in Figure 6(a), the number of storage units in the r delay lines decreases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has (r-1)Q storage units, each delay line decreases by Q storage units sequentially, and delay line r-1 has 0 storage units. Figure 6(b) is a schematic diagram of the second structure of convolutional interleaving in an embodiment of this application. As shown in Figure 6(b), the number of storage units in the r delay lines increases sequentially according to the sequence number of the r delay lines. That is, delay line 0 has 0 storage units, each delay line increases by Q storage units sequentially, and delay line r-1 has (r-1)Q storage units.

[0145] It should be noted that at any given moment, the input and output switches of the convolutional interleaver are located on the same delay line. After the current delay line receives and outputs d bits in a single input, the switch is switched to the next delay line. This ensures that the bits in the input data stream are sequentially input to the r delay lines according to their sequence numbers, and that the consecutive r×d bits in the output data stream include the d bits output from each delay line. The specific data read / write operations are as follows: d bits are read from the memory cell closest to the output port of the current delay line; the d bits stored in each memory cell of the current delay line are transferred to the next memory cell; then, d bits are written to the memory cell closest to the input port of the current delay line. Afterward, the switch is moved to the next delay line, and the above operations are repeated, and so on.

[0146] It should be understood that when the same parameters r, Q, and d are used, the convolutional interleaving processing in Figure 6(a) and the convolutional interleaving processing in Figure 6(b) are the inverse operations of each other. That is, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 6(a), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 6(b). Similarly, when the sending-end processing module uses the convolutional interleaving structure shown in Figure 6(b), the corresponding convolutional deinterleaving in its receiving-end processing module uses the structure shown in Figure 6(a).

[0147] Typically, the number of bits stored in each memory cell is d = a. RS ×10=40. Based on the obtained four-symbol boundaries, the 40 bits stored in each storage unit come from 40 consecutive bits in a first data stream, corresponding to 4 RS symbols. The 4 RS symbols come from 4 different RS codewords.

[0148] After the p first data streams are encoded using internal codes, they undergo dual-polarization symbol mapping to obtain a single dual-polarization data stream. This dual-polarization symbol mapping can be dual-polarization quadrature amplitude modulation (DP-QAM). In some specific applications, the dual-polarization symbol mapping can also be DP-16QAM symbol mapping, DP-8QAM symbol mapping, or DP-QPSK symbol mapping, etc.

[0149] In some specific applications, the data processing method further includes: symbol multiplexing the q second data streams to obtain q / 2 third data streams, followed by convolutional interleaving and internal code encoding. The symbol multiplexing multiplexes two second data streams to obtain one third data stream; this symbol multiplexing is also called 2:1 symbol multiplexing or q:(q / 2) symbol multiplexing. Alternatively, the symbol multiplexing of the q second data streams to obtain q / 4 third data streams, followed by convolutional interleaving and internal code encoding. The symbol multiplexing multiplexes four second data streams to obtain one third data stream; this symbol multiplexing is also called 4:1 symbol multiplexing or q:(q / 4) symbol multiplexing.

[0150] It should be noted that for q = 2 × p, the q:p symbol multiplexing includes p 2:1 symbol multiplexings, and each of the p 2:1 symbol multiplexings corresponds one-to-one with the aforementioned p first data streams. More specifically, each 2:1 symbol multiplexing multiplexes the two second data streams obtained by demultiplexing and deskewing one first data stream into a 2:1 symbol multiplexing. This 2:1 symbol multiplexing, combined with the obtained four-symbol boundary, uses a round-robin method with four symbols (containing a total of 40 bits) to multiplex the two input second data streams into one output third data stream. The p 2:1 symbol multiplexings multiplex the input q = 2 × p second data streams to output p third data streams.

[0151] It should be noted that for q = 4 × p, the q:p symbol multiplexing includes p 4:1 symbol multiplexings, and each of the p 4:1 symbol multiplexings corresponds one-to-one with the aforementioned p first data streams. More specifically, each 4:1 symbol multiplexing multiplexes the four second data streams obtained by demultiplexing the first data stream using 1:4 symbols and then removing skew, then performs 4:1 symbol multiplexing on them. This 4:1 symbol multiplexing, combined with the obtained four-symbol boundary, uses a round-robin method with four symbols (containing a total of 40 bits) to multiplex the four input second data streams to obtain one output third data stream. The p 4:1 symbol multiplexings multiplex the input q = 4 × p second data streams to output p third data streams.

[0152] In this embodiment, the data processing flow can be divided into two parts. The first data processing may include p:q symbol demultiplexing, alignment identifier locking, and deskewing. The second data processing, in addition to internal code encoding and dual polarization symbol mapping, may also include at least one of bit block distribution, circular shift, codeword interleaver, and pilot insertion. The pilot insertion is also called framing processing.

[0153] It should be noted that in some specific applications, the above bit-block distribution is based on K-bit-block distribution, which distributes the bits in each input data stream to obtain multiple output data streams. In other specific applications, K is not an integer multiple of 40, and the above bit-block distribution is based on... Bit block distribution distributes the bits in each input data stream to obtain multiple output data streams. This indicates rounding down. Typically, the bit-grouping method described above distributes the bits in each input data stream into two or four output data streams.

[0154] It should be noted that in some specific applications, the convolutional interleaving operation can be skipped to achieve a lower latency for the overall cascaded FEC scheme, which can be applied in application scenarios requiring low latency.

[0155] The following examples, using a linear block code with internal code N=126 and K=110 as an example, provide several implementations to illustrate the possible values ​​of p and q.

[0156] Example 1: Consider 1.6TBASE-R transmission, p = 8 and q = 2 × p = 16.

[0157] like Figure 7As shown, the 8 AUI data streams of 1.6TAUI-8 are PAM4 decoded to obtain p = 8 first data streams. This PAM4 decoding is also called PAM4 demodulation. By performing 8:16 symbol demultiplexing and alignment identifier locking on the p = 8 first data streams, the four symbol boundaries (also called the 4 symbol boundaries) of the p = 8 first data streams can be obtained, and q = 16 demultiplexed data streams implementing alignment identifier locking can be obtained. The 8:16 symbol demultiplexing includes p = 8 1:2 symbol demultiplexings, as shown in Figure 5(b). Each 1:2 symbol demultiplexing uses a round-robin method, distributing 40 bits at a time, to demultiplex the input 1 first data stream to obtain 2 output demultiplexed data streams. The 16 demultiplexed data streams implementing locking are also called 16 locked data streams.

[0158] The 16 locked data streams are subjected to 40-bit deskew to obtain q = 16 second data streams. Based on the obtained four-symbol boundaries, the q = 16 second data streams undergo a second data processing process including internal code encoding and DP-16QAM modulation (also known as symbol mapping) to obtain one DP-16QAM data stream. The second data processing may also include convolutional interleaving, cyclic shifting, interleaving, and pilot insertion. The pilot insertion is also known as framing.

[0159] The convolutional interleaver contains r = 3 delay lines, with a difference of Q = 24 between the number of storage units in each pair of adjacent delay lines. Each storage unit stores d = 40 bits. Based on the obtained four-symbol boundaries, the d = 40 bits stored in each storage unit in the convolutional interleaver correspond to 4 RS symbols. Furthermore, based on the obtained four-symbol boundaries, the cyclic shift is performed on the 11 symbols corresponding to the 110 information bits in each codeword at the symbol level.

[0160] In the data processing method proposed in this embodiment, a four-symbol boundary is obtained before the internal code encoding. By utilizing the four-symbol boundary, the 110 information bits in the internal code (126,110) encoding come from 11 different RS codewords, thereby enabling the cascaded FEC scheme to have better error correction performance and be applicable to a wide range of transmission scenarios.

[0161] It should be noted that, as Figure 7The PAM4 decoding of the 8 AUI data streams of 1.6TAUI-8 yields p=8 first data streams. This can be considered as performing 1.6TBASE-R8:8SM-PMA processing on the 8 AUI data streams of 1.6TAUI-8 to obtain p=8 first data streams. Figure 7 The PAM4 decoding, 8:16 symbol demultiplexing, and alignment identifier locking in the process can be considered as 1.6TBASE-R8:16SM-PMA processing to obtain the p=16 data streams that achieve locking.

[0162] It should be noted that in some specific applications, such as Figure 8 As shown, the convolutional interleaving operation is bypassed, resulting in lower latency for the overall cascaded FEC scheme, which can be applied to application scenarios requiring low latency.

[0163] It should be noted that, Figure 7 As shown, the proposed data processing method first performs internal code encoding and then performs cyclic shifting, or it can be done as follows: Figure 9 As shown, a cyclic shift is performed first, followed by internal code encoding.

[0164] Example 2: Consider 1.6TBASE-R transmission, p=8 and q=2×p=16. Each data stream after convolutional interleaving is divided into 1:2 bit groups to obtain 2 output data streams.

[0165] Based on Example 1, the 16 second data streams (q=16) obtained after 40-bit deskew are first subjected to convolutional interleaving, and then distributed as 1:2 bit groups, resulting in a total of 32 data streams. More specifically, as... Figure 10 As shown, each second data stream undergoes convolutional interleaving and then bit-grouping in a 1:2 ratio to obtain two output data streams; the 16 second data streams undergo convolutional interleaving and then bit-grouping in a 1:2 ratio to obtain a total of 32 data streams. Then, these data streams are processed as follows... Figure 10 The diagram illustrates internal code encoding, cyclic shifting, and other operations. In some specific applications, the bit block distribution shown uses 110-bit granules, distributed in a round-robin manner for K=110 bit blocks. In other specific applications, the bit block distribution shown employs... Bit particles are distributed in 120-bit blocks using a round-robin method.

[0166] It should be noted that after the 32 data streams are distributed, as follows: Figure 10The processing of internal code encoding, cyclic shifting, interleaving, pilot insertion, and DP-16QAM modulation shown is the same as the existing OIF-800LR scheme, making the proposed 1.6T data processing method compatible with the OIF-800LR scheme and easy to implement in hardware.

[0167] Example 3: Consider a 1.6TBASE-R transmission, where p = 8 and q = 2 × p = 16. The second data processing involves 16:8 symbol multiplexing.

[0168] Based on Example 1, the 16 second data streams (q=16) obtained after 40-bit deskew are first multiplexed in a 16:8 ratio to obtain 8 third data streams, which are then subjected to convolutional interleaving, as follows: Figure 11 The convolutional interleaving processing rate is approximately 200G, the same as that used in the existing 1.6T-DR8-2 standard, which facilitates hardware implementation.

[0169] The 16:8 symbol multiplexing comprises eight 2:1 symbol multiplexings, each corresponding one-to-one with one of the eight first data streams. More specifically, each 2:1 symbol multiplexing multiplexes one first data stream by performing 1:2 symbol demultiplexing and de-skewing to obtain two second data streams, which are then multiplexed in a 2:1 symbol manner. This single 2:1 symbol multiplexing, combined with the acquired four-symbol boundary, uses a round-robin method with four symbols (containing a total of 40 bits) to multiplex the two input second data streams to obtain one output third data stream. The eight 2:1 symbol multiplexings multiplex the 16 input second data streams to obtain eight third data streams.

[0170] Furthermore, such as Figure 12 As shown, each third data stream undergoes convolutional interleaving and then is divided into 1:4 bit groups to obtain 4 output data streams. Eight third data streams undergo convolutional interleaving and then are divided into 1:4 bit groups to obtain a total of 32 output data streams. Then, these data streams are processed as follows... Figure 12 The diagram illustrates internal code encoding, cyclic shifting, and other operations. In some specific applications, the bit block distribution shown uses 110-bit granules, distributed in a round-robin manner for K=110 bit blocks. In other specific applications, the bit block distribution shown employs... Bit particles are distributed in 120-bit blocks using a round-robin method. After distribution, a total of 32 data streams are obtained, as follows: Figure 12The processing of internal code encoding, cyclic shifting, interleaving, pilot insertion (also known as framing), and DP-16QAM modulation shown is the same as the existing OIF-800LR scheme, making the proposed 1.6T data processing method compatible with the OIF-800LR scheme and easy to implement in hardware.

[0171] Example 4: Consider 1.6TBASE-R code encoding, p = 4 and q = 4 × p = 16.

[0172] like Figure 13 As shown, the four AUI data streams of 1.6TAUI-4 are processed by 1.6TBASE-R 4:4SM-PMA to obtain p = 4 first data streams. Performing 4:16 symbol demultiplexing and alignment identifier locking on the p = 4 first data streams yields the four symbol boundaries (also called the four symbol boundaries) of the p = 4 first data streams and q = 16 demultiplexed data streams implementing alignment identifier locking. The 4:16 symbol demultiplexing includes p = 4 1:4 symbol demultiplexings, as shown in Figure 5(c). Each 1:4 symbol demultiplexing uses a round-robin method, distributing 40 bits at a time, to demultiplex the input one first data stream into four output demultiplexed data streams. These 16 demultiplexed data streams implementing locking are also called 16 locked data streams.

[0173] The 16 locked data streams are subjected to 40-bit deskew to obtain q = 16 second data streams. Based on the obtained four-symbol boundaries, the q = 16 second data streams undergo a second data processing procedure including internal code encoding and DP-16QAM modulation (also known as symbol mapping) to obtain one DP-16QAM data stream. The second data processing also includes convolutional interleaving, cyclic shifting, interleaving, and pilot insertion. The pilot insertion is also known as framing.

[0174] The convolutional interleaver contains r = 3 delay lines, with a difference of Q = 24 between the number of storage units in each pair of adjacent delay lines. Each storage unit stores d = 40 bits. Based on the obtained four-symbol boundaries, the d = 40 bits stored in each storage unit in the convolutional interleaver correspond to 4 RS symbols. Furthermore, based on the obtained four-symbol boundaries, the cyclic shift is performed on the 11 symbols corresponding to the 110 information bits in each codeword at the symbol level.

[0175] It should be understood that in this embodiment, when p=4, the convolutional interleaving operation can be skipped to achieve lower latency for the overall cascaded FEC scheme, making it applicable to low-latency applications. Furthermore, in the second data processing, internal code encoding can be performed first, followed by cyclic shifting, or vice versa; this application does not limit this. Additionally, the second data processing can also include 16:4 symbol multiplexing, multiplexing the 16 second data streams to obtain 4 data streams for subsequent convolutional interleaving, internal code encoding, and other steps.

[0176] In this embodiment, before internal code encoding, a four-symbol boundary is obtained, and the four-symbol boundary is used to make the 110 information bits of the internal code (126,110) come from 11 different RS codewords, so that the cascaded FEC scheme has good error correction performance and can be applied to a variety of transmission scenarios.

[0177] Figure 14 This is a schematic diagram of a data processing device according to an embodiment of this application. Figure 14 As shown, the data processing device includes a first processing unit 1401 and a second processing unit 1402; wherein the first processing unit 1401 is used to perform the first data processing described in the previous embodiments, and the second processing unit 1402 is used to perform the second data processing described in the previous embodiments. The specific data processing methods have been described in detail in the previous embodiments and will not be repeated here.

[0178] It should be understood that the data processing apparatus provided in this application can also be implemented in other ways. For example, the unit division in the above apparatus is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system. In addition, the functional units in the various embodiments of this application may be integrated into one processing unit, or they may be independent physical units, or two or more functional units may be integrated into one processing unit. The integrated units described above can be implemented in hardware or as software functional units.

[0179] Figure 15 This is a schematic diagram of one structure of the optical module in an embodiment of this application. Figure 15As shown, the optical module includes a processor 1501 and an interface 1502. The processor 1501 is used to perform the operations performed by the data processing device in the above embodiments. The interface 1502 can be a transceiver or an input / output interface. The interface 1502 is used to receive signals from other devices and transmit them to the processor 1501 or to send signals from the processor 1501 to other devices. As an example, after the processor 1501 performs the internal code encoding process to obtain an encoded data stream, it sends the encoded data stream through the interface 1502. In this example, the interface 1502 can specifically refer to an electrical interface. As another example, after the processor 1501 performs the internal code encoding process to obtain an encoded data stream, it performs symbol mapping to obtain a symbol stream to be transmitted. The modulator in the optical module performs signal processing such as electro-optic conversion according to the symbol stream to be transmitted to obtain an optical signal, and then sends the optical signal through the interface 1502. In this example, the interface 1502 can specifically refer to an optical interface. Optionally, the optical module may also include a memory 1503, wherein the memory 1503 is used to store program instructions and / or data.

[0180] Typically, an optical module consists of optoelectronic devices, a processor, and an interface. The optoelectronic devices include transmitting and receiving devices. The transmitting end of the optical module converts electrical signals into optical signals and transmits them through optical fibers. The receiving end of the optical module receives the optical signals and converts them back into electrical signals.

[0181] It should be noted that the types of optical modules in this application embodiment include, but are not limited to, normal optical modules, near package optics (NPO) modules, and co-packaged optics (CPO) modules. Normal optical modules can perform functions including, but not limited to, digital signal processing (DSP) and clock data recovery (CDR). For example, a normal optical module converts analog signals to digital signals, performs DSP on the digital signals, and then converts them back to analog signals before sending them to the host device. Because DSP requires retiming, a normal optical module can also be called a retimed module. Normal optical modules connect to the host device via an attachment unit interface (AUI). NPO and CPO modules do not have pluggable physical packages and are closer to the host device. NPO and CPO modules can also be called optical engines. NPO or CPO technology is a technology that "packages" the host device (or host chip) and the optical engine. When NPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called an NPO module. When CPO technology is used to encapsulate the host-side device and the optical engine, the optical engine can be called a CPO module.

[0182] Figure 16 This is a schematic diagram of the structure of a communication device in an embodiment of this application. Figure 16 As shown, the communication device includes a host-side device 1601 and an optical module 1602. The host-side device 1601 sends data to the optical module 1602, and the optical module 1602 generates an optical signal based on the data sent by the host-side device 1601 and transmits the optical signal through the channel. For example, the host-side device can be a switch, router, or server. This communication device can be a communication device that includes a host-side device 1601 and an optical module 1602.

[0183] This application also provides an Optical Transport Network (OTN) device, which includes line-side equipment and client-side equipment. The client-side equipment may also be referred to as a tributary-side equipment in some scenarios. The line-side equipment includes a processor and an interface. The processor is used to execute the data processing methods described in the above embodiments. The interface can be a transceiver or an input / output interface, used to receive signals from other devices outside the line-side equipment and transmit them to the processor, or to send signals from the processor to other devices outside the line-side equipment.

[0184] This application also provides a chip. The chip integrates circuitry for implementing the functions of the aforementioned processor and one or more interfaces. As an example, the chip integrates a memory. As another example, when the chip does not integrate a memory, it can be connected to an external memory via the interface. The chip can perform the method steps of any one or more of the foregoing embodiments. Alternatively, the chip can implement the actions performed by the data processing device in the foregoing embodiments based on program code stored in the memory.

[0185] As an example, the chip in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0186] This application also provides a computer-readable storage medium, including a program or instructions that, when run on a computer, cause the data processing method as described in the above embodiments to be implemented.

[0187] It should be understood that the processor mentioned in the embodiments of this application can be implemented in hardware or software. When implemented in hardware, the processor can be a logic circuit, integrated circuit, etc. When implemented in software, the processor can be a general-purpose processor that reads software code stored in memory. The memory can exist independently and be connected to the processor, or the memory can be integrated with the processor.

[0188] As an example, the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor, any conventional processor, or a processing circuit that implements a specific function.

[0189] In embodiments of this application, the memory may be random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to a processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium may also be a component of the processor. The processor and storage medium may reside in an ASIC. Additionally, the ASIC may reside in a network device or a terminal device. Alternatively, the processor and storage medium may exist as discrete components in the network device or terminal device.

[0190] In the above embodiments, it can be implemented entirely or partially by software, hardware, firmware, or any combination thereof.

[0191] When implemented in hardware, the data processing method provided in this application embodiment may be implemented without reading software code or instructions. For example, it may be implemented by CPU, DSP, ASIC, FPGA, other programmable logic devices, transistor logic devices, hardware components, or any combination thereof.

[0192] When implemented using software, it can be implemented entirely or partially in the form of a computer program product. A computer program product includes one or more computer programs or instructions. When the computer program or instructions are loaded and executed on a computer, all or part of the processes or functions of the embodiments of this application are performed. The computer can be a general-purpose computer, a special-purpose computer, a computer network, a network device, a terminal device, or other programmable device. The computer program or instructions can be stored in or transmitted through a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computer can access, or a data storage device such as a server that integrates one or more available media. The available medium can be a magnetic medium, such as a floppy disk, hard disk, or magnetic tape; it can also be an optical medium, such as a Digital Versatile Disc (DVD); or it can be a semiconductor medium, such as a solid-state disk (SSD).

[0193] Finally, it should be noted that the above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A data processing method, characterized in that, include: The p first data streams encoded by Reed-Solomon RS are demultiplexed with p:q symbols, aligned identifiers are locked and deskewed to obtain q second data streams, where p is an integer greater than or equal to 1, q is an integer and q = 2 × p; The q second data streams are subjected to data processing including internal code encoding and dual polarization symbol mapping to obtain a single dual polarization data stream.

2. The method according to claim 1, characterized in that, The process of performing p:q symbol demultiplexing, alignment identifier locking, and deskewing on p first data streams encoded by Reed-Solomon RS to obtain q second data streams specifically includes: The p first data streams encoded by Reed-Solomon RS are demultiplexed with p:q symbols to obtain q fourth data streams; Alignment identifiers are locked for each of the q fourth data streams, and deskewing is performed to obtain the q second data streams.

3. The method according to claim 2, characterized in that, Alignment identifier locking is performed on each of the q fourth data streams, resulting in four symbol boundaries, where there are p four symbol boundaries, each corresponding to one of the p first data streams.

4. The method according to any one of claims 1-3, characterized in that, The p:q symbol demultiplexing includes p 1:2 symbol demultiplexings, wherein each of the p 1:2 symbol demultiplexings corresponds one-to-one with a p first data stream.

5. The method according to claim 4, characterized in that, The 1:2 symbol demultiplexing adopts a round-robin method of distributing 40 bits at a time to demultiplex the corresponding first data stream to obtain two fourth data streams.

6. The method according to claim 5, characterized in that, If at least one of the two fourth data streams fails to achieve alignment identifier locking within the threshold time interval, the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is shifted, and 1:2 symbol demultiplexing is performed again to obtain two fourth data streams again. Alignment flags are locked for the two newly acquired fourth data streams.

7. The method according to claim 6, characterized in that, The granularity of shifting the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is 1 bit; or The granularity of shifting the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is 40×m+1 bits, where m is an integer greater than 0.

8. The method according to any one of claims 1-7, characterized in that, p = 8, q = 16; the codeword length of the internal code is 126 bits, of which 110 bits are information bits and 16 bits are parity bits; or, the codeword length of the internal code is 128 bits, of which 120 bits are information bits and 8 bits are parity bits.

9. The method according to any one of claims 1-8, characterized in that, The codeword length of the RS is 544 symbols, of which the information length is 514 symbols, and each symbol contains 10 bits.

10. The method according to claim 9, characterized in that, Before each of the first data streams is encoded by the internal code, it is also subjected to convolutional interleaving. The convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, and the delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

11. The method according to claim 10, characterized in that, Each delay line receives 40 bits as input and outputs 40 bits at a time. After convolution and interleaving, the output data stream contains a continuous r×40 bits, including the 40 bits output by each delay line. The 40 bits stored in the storage unit are 4 RS symbols.

12. The method according to any one of claims 1-11, characterized in that, There is no skew between any two of the q second data streams; or, there is a skew of dskew bits between any two of the q second data streams, where d skew It is a multiple of 40.

13. The method according to any one of claims 1-12, characterized in that, The dual polarization symbol mapping is any one of DP-16QAM symbol mapping, DP-8QAM symbol mapping, or DP-QPSK symbol mapping.

14. The method according to any one of claims 1-13, characterized in that, Before encoding the q second data streams using internal codes, the method further includes: With K or Using bits as the granularity, each second data stream is distributed in a round-robin fashion to obtain two distributed data streams, for a total of 2q distributed data streams, where K is an integer and represents the information bit length of the internal code. This indicates rounding down to the nearest integer.

15. The method according to any one of claims 1-13, characterized in that, The q second data streams are subjected to data processing including internal code encoding and dual polarization symbol mapping to obtain one dual polarization data stream, specifically including: The q second data streams are multiplexed using the symbol q:p to obtain p third data streams; The p third data streams are subjected to data processing including internal code encoding and dual polarization symbol mapping to obtain the 1 dual polarization data stream.

16. The method according to claim 15, characterized in that, Before encoding the q second data streams using internal codes, the method further includes: With K or Using bits as the granularity, each second data stream is distributed in a round-robin manner to obtain 4 distributed data streams, for a total of 4q distributed data streams, where K is an integer and is the information bit length of the internal code. This indicates rounding down to the nearest integer.

17. A data processing apparatus, characterized in that, include: First processing unit and second processing unit; The first processing unit is used to perform p:q symbol demultiplexing, alignment identifier locking and deskewing on p first data streams encoded by Reed-Solomon RS to obtain q second data streams, where p is an integer greater than or equal to 1, q is an integer and q = 2 × p; The second processing unit is used to perform data processing on the q second data streams, including internal code encoding and dual polarization symbol mapping, to obtain a single dual polarization data stream.

18. The apparatus according to claim 17, characterized in that, The first processing unit is specifically used for: The p first data streams encoded by Reed-Solomon RS are demultiplexed with p:q symbols to obtain q fourth data streams; Alignment identifiers are locked for each of the q fourth data streams, and deskewing is performed to obtain the q second data streams.

19. The apparatus according to claim 18, characterized in that, The first processing unit performs alignment identification locking on the q fourth data streams respectively, and also obtains four symbol boundaries, wherein there are p four symbol boundaries, which correspond one-to-one with the p first data streams.

20. The apparatus according to any one of claims 17-19, characterized in that, The p:q symbol demultiplexing includes p 1:2 symbol demultiplexings, wherein each of the p 1:2 symbol demultiplexings corresponds one-to-one with a p first data stream.

21. The apparatus according to claim 20, characterized in that, The 1:2 symbol demultiplexing adopts a round-robin method of distributing 40 bits at a time to demultiplex the corresponding first data stream to obtain two fourth data streams.

22. The apparatus according to claim 21, characterized in that, If at least one of the two fourth data streams fails to achieve alignment identifier locking within the threshold time interval, the first processing unit is further configured to shift the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing, and re-perform 1:2 symbol demultiplexing to obtain two fourth data streams again; and perform alignment identifier locking on the two re-obtained fourth data streams respectively.

23. The apparatus according to claim 22, characterized in that, The granularity of shifting the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is 1 bit; or The granularity of shifting the boundary of the 40 bits distributed in the 1:2 symbol demultiplexing is 40×m+1 bits, where m is an integer greater than 0.

24. The apparatus according to any one of claims 17-23, characterized in that, p = 8, q = 16; the codeword length of the internal code is 126 bits, of which 110 bits are information bits and 16 bits are parity bits; or, the codeword length of the internal code is 128 bits, of which 120 bits are information bits and 8 bits are parity bits.

25. The apparatus according to any one of claims 17-24, characterized in that, The codeword length of the RS is 544 symbols, of which the information length is 514 symbols, and each symbol contains 10 bits.

26. The apparatus according to claim 25, characterized in that, The second processing unit is also used to perform convolutional interleaving on the received data stream. The convolutional interleaving includes delaying the input data stream according to r delay lines, where r is an integer greater than 1. Each delay line includes a different number of storage units, and the delay line with the smallest number of storage units includes 0 storage units. The difference in the number of storage units between any two adjacent delay lines is Q. Each storage unit is used to store 40 bits, where Q is an integer greater than or equal to 1.

27. The apparatus according to claim 26, characterized in that, Each delay line receives 40 bits as input and outputs 40 bits at a time. After convolution and interleaving, the output data stream contains a continuous r×40 bits, including the 40 bits output by each delay line. The 40 bits stored in the storage unit are 4 RS symbols.

28. The apparatus according to any one of claims 17-27, characterized in that, There is no skew between any two of the q second data streams; or, there is a d skew between any two of the q second data streams. skew The skewness of bits, where d skew It is a multiple of 40.

29. The apparatus according to any one of claims 17-28, characterized in that, The dual polarization symbol mapping is any one of DP-16QAM symbol mapping, DP-8QAM symbol mapping, or DP-QPSK symbol mapping.

30. The apparatus according to any one of claims 17-29, characterized in that, The second processing unit is further configured to, before encoding the q second data streams using internal codes, use K or... Using bits as the granularity, each second data stream is distributed in a round-robin fashion to obtain two distributed data streams, for a total of 2q distributed data streams, where K is an integer and represents the information bit length of the internal code. This indicates rounding down to the nearest integer.

31. The apparatus according to any one of claims 17-29, characterized in that, The second processing unit is specifically used for: The q second data streams are multiplexed using the symbol q:p to obtain p third data streams; The p third data streams are subjected to data processing including internal code encoding and dual polarization symbol mapping to obtain the 1 dual polarization data stream.

32. The apparatus according to claim 31, characterized in that, The second processing unit is further configured to, before encoding the q second data streams using internal codes, use K or... Using bits as the granularity, each second data stream is distributed in a round-robin fashion to obtain 4 distributed data streams, for a total of 4q distributed data streams, where K is an integer and is the information bit length of the internal code. This indicates rounding down to the nearest integer.

33. A chip, characterized in that, The chip is used to perform the method as described in any one of claims 1 to 16.

34. An optical module, characterized in that, The optical module includes a processor and an interface, wherein the processor is used to perform the method as described in any one of claims 1 to 16 and to transmit and receive signals through the interface.

35. A communication device, characterized in that, The transmitting device includes a host-side device and an optical module as described in claim 34, wherein the optical module is connected to the host-side device.

36. A communication system, characterized in that, include: A first communication device and a second communication device, wherein at least one of the first communication device and the second communication device is the communication device as described in claim 35, and the first communication device and the second communication device are connected.

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