Device, method and system for testing fault ride-through capability of static var compensator

Abstract

The invention relates to a fault ride-through capability testing device, method and system for a static var compensator, the testing device is connected with a static var compensator SVG to be tested, the SVG to be tested is connected with a regulation and control system, the regulation and control system is connected with a grid-connected transformer, the grid-connected transformer is respectively connected with a power grid and the SVG to be tested, and the grid-connected transformer is connected with a power grid. The device comprises a first processor, a second processor and a first high-voltage side acquisition end, the first processor is connected with the regulation and control system and the second processor, the first high-voltage side acquisition end is connected between the high-voltage side of the grid-connected transformer and a power grid, and the second processor is connected with the first high-voltage side acquisition end. According to the invention, the safety of SVG and power grid operation during an online test period is practically guaranteed, the synchronization efficiency of the test voltage output by the test device and the SVG grid-connected point voltage is also improved, and the test device can enable the output test voltage to reach a set variation amplitude under any condition of the port voltage of the to-be-tested SVG.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of grid-connected control of power electronic equipment, and particularly relates to a static var compensator fault ride-through capability testing device, method and system. BACKGROUND

[0002] The SVG plays a crucial role in improving the voltage operation stability of the grid-connected point of the new energy and energy storage power station, especially in weak grid areas. The basic working principle is that, in normal operation, the SVG responds to the reactive power / voltage adjustment instructions issued by the regulation system, and the control mode is generally divided into constant reactive power and constant voltage modes; in fault conditions, the SVG performs fault ride-through control and autonomously supports the fault voltage.

[0003] At present, the fault ride-through capability of the SVG is generally verified through isolated grid type field testing and semi-physical simulation testing. The isolated grid type field testing is carried out by isolating the SVG to be tested from the real power grid and connecting the SVG to a power grid simulation source. However, due to the terrain conditions of the field testing and the volume of the power grid simulation source, the existing isolated grid testing equipment cannot meet the testing capacity requirements of the large-capacity SVG in complex terrains. The semi-physical simulation testing is carried out by connecting the SVG to a real-time simulator with a test power grid model. Although it is not affected by the capacity of the simulation power grid source, it is a non-power type test and cannot verify the power response dynamic behavior of the static var compensator. Therefore, it is urgent to develop an online testing method for the fault ride-through capability of the large-capacity SVG in complex terrains. SUMMARY

[0004] To overcome the problems in the related art, the present application provides a static var compensator fault ride-through capability testing device, method and system.

[0005] According to a first aspect of an embodiment of the present application, a static var compensator fault ride-through capability testing device is provided, which is connected to a static var compensator SVG to be tested, the SVG to be tested is connected to a regulation system, the regulation system is connected to a grid-connected transformer, the grid-connected transformer is connected to a power grid and the SVG to be tested respectively, and the testing device comprises a first processor, a second processor and a first high-voltage side acquisition end. The first processor is connected to the regulation system and the second processor respectively, and is configured to send a recording instruction corresponding to each target reactive power instruction to the first high-voltage side acquisition end when receiving each target reactive power instruction issued by the regulation system. The first high-voltage side acquisition end is connected between the grid-connected transformer and the power grid, and is configured to collect target current data and target voltage data between the SVG to be tested and the grid-connected transformer when receiving the recording instruction, and send the target current data and target voltage data to the second processor. The second processor is connected with the first high-voltage side acquisition end, is used for determining an online test working condition set by using the target current data and the target voltage data, setting a fault ride-through control coefficient of the SVG to be tested according to the online test working condition set, is further used for synchronizing the grid-connected point voltage of the test device with the SVG to be tested by using a pre-established linear interpolation model, and is further used for determining a deviation coefficient by using a segmented amplitude coefficient compensation strategy, determining a final output voltage according to the deviation coefficient, and making the SVG to be tested support reactive power by using the final output voltage in fault ride-through.

[0006] Preferably, the device further comprises a first low-voltage side acquisition end, an AD module, a DA module and a test voltage output end. The AD module is connected with the first high-voltage side acquisition end, the first low-voltage side acquisition end and the second processor respectively, and the DA module is connected with the second processor and the test voltage output end respectively.

[0007] Preferably, the AD module is used for analog-digital conversion. The DA module is used for power amplification of a digital signal.

[0008] Preferably, the first high-voltage side acquisition end is connected with a first current transformer through a first current clamp meter, and is connected with a first voltage transformer. The first low-voltage side acquisition end is connected with a second current transformer through a second current clamp meter, and is connected with a second voltage transformer. The first current transformer and the first voltage transformer are arranged on an electrical primary connection between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are arranged on an electrical primary connection between the grid-connected transformer and the SVG to be tested.

[0009] Preferably, the SVG to be tested comprises a second high-voltage side acquisition end and a second low-voltage side acquisition end. The second high-voltage side acquisition end is connected with a first current transformer through a first current clamp meter, and is connected with a first voltage transformer. The second low-voltage side acquisition end is connected with a second current transformer through a second current clamp meter, and is connected with a second voltage transformer. The first current transformer and the first voltage transformer are arranged on an electrical primary connection between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are arranged on an electrical primary connection between the grid-connected transformer and the SVG to be tested.

[0010] Preferably, the target reactive power instructions include a capacitive maximum reactive power instruction, an inductive maximum reactive power instruction, and an initial reactive power instruction. The target reactive power instructions are issued in the following order: the capacitive maximum reactive power instruction, the inductive maximum reactive power instruction, and the initial reactive power instruction.

[0011] Preferably, the regulation system is configured to send the target reactive power instructions to the SVG under test and the first processor according to the order in which the target reactive power instructions are issued, and the time interval between the target reactive power instructions is a preset time interval. The SVG under test is configured to send the target reactive power to the power grid when receiving the target reactive power instructions, and the maintenance time of the target reactive power is a preset time interval.

[0012] Preferably, the first high-voltage side acquisition terminal is configured to: record the current data and voltage data between the SVG under test and the grid-connected transformer when receiving the recording instruction corresponding to the target reactive power instruction; select the current data and voltage data in the preset time window in the maintenance time corresponding to the target reactive power instruction as target current data and target voltage data, and send the target current data and target voltage data to the second processor.

[0013] Preferably, the second processor includes: a first calculation unit configured to calculate the voltage effective value and the actual output reactive power using the target current data and target voltage data; a second calculation unit configured to calculate the grid reactance of the SVG under test using the voltage effective value and the actual output reactive power; a third calculation unit configured to calculate the online test working condition set using the grid reactance of the SVG under test and a preset safe operation boundary. The voltage effective value includes an inductive maximum reactive power test calculated per-unit voltage effective value and a capacitive maximum reactive power test calculated per-unit voltage effective value, and the actual output reactive power includes an inductive maximum reactive power test calculated per-unit actual output reactive power and a capacitive maximum reactive power test calculated per-unit actual output reactive power. The preset safe operation boundary includes a deviation of the grid point voltage, an action threshold for the SVG under test to enter low voltage ride through, and an action threshold for the SVG under test to enter high voltage ride through.

[0014] Preferably, the third calculation unit includes: The first calculation module is configured to calculate an actual maximum reactive power value during the online test by using the grid reactance of the SVG to be tested and a preset safe operation boundary. The second calculation module is configured to calculate a low-voltage fault ride-through control coefficient during the online test and a high-voltage fault ride-through control coefficient during the online test by using the actual maximum reactive power value during the online test, respectively, wherein the low-voltage fault ride-through control coefficient during the online test and the high-voltage fault ride-through control coefficient during the online test are the set of online test working conditions.

[0015] Preferably, the first calculation module is specifically configured to: calculate a theoretical maximum reactive power value during the online test by using the grid reactance of the SVG to be tested and a preset safe operation boundary. calculate the actual maximum reactive power value during the online test by using the theoretical maximum reactive power value during the online test.

[0016] Preferably, the first processor further comprises: The control unit is configured to control the first high-voltage side acquisition end or the first low-voltage side acquisition end to acquire an actual output voltage value of the test device according to a test requirement after setting the fault ride-through control coefficient of the SVG to be tested, and send the actual output voltage value of the test device to the second processor.

[0017] Preferably, the second processor further comprises: The fourth calculation unit is configured to calculate an output voltage reference value of the test device at a next time point by using a pre-established linear interpolation model based on the actual output voltage value of the test device after setting the fault ride-through control coefficient of the SVG to be tested. The voltage synchronization unit is configured to send the output voltage reference value of the test device at the next time point to the DA module for power amplification to obtain an output test voltage of the test device when output voltage errors of the test device at a continuous preset number of time points are all less than or equal to a maximum allowed error of the test device, so that the DA module sends the output test voltage to a test voltage output end, and the test voltage output end connects the output test voltage to a low-voltage side voltage acquisition end of the SVG to synchronize a point of common coupling voltage of the test device and the SVG to be tested.

[0018] Preferably, the second processor further comprises: The fifth calculation unit is configured to calculate a deviation coefficient by using the actual output voltage value of the test device. The compensation unit is configured to, after the voltage synchronization is completed, determine whether to compensate the amplitude of the output signal of the DA module by using the received preset SVG high-low pass online test signal sequence current state sent by the first processor, if no compensation is needed, send the SVG high-low pass online test signal sequence current state to the DA module, so that the DA module determines the final output voltage according to the current state, and if compensation is needed, calculate a compensation coefficient by using the deviation coefficient, and send the compensation coefficient and the current state to the DA module, so that the DA module determines the final output voltage according to the compensation coefficient and the current state.

[0019] Preferably, the compensation unit is specifically configured to: when the SVG high-low pass online test signal sequence current state is 1, no compensation is needed for the amplitude of the output signal of the DA module, and when the SVG high-low pass online test signal sequence current state is K u , compensation is needed for the amplitude of the output signal of the DA module.

[0020] Preferably, the DA module is further configured to: send the final output voltage to the test voltage output end, so that the test voltage output end sends the final output voltage to the SVG to be tested, and then the SVG to be tested uses the final output voltage to provide reactive power support for fault ride-through.

[0021] Preferably, the calculation formula of the grid reactance of the SVG to be tested comprises:

[0022] In the above formula, X grid is the grid reactance of the SVG to be tested, V 1 is the effective value of the per-unit voltage calculated by the maximum test of inductive reactive power, V 2 is the effective value of the per-unit voltage calculated by the maximum test of capacitive reactive power, Q 1 is the actual output reactive power of the per-unit voltage calculated by the maximum test of inductive reactive power, Q 2 is the actual output reactive power of the per-unit voltage calculated by the maximum test of capacitive reactive power.

[0023] Preferably, the calculation formula of the theoretical maximum allowed value of the reactive power during the online test comprises:

[0024] The calculation formula of the actual maximum allowed value of the reactive power during the online test comprises:

[0025] In the above formula, Q Em is the theoretical maximum allowed value of reactive power during online testing, X grid is the grid reactance of the SVG to be tested, K B is the deviation of the grid point voltage, Q m is the actual maximum allowed value of reactive power during online testing, K is the maximum reactive overload factor of the SVG to be tested, Q N is the rated power of the SVG to be tested.

[0026] Preferably, the calculation formula of the low-voltage fault ride-through control coefficient during online testing includes:

[0027] The calculation formula of the high-voltage fault ride-through control coefficient during online testing includes:

[0028] In the above formula, K L is the low-voltage fault ride-through control coefficient during online testing, U L is the voltage value after the grid point voltage drops, Q m is the actual maximum allowed value of reactive power during online testing, ω 1 is the action threshold for the SVG to enter low-voltage ride-through, ω 2 is the action threshold for the SVG to enter high-voltage ride-through, K H is the high-voltage fault ride-through control coefficient during online testing, U H is the voltage value after the grid point voltage drops.

[0029] Preferably, the calculation formula of the linear interpolation model includes:

[0030] In the above formula, , T test is the total time of testing, U a is the output voltage reference value of the testing device at time k +1, k +1, N dTo match the control delay interval value of the test device, U r This represents the actual output voltage value of the testing device. e To test the output voltage error of the device, e max This represents the maximum permissible error of the testing device.

[0031] Preferably, the formula for calculating the control delay interval of the matching test device includes:

[0032] The formula for calculating the output voltage error of the testing device includes:

[0033] The formula for calculating the maximum permissible error of the testing device includes:

[0034] In the above formula, , T test To test the total time, T d To match the control delay of the test equipment, T s For signal output period, U a ( k-N d +1) is ( k-N d The output voltage reference value at time +1) U r ( k-N d +1) is ( k-N d Measured output voltage at time +1) U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage. f 0 represents frequency.

[0035] Preferably, the formula for calculating the deviation coefficient includes:

[0036] In the above formula, K 1 is the deviation coefficient. U r This represents the actual output voltage value of the testing device. U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage.

[0037] Preferably, the SVG high-low pass online test signal sequence is:

[0038] In the above formula, , T test is the total test time, S k is the SVG high-low pass online test signal sequence at k K u is the drop / jump amplitude of the final output voltage relative to the secondary voltage rating of the SVG grid point voltage.

[0039] Preferably, the compensation coefficient calculation formula includes: K BC K u K 1 In the above formula, K BC is the compensation coefficient, K u is the drop / jump amplitude of the final output voltage relative to the secondary voltage rating of the SVG grid point voltage, K 1 is the deviation coefficient.

[0040] Preferably, the final output voltage calculation formula includes:

[0041] In the above formula, U O k is the final output voltage at k Ua k is the output voltage reference value of the test device at k S k is the SVG high-low pass online test signal sequence at k K BC is the compensation coefficient.

[0042] According to a second aspect of the embodiment of the present application, a static reactive power compensation device fault ride-through capability online test method is provided, which is suitable for the static reactive power compensation device fault ride-through capability test device, and includes: When the first processor receives each target reactive power instruction issued by the control system, the first processor sends a recording wave instruction corresponding to each target reactive power instruction to the first high-voltage side collection end; ​​​​​​​​​​The first high-voltage side acquisition end collects target current data and target voltage data between the SVG to be tested and the grid-connected transformer when the recording instruction is received, and sends the target current data and target voltage data to the second processor; The second processor determines an online test working condition set according to the target current data and target voltage data, so as to set a fault ride-through control coefficient of the SVG to be tested according to the online test working condition set; After setting the fault ride-through control coefficient of the SVG to be tested, the second processor synchronizes the voltage of the test device and the grid-connected point of the SVG to be tested by using a pre-established linear interpolation model; After the voltage synchronization is completed, the second processor determines a deviation coefficient by using a segmented amplitude coefficient compensation strategy, so as to determine a final output voltage according to the deviation coefficient, and make the SVG to be tested provide reactive power support for fault ride-through by using the final output voltage.

[0043] According to a third aspect of the embodiment of the present application, a static reactive power compensation device fault ride-through capability online test system is provided, which comprises a control system, a SVG to be tested, and the static reactive power compensation device fault ride-through capability test device; the control system is connected with the test device and the SVG to be tested respectively, the SVG to be tested, a grid-connected transformer, and a power grid are connected in sequence; the control system is configured to send each target reactive power instruction to the SVG to be tested and a first processor in the test device respectively; The SVG to be tested is configured to send reactive power corresponding to the target reactive power instruction to the power grid when the target reactive power instruction is received, and the maintenance time of the reactive power is a preset time interval; The first processor in the test device is configured to send a recording instruction corresponding to each target reactive power instruction to a first high-voltage side acquisition end in the test device when each target reactive power instruction sent by the control system is received; The first high-voltage side acquisition end in the test device is configured to collect target current data and target voltage data between the SVG to be tested and the grid-connected transformer when the recording instruction is received, and send the target current data and target voltage data to a second processor in the test device; The second processor in the test device is configured to determine an online test working condition set by using the target current data and the target voltage data, set a fault ride-through control coefficient of the SVG to be tested according to the online test working condition set, perform voltage synchronization between the test device and a point of common coupling of the SVG to be tested by using a pre-established linear interpolation model, and determine a deviation coefficient by using a segmented amplitude coefficient compensation strategy, so as to determine a final output voltage according to the deviation coefficient, and make the SVG to be tested support reactive power by using the final output voltage during fault ride-through.

[0044] According to a fourth aspect of the embodiments of the present application, an electronic device is provided, comprising at least one processor and a memory; the memory and the processor are connected through a bus; The memory is configured to store one or more programs. When the one or more programs are executed by the at least one processor, the static reactive power compensation device fault ride-through capability online test method is implemented.

[0045] According to a fifth aspect of the embodiments of the present application, a readable storage medium having an execution program stored thereon is provided, and the execution program is executed to implement the static reactive power compensation device fault ride-through capability online test method.

[0046] The technical solutions provided by the present application have the following beneficial effects: The application provides a static var compensator fault ride-through capability testing device, method and system. BRIEF DESCRIPTION OF DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced as follows. Obviously, the drawings in the following description only show some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0048] Figure 1 It is a structural block diagram of a static var compensator fault ride-through capability testing device provided by the embodiment of the present application; Figure 2 It is a flowchart of a static var compensator fault ride-through capability online testing method provided by the embodiment of the present application; Figure 3 It is a flowchart of a static var compensator fault ride-through capability online testing system provided by the embodiment of the present application; Figure 4 is a capacitive reactive power / voltage control test waveform diagram of SVG provided by an embodiment of the present application; Figure 5 is an inductive reactive power / voltage control test waveform diagram of SVG provided by an embodiment of the present application; Figure 6 is a fast synchronization waveform diagram of a test device provided by an embodiment of the present application; Figure 7 is a SVG fault ride-through test waveform diagram after segment amplitude coefficient compensation provided by an embodiment of the present application; Figure 8 is a structural block diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be described clearly and completely below with reference to the drawings. Obviously, the following embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0050] Embodiment one In order to solve the problem that the fault ride-through capability of large-capacity SVG under current complex terrain conditions is difficult to carry out power type test, the present application provides a static reactive power compensation device fault ride-through capability test device. The test device is connected with the static reactive power compensation device SVG to be tested. The SVG to be tested is connected with a control system. The control system is connected with a grid-connected transformer. The grid-connected transformer is connected with a power grid and the SVG to be tested, respectively, as shown in Figure 1 The test device comprises a first processor, a second processor and a first high-voltage side acquisition end. The first processor is connected with the control system and the second processor, respectively, and is used for sending a recording instruction corresponding to each target reactive power instruction to the first high-voltage side acquisition end when receiving each target reactive power instruction issued by the control system. The first high-voltage side acquisition end is connected between the grid-connected transformer and the power grid, and is used for collecting target current data and target voltage data between the SVG to be tested and the grid-connected transformer when receiving the recording instruction, and sending the target current data and the target voltage data to the second processor. The second processor is connected with the first high-voltage side collection end, and is configured to determine an online test working condition set by using the target current data and the target voltage data, to set a fault ride-through control coefficient of the SVG to be tested according to the online test working condition set, to perform voltage synchronization of a grid-connected point of the test device and the SVG to be tested by using a pre-established linear interpolation model, and to determine a deviation coefficient by using a segmented amplitude coefficient compensation strategy, so as to determine a final output voltage according to the deviation coefficient, and to make the SVG to be tested support reactive power by using the final output voltage in fault ride-through.

[0051] It should be noted that the high-voltage side of the grid-connected transformer is connected with the power grid, and the low-voltage side of the grid-connected transformer is connected with the SVG to be tested. Therefore, the first high-voltage side collection end is connected between the high-voltage side of the grid-connected transformer and the power grid, and the first high-voltage side collection end collects the target current data and the target voltage data between the SVG to be tested and the high-voltage side of the grid-connected transformer.

[0052] In some embodiments, the first processor can be but is not limited to a CPU processor, and the second processor can be but is not limited to an FPGA processor. The SVG to be tested, the grid-connected transformer and the power grid are connected in sequence through electrical primary wiring, and the regulation and control system is connected with the SVG to be tested and the test device through communication wiring.

[0053] It should be noted that after receiving the final output voltage, the SVG to be tested supports reactive power according to its fault ride-through control logic.

[0054] Further, the device further comprises a first low-voltage side collection end, an AD module, a DA module and a test voltage output end. The AD module is connected with the first high-voltage side collection end, the first low-voltage side collection end and the second processor respectively, and the DA module is connected with the second processor and the test voltage output end respectively.

[0055] Further, the AD module is configured to perform analog-to-digital conversion. The DA module is configured to perform power amplification on a digital signal.

[0056] Further, the first high-voltage side collection end is connected with the first current transformer through a first current clamp meter, and the first high-voltage side collection end is connected with the first voltage transformer. The first low-voltage side collection end is connected with the second current transformer through a second current clamp meter, and the first low-voltage side collection end is connected with the second voltage transformer. The first current transformer and the first voltage transformer are arranged on the electrical primary wiring between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are arranged on the electrical primary wiring between the grid-connected transformer and the SVG to be tested.

[0057] Further, the static reactive power compensation device comprises a second high-voltage side acquisition end and a second low-voltage side acquisition end; The second high-voltage side acquisition end is connected with the first current transformer through a first current clamp meter, and the second high-voltage side acquisition end is connected with the first voltage transformer; The second low-voltage side acquisition end is connected with the second current transformer through a second current clamp meter, and the second low-voltage side acquisition end is connected with the second voltage transformer; The first current transformer and the first voltage transformer are arranged on the electrical primary wiring between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are arranged on the electrical primary wiring between the grid-connected transformer and the SVG to be tested.

[0058] In some embodiments, the high-voltage side acquisition end of the SVG to be tested, the first current clamp meter and the first current transformer are sequentially connected through electrical secondary wiring, the test device, the first current clamp meter and the first current transformer are sequentially connected through electrical secondary wiring, the low-voltage side acquisition end of the SVG to be tested, the second current clamp meter and the second current transformer are sequentially connected through electrical secondary wiring, the low-voltage side acquisition end of the test device, the second current clamp meter and the second current transformer are sequentially connected through electrical secondary wiring, the high-voltage side acquisition end of the SVG to be tested and the first voltage transformer are connected through electrical secondary wiring, and the low-voltage side acquisition end of the SVG to be tested and the first voltage transformer are connected through electrical secondary wiring.

[0059] Further, each target reactive power instruction comprises a capacitive maximum reactive power instruction, an inductive maximum reactive power instruction and an initial reactive power instruction. The sequence of issuing each target reactive power instruction is: the capacitive maximum reactive power instruction, the inductive maximum reactive power instruction and the initial reactive power instruction.

[0060] Further, the regulation system is configured to send each target reactive power instruction to the SVG to be tested and the first processor according to the sequence of issuing each target reactive power instruction, and the time interval between each target reactive power instruction is a preset time interval. The SVG to be tested is configured to send the target reactive power corresponding to the target reactive power instruction to the power grid when receiving the target reactive power instruction, and the maintenance time of sending the target reactive power is the preset time interval, so as to respond to the instruction of the regulation system.

[0061] It should be noted that the "preset time interval" is not limited in the present application, and can be set by a person skilled in the art according to engineering requirements, expert experience or experimental data.

[0062] Further, the first high-voltage side acquisition end is specifically configured to: When receiving the recording instruction corresponding to each target reactive power instruction, record the current data and voltage data between the SVG to be tested and the grid-connected transformer; The current data and voltage data of a preset time window in the maintaining time corresponding to each target reactive power instruction are selected as target current data and target voltage data, and the target current data and target voltage data are sent to the second processor.

[0063] It can be understood that when the recording wave instruction corresponding to each target reactive power instruction is received, the current data and voltage data between the SVG to be tested and the high-voltage side of the grid-connected transformer are recorded.

[0064] It should be noted that the present application does not limit the "preset time window", which can be set by a person skilled in the art according to engineering requirements, expert experience or experimental data, etc.

[0065] For example, 1) the capacitive maximum reactive power instruction is issued to the SVG to be tested through the regulation system; after maintaining for 2 min, the inductive maximum reactive power instruction is issued to the SVG to be tested; after maintaining for 2 min, the initial reactive power instruction is issued to the SVG to be tested; when the control instruction is issued to the SVG to be tested by the regulation system, it is simultaneously forwarded to the test device to trigger the recording wave function of the test device; 2) During the test, the test device records the voltage and current data of the high-voltage side of the grid-connected transformer, and selects the data of the last 30s of each instruction maintaining period to calculate the voltage effective value V and the actual output reactive power with a 20ms time window. Q .

[0066] Further, the second processor comprises: a first calculation unit configured to calculate the voltage effective value and the actual output reactive power by using the target current data and the target voltage data; a second calculation unit configured to calculate the grid reactance of the SVG to be tested by using the voltage effective value and the actual output reactive power; Specifically, the calculation formula of the grid reactance of the SVG to be tested comprises:

[0067] In the above formula, X grid is the grid reactance of the SVG to be tested, V 1 is the voltage effective value after normalization calculated in the inductive maximum reactive power test, V 2 is the voltage effective value after normalization calculated in the capacitive maximum reactive power test, Q 1 is the actual output reactive power after normalization calculated in the inductive maximum reactive power test, Q 2 is the actual output reactive power after normalization calculated in the capacitive maximum reactive power test; a third calculation unit configured to calculate the online test working condition set by using the grid reactance of the SVG to be tested and a preset safe operation boundary. The voltage effective value includes a maximum test calculated unit power factor voltage effective value and a maximum test calculated capacitive reactive voltage effective value, and the actual output reactive power includes a maximum test calculated unit power factor actual output reactive power and a maximum test calculated capacitive reactive actual output reactive power. The preset safe operation boundary includes a grid point voltage deviation, an action threshold of the SVG entering low voltage ride through, and an action threshold of the SVG entering high voltage ride through.

[0068] It should be noted that the "voltage effective value and actual output reactive power calculation" method involved in the embodiments of the present application is well known to those skilled in the art, and therefore, the specific implementation method is not described in detail.

[0069] Further, the third calculation unit comprises: The first calculation module is configured to calculate a maximum allowed value of the actual reactive power during the online test by using the grid reactance of the SVG to be tested and the preset safe operation boundary. The second calculation module is configured to calculate a low voltage fault ride through control coefficient during the online test and a high voltage fault ride through control coefficient during the online test by using the maximum allowed value of the actual reactive power during the online test, and the low voltage fault ride through control coefficient during the online test and the high voltage fault ride through control coefficient during the online test are the online test working condition set.

[0070] Further, the first calculation module is specifically configured to: calculate a maximum allowed value of the theoretical reactive power during the online test by using the grid reactance of the SVG to be tested and the preset safe operation boundary. calculate the maximum allowed value of the actual reactive power during the online test by using the maximum allowed value of the theoretical reactive power during the online test. Specifically, the calculation formula of the maximum allowed value of the theoretical reactive power during the online test comprises:

[0071] The calculation formula of the maximum allowed value of the actual reactive power during the online test comprises:

[0072] In the above formula, Q Em is the maximum allowed value of the theoretical reactive power during the online test, X grid is the grid reactance of the SVG to be tested, K B is the grid point voltage deviation, Q ma maximum allowed value of the actual reactive power during the online test, K a maximum reactive overload multiple of the SVG to be tested, Q N a rated power of the SVG to be tested.

[0073] Further, the calculation formula of the low-voltage fault ride-through control coefficient during the online test includes:

[0074] the calculation formula of the high-voltage fault ride-through control coefficient during the online test includes:

[0075] In the above formula, K L a low-voltage fault ride-through control coefficient during the online test, U L a voltage value after voltage drop of the grid-connected point, Q m a maximum allowed value of the actual reactive power during the online test, ω 1 is an action threshold for the SVG to be tested to enter low-voltage ride-through, ω 2 is an action threshold for the SVG to be tested to enter high-voltage ride-through, K H a high-voltage fault ride-through control coefficient during the online test, U H a voltage value after voltage drop of the grid-connected point.

[0076] Further, the first processor further includes: a control unit configured to, after setting the fault ride-through control coefficient of the SVG to be tested, control the first high-voltage side acquisition end or the first low-voltage side acquisition end to acquire the actual output voltage value of the test device according to the test requirement, and send the actual output voltage value of the test device to the second processor.

[0077] It should be noted that the present application does not limit the "test requirement", which can be set by the person skilled in the art according to engineering requirements, expert experience or experimental data, etc. For example, when the fault ride-through control strategy of the SVG to be tested is based on low-voltage side voltage action, the test requirement is that the test device is synchronized with the low-voltage side voltage, and at this time the first low-voltage side acquisition end is required to acquire the actual output voltage value of the test device; similarly, when the fault ride-through control strategy of the SVG to be tested is based on high-voltage side voltage action, the test requirement is that the test device is synchronized with the high-voltage side voltage, and at this time the first high-voltage side acquisition end is required to acquire the actual output voltage value of the test device.

[0078] Further, the second processor further includes: The fourth calculation unit is configured to, after setting the fault ride-through control coefficient of the SVG to be tested, calculate the output voltage reference value of the test device at the next moment based on the actual output voltage of the test device and a pre-established linear interpolation model; The voltage synchronization unit is configured to, when the output voltage error of the test device at the continuous preset number of moments is less than or equal to the maximum allowable error of the test device, send the output voltage reference value of the test device at the next moment to the DA module for power amplification to obtain an output test voltage of the test device, so that the DA module sends the output test voltage to the test voltage output end, and the test voltage output end connects the output test voltage to the low-voltage side voltage collection end of the SVG to synchronize the grid-connected point voltage of the test device and the SVG to be tested. Specifically, the calculation formula of the linear interpolation model comprises:

[0079] In the above formula, , T test is the total test time, U a is the output voltage reference value of the test device at the moment k +1, k +1, N d is the interval value matching the control time delay of the test device, U r is the actual output voltage of the test device, e is the output voltage error of the test device, e max is the maximum allowable error of the test device; The calculation formula of the interval value matching the control time delay of the test device comprises:

[0080] The calculation formula of the output voltage error of the test device comprises:

[0081] The calculation formula of the maximum allowable error of the test device comprises:

[0082] In the above formula, , T test is the total test time, T d is the control time delay matching the test device, T s is the signal output period, U a is thek-N d +1) is the output voltage reference value at the moment of t k-N d +1) is the output voltage reference value at the moment of t U r k-N d +1) is the output voltage reference value at the moment of t k-N d +1) is the output voltage reference value at the moment of t U pccN +1) is the output voltage reference value at the moment of t f 0 is the frequency.

[0083] Further, the second processor further comprises: The fifth calculation unit is configured to calculate the deviation coefficient by using the output voltage actual value of the test device. Specifically, the calculation formula of the deviation coefficient comprises:

[0084] In the above formula, K 1 is the deviation coefficient, U r +1) is the output voltage actual value of the test device, U pccN +1) is the secondary voltage rated value of the SVG grid connection point voltage, that is, the voltage rated value of the grid connection point voltage after being transformed by the voltage transformer, which is generally 100V. The compensation unit is configured to, after the voltage synchronization is completed, determine whether to compensate the output signal amplitude of the DA module by using the current state of the preset SVG high-low on-line test signal sequence received by the first processor, if no compensation is needed, send the current state of the SVG high-low on-line test signal sequence to the DA module, so that the DA module determines the final output voltage according to the current state, and if compensation is needed, calculate the compensation coefficient by using the deviation coefficient, and send the compensation coefficient and the current state to the DA module, so that the DA module determines the final output voltage according to the compensation coefficient and the current state.

[0085] Further, the compensation unit is specifically configured to: When the current state of the SVG high-low on-line test signal sequence is 1, no compensation is needed for the output signal amplitude of the DA module, and when the current state of the SVG high-low on-line test signal sequence is K u 1, compensation is needed for the output signal amplitude of the DA module.

[0086] Further, the DA module is further configured to: ​The final output voltage is sent to the test voltage output terminal, so that the test voltage output terminal sends the final output voltage to the SVG under test, thereby enabling the SVG under test to use the final output voltage for reactive power support during fault ride-through.

[0087] Furthermore, the SVG high-low crossing online test signal sequence is as follows:

[0088] In the above formula, , T test To test the total time, S ( k )for k SVG high-low crossover online test signal sequence, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point.

[0089] Furthermore, the formula for calculating the compensation coefficient includes: K BC = K u / K 1 In the above formula, K BC For compensation coefficient, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point. K 1 represents the deviation coefficient.

[0090] Furthermore, the formula for calculating the final output voltage includes:

[0091] In the above formula, U O ( k )for k The final output voltage at time [time]. Ua ( k ) for the test device in k The output voltage reference value at that moment. S ( k )for k SVG high-low crossover online test signal sequence, K BC This is the compensation coefficient.

[0092] The application provides a static var compensator fault ride-through capability testing device, which not only practically guarantees the safety of the SVG and the power grid during online testing, but also improves the synchronization efficiency of the test device output test voltage and the SVG grid connection point voltage, so that the port voltage of the SVG to be tested can reach the set change range under any condition, and the compliance of the test signal and the reliability of the test result are guaranteed.

[0093] Embodiment two The application also provides a static var compensator fault ride-through capability online testing method, which is suitable for the static var compensator fault ride-through capability testing device, as shown in the figure, and includes the following steps. Figure 2 Step 1: when the first processor receives each target reactive power instruction issued by the regulation system, the first processor sends the recording instruction corresponding to each target reactive power instruction to the first high-voltage side collection end; Step 2: when the first high-voltage side collection end receives the recording instruction, the first high-voltage side collection end collects the target current data and target voltage data between the SVG to be tested and the grid-connected transformer, and sends the target current data and target voltage data to the second processor; Step 3: the second processor determines the online test working condition set according to the target current data and target voltage data, so as to set the fault ride-through control coefficient of the SVG to be tested according to the online test working condition set; Step 4: after setting the fault ride-through control coefficient of the SVG to be tested, the second processor uses the pre-established linear interpolation model to synchronize the grid connection point voltage of the test device and the SVG to be tested; Step 5: after the voltage synchronization is completed, the second processor determines the deviation coefficient by using the segmented amplitude coefficient compensation strategy, so as to determine the final output voltage according to the deviation coefficient, and makes the SVG to be tested use the final output voltage to support the reactive power during fault ride-through.

[0094] Further, the method further includes: analog-to-digital conversion is performed by using an AD module; Digital signals are power amplified by using a DA module.

[0095] Further, each target reactive power instruction includes a capacitive maximum reactive power instruction, an inductive maximum reactive power instruction and an initial reactive power instruction. The sequence of issuing each target reactive power instruction is: the capacitive maximum reactive power instruction, the inductive maximum reactive power instruction and the initial reactive power instruction.

[0096] Further, the method further includes: ​The regulating system sends each target reactive power instruction to the SVG to be tested and the first processor according to the sending sequence of each target reactive power instruction, and the sending time interval between each target reactive power instruction is a preset time interval. When the SVG to be tested receives each target reactive power instruction, the SVG to be tested sends the corresponding reactive power to the power grid, and the maintenance time of the reactive power is the preset time interval.

[0097] Further, step 2 comprises: step 21: when the first high-voltage side acquisition end receives the recording instruction corresponding to each target reactive power instruction, recording the current data and voltage data between the SVG to be tested and the grid-connected transformer; Step 22: using the first high-voltage side acquisition end to select the current data and voltage data in the preset time window in the maintenance time corresponding to each target reactive power instruction as target current data and target voltage data, and sending the target current data and target voltage data to the second processor.

[0098] Further, step 3 comprises: Step 31: the second processor calculates the voltage effective value and the actual output reactive power by using the target current data and the target voltage data; Step 32: the second processor calculates the grid reactance of the SVG to be tested by using the voltage effective value and the actual output reactive power; Step 33: the second processor calculates the online test working condition set by using the grid reactance of the SVG to be tested and the preset safe operation boundary. The voltage effective value comprises: the per-unit voltage effective value calculated by the maximum inductive reactive power test and the per-unit voltage effective value calculated by the maximum capacitive reactive power test; the actual output reactive power comprises: the per-unit actual output reactive power calculated by the maximum inductive reactive power test and the per-unit actual output reactive power calculated by the maximum capacitive reactive power test. The preset safe operation boundary comprises: the deviation of the grid point voltage, the action threshold of the SVG to be tested entering the low voltage ride through, and the action threshold of the SVG to be tested entering the high voltage ride through.

[0099] Further, step 33 comprises: Step 331: the second processor calculates the actual maximum allowable value of the reactive power during the online test by using the grid reactance of the SVG to be tested and the preset safe operation boundary. Step 332: the second processor calculates the low voltage fault ride through control coefficient during the online test and the high voltage fault ride through control coefficient during the online test by using the actual maximum allowable value of the reactive power during the online test, and the low voltage fault ride through control coefficient during the online test and the high voltage fault ride through control coefficient during the online test are the online test working condition set.

[0100] Further, step 331 comprises: Step 331a: using the power grid reactance of the SVG to be tested and the preset safe operation boundary, a theoretical maximum allowed value of the reactive power during the online test is calculated; Step 331b: using the theoretical maximum allowed value of the reactive power during the online test, an actual maximum allowed value of the reactive power during the online test is calculated.

[0101] Further, the method further comprises: After setting the fault ride-through control coefficient of the SVG to be tested, the first processor is used to control the first high-voltage side acquisition end or the first low-voltage side acquisition end to collect the actual output voltage value of the test device according to the test requirement, and the actual output voltage value of the test device is sent to the second processor.

[0102] Further, step 4 comprises: Step 41: after setting the fault ride-through control coefficient of the SVG to be tested, the second processor is used to calculate the output voltage reference value of the test device at the next moment based on the actual output voltage value of the test device by using the pre-established linear interpolation model; Step 42: when the output voltage error of the test device at a continuous preset number of moments is less than or equal to the maximum allowed error of the test device, the output voltage reference value of the test device at the next moment is sent to the DA module for power amplification by the second processor to obtain the output test voltage of the test device, so that the DA module sends the output test voltage to the test voltage output end, and the test voltage output end connects the output test voltage to the low-voltage side voltage acquisition end of the SVG for voltage synchronization of the test device and the grid point voltage of the SVG to be tested.

[0103] Further, step 5 comprises: Step 51: using the second processor to calculate the deviation coefficient using the actual output voltage value of the test device; Step 52: after the voltage synchronization is completed, the second processor is used to determine whether to compensate the output signal amplitude of the DA module using the current state of the received SVG high-low on-line test signal sequence sent by the first processor, if no compensation is needed, the current state of the SVG high-low on-line test signal sequence is sent to the DA module, so that the DA module determines the final output voltage according to the current state; if compensation is needed, a compensation coefficient is calculated using the deviation coefficient, and the compensation coefficient and the current state are sent to the DA module, so that the DA module determines the final output voltage according to the compensation coefficient and the current state.

[0104] Further, step 52 comprises: Step 521: when the current state of the SVG high-low pass online test signal sequence is 1, no compensation is needed for the output signal amplitude of the DA module; when the current state of the SVG high-low pass online test signal sequence is K u , compensation is needed for the output signal amplitude of the DA module.

[0105] Further, the method further comprises: sending the final output voltage to the test voltage output end by the DA module, so that the test voltage output end sends the final output voltage to the SVG to be tested, and then the SVG to be tested uses the final output voltage to perform fault ride-through reactive power support.

[0106] Further, the formula for calculating the grid reactance of the SVG to be tested comprises:

[0107] In the above formula, X grid is the grid reactance of the SVG to be tested, V 1 is the maximum test calculated per-unit voltage effective value of inductive reactive power, V 2 is the maximum test calculated per-unit voltage effective value of capacitive reactive power, Q 1 is the maximum test calculated per-unit actual output reactive power of inductive reactive power, Q 2 is the maximum test calculated per-unit actual output reactive power of capacitive reactive power.

[0108] Further, the formula for calculating the theoretical maximum allowable value of reactive power during online testing comprises:

[0109] The formula for calculating the actual maximum allowable value of reactive power during online testing comprises:

[0110] In the above formula, Q Em is the theoretical maximum allowable value of reactive power during online testing, X grid is the grid reactance of the SVG to be tested, K B is the deviation of the grid point voltage, Q m is the actual maximum allowable value of reactive power during online testing, K is the maximum reactive overload multiple of the SVG to be tested, Q N is the rated power of the SVG to be tested.

[0111] Further, the calculation formula of the low-voltage fault ride-through control coefficient during the online test includes:

[0112] The calculation formula of the high-voltage fault ride-through control coefficient during the online test includes:

[0113] In the above formula, K L is the low-voltage fault ride-through control coefficient during the online test, U L is the voltage value after the voltage drop of the grid-connected point, Q m is the actual maximum allowed value of the reactive power during the online test, ω 1 is the action threshold of the SVG to be tested entering low-voltage ride-through, ω 2 is the action threshold of the SVG to be tested entering high-voltage ride-through, K H is the high-voltage fault ride-through control coefficient during the online test, U H is the voltage value after the voltage drop of the grid-connected point.

[0114] Further, the calculation formula of the linear interpolation model includes:

[0115] In the above formula, , T test is the total time of the test, U a is the output voltage reference value of the test device at time k +1, k +1, N d is the interval value matching the control delay of the test device, U r is the actual output voltage of the test device, e is the output voltage error of the test device, e max is the maximum allowed error of the test device.

[0116] Further, the calculation formula of the interval value matching the control delay of the test device includes:

[0117] The calculation formula of the output voltage error of the test device includes:

[0118] The formula for calculating the maximum permissible error of the testing device includes:

[0119] In the above formula, , T test To test the total time, T d To match the control delay of the test equipment, T s For signal output period, U a ( k-N d +1) is ( k-N d The output voltage reference value at time +1) U r ( k-N d +1) is ( k-N d Measured output voltage at time +1) U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage. f 0 represents frequency.

[0120] Furthermore, the formula for calculating the deviation coefficient includes:

[0121] In the above formula, K 1 represents the deviation coefficient. U r This represents the actual output voltage value of the testing device. U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage.

[0122] Furthermore, the SVG high-low crossing online test signal sequence is as follows:

[0123] In the above formula, , T test To test the total time, S ( k )for k SVG high-low crossover online test signal sequence, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point.

[0124] Furthermore, the formula for calculating the compensation coefficient includes: KBC = K u / K 1 In the above formula, K BC For compensation coefficient, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point. K 1 represents the deviation coefficient.

[0125] Furthermore, the formula for calculating the final output voltage includes:

[0126] In the above formula, U O ( k )for k The final output voltage at time [time]. Ua ( k ) for the test device in k The output voltage reference value at that moment. S ( k )for k SVG high-low crossover online test signal sequence, K BC This is the compensation coefficient.

[0127] The present invention provides an online testing method for the fault ride-through capability of a static var compensator (SVG). This method not only effectively ensures the safety of the SVG and the power grid during online testing, but also improves the synchronization efficiency between the output test voltage of the testing device and the voltage at the SVG's grid connection point. It enables the testing device to output the test voltage to the set variation range under any condition, thus ensuring the compliance of the test signal and the reliability of the test results.

[0128] Example 3 An online testing system for the fault ride-through capability of a static var compensator, such as Figure 3 As shown, it includes: a control system, a static var compensator (SVG) under test, and the aforementioned static var compensator fault ride-through capability testing device. The control system is connected to the test device and the SVG under test respectively, and the SVG under test, the grid-connected transformer and the power grid are connected in sequence. The control system is used to send target reactive power commands to the SVG under test and the first processor in the test device, respectively. The SVG under test is used to send reactive power corresponding to each target reactive power command to the power grid when each target reactive power command is received, and the duration of sending reactive power is a preset time interval. The first processor in the testing device is configured to send a recording instruction corresponding to each target reactive power instruction to the first high-voltage side acquisition end in the testing device when receiving each target reactive power instruction issued by the regulation system. The first high-voltage side acquisition end in the testing device is configured to acquire target current data and target voltage data between the SVG to be tested and the grid-connected transformer when receiving the recording instruction, and send the target current data and the target voltage data to the second processor in the testing device. The second processor in the testing device is configured to determine an online test working condition set by using the target current data and the target voltage data, set a fault ride-through control coefficient of the SVG to be tested according to the online test working condition set, perform voltage synchronization between the testing device and the grid connection point of the SVG to be tested by using a pre-established linear interpolation model, determine a deviation coefficient by using a segmented amplitude coefficient compensation strategy, and determine a final output voltage according to the deviation coefficient, so that the SVG to be tested performs fault ride-through reactive power support by using the final output voltage.

[0129] It should be noted that the high-voltage side of the grid-connected transformer is connected with the power grid, and the low-voltage side of the grid-connected transformer is connected with the SVG to be tested, so the first high-voltage side acquisition end acquires the target current data and the target voltage data between the SVG to be tested and the high-voltage side of the grid-connected transformer.

[0130] Further, the AD module in the testing device is configured to perform analog-to-digital conversion. The DA module in the testing device is configured to perform power amplification on the digital signal.

[0131] Further, each target reactive power instruction includes a capacitive maximum reactive power instruction, an inductive maximum reactive power instruction and an initial reactive power instruction. The issuance order of each target reactive power instruction is: the capacitive maximum reactive power instruction, the inductive maximum reactive power instruction and the initial reactive power instruction.

[0132] Further, the regulation system is specifically configured to: send each target reactive power instruction to the SVG to be tested and the first processor respectively according to the issuance order of each target reactive power instruction, and the issuance time interval between each target reactive power instruction is a preset time interval.

[0133] Further, the first high-voltage side acquisition end is specifically configured to: record the current data and the voltage data between the SVG to be tested and the grid-connected transformer after receiving the recording instruction corresponding to each target reactive power instruction; select the current data and the voltage data in a preset time window in the maintenance time corresponding to each target reactive power instruction as the target current data and the target voltage data, and send the target current data and the target voltage data to the second processor.

[0134] Further, the second processor comprises: a first calculation unit, configured to calculate a voltage effective value and an actual output reactive power by using target current data and target voltage data; a second calculation unit, configured to calculate a grid reactance of the SVG to be tested by using the voltage effective value and the actual output reactive power; a third calculation unit, configured to calculate an online test working condition set by using the grid reactance of the SVG to be tested and a preset safe operation boundary; The voltage effective value comprises a per-unit voltage effective value calculated in a maximum inductive reactive test and a per-unit voltage effective value calculated in a maximum capacitive reactive test; and the actual output reactive power comprises a per-unit actual output reactive power calculated in the maximum inductive reactive test and a per-unit actual output reactive power calculated in the maximum capacitive reactive test. The preset safe operation boundary comprises a deviation of a grid point voltage, an action threshold of low voltage ride through of the SVG to be tested, and an action threshold of high voltage ride through of the SVG to be tested.

[0135] Further, the third calculation unit comprises: a first calculation module, configured to calculate an actual maximum allowable value of the reactive power during the online test by using the grid reactance of the SVG to be tested and the preset safe operation boundary; a second calculation module, configured to calculate a low voltage fault ride through control coefficient during the online test and a high voltage fault ride through control coefficient during the online test respectively by using the actual maximum allowable value of the reactive power during the online test, the low voltage fault ride through control coefficient during the online test and the high voltage fault ride through control coefficient during the online test being the online test working condition set.

[0136] Further, the first calculation module is specifically configured to: calculate a theoretical maximum allowable value of the reactive power during the online test by using the grid reactance of the SVG to be tested and the preset safe operation boundary; calculate the actual maximum allowable value of the reactive power during the online test by using the theoretical maximum allowable value of the reactive power during the online test.

[0137] Further, the first processor further comprises: a control unit, configured to control the first high voltage side acquisition end or the first low voltage side acquisition end to acquire an actual output voltage value of the test device according to a test requirement after setting the fault ride through control coefficient of the SVG to be tested, and send the actual output voltage value of the test device to the second processor.

[0138] Further, the second processor further comprises: The fourth calculation unit is configured to, after setting the fault ride-through control coefficient of the SVG to be tested, calculate the output voltage reference value of the test device at the next moment based on the actual output voltage of the test device and using a linear interpolation model established in advance; The voltage synchronization unit is configured to, when the output voltage errors of the test device at the continuous preset number of moments are all less than or equal to the maximum allowable error of the test device, send the output voltage reference value of the test device at the next moment to the DA module for power amplification to obtain an output test voltage of the test device, so that the DA module sends the output test voltage to the test voltage output end, and the test voltage output end connects the output test voltage to the low-voltage side voltage acquisition end of the SVG to synchronize the grid-connected point voltage of the test device and the SVG to be tested.

[0139] Further, the second processor further comprises: The fifth calculation unit is configured to calculate the deviation coefficient using the actual output voltage of the test device. The compensation unit is configured to, after the voltage synchronization is completed, determine whether to compensate the output signal amplitude of the DA module using the current state of the preset SVG high-low on-line test signal sequence received by the first processor, if no compensation is needed, send the current state of the SVG high-low on-line test signal sequence to the DA module, so that the DA module determines the final output voltage according to the current state, and if compensation is needed, calculate a compensation coefficient using the deviation coefficient, and send the compensation coefficient and the current state to the DA module, so that the DA module determines the final output voltage according to the compensation coefficient and the current state.

[0140] Further, the compensation unit is specifically configured to: When the current state of the SVG high-low on-line test signal sequence is 1, no compensation is needed for the output signal amplitude of the DA module, and when the current state of the SVG high-low on-line test signal sequence is K u When the current state of the SVG high-low on-line test signal sequence is 0, compensation is needed for the output signal amplitude of the DA module.

[0141] Further, the DA module is further configured to: Send the final output voltage to the test voltage output end, so that the test voltage output end sends the final output voltage to the SVG to be tested, and then the SVG to be tested uses the final output voltage to provide reactive power support for fault ride-through.

[0142] Further, the calculation formula of the grid reactance of the SVG to be tested comprises:

[0143] In the above formula, X grid is the grid reactance of the SVG to be tested, V1 is the effective value of the post-standard voltage calculated by the maximum test of inductive reactive power, V 2 is the effective value of the post-standard voltage calculated by the maximum test of capacitive reactive power, Q 1 is the actual output reactive power of the post-standard calculated by the maximum test of inductive reactive power, Q 2 is the actual output reactive power of the post-standard calculated by the maximum test of capacitive reactive power.

[0144] Further, the calculation formula of the theoretical maximum allowable value of the reactive power during online testing includes:

[0145] The calculation formula of the actual maximum allowable value of the reactive power during online testing includes:

[0146] In the above formula, Q Em is the theoretical maximum allowable value of the reactive power during online testing, X grid is the grid reactance of the SVG to be tested, K B is the deviation of the grid point voltage, Q m is the actual maximum allowable value of the reactive power during online testing, K is the maximum reactive power overload factor of the SVG to be tested, Q N is the rated power of the SVG to be tested.

[0147] Further, the calculation formula of the low voltage fault ride-through control coefficient during online testing includes:

[0148] The calculation formula of the high voltage fault ride-through control coefficient during online testing includes:

[0149] In the above formula, K L is the low voltage fault ride-through control coefficient during online testing, U L is the voltage value after the grid point voltage drops, Q m is the actual maximum allowable value of the reactive power during online testing, ω 1 is the action threshold for the SVG to be tested to enter low voltage ride-through, ω 2 is the action threshold for the SVG to be tested to enter high voltage ride-through, K H is the high voltage fault ride-through control coefficient during online testing,U H is the voltage value after the grid-connected point voltage dip.

[0150] Further, the calculation formula of the linear interpolation model comprises:

[0151] In the above formula, , T test is the total test time, U a is the output voltage reference value of the test device at time k +1, k +1, N d is the interval value matching the control time delay of the test device, U r is the actual output voltage value of the test device, e is the output voltage error of the test device, e max is the maximum allowable error of the test device.

[0152] Further, the calculation formula of the interval value matching the control time delay of the test device comprises:

[0153] The calculation formula of the output voltage error of the test device comprises:

[0154] The calculation formula of the maximum allowable error of the test device comprises:

[0155] In the above formula, , T test is the total test time, T d is the control time delay matching the test device, T s is the signal output period, U a is the output voltage reference value at time k-N d +1, k-N d +1, U r is the output voltage actual measurement value at time k-N d +1, k-N d +1, UpccN This refers to the rated secondary voltage of the SVG grid connection point voltage. f 0 represents frequency.

[0156] Furthermore, the formula for calculating the deviation coefficient includes:

[0157] In the above formula, K 1 represents the deviation coefficient. U r This represents the actual output voltage value of the testing device. U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage.

[0158] Furthermore, the SVG high-low crossing online test signal sequence is as follows:

[0159] In the above formula, , T test To test the total time, S ( k )for k SVG high-low crossover online test signal sequence, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point.

[0160] Furthermore, the formula for calculating the compensation coefficient includes: K BC = K u / K 1 In the above formula, K BC For compensation coefficient, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point. K 1 represents the deviation coefficient.

[0161] Furthermore, the formula for calculating the final output voltage includes:

[0162] In the above formula, U O ( k )for k The final output voltage at time [time]. Ua ( k ) for the test device in k The output voltage reference value at that moment.S k ) is k SVG high-low pass online test signal sequence, K BC is a compensation coefficient.

[0163] The static reactive power compensation device fault ride-through capability online test system provided by the application not only practically guarantees the safety of the SVG and power grid during online testing, but also improves the synchronization efficiency of the test device output test voltage and the SVG grid connection point voltage, realizes that the port voltage of the SVG to be tested can reach the set change range under any condition, guarantees the compliance of the test signal and the reliability of the test result.

[0164] Embodiment four To further illustrate the static reactive power compensation device fault ride-through capability online test system described above, the application provides a specific example, as shown in Figure 3 , including the following steps: Step 1: Build a static reactive power compensation device SVG fault ride-through capability online test system, develop reactive power / voltage control capability test, determine the online test working condition set of the fault ride-through capability in combination with the test data and the safe operation boundary.

[0165] Further, step 1 includes the following content: First, build the SVG fault ride-through capability online test system as shown in Figure 3 , under normal operation, the high-voltage side voltage and current collection end of the SVG to be tested are connected through electrical direct connection line (such as electrical secondary wiring) to the voltage transformer and current transformer of the grid-connected transformer high-voltage side respectively; the low-voltage side voltage and current collection end of the SVG to be tested is also connected through electrical direct connection line (such as electrical secondary wiring) to the voltage transformer and current transformer of the grid-connected transformer low-voltage side respectively, and can receive the reactive power / voltage adjustment instruction issued by the regulation and control system. When online testing, the test device needs to be connected, the high-voltage side voltage and current collection end of the test device is connected through electrical direct connection line to the voltage transformer and current transformer of the grid-connected transformer high-voltage side respectively; the low-voltage side voltage and current collection end is also connected through electrical direct connection line to the voltage transformer and current transformer of the grid-connected transformer high-voltage side respectively.

[0166] ​Specifically, the high-voltage side voltage and current acquisition terminals of the SVG under test and the test device are respectively connected to the first current transformer via a first current clamp meter; the low-voltage side voltage and current acquisition terminals of the SVG under test and the test device are respectively connected to the second current transformer via a second current clamp meter; the high-voltage side voltage and current acquisition terminals of the SVG under test and the test device are respectively connected to the first voltage transformer; the low-voltage side voltage and current acquisition terminals of the SVG under test and the test device are respectively connected to the second voltage transformer; the SVG under test, the grid-connected transformer, and the power grid are connected sequentially via primary electrical wiring, and the control system is connected to the SVG under test and the test device via communication wiring.

[0167] Next, the reactive power / voltage control capability of the SVG under test is tested. The test steps are as follows: 1) The control system sends a capacitive maximum reactive power command to the SVG under test; after holding for 2 minutes, it sends an inductive maximum reactive power command to the SVG under test; after holding for 2 minutes, it sends an initial reactive power command to the SVG under test; when the control system sends a control command to the SVG under test, it simultaneously forwards the command to the test device, triggering the waveform recording function of the test device.

[0168] 2) During the test, the testing device records the voltage and current data on the high-voltage side of the grid-connected transformer, and selects the data from the last 30 seconds of each command duration, using a 20ms time window to calculate the effective voltage value. V With actual output reactive power Q The calculation is as follows:

[0169]

[0170]

[0171]

[0172]

[0173]

[0174]

[0175]

[0176]

[0177] In the above formula, V re To measure the real part of the fundamental effective value of the phase voltage, TAs the reference period for measuring the signal, t 0 represents the start time of the calculation data window. t For a moment, u ( t () represents the instantaneous value of the measured phase voltage. f To measure the reference frequency of the signal, V lm To measure the imaginary part of the fundamental effective value of the phase voltage, V To measure the fundamental effective value of the phase voltage (i.e., the effective value of the voltage). φ V To measure the phase of the fundamental effective value of the phase voltage, I re To measure the real part of the fundamental effective value of the phase current. i ( t () represents the instantaneous value of the measured phase current. I lm To measure the imaginary part of the fundamental effective value of the phase current, I To measure the fundamental effective value of the phase current, φ I To measure the phase of the fundamental effective value of the phase current, Q This represents the actual output reactive power.

[0178] 3) Calculate the grid reactance of the SVG to be measured. X grid The calculation formula is as follows: (1) In the above formula, V 1 represents the per-unit effective voltage value calculated from the maximum inductive reactive power test. V 2 represents the per-unit effective voltage value calculated from the maximum capacitive reactive power test. Q 1 represents the actual per-unit output reactive power calculated from the maximum inductive reactive power test. Q 2 represents the actual per-unit output reactive power calculated from the maximum capacitive reactive power test.

[0179] Finally, based on the calculated grid reactance and safe operation boundary, the online test condition set is determined. The online test condition set includes: the actual maximum allowable value of reactive power during online testing. Q m Low-voltage fault ride-through control coefficient during online testing K L High-voltage fault ride-through control coefficient during online testing K H The specific steps are as follows: 1) According to the constraint of grid voltage deviation in GB / T12325 "Power quality-supply voltage deviation", the voltage deviation of the grid connection point of the SVG connected to the grid through voltage level above 35kV should be within ±10%, combined with grid reactance K B . X grid The theoretical maximum allowed value of reactive power during online test can be calculated as Q Em : (2) Considering that the value of calculated by formula (2) in strong grid may be greater than the maximum reactive overload capacity of the SVG, the actual maximum allowed value of reactive power during online test is obtained as Q Em : Q m (3) In formula (3), k is the maximum reactive overload multiple of the SVG to be tested, and P is the rated power of the SVG to be tested. K Q N

[0180] 2) According to the actual maximum allowed value of reactive power output by the SVG to be tested during online test and the low voltage fault ride through control equation, the low voltage fault ride through control coefficient during online test is determined K L . (4) In formula (4), I and V are the reactive current output by the SVG to be tested and the voltage of the grid connection point, respectively. Considering that the reactive current output by the SVG to be tested during online test is equivalent to the actual output reactive power, formula (4) can be written as I q : U pcc I q Q (5) If the grid management department requires the voltage of the grid connection point to drop to above V, the SVG to be tested should be able to reliably support it, and the low voltage fault ride through control coefficient during online test can be determined by substituting formula (5) into formula (6): U L (6) In formula (6), k is the low voltage fault ride through control coefficient during online test, and V is the voltage of the grid connection point. U L ​​​​​​​The voltage value after the voltage drop of the grid-connected point.

[0181] 3) Similarly, the high-voltage fault ride-through control coefficient during the online test can be determined according to the actual maximum allowed value of the reactive power output of the SVG to be tested during the online test and the high-voltage fault ride-through control equation K H : (7) In the above formula, U H The voltage value after the voltage drop of the grid-connected point.

[0182] Step 2: Set the fault ride-through control coefficient of the SVG to be tested to the control coefficient during the low-voltage test obtained in step 1 K L and the high-voltage fault ride-through control coefficient during the online test K H At the same time, a linear interpolation model matching the synchronization control delay is established to synchronize the test device with the voltage of the grid-connected point of the SVG to be tested, and the test voltage output end of the test device is connected to the low-voltage side voltage acquisition end of the SVG to be tested.

[0183] Further, step 2 includes the following contents: The test device generally consists of an AD module, an FPGA processor (i.e., a second processor), a CPU processor (i.e., a first processor), and a DA module, wherein the AD module is used to collect the voltage and current signals of the high-voltage side and the low-voltage side of the grid-connected transformer; the FPGA processor is used to process the collection information of the AD module and control the output of the DA module; the CPU processor is mainly used to process the information received through the network, human-computer interaction, etc.; the DA module is used to output the digital signal provided by the FPGA processor after power amplification. The output test voltage of the test device is synchronized with the voltage of the SVG grid-connected point as follows: 1) Establish a linear interpolation model matching the synchronization control delay of the test device, and the expression is as follows: (8) In the above formula, , T test is the total time of the test, U a ( k +1) is the output voltage reference value of the test device at time k +1; N d is the interval value matching the control delay of the test device, N d is an integer, and the calculated value can be rounded; Ur the actual value of the output voltage of the testing device, e the error of the output voltage of the testing device, e max the maximum allowable error of the testing device, T d the control time delay of the matching testing device, T s the signal output period, U a k-N d the output voltage reference value at the moment of t+1, k-N d the output voltage actual value at the moment of t+1. Wherein, U r k-N d the output voltage actual value at the moment of t+1. Wherein, k-N d the output voltage actual value at the moment of t+1. Wherein, e max the calculation formula is as follows: (9) In the above formula, U pccN the quadratic voltage rated value of the SVG grid-connected point voltage; f 0 is the frequency, taking 50.

[0184] 2) Embedding the established linear interpolation model into the FPGA processor, and according to the AD module sampling data, quickly processing and calculating the output voltage reference value at the next moment U a k +1), and outputting after power amplification by the DA module; 3) The FPGA processor judges the synchronization state of the output voltage based on the error of the output voltage actual value and the output voltage reference value of the testing device e If the voltage error of the continuous 10 moments is less than e max , the state of completing the output voltage synchronization is displayed on the client interface of the testing device. At this time, the output test voltage of the testing device is connected to the low-voltage side voltage acquisition end of the SVG.

[0185] Step 3: The CPU processor receives the preset SVG high-low wearing online test signal sequence through the communication port, and adopts the segmented amplitude coefficient compensation strategy, sends the processed test signal sequence to the DA module through the FPGA processor, and outputs the final output voltage.

[0186] Further, step 3 includes the following contents: ​​​SVG high-low penetration online test signal sequence S ( k As shown below: (10) In the above formula, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point.

[0187] Considering that the port voltage of the SVG under test may deviate from the rated voltage value before online testing, the test voltage directly generated based on the test signal sequence may not reach the preset drop / rise amplitude, thus failing to meet the test requirements. Therefore, a segmented amplitude coefficient compensation strategy is adopted, with the following steps: First, the FPGA processor calculates the deviation coefficient based on the actual voltage acquired by the AD converter. K 1. The calculation formula is as follows: (11) In the above formula, U r This represents the actual output voltage value of the testing device. U pccN This is the rated secondary voltage of the SVG grid connection point voltage, that is, the rated voltage of the grid connection point voltage after being transformed by the voltage transformer, which is generally 100V.

[0188] Then, the FPGA processor will K 1. The signal is sent to the CPU processor. The CPU performs segmented amplitude coefficient compensation based on the received SVG high / low pass-through online test signal sequence: when the sequence state is "1", no intervention is made on the amplitude of the DA module output signal; when the sequence state is "...", no intervention is made on the amplitude of the DA module output signal. K u When this occurs, the amplitude of the output signal of the DA module is compensated, and the compensation coefficient is... K BC = K u / K 1.

[0189] Finally, the amplitude compensation coefficient is sent to the DA module via the FPGA processor. The DA module determines the final output voltage and outputs it to the test voltage output terminal to meet the set drop / rise amplitude requirements. This allows the test voltage output terminal to send the final output voltage to the SVG under test, enabling the SVG to utilize the final output voltage for reactive power support during fault ride-through. The formula for calculating the final output voltage includes:

[0190] In the above formula, U O( k ) is the final output voltage of the test device at the moment, k Ua ( k ) is the output voltage reference value of the test device at the moment. k

[0191] The application provides a static var compensator fault ride-through capability test device, method and system, which contains the selection of an online test working condition set, a fast synchronization control strategy of the test device and system and a segmented amplitude coefficient compensation strategy. (1) The working condition set of the SVG online test of the application is formulated in consideration of the maximum reactive power overload capability of the SVG and the safe boundary of the grid operation voltage, which effectively guarantees the safety of the SVG and the grid operation during the online test.

[0192] (2) The fast synchronization control strategy in the application realizes the fast synchronization of the test device output test voltage and the grid connection point voltage within 1ms, improves the synchronization efficiency of the two, and is superior to the synchronization time of the current similar device (the synchronization time of the current similar device is generally 10ms-60ms).

[0193] (3) The segmented amplitude coefficient compensation strategy in the application takes into account the offset of the port voltage of the SVG to be tested, so that the port voltage of the SVG to be tested can reach the set change amplitude under any condition, and the compliance of the test signal and the reliability of the test result are guaranteed.

[0194] In order to further verify the effectiveness of the application, an SVG configured in a certain light storage power station in Yunnan is selected for actual measurement verification, the grid connection point voltage of the SVG to be tested is 35kV, the rated reactive power is 30MVar, the maximum reactive power overload multiple is 1.2, and the rated phase voltage of the secondary side is 57.735V.

[0195] According to the above step 1, the reactive power / voltage control capability test of the SVG to be tested is first carried out, and the test waveform is as shown in Figure 4 and Figure 5 , in which U r is the actual output voltage value of the test device, Q r , Q s are the reactive power control response value and the true value of the SVG to be tested respectively.

[0196] Then, according to the test data, it is calculated that the grid connection point voltage of the SVG to be tested is 21.09kV when the maximum inductive reactive power of 30MVar is output, and the grid connection point voltage is 21.81kV when the maximum capacitive reactive power of-30MVar is output, and thus the standardized grid impedance can be calculated.​​X grid It is 0.018.

[0197] Finally, the actual maximum allowable reactive power during the online testing of the SVG under test can be calculated. Q m The per-unit value is 1.2. Local power grid management departments require that the SVG under test should reliably withstand voltage drops below 0.3 or rises below 1.2 at the grid connection point. Therefore, the low-voltage fault ride-through control coefficient of the SVG under test during online testing can be calculated. K L The high-voltage fault ride-through control factor during online testing is 2. K H The value is 12, thus completing the selection of the online test case set.

[0198] Based on step 2 above, a linear interpolation model matching the control delay of the test device is established, and the control delay of the device... T d The signal output period is 5ms. T s The time interval is 0.08ms, from which the matching interval can be calculated. N d The value is 62.5, which is rounded down to 63; simultaneously, the rated phase voltage on the secondary side of the SVG under test can be used to calculate the error criterion. e max The value is 1.43. After applying the fast synchronization strategy of this invention, the output voltage synchronization effect of the test device is as follows: Figure 6 As shown in the figure, Uain and Uaout are the measured voltage at the SVG grid connection point and the output test voltage, respectively, measured by the test device.

[0199] from Figure 6 As can be seen from the above, after adopting the fast synchronization control strategy of the present invention, when the voltage at the grid connection point of the SVG under test fluctuates, the test device can quickly synchronize and track it, with a synchronization time of less than 1ms.

[0200] Based on step 3 above, the fault ride-through test waveform of the SVG under test after piecewise amplitude coefficient compensation is as follows: Figure 7 As shown, Figure 7 In this context, Ut_pos represents the per-unit value of the test voltage, and Iq_pos and Iqs_pos represent the actual and theoretical values ​​of the reactive current, respectively. Figure 7 As can be seen from the data, initially, because the grid connection point of the SVG under test is higher than the rated value, the output test voltage of the test device is higher than the rated value; at the time of the fault, the set voltage drop factor... K With u=0.7, the actual output voltage drops to 0.7 as can be seen from the test waveform, thus achieving segmented amplitude coefficient compensation.

[0201] It is understood that the same or similar parts in the above embodiments can be referred to each other, and the contents not described in detail in some embodiments can be referred to the same or similar contents in other embodiments.

[0202] Example 5 like Figure 8 As shown, the present invention also provides an electronic device, which may be a computer device, a microcontroller device, a smart mobile device, etc. The electronic device in this embodiment may include a processor, a memory, a transceiver component, etc. The memory, processor, and transceiver component are connected via a bus; the memory can be used to store executable programs, and an exemplary executable program may include instructions; the processor is used to execute the instructions stored in the memory. The memory can also be used to store data, which can be accessed and / or modified when instructions are executed.

[0203] The processor may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. It is the computing and control core of the terminal, and it is suitable for implementing one or more instructions. Specifically, it is suitable for loading and executing one or more instructions in the storage medium to realize the corresponding method flow or corresponding function, so as to realize the steps of the online test method for the fault ride-through capability of a static var compensator in the above embodiment.

[0204] Example 6 Based on the same inventive concept, the application further provides a readable storage medium, specifically, an electronic device readable storage medium (Memory). The electronic device readable storage medium is a memory device in the electronic device, and is used for storing programs and data. It can be understood that the storage medium herein can include a built-in storage medium in the electronic device, and of course can also include an extended storage medium supported by the electronic device. The storage medium provides a storage space, and the storage space stores an operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by the processor are also stored in the storage space, and the instructions can be one or more execution programs (including program codes). It should be noted that the storage medium herein can be a high-speed RAM memory or a non-volatile memory, for example, at least one disk memory. The processor loads and executes one or more instructions stored in the storage medium, so as to realize the steps of the online test method for the fault ride-through capability of the static reactive power compensation device in the above embodiment.

[0205] Those skilled in the art should understand that the embodiments of the application can be provided as a method, a system, or a computer program product. Therefore, the application can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the application can take the form of a computer program product implemented on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage, etc.) containing computer-usable program code.

[0206] The application is described with reference to flowcharts and / or block diagrams of the method, device (system), and computer program product according to the embodiments of the application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, and the combination of the flows and / or blocks in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device that implements the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1 an apparatus that performs the functions specified in the flow(s) or block(s).

[0207] These computer program instructions can also be stored in a computer-readable memory capable of guiding the computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction apparatus, which implements the flowcharts and / or block diagrams. Figure 1 one or more flows and / or blocks Figure 1the function specified in the one or more blocks.

[0208] These computer program instructions can also be loaded into computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable data processing devices to generate computer-implemented processes, so that the instructions executed on the computer or other programmable devices provide processes for implementing the flow Figure 1 one or more flows and / or blocks Figure 1 the function specified in the one or more blocks.

[0209] Finally, it should be noted that: the above examples are only used to illustrate the technical solutions of the present application, but not to limit it, although the above embodiments of the present application have been described in detail, those skilled in the art should understand: the specific embodiments of the present application can be modified or replaced by the same, without departing from the spirit and scope of the present application, any modification or equivalent replacement, which should be covered within the scope of protection of the claims of the present application.

Claims

1. A fault ride-through capability testing device for a static var compensator (SVG), wherein the testing device is connected to the SVG under test, the SVG under test is connected to a control system, the control system is connected to a grid-connected transformer, and the grid-connected transformer is connected to both the power grid and the SVG under test, characterized in that, include: First processor, second processor, and first high-voltage side acquisition terminal; The first processor is connected to the control system and the second processor respectively, and is used to send the waveform recording command corresponding to each target reactive power command to the first high-voltage side acquisition terminal when it receives each target reactive power command issued by the control system. The first high-voltage side acquisition terminal is connected between the grid-connected transformer and the power grid. When the waveform recording command is received, it is used to acquire the target current data and target voltage data between the SVG under test and the grid-connected transformer, and send the target current data and target voltage data to the second processor. The second processor is connected to the first high-voltage side acquisition terminal and is used to determine the online test condition set using the target current data and target voltage data, so as to set the fault ride-through control coefficient of the SVG under test according to the online test condition set; It is also used to synchronize the grid connection point voltage of the test device and the SVG under test using a pre-established linear interpolation model; It is also used to determine the deviation coefficient by adopting a segmented amplitude coefficient compensation strategy, so as to determine the final output voltage based on the deviation coefficient, so that the SVG under test can use the final output voltage to provide reactive power support for fault ride-through.

2. The apparatus according to claim 1, characterized in that, Also includes: The first low-voltage side includes the acquisition terminal, AD module, DA module, and test voltage output terminal; The AD module is connected to the first high-voltage side acquisition terminal, the first low-voltage side acquisition terminal, and the second processor, respectively; the DA module is connected to the second processor and the test voltage output terminal, respectively.

3. The apparatus according to claim 2, characterized in that, The AD module is used for analog-to-digital conversion; The DA module is used to amplify the power of digital signals.

4. The apparatus according to claim 2, characterized in that, The first high-voltage side acquisition terminal is connected to the first current transformer via a first current clamp meter, and the first high-voltage side acquisition terminal is connected to the first voltage transformer; The first low-voltage side acquisition terminal is connected to the second current transformer via a second current clamp meter, and the first low-voltage side acquisition terminal is connected to the second voltage transformer; The first current transformer and the first voltage transformer are both installed on the primary electrical connection between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are both installed on the primary electrical connection between the grid-connected transformer and the SVG under test.

5. The apparatus according to claim 1, characterized in that, The static var compensator includes: a second high-voltage side acquisition terminal and a second low-voltage side acquisition terminal; The second high-voltage side acquisition terminal is connected to the first current transformer via the first current clamp meter, and the second high-voltage side acquisition terminal is connected to the first voltage transformer; The second low-voltage side acquisition terminal is connected to the second current transformer via a second current clamp meter, and the second low-voltage side acquisition terminal is connected to the second voltage transformer; The first current transformer and the first voltage transformer are both installed on the primary electrical connection between the grid-connected transformer and the power grid, and the second current transformer and the second voltage transformer are both installed on the primary electrical connection between the grid-connected transformer and the SVG under test.

6. The apparatus according to claim 1, characterized in that, The target reactive power commands include: capacitive maximum reactive power command, inductive maximum reactive power command, and initial reactive power command; The order in which the target reactive power commands are issued is as follows: capacitive maximum reactive power command, inductive maximum reactive power command, and initial reactive power command.

7. The apparatus according to claim 6, characterized in that, The control system is used to send each target reactive power instruction to the SVG under test and the first processor respectively according to the order of issuance of each target reactive power instruction, and the time interval between issuance of each target reactive power instruction is a preset time interval. The SVG under test is used to send reactive power corresponding to each target reactive power command to the power grid when it receives each target reactive power command, and the duration of sending reactive power is a preset time interval.

8. The apparatus according to claim 6, characterized in that, The first high-voltage side acquisition terminal is specifically used for: Upon receiving the waveform recording command corresponding to each target reactive power command, the current and voltage data between the SVG under test and the grid-connected transformer are recorded. The current and voltage data within a preset time window of the maintenance time corresponding to each target reactive power command are selected as the target current data and target voltage data, and the target current data and target voltage data are sent to the second processor.

9. The apparatus according to claim 1, characterized in that, The second processor includes: The first calculation unit is used to calculate the effective voltage value and the actual output reactive power using the target current data and target voltage data. The second calculation unit is used to calculate the grid reactance of the SVG under test using the effective voltage value and the actual output reactive power; The third calculation unit is used to calculate the online test condition set using the grid reactance of the SVG under test and the preset safe operating boundary; The effective voltage value includes: the effective voltage value per unit calculated by the maximum inductive reactive power test and the effective voltage value per unit calculated by the maximum capacitive reactive power test; the actual output reactive power includes: the actual output reactive power per unit calculated by the maximum inductive reactive power test and the actual output reactive power per unit calculated by the maximum capacitive reactive power test. The preset safe operating boundaries include: the deviation of the grid connection point voltage, the action threshold for the SVG under test to enter low voltage ride-through, and the action threshold for the SVG under test to enter high voltage ride-through.

10. The apparatus according to claim 9, characterized in that, The third computing unit includes: The first calculation module is used to calculate the actual maximum allowable value of reactive power during online testing by using the grid reactance of the SVG under test and the preset safe operation boundary. The second calculation module is used to calculate the low-voltage fault ride-through control coefficient and the high-voltage fault ride-through control coefficient during the online test using the actual maximum allowable value of reactive power during the online test. The low-voltage fault ride-through control coefficient and the high-voltage fault ride-through control coefficient during the online test are the online test condition set.

11. The apparatus according to claim 10, characterized in that, The first calculation module is specifically used for: Using the grid reactance of the SVG under test and the preset safe operating boundary, the theoretical maximum allowable value of reactive power during online testing is calculated; Using the theoretical maximum allowable value of reactive power during the online test, the actual maximum allowable value of reactive power during the online test is calculated.

12. The apparatus according to claim 2, characterized in that, The first processor further includes: The control unit is used to control the first high-voltage side acquisition terminal or the first low-voltage side acquisition terminal to acquire the actual value of the output voltage of the test device according to the test requirements after setting the fault ride-through control coefficient of the SVG under test, and send the actual value of the output voltage of the test device to the second processor.

13. The apparatus according to claim 12, characterized in that, The second processor further includes: The fourth calculation unit is used to calculate and generate the reference value of the output voltage of the test device at the next moment based on the actual value of the output voltage of the test device after setting the fault ride-through control coefficient of the SVG under test and using a pre-established linear interpolation model. The voltage synchronization unit is used to send the output voltage reference value of the test device at the next moment to the DA module for power amplification when the output voltage error of the test device is less than or equal to the maximum permissible error of the test device for a consecutive preset number of time moments, so as to obtain the output test voltage of the test device. The DA module then sends the output test voltage to the test voltage output terminal, and the test voltage output terminal connects the output test voltage to the low-voltage side voltage acquisition terminal of the SVG to synchronize the grid connection point voltage of the test device and the SVG under test.

14. The apparatus according to claim 13, characterized in that, The second processor further includes: The fifth calculation unit is used to calculate the deviation coefficient using the actual output voltage value of the test device; The compensation unit is used to determine, after voltage synchronization is completed, whether to compensate the output signal amplitude of the DA module by using the current state of the preset SVG high-low passthrough online test signal sequence sent by the first processor. If no compensation is needed, the current state of the SVG high-low passthrough online test signal sequence is sent to the DA module so that the DA module can determine the final output voltage based on the current state. If compensation is needed, a compensation coefficient is calculated using the deviation coefficient, and the compensation coefficient and the current state are sent to the DA module so that the DA module can determine the final output voltage based on the compensation coefficient and the current state.

15. The apparatus according to claim 14, characterized in that, The compensation unit is specifically used for: When the current state of the SVG high-low penetration online test signal sequence is 1, no compensation is needed for the output signal amplitude of the DA module; when the current state of the SVG high-low penetration online test signal sequence is... K u At this time, it is necessary to compensate for the amplitude of the output signal of the DA module.

16. The apparatus according to claim 14, characterized in that, The DA module is also used for: The final output voltage is sent to the test voltage output terminal, so that the test voltage output terminal sends the final output voltage to the SVG under test, thereby enabling the SVG under test to use the final output voltage for reactive power support during fault ride-through.

17. The apparatus according to claim 9, characterized in that, The formula for calculating the grid reactance of the SVG under test includes: In the above formula, X grid The grid reactance of the SVG to be tested. V 1 represents the per-unit effective voltage value calculated from the maximum inductive reactive power test. V 2 represents the per-unit effective voltage value calculated from the maximum capacitive reactive power test. Q 1 represents the actual per-unit output reactive power calculated from the maximum inductive reactive power test. Q 2 represents the actual per-unit output reactive power calculated from the maximum capacitive reactive power test.

18. The apparatus according to claim 11, characterized in that, The formula for calculating the theoretical maximum allowable value of reactive power during online testing includes: The formula for calculating the actual maximum allowable value of reactive power during online testing includes: In the above formula, Q Em This represents the theoretical maximum permissible value of reactive power during online testing. X grid The grid reactance of the SVG to be tested. K B For the deviation of the grid connection point voltage, Q m This represents the actual maximum permissible value of reactive power during online testing. K The maximum reactive power overload multiple of the SVG under test. Q N This represents the rated power of the SVG under test.

19. The apparatus according to claim 10, characterized in that, The formula for calculating the low-voltage fault ride-through control coefficient during the online test includes: The formula for calculating the high-voltage fault ride-through control coefficient during the online test includes: In the above formula, K L This refers to the low-voltage fault ride-through control factor during online testing. U L The voltage value after the voltage drop at the grid connection point. Q m This represents the actual maximum permissible value of reactive power during online testing. ω 1 represents the threshold value for the under-voltage ride-through of the SVG under test. ω 2 represents the action threshold for the SVG under test to enter high-voltage ride-through. K H This refers to the high-voltage fault ride-through control factor during online testing. U H This is the voltage value after the voltage drop at the grid connection point.

20. The apparatus according to claim 13, characterized in that, The calculation formula of the linear interpolation model includes: In the above formula, , T test To test the total time, U a ( k +1) is the test device in k The output voltage reference value at time +1 N d To match the control delay interval value of the test device, U r This represents the actual output voltage value of the testing device. e To test the output voltage error of the device, e max This represents the maximum permissible error of the testing device.

21. The apparatus according to claim 20, characterized in that, The formula for calculating the control delay interval of the matching test device includes: The formula for calculating the output voltage error of the testing device includes: The formula for calculating the maximum permissible error of the testing device includes: In the above formula, , T test To test the total time, T d To match the control delay of the test equipment, T s For signal output period, U a ( kN d +1) is ( kN d The output voltage reference value at time +1) U r ( kN d +1) is ( kN d Measured output voltage at time +1) U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage. f 0 represents frequency.

22. The apparatus according to claim 14, characterized in that, The formula for calculating the deviation coefficient includes: In the above formula, K 1 is the deviation coefficient. U r This represents the actual output voltage value of the testing device. U pccN This refers to the rated secondary voltage of the SVG grid connection point voltage.

23. The apparatus according to claim 14, characterized in that, The SVG high-low penetration online test signal sequence is as follows: In the above formula, , T test To test the total time, S ( k )for k SVG high-low crossover online test signal sequence, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point.

24. The apparatus according to claim 14, characterized in that, The formula for calculating the compensation coefficient includes: K BC = K u / K 1 In the above formula, K BC For compensation coefficient, K u The drop / surge of the final output voltage relative to the secondary voltage rating of the SVG grid connection point. K 1 represents the deviation coefficient.

25. The apparatus according to claim 14, characterized in that, The formula for calculating the final output voltage includes: In the above formula, U O ( k )for k The final output voltage at time [time]. Ua ( k ) for the test device in k The output voltage reference value at that moment. S ( k )for k SVG high-low crossover online test signal sequence, K BC This is the compensation coefficient.

26. An online testing method for the fault ride-through capability of a static var compensator, applicable to the fault ride-through capability testing device for a static var compensator as described in any one of claims 1-25, characterized in that, include: When the first processor receives the target reactive power commands issued by the control system, it sends the waveform recording command corresponding to each target reactive power command to the first high-voltage side acquisition terminal. When the first high-voltage side acquisition terminal receives the waveform recording command, it uses the first high-voltage side acquisition terminal to acquire the target current data and target voltage data between the SVG under test and the grid-connected transformer, and sends the target current data and target voltage data to the second processor; The second processor determines the online test condition set based on the target current data and target voltage data, and sets the fault ride-through control coefficient of the SVG under test according to the online test condition set; After setting the fault ride-through control coefficient of the SVG under test, the second processor uses a pre-established linear interpolation model to synchronize the grid connection point voltage of the test device and the SVG under test. After voltage synchronization is completed, the second processor uses a segmented amplitude coefficient compensation strategy to determine the deviation coefficient, and determines the final output voltage based on the deviation coefficient, so that the SVG under test can use the final output voltage to provide reactive power support for fault ride-through.

27. An online testing system for the fault ride-through capability of a static var compensator, characterized in that, include: Control system, SVG under test and fault ride-through capability testing device for SVG as described in any one of claims 1-25; The control system is connected to the test device and the SVG under test respectively, and the SVG under test, the grid-connected transformer and the power grid are connected in sequence; the control system is used to send target reactive power commands to the SVG under test and the first processor in the test device respectively; The SVG under test is used to send reactive power corresponding to the target reactive power command to the power grid when it receives the target reactive power command, and the duration of sending reactive power is a preset time interval. The first processor in the testing device is used to send the waveform recording command corresponding to each target reactive power command to the first high-voltage side acquisition terminal in the testing device when it receives each target reactive power command issued by the control system. The first high-voltage side acquisition terminal in the test device is used to acquire the target current data and target voltage data between the SVG under test and the grid-connected transformer when the waveform recording command is received, and send the target current data and target voltage data to the second processor in the test device; The second processor in the testing device is used to determine an online test condition set using the target current data and target voltage data, so as to set the fault ride-through control coefficient of the SVG under test according to the online test condition set. And the grid connection point voltage of the test device and the SVG under test is synchronized using a pre-established linear interpolation model; And a segmented amplitude coefficient compensation strategy is adopted to determine the deviation coefficient, so as to determine the final output voltage based on the deviation coefficient, so that the SVG under test can use the final output voltage to support reactive power during fault ride-through.

28. An electronic device, characterized in that, include: At least one processor and memory; The memory and processor are connected via a bus; The memory is used to store one or more programs; When the one or more programs are executed by the at least one processor, the online test method for fault ride-through capability of the static var compensator as described in claim 26 is implemented.

29. A readable storage medium, characterized in that, It contains an execution program, which, when executed, implements the online test method for the fault ride-through capability of the static var compensator as described in claim 26.

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