Method, device and equipment for acquiring logs of heterogeneous multi-core processor

Abstract

The invention discloses a heterogeneous multi-core processor log acquisition method, device and equipment. Comprising the following steps: screening a DSP main core processor from a plurality of DSPs, and setting a ping-pong cache on the DSP main core processor; the logs generated by each DSP processor are stored in a ping-pong cache, and the logs in the ping-pong cache are sent to an ARM processor through a main core; and uniformly outputting the logs received by the ARM processor and the logs generated by the ARM processor according to a pre-configured log output mode. The DSP main core processor collects logs generated by the DSPs based on a ping-pong cache mode, resource competition and interference caused by multiple cores are avoided, the DSP main core processor uniformly outputs the obtained logs of all the processors in a pre-configured log output mode, and therefore the logs from heterogeneous processing are uniformly processed, and the processing efficiency is improved. Unified and standardized processing of the logs of the heterogeneous multi-core processor is realized under the condition of saving resource overhead.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of communication technology, in particular to a heterogeneous multi-core processor log acquisition method, device and equipment. BACKGROUND

[0002] In the design of communication baseband chips, a heterogeneous multi-core architecture is basically adopted. Although these co-processors can have independent debug ports for daily development and debugging, the co-processors do not have the ability to access non-volatile memory.

[0003] In the current heterogeneous multi-core system, not only multiple processors are included, but also processors with different structures are included. Due to the heterogeneity, the format, interface and time of each processor are different when the log is acquired, thereby causing the logs to be not unified. Due to the multi-core, the processors compete for bandwidth and other resources when acquiring the log, thereby causing the performance and real-time interference. Therefore, it is very challenging to implement efficient, low-overhead, low-interference, time-accurate and easy-to-analyze log recording on the heterogeneous multi-core system, and often a difficult trade-off needs to be made between log detail level, system performance overhead, development and debugging convenience and implementation complexity. SUMMARY

[0004] The present application provides a heterogeneous multi-core processor log acquisition method, device and equipment to realize efficient, low-interference acquisition of format-unified logs.

[0005] According to an aspect of the present application, a heterogeneous multi-core processor log acquisition method is provided, comprising: saving the logs generated by each processor in a heterogeneous multi-core system to a storage medium of the processor, wherein the processor includes an advanced reduced instruction set machine (ARM) processor and multiple digital signal (DSP) processors, and the structures of the ARM processor and the DSP processors are different;

[0006] selecting a DSP master core processor from the multiple DSP processors, and setting a ping-pong buffer on the DSP master core processor;

[0007] storing the logs generated by each DSP processor into the ping-pong buffer, and sending the logs in the ping-pong buffer to the ARM processor through the master core;

[0008] unifying the logs received by the ARM processor and the logs generated by the ARM processor itself according to a pre-configured log output mode.

[0009] According to another aspect of the present application, there is provided an apparatus for acquiring logs of a heterogeneous multi-core processor, comprising: a log generation module configured to store logs generated by each processor in a heterogeneous multi-core system in a storage medium of the processor, wherein the processors comprise an advanced reduced instruction set computer (ARM) processor and a plurality of digital signal (DSP) processors, and the ARM processor and the DSP processors are not of the same structure;

[0010] a DSP master core processor screening module configured to screen a DSP master core processor from the plurality of DSP processors, and set a ping-pong buffer on the DSP master core processor;

[0011] a log ping-pong buffer module configured to store logs generated by each of the DSP processors in the ping-pong buffer, and send the logs in the ping-pong buffer to the ARM processor through the master core;

[0012] a log output module configured to output the logs received by the ARM processor and the logs generated by the ARM processor itself according to a pre-configured log output mode.

[0013] According to another aspect of the present application, there is provided a computer device, comprising:

[0014] at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the method according to any one of the embodiments of the present application.

[0015] According to another aspect of the present application, there is provided a computer readable storage medium storing computer instructions for enabling a processor to perform the method according to any one of the embodiments of the present application.

[0016] The technical solution of the embodiments of the present application determines a DSP master core processor from a plurality of DSP processors, and collects logs generated by each DSP processor based on a ping-pong buffer mode through the DSP master core processor, thereby avoiding resource competition and interference caused by multi-cores, and the DSP master core processor outputs the logs of all processors acquired by the DSP master core processor in a pre-configured log output mode, thereby uniformly processing logs from heterogeneous processing, to realize unified and standardized processing of logs of a heterogeneous multi-core processor while saving resource overhead.

[0017] It is to be understood that the details set forth herein do not limit the scope of the embodiments of the application to the specific embodiments described. Rather, the scope of the embodiments of the application is to be defined by the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments description. Obviously, the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can also be obtained without creative labor based on these drawings.

[0019] Figure 1 is a flow chart of a heterogeneous multi-core processor log acquisition method according to the first embodiment of the present application;

[0020] Figure 2 is a structural schematic diagram of a heterogeneous multi-core system according to the first embodiment of the present application;

[0021] Figure 3 is a flow chart of a heterogeneous multi-core processor log acquisition method according to the first embodiment of the present application;

[0022] Figure 4 is a structural schematic diagram of a heterogeneous multi-core processor log acquisition device according to the third embodiment of the present application;

[0023] Figure 5 is a structural schematic diagram of an electronic device according to the fourth embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the technical personnel in the art better understand the present application scheme, the following will combine the drawings in the embodiments of the present application, and the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only some embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor should belong to the scope of protection of the present application.

[0025] It is to be understood that the terms "first", "second", and the like used in the description and the claims of the present application as well as the above-described drawings are used to distinguish similar objects, and are not necessarily used to describe a particular sequential or chronological order. It should be understood that the data thus used can be interchanged, where appropriate, so that the embodiments of the present application described herein can be carried out in other than the order shown or described herein. Furthermore, "comprise" and "have" and any variations thereof are intended to cover a non-exclusive inclusion, for example, a process, method, article, or apparatus that comprises a list of steps or units is not necessarily limited to those steps or units that are clearly listed, but can include other steps or units that are not clearly listed or inherent to such processes, methods, articles, or apparatus.

[0026] Embodiment one

[0027] Figure 1 A flowchart of a matrix calculation method in communication interference suppression combination is provided for the first embodiment of the present application. The present embodiment can be applied to the case of calculating the matrix in communication interference suppression combination. The method can be executed by a matrix calculation device in communication interference suppression combination, which can be realized in the form of hardware and / or software. As shown in Figure 1 , the method comprises:

[0028] In step S101, the logs generated by each processor in the heterogeneous multi-core system are saved in the storage medium of the processor.

[0029] As shown in Figure 2 , the structure of the heterogeneous multi-core system is shown in the figure. The heterogeneous multi-core system includes an ARM (Advanced RISC Machine) processor and a plurality of DSP (digital signal processor) processors. The structures of the ARM processor and the DSP processor are different. Of course, the present embodiment is only an example and does not limit the number of processors included in the heterogeneous multi-core system. As long as there are processors with different structures and the number of processors included is more than one, it is within the protection scope of the present application.

[0030] In the running process of each processor, a large number of logs are generated, and the generated logs are saved in the storage medium of the processor. The storage medium is located in Figure 2The storage medium in the shown log module can be fixed double data rate (DDR) memory or smart media (SM) card, and the specific type of the storage medium is not limited in the embodiment. Each processor stores the log independently and does not affect each other.

[0031] In step S102, one DSP main core processor is selected from the plurality of DSP processors, and a ping-pong cache is set on the DSP main core processor.

[0032] Optionally, the selection of the DSP main core processor from the plurality of DSP processors includes: obtaining the service processing amount of each DSP processor, taking the DSP processor with the smallest service processing amount as the DSP main core processor, and taking the DSP processors except the DSP main core processor as slave core processors. The ping-pong cache on the DSP main core processor includes two cache areas.

[0033] Specifically, one DSP main core processor is selected from the plurality of DSP processors in the embodiment, and the remaining DSP processors are taken as slave core processors, and the selected DSP main core processor is used to collect the logs of the other slave core processors. When the selection is performed, the selection can be performed according to the size of the service processing amount. Since the smaller the service processing amount is, the more idle the processor is, the DSP processor with the smallest service processing amount can be taken as the DSP main core processor, that is, the most idle DSP processor is selected from the plurality of processors as the DSP main core processor, so that the influence on the other services being executed can be minimized when the log collection is performed. In addition, after the DSP main core processor is determined, a ping-pong cache is set on the DSP main core processor in the embodiment, and the ping-pong cache mainly includes two cache areas, pingpang0 and pingpang1. The DSP main core processor uses the two cache areas to ping-pong store the logs generated by the slave core processors and itself.

[0034] In step S103, the logs generated by each DSP processor are respectively stored in the ping-pong cache, and the logs in the ping-pong cache are sent to the ARM processor through the main core.

[0035] Optionally, the logs generated by each DSP processor are respectively stored in the ping-pong cache, including: a sub-queue is created for each DSP processor, and the logs saved in the storage medium of each DSP processor are respectively transmitted into the corresponding sub-queue; the DSP main core processor traverses each sub-queue, and stores the read logs in the ping-pong cache.

[0036] Optionally, the read logs are stored in a ping-pong cache, including: determining the target cache area based on the current free state of each cache area in the ping-pong cache; and storing the currently read logs in the target cache area of ​​the ping-pong cache, wherein the target cache areas determined at adjacent times are different.

[0037] Specifically, in this embodiment, when the DSP main core processor collects logs, in order to avoid resource contention among multiple core processors, a sub-queue is created for each DSP processor. For example, the sub-queue created for slave core processor DSP0 is sub-queue 0, the sub-queue created for slave core processor DSP1 is sub-queue 1, and so on, and the sub-queue created for slave core processor DSPn is sub-queue n. In this embodiment, a sub-queue x is also created for the DSP main core processor x itself. The sub-queue can be a hardware queue or a software queue.

[0038] Software queues and hardware queues are two different implementations of task scheduling in computer systems, differing significantly in application scenarios, performance, and flexibility. Software queues are implemented by the operating system or application programs through code, using data structures such as linked lists and arrays, and rely on the CPU to execute scheduling logic. Hardware queues are directly managed by dedicated hardware, such as controllers or network interface cards, implemented through registers or on-chip caches, without CPU intervention. This embodiment is merely illustrative and does not limit the type of sub-queue. Once the sub-queues corresponding to each DSP processor are created, each DSP processor will transfer the logs saved in its own storage medium to the corresponding sub-queue. For example, logs saved from the core processor DSP1 to its own log module will be transferred to sub-queue 1, logs saved from the core processor DSP2 to its own log module will be transferred to sub-queue 2, and so on. For the DSP main core processor DSPx, logs saved in its own log module will be transferred to sub-queue x. The DSP main core processor will periodically traverse each sub-queue and store the logs in the traversed sub-queues into a judgment cache.

[0039] It's worth noting that after the DSP main core processor reads logs from the subqueue, since the ping-pong cache contains two buffers, pingpang0 and pingpang1, the DSP main core processor determines a target buffer based on the current free state of each buffer in the ping-pong cache and saves the currently read logs to the target buffer. For example, if the DSP main core processor previously traversed subqueue 0 and saved the logs generated by slave processor DSP0 in subqueue 0 to pingpang0, and at the current moment the DSP main core processor is traversing subqueue 1, since the logs in pingpang0 have not yet been fully transmitted to the ARM processor, to prevent the logs currently read in subqueue 1 from overwriting the untransmitted logs in pingpang0, the DSP main core processor will save the newly read logs in subqueue 1 to pingpang1. This avoids log loss caused by competition for cache resources between different slave processors. Of course, this embodiment only uses the example of saving the logs in sub-queue 1 in the ping-pong cache, and does not limit the target cache area corresponding to the logs read in each sub-queue. As long as the logs generated by each DSP processor can be collected while avoiding the loss of logs due to competition for cache resources, it is within the protection scope of this application.

[0040] Optionally, the main core sends the logs located in the ping-pong buffer to the ARM processor, including: creating a main queue for the ARM processor; the DSP main core processor passing the logs located in the ping-pong buffer to the main queue via an interrupt; and sending the logs to the ARM processor through the main queue, wherein the main queue includes a hardware queue or a software queue.

[0041] Specifically, this embodiment also creates a main queue for the ARM processor. This main queue can be a hardware queue or a software queue, and its type can be the same as or different from the sub-queues. This embodiment does not limit the specific type of the main queue. Furthermore, while the DSP main core processor collects logs from each DSP processor through the ping-pong buffer, it also passes the logs in the ping-pong buffer to the main queue. The main queue then sends the logs collected by the DSP main core processor to the ARM processor. Specifically, the DSP main core processor passes the logs from the ping-pong buffer to the main queue using an interrupt mechanism and saves the logs generated by the DSP processors to the ARM log module. Simultaneously, the logs generated by the ARM processor itself are also saved to the log module. Therefore, the ARM processor's log module contains both its own logs and logs collected from all DSP processors by the DSP main core processor.

[0042] Step S104: Output the logs received by the ARM processor and the logs generated by the ARM processor itself in a unified manner according to the pre-configured log output method.

[0043] Optionally, the logs received by the ARM processor and the logs generated by the ARM processor itself are output uniformly according to a pre-configured log output method, including: the ARM processor creates a log processing task through a log processing function; the log processing task parses the received logs and the logs generated by the ARM processor itself to obtain the log parsing results; the pre-configured log output method is determined, and the log parsing results are output uniformly according to the log output method, wherein the log output method includes network port output and file write output.

[0044] Specifically, in this embodiment, since the ARM processor and DSP processor are heterogeneous processors, the structures of the generated logs also differ. Direct output would increase the complexity of subsequent log analysis due to the inconsistency of logs. Therefore, in this embodiment, the ARM processor creates a log processor task through a log processor function. This log processing task is used to parse all received logs to obtain log parsing results with a unified format, thereby achieving standardized log processing. Furthermore, this embodiment pre-configures the log output method, such as network port output and file output. Of course, this embodiment is only an example and does not limit the log output method. The final log format obtained will differ depending on the log output method. For example, when the log output method is determined to be file output, the log parsing result is output in file format; when the log output method is determined to be network port output, the log parsing result is output in network port log format. Regardless of the log output method used, as long as the logs generated by the ARM processor and the DSP processor are output uniformly in the same way, ensuring the consistency of the final output format of logs with different formats, it is within the scope of protection of this application.

[0045] This implementation identifies a DSP master core processor from multiple DSP processors and collects logs generated by each DSP processor using a ping-pong cache method. This avoids resource contention and interference caused by multiple cores. The DSP master core processor outputs all the logs from the processors using a pre-configured log output method, thereby uniformly processing logs from heterogeneous processors. This achieves unified and standardized processing of logs from heterogeneous multi-core processors while saving resource overhead.

[0046] Example 2

[0047] Figure 3 This is a flowchart of a method for obtaining logs from a heterogeneous multi-core processor according to Embodiment 2 of the present invention. Based on the above embodiments, after uniformly outputting logs according to a pre-configured log output method, it further includes: detecting the format of the output logs; and generating a log detection report based on the log detection results. Figure 2 As shown, the method includes:

[0048] Step S201: Save the logs generated by each processor in the heterogeneous multi-core system to its own storage medium.

[0049] Step S202: Select a DSP main core processor from multiple DSP processors and set a ping-pong cache on the DSP main core processor.

[0050] Optionally, a DSP master core processor is selected from multiple DSP processors, including: obtaining the service processing volume of each DSP processor, selecting the DSP processor with the smallest service processing volume as the DSP master core processor, and selecting the DSP processors excluding the DSP master core processor as slave core processors, wherein the ping-pong cache of the DSP master core processor includes two cache areas.

[0051] Step S203: The logs generated by each DSP processor are stored in the ping-pong cache, and the logs in the ping-pong cache are sent to the ARM processor through the main core.

[0052] Optionally, the logs generated by each DSP processor are stored in a ping-pong cache, including: creating a sub-queue for each DSP processor, with each DSP processor transferring the logs saved in its own storage medium to the corresponding sub-queue; and the DSP main core processor traversing each sub-queue and storing the read logs in the ping-pong cache.

[0053] Optionally, the read logs are stored in a ping-pong cache, including: determining the target cache area based on the current free state of each cache area in the ping-pong cache; and storing the currently read logs in the target cache area of ​​the ping-pong cache, wherein the target cache areas determined at adjacent times are different.

[0054] Optionally, the main core sends the logs located in the ping-pong buffer to the ARM processor, including: creating a main queue for the ARM processor; the DSP main core processor passing the logs located in the ping-pong buffer to the main queue via an interrupt; and sending the logs to the ARM processor through the main queue, wherein the main queue includes a hardware queue or a software queue.

[0055] Step S204: Output the logs received by the ARM processor and the logs generated by the ARM processor itself in a unified manner according to the pre-configured log output method.

[0056] Optionally, the logs received by the ARM processor and the logs generated by the ARM processor itself are output uniformly according to a pre-configured log output method, including: the ARM processor creates a log processing task through a log processing function; the log processing task parses the received logs and the logs generated by the ARM processor itself to obtain the log parsing results; the pre-configured log output method is determined, and the log parsing results are output uniformly according to the log output method, wherein the log output method includes network port output and file write output.

[0057] Step S205: Detect the format of the output logs and generate a log detection report based on the log detection results.

[0058] Specifically, in this embodiment, after obtaining the logs output by the ARM processor, the format of the output logs is checked. Specifically, the system checks for any format inconsistencies in the output logs and generates a log detection report based on the detection results. The log detection report includes the log detection time and the detection result, such as success or failure. A detection failure indicates that there are format inconsistencies in the output logs, while a detection success indicates that there are no format inconsistencies in the output logs. Furthermore, if the detection result is failure, it also lists logs with formats inconsistent with other logs and displays the log detection report on the user interface.

[0059] It should be noted that when the log detection report indicates a failure, an alarm command will be generated simultaneously with the log detection report to prompt maintenance personnel to promptly inspect the software or hardware devices, determine the cause of the log output error, and perform timely repairs, thereby improving the efficiency and accuracy of log acquisition. Furthermore, the alarm command can be displayed in the form of voice or image; this embodiment does not limit the specific display format of the alarm command, as long as it serves as a prompt to the user, it falls within the scope of protection of this application.

[0060] This implementation identifies a DSP master core processor from multiple DSP processors and collects logs generated by each DSP processor using a ping-pong cache method. This avoids resource contention and interference caused by multiple cores. The DSP master core processor outputs all the logs from the processors using a pre-configured log output method, thereby uniformly processing logs from heterogeneous processors. This achieves unified and standardized processing of logs from heterogeneous multi-core processors while saving resource overhead.

[0061] Example 3

[0062] Figure 4 This is a schematic diagram of a device for acquiring logs of a heterogeneous multi-core processor, provided in Embodiment 3 of the present invention. Figure 4 As shown, the device includes: a log generation module 310, a DSP main core processor filtering module 320, a log ping-pong cache module 330, and a log output module 340.

[0063] The log generation module 310 is used to save the logs generated by each processor in the heterogeneous multi-core system to its own storage medium. The processor includes an Advanced Reduced Instruction Set Machine (ARM) processor and multiple Digital Signal Processors (DSPs), and the ARM processor and DSP processors have different structures.

[0064] The DSP main core processor filtering module 320 is used to filter out a DSP main core processor from multiple DSP processors and set a ping-pong cache on the DSP main core processor;

[0065] The log ping-pong cache module 330 is used to store the logs generated by each DSP processor into the ping-pong cache, and send the logs in the ping-pong cache to the ARM processor through the main core;

[0066] The log output module 340 is used to output the logs received by the ARM processor and the logs generated by the ARM processor itself in a unified manner according to the pre-configured log output method.

[0067] Optionally, a DSP main core processor filtering module is used to obtain the workload of each DSP processor and select the DSP processor with the lowest workload as the DSP main core processor.

[0068] The DSP processor, excluding the DSP master core processor, is used as the slave core processor. The ping-pong cache of the DSP master core processor includes two cache areas.

[0069] Optionally, the log ping-pong caching module includes a ping-pong caching unit, which is used to create a sub-queue for each DSP processor, and each DSP processor will pass the logs saved in its own storage medium to the corresponding sub-queue;

[0070] The DSP main core processor traverses each sub-queue and stores the read logs in the ping-pong buffer.

[0071] Optionally, the ping-pong cache unit is also used to determine the target cache area based on the current free state of each cache area in the ping-pong cache;

[0072] The currently read log is stored in the target cache area of ​​the ping-pong cache, where the target cache areas determined at adjacent times are different.

[0073] Optionally, the log ping-pong buffer module includes a log sending unit, which is used to create a main queue for the ARM processor. The DSP main core processor transmits the logs located in the ping-pong buffer to the main queue via interrupt.

[0074] Logs are sent to the ARM processor via a main queue, which can be either a hardware queue or a software queue.

[0075] Optional, a log output module, used by the ARM processor to create log processing tasks via log processing functions;

[0076] The log processing task parses the received logs and the logs generated by the ARM processor itself to obtain the log parsing results.

[0077] Determine the pre-configured log output method and output the log parsing results uniformly according to the log output method. The log output method includes network port output and file write output.

[0078] Optionally, the device also includes a log detection module for detecting the format of the output logs;

[0079] A log detection report is generated based on the log detection results.

[0080] The heterogeneous multi-core processor log acquisition device provided in this embodiment of the invention can execute the heterogeneous multi-core processor log acquisition method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0081] Example 4

[0082] Figure 4A schematic diagram of an electronic device 10, which can be used to implement embodiments of the present invention, is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0083] The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the invention described and / or claimed herein.

[0084] like Figure 4 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded from storage unit 18 into the RAM 13. The RAM 13 may also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0085] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0086] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as the method for obtaining logs from a heterogeneous multi-core processor.

[0087] In some embodiments, the method for acquiring heterogeneous multi-core processor logs may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the method for acquiring heterogeneous multi-core processor logs described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the method for acquiring heterogeneous multi-core processor logs by any other suitable means (e.g., by means of firmware).

[0088] Various embodiments of the apparatuses and techniques described above herein can be implemented in digital electronic circuit devices, integrated circuit devices, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), device-on-a-chip (SoC) devices, complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable device including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage device, at least one input device, and at least one output device, and transmitting data and instructions to the storage device, the at least one input device, and the at least one output device.

[0089] Computer programs used to implement the methods of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable overhead crane operation alarm device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer programs can be executed entirely on the machine, partially on the machine, as a standalone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0090] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution means, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor devices, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0091] To provide interaction with a user, the apparatus and techniques described herein can be implemented on a device having: a display device (e.g., a touchscreen) for displaying information to the user; and buttons through which the user can provide input to the device. Other types of apparatus can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or haptic feedback); and input from the user can be received in any form (including voice input, speech input, or haptic input).

[0092] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0093] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method for obtaining logs of a heterogeneous multi-core processor, characterized in that, include: Logs generated by each processor in the heterogeneous multi-core system are saved to their own storage media. The processor includes an Advanced Reduced Instruction Set Machine (ARM) processor and multiple Digital Signal Processors (DSPs), and the ARM processor and the DSP processors have different architectures. Select a DSP main core processor from the plurality of DSP processors, and set a ping-pong cache on the DSP main core processor; The logs generated by each of the DSP processors are stored in the ping-pong cache, and the logs in the ping-pong cache are sent to the ARM processor through the main core; The logs received by the ARM processor and the logs generated by the ARM processor itself are output uniformly according to the pre-configured log output method.

2. The method according to claim 1, characterized in that, The step of selecting a DSP main core processor from the plurality of DSP processors includes: The service processing volume of each DSP processor is obtained, and the DSP processor with the smallest service processing volume is selected as the DSP main core processor. The DSP processor, excluding the DSP main core processor, is used as a slave core processor, wherein the ping-pong cache located in the DSP main core processor includes two cache areas.

3. The method according to claim 1, characterized in that, The step of storing the logs generated by each of the DSP processors into the ping-pong cache includes: A sub-queue is created for each of the DSP processors, and each DSP processor transfers the logs saved in its own storage medium to the corresponding sub-queue. The DSP main core processor traverses each of the sub-queues and stores the read logs into the ping-pong cache.

4. The method according to claim 3, characterized in that, The step of storing the read logs into the ping-pong cache includes: The target cache area is determined based on the current free state of each cache area in the ping-pong cache. The currently read log is stored in the target cache area of ​​the ping-pong cache, wherein the target cache area determined at adjacent time points is different.

5. The method according to claim 1, characterized in that, The step of sending the logs located in the ping-pong cache to the ARM processor via the main core includes: A main queue is created for the ARM processor, and the DSP main core processor transmits the logs located in the ping-pong buffer to the main queue via an interrupt. The logs are sent to the ARM processor via the main queue, wherein the main queue includes a hardware queue or a software queue.

6. The method according to claim 1, characterized in that, The step of uniformly outputting the logs received by the ARM processor and the logs generated by the ARM processor itself according to a pre-configured log output method includes: The ARM processor creates a log processing task through a log processing function; The log processing task parses the received logs and the logs generated by the ARM processor itself to obtain the log parsing results. Determine the pre-configured log output method, and output the log parsing results uniformly according to the log output method, wherein the log output method includes network port output and file write output.

7. The method according to claim 1, characterized in that, After uniformly outputting logs according to the pre-configured log output method, the following is also included: The format of the output logs is checked; A log detection report is generated based on the log detection results.

8. A device for acquiring logs of a heterogeneous multi-core processor, characterized in that, include: The log generation module is used to save the logs generated by each processor in the heterogeneous multi-core system to its own storage medium. The processor includes an Advanced Reduced Instruction Set Machine (ARM) processor and multiple Digital Signal Processors (DSPs), and the ARM processor and the DSP processors have different structures. A DSP main core processor filtering module is used to filter out a DSP main core processor from a plurality of DSP processors and set a ping-pong cache on the DSP main core processor; The log ping-pong cache module is used to store the logs generated by each of the DSP processors into the ping-pong cache, and send the logs located in the ping-pong cache to the ARM processor through the main core; The log output module is used to output the logs received by the ARM processor and the logs generated by the ARM processor itself in a unified manner according to a pre-configured log output method.

9. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the program, it implements the method as described in any one of claims 1-7.

10. A storage medium for computer-executable instructions, wherein a computer program is stored thereon, characterized in that, When the program is executed by the processor, it implements the method as described in any one of claims 1-7.

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