FPGA-based standard output serial port and working method thereof, medium and equipment

Abstract

The invention discloses a standard output serial port based on an FPGA (Field Programmable Gate Array) and a working method thereof, a medium and equipment, and relates to the technical field of signal communication, the standard output serial port comprises a synchronous serial port control module, an FIFO (First In First Out) module, a frequency division module and a standard serial port output module, the synchronous serial port control module is respectively connected with the FIFO module, the frequency division module and the standard serial port output module; the synchronous serial port control module is used for instantiating and calling the FIFO module, the frequency division module and the standard serial port output module, the FIFO module is used for reading and writing an input signal, the frequency division module is used for improving the precision of aligning a synchronous signal, and the standard serial port output module outputs a serial signal based on the state of a state machine. According to the invention, the serial port output module can be universally applied to the requirement of converting parallel data into serial data. Compared with a CPU for realizing serial port communication, the method has the characteristics of lower clock jitter, high-precision alignment and predictable alignment error, and the reliability and certainty of the method have better guarantee capability.

Description

Technical Field

[0001] This invention relates to the field of signal communication technology, specifically to a standard output serial port based on FPGA and its working method, medium, and device. Background Technology

[0002] Currently, serial signals are increasingly used in the field of electronic technology. Asynchronous transceivers transmit signals as serial signal outputs, and the requirements for timing consistency, bit error rate, and anti-interference capabilities are becoming increasingly stringent. The importance of aligning the trigger edges is also becoming more significant. Sequential software programming with a fixed instruction set as its core architecture often suffers from unpredictable operating system scheduling and interrupt responses due to reliance on peripherals or software for clock management, making strict alignment difficult. Existing schematic diagrams of serial communication implemented through the CPU are shown below. Figure 1 As shown; however, based on programmable hardware, multi-clock domain FPGAs with parallel logic design have high timing determinism, can strictly achieve trigger edge alignment, which helps to eliminate signal uncertainty, improve system reliability and optimize power consumption.

[0003] In FPGAs, common serial communication typically involves a receiver module (RX) and a standard serial output module (TX). To ensure data continuity and buffering, a FIFO is introduced as a buffer between reception and transmission. The standard serial output module often depends solely on the FIFO, the receiver module, and its own state, leading to issues with low alignment accuracy between the serial output and the synchronization signal. A schematic diagram of existing FPGA-based serial communication implementations is shown below. Figure 2 As shown. Summary of the Invention

[0004] The purpose of this invention is to overcome the shortcomings of the prior art and provide a standard output serial port based on FPGA, as well as its working method, medium, and device.

[0005] The objective of this invention is achieved through the following technical solution: In a first aspect, the present invention discloses a standard output serial port based on FPGA, including a synchronous serial port control module, a FIFO module, a frequency divider module, and a standard serial port output module. The synchronous serial port control module is connected to the FIFO module, the frequency divider module, and the standard serial port output module respectively. The synchronous serial port control module is used to instantiate and call the FIFO module, the frequency divider module, and the standard serial port output module. The FIFO module is used to read and write input signals. The frequency divider module is used to improve the accuracy of the alignment synchronization signal. The standard serial port output module outputs serial signals based on the state of the state machine.

[0006] Secondly, this invention discloses a method for operating a standard output serial port based on an FPGA, used in the FPGA-based standard output serial port described in the first aspect, comprising the following steps: S1. An external device inputs a signal to the standard output serial port based on the FPGA. The external device includes an FPGA and a CPU. The input signal is parallel data. S2. The input signal enters the FIFO module. Based on the FIFO module status and the data update flag of the input signal, the write control operation is performed on the input signal. The system waits for the read enable operation of the FIFO module. The input signal is buffered or shifted through the synchronous serial port control module. Then, the D flip-flop is used to obtain the data update flag and synchronization signal of the input signal. S3. Based on the FIFO module status, synchronization signal input, and standard serial port output module status, enable the FIFO module to perform a read enable operation, pull the read enable high, and enable the standard serial port output module to enter the valid state for sending data. S4. The signal read from the FIFO module is processed by the standard serial port output module, converted into a serial signal, and then output as an output signal by aligning the synchronization signal through the frequency division module.

[0007] Based on the second aspect, the standard serial port output module described in step S3 adopts a state machine writing method, which determines the next state through multiple signals and the current state of the state machine. The initial and default states of the state machine are both idle. In the idle state, the state machine waits for a synchronization signal to trigger. Based on the busy signal of the standard serial port output module at this time, pulling the busy signal high controls the state machine to enter the waiting state; or pulling the busy signal low controls the state machine to enter the transmit high state. If the busy signal is pulled low and the FIFO module has a buffered signal that can be read, the standard serial port output module enters the transmit state. After the transmission is completed, it enters the waiting state again, completing the state transition.

[0008] Based on the second aspect, the state machine changes are as follows: Idle state, waiting to send data; In the transmit state, data is placed into the transmit buffer. In this state, the clock of the trigger signal output by the synchronous frequency divider is aligned with the synchronous signal. After waiting for the synchronous signal input, the system enters the next state. To initialize the state, pull the bus low, i.e., clear it to 0; Data bit status, outputting data bit by bit to the bus; The check bit status is output according to the frame format configuration. When the stop bit is in the state, write "1" to the bus; Status sent.

[0009] Thirdly, the present invention also discloses a computer-readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the method described above.

[0010] Fourthly, the present invention also discloses an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: when the processor executes the computer program, it implements the method described above.

[0011] The beneficial effects of this invention are: 1) Enables the serial output module to be widely used in applications requiring parallel data to serial data conversion.

[0012] 2) The introduced trigger signal alignment function has the function of high-precision synchronous trigger signal processing under the FPGA clock processing of up to 100MHz, and the error of the signal alignment trigger edge can reach the nanosecond level.

[0013] 3) Selectable baud rate, controllable input data transmission length, adaptable to various types of signals.

[0014] 4) After aligning the trigger edge (synchronization signal), the output signal has a precise bit width, a determined transition time, good anti-interference capability, and high timing consistency. It can reduce metastability and eliminate uncertainty.

[0015] 5) Compared with CPU-based serial communication, this invention features lower clock jitter, high-precision alignment, and predictable alignment error, providing better assurance of reliability and determinism. Attached Figure Description

[0016] Figure 1 A schematic diagram illustrating the implementation of serial communication for a CPU using existing technology; Figure 2 A schematic diagram illustrating the implementation of serial communication on an existing FPGA. Figure 3 This is a schematic diagram of a standard output serial port based on FPGA according to an embodiment of the present invention; Figure 4 This is an RTL connection diagram of a standard output serial port based on an FPGA according to an embodiment of the present invention; Figure 5 This is a schematic diagram of data / signal processing based on a standard output serial port of FPGA according to an embodiment of the present invention; Figure 6 This is a schematic diagram of the output state machine transformation of a standard output serial port based on FPGA according to an embodiment of the present invention. Detailed Implementation

[0017] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] This invention discloses a standard output serial port based on FPGA and its working method. It provides an FPGA design integrating standard serial port output and a FIFO buffer module, avoiding the problem of low alignment accuracy between serial port output and synchronization signal in software implementations. Based on FPGA implementation, a synchronous serial port control module is used as the top-level module, and a FIFO module, a frequency divider module, and a standard serial port output module are instantiated to achieve the overall transmission function. To meet the requirements of universality and timing in signal output module application, this invention integrates the FIFO into the standard serial port output module and introduces a frequency divider module to improve the accuracy of the alignment trigger edge (synchronization signal). Furthermore, state control is applied to the functional implementation, thereby achieving the function of aligning the standard serial port output with the synchronization signal. Its structural diagram is shown below. Figure 3 As shown, the synchronous serial port control module is connected to the FIFO module, the frequency divider module, and the standard serial port output module, respectively. The synchronous serial port control module is used to instantiate and call the FIFO module, the frequency divider module, and the standard serial port output module. The FIFO module is used to read and write the input signal. The frequency divider module is used to improve the accuracy of the alignment synchronization signal. The standard serial port output module outputs a serial signal based on the state of the state machine.

[0019] For example, an RTL connection diagram of a standard output serial port based on an FPGA is shown below. Figure 4As shown, the synchronous serial port module employs multiple parallel timing logic judgments and simultaneously calls sub-modules (FIFO module, frequency divider module, and standard serial port output module) to achieve the following functions: buffering or shifting some input signals (such as synchronous trigger signals, data update flags, data length bit update flags, etc.) using buff buffers or shift registers (baud rate, etc.); using D flip-flops to time the signal, facilitating the capture of the rising edge (trigger edge) of the synchronous trigger signal; and providing flags for some functions (data update judgment, baud rate change judgment). Signal baud rate selection is a necessary option for serial port transmission; signal baud rate changes are dynamically adjusted to follow the signal's baud rate, reducing the bit error rate. The number of bits transmitted for each group is controlled according to the length of the input data. The FIFO module provides read / write enable control. The synchronous serial port output function status control (idle, wait, send) is implemented. The FIFO reset function control, in the case of basic implementation, only uses the reset signal for control, as read and write functions have separate control logic, and errors in the FIFO module are largely avoidable. The sub-modules (FIFO module, frequency divider module, and standard serial port transmit module) are instantiated, controlling the signal connections of the sub-modules. The above points summarize the components of a synchronous serial port. The FPGA timing logic, which combines sequential logic with status bit transitions, offers excellent controllability and responsiveness, enabling real-time control of state changes and data transmission. Even when unknown states, high-impedance states, or race conditions and hazards arise due to poor clock edge quality, the synchronous serial port's internal error judgment and jump timing logic can still be used to escape unknown error states. Furthermore, this synchronous serial port can optionally include data bit counting and a data transmission start flag for better data transmission positioning. The parallel timing logic offers good compatibility and facilitates the introduction of more control functions on top of the basic functionality.

[0020] This invention also discloses a method for operating a standard output serial port based on an FPGA, used in the aforementioned standard output serial port based on an FPGA, the data / signal processing schematic of which is shown below. Figure 5 As shown; including the following steps: S1. An external device inputs a signal to the standard output serial port based on the FPGA. The external device includes the FPGA, CPU, etc., and the input signal is parallel data. S2. The input signal enters the FIFO module. Based on the FIFO module status and the data update flag of the input signal, the write control operation is performed on the input signal. The system waits for the read enable operation of the FIFO module. The input signal is buffered or shifted through the synchronous serial port control module. Then, the D flip-flop is used to obtain the data update flag and synchronization signal of the input signal. S3. Based on the FIFO module status, synchronization signal input, and standard serial port output module status, enable the FIFO module to perform a read enable operation, pull the read enable high, and enable the standard serial port output module to enter the valid state for sending data. S4. The signal read from the FIFO module is processed by the standard serial port output module, converted into a serial signal, and then output as an output signal by aligning the synchronization signal through the frequency division module.

[0021] Specifically, the output state machine transition diagram is as follows: Figure 6 As shown, the standard serial port output module described in step S3 uses a state machine approach to determine the next state based on multiple signals and the current state of the state machine. The initial and default states of the state machine are both idle. In the idle state, the state machine waits for a synchronization signal to trigger. Based on the busy signal of the standard serial port output module at this time, pulling the busy signal high controls the state machine to enter the waiting state; or pulling the busy signal low controls the state machine to enter the transmit high state. If the busy signal is pulled low and the FIFO module has a buffered signal that can be read, the standard serial port output module enters the transmit state. After the transmission is completed, it enters the waiting state again, completing the state transition. The specific state changes of the state machine are as follows: Idle state, waiting to send data; In the transmit state, data is placed into the transmit buffer. In this state, the clock of the trigger signal output by the synchronous frequency divider is aligned with the synchronous signal. After waiting for the synchronous signal input, the system enters the next state. To initialize the state, pull the bus low, i.e., clear it to 0; Data bit status, outputting data bit by bit to the bus; The check bit status is output according to the frame format configuration. When the stop bit is in the state, write "1" to the bus; Status sent.

[0022] By way of example, the present invention also provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0023] For example, the aforementioned computer-readable storage media may include, but are not limited to, various media capable of storing computer programs, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0024] By way of example, the present invention also provides an electronic device including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0025] For example, the above-mentioned electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor and the input / output device is connected to the processor.

[0026] In summary, this invention discloses a standard output serial port based on FPGA, its working method, medium, and device, enabling the serial port output module to be widely used in applications requiring parallel data to serial data conversion. The introduced trigger signal alignment function, under FPGA clock processing up to 100MHz, provides a high-precision synchronous trigger signal, with signal alignment trigger edge error reaching the nanosecond level. It offers selectable baud rates, controllable input data transmission length, and adaptability to various signal types. After trigger edge alignment, the output signal has precise bit width, determined transition times, good anti-interference capability, and high timing consistency, reducing metastability and eliminating uncertainty. Compared to CPU-based serial communication, this invention features lower clock jitter, high-precision alignment, and predictable alignment errors, ensuring better reliability and determinism.

[0027] The above description is merely a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the forms disclosed herein and should not be construed as excluding other embodiments. It can be used in various other combinations, modifications, and environments, and can be altered within the scope of the concept described herein through the above teachings or related technologies or knowledge. Modifications and variations made by those skilled in the art that do not depart from the spirit and scope of the present invention should be within the protection scope of the appended claims.

Claims

1. A standard output serial port based on FPGA, characterized in that: It includes a synchronous serial port control module, a FIFO module, a frequency divider module, and a standard serial port output module. The synchronous serial port control module is connected to the FIFO module, the frequency divider module, and the standard serial port output module, respectively. The synchronous serial port control module is used to instantiate and call the FIFO module, the frequency divider module, and the standard serial port output module. The FIFO module is used to read and write input signals. The frequency divider module is used to improve the accuracy of the alignment synchronization signal. The standard serial port output module outputs serial signals based on the state machine's state.

2. A method for operating a standard output serial port based on an FPGA, used in the standard output serial port based on an FPGA as described in claim 1, characterized in that, Includes the following steps: S1. An external device inputs a signal to the standard output serial port based on the FPGA. The external device includes an FPGA and a CPU. The input signal is parallel data. S2. The input signal enters the FIFO module. Based on the FIFO module status and the data update flag of the input signal, the write control operation is performed on the input signal. The system waits for the read enable operation of the FIFO module. The input signal is buffered or shifted through the synchronous serial port control module. Then, the D flip-flop is used to obtain the data update flag and synchronization signal of the input signal. S3. Based on the FIFO module status, synchronization signal input, and standard serial port output module status, enable the FIFO module to perform a read enable operation, pull the read enable high, and enable the standard serial port output module to enter the valid state for sending data. S4. The signal read from the FIFO module is processed by the standard serial port output module, converted into a serial signal, and then output as an output signal by aligning the synchronization signal through the frequency division module.

3. The method for operating a standard output serial port based on an FPGA according to claim 2, characterized in that, The standard serial port output module described in step S3 uses a state machine approach, which determines the next state based on multiple signals and the current state of the state machine. The initial and default states of the state machine are both idle. In the idle state, the state machine waits for a synchronization signal to trigger. Based on the busy signal of the standard serial port output module at this time, pulling the busy signal high controls the state machine to enter the waiting state; or pulling the busy signal low controls the state machine to enter the transmit high state. If the busy signal is pulled low and the FIFO module has a buffered signal that can be read, the standard serial port output module enters the transmit state. After the transmission is completed, it enters the waiting state again, completing the state transition.

4. The method for operating a standard output serial port based on an FPGA according to claim 3, characterized in that, The state machine changes are as follows: Idle state, waiting to send data; In the transmit state, data is placed into the transmit buffer. In this state, the clock of the trigger signal output by the synchronous frequency divider is aligned with the synchronous signal. After waiting for the synchronous signal input, the system enters the next state. To initialize the state, pull the bus low, i.e., clear it to 0; Data bit status, outputting data bit by bit to the bus; The check bit status is output according to the frame format configuration. When the stop bit is in the state, write "1" to the bus; Status sent.

5. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the method described in any one of claims 2-4.

6. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, it implements the method described in any one of claims 2-4.

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