Critical path screening method and system based on chip time sequence report

Abstract

The invention relates to the technical field of chip design, and provides a critical path screening method based on a chip time sequence report, which comprises the following steps: collecting chip time sequence report data, screening out first N critical paths from the data based on time sequence index data, and establishing a path ID-delay type-scene three-dimensional data model; and calculating the delay ratio of the unit delay to the interconnection line delay in each critical path. Performing single-type delay, type relevance and RC condition influence comparison on different scenes to obtain delay characteristic data. The invention discloses a system for executing the method, which can avoid full data redundancy and improve the analysis efficiency by screening the first N critical paths. And the delay change rule in different scenes is quantified. The delay characteristic data reflects the actual influence of the key path delay on the time sequence, so that a designer can quickly position the delay bottleneck of the key path, and a basis and a reference are provided for the targeted optimization of the total delay of the chip in the later period.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a critical path screening method and system based on chip timing reports. Background Technology

[0002] The rapid development of digital chip design technology is driving chips towards greater complexity and integration, leading to a continuous expansion in design scale and a significant increase in operating frequency. These changes pose increasingly stringent challenges to chip performance, operational reliability, and development process efficiency.

[0003] CN118261096B discloses a critical path filtering method and system based on chip timing reports. The critical path filtering method includes: Step S1, reading a top-level timing report file containing timing violation data for all paths, wherein the violation data includes at least path information, and the cell name, cell type, cell boundary conditions, and delay information of the device cells on the path; Step S2, extracting the corresponding cell boundary conditions and delay information from the top-level timing report file under different conditions according to the cell type, wherein the cell boundary conditions include the transition time of the input signal and the output load; The delay information is mapped to the corresponding unit boundary conditions in the form of a two-dimensional array variable. The buffer type is different under different conditions, and the different conditions include process, voltage, and temperature conditions. In step S3, a linear fitting function is called, and the unit boundary conditions and the delay information in step S2 are used as input data. The linear fitting function is superimposed to output the binary function parameter set of the linear fitting function. In step S4, the unit boundary conditions and violation information corresponding to all target registers are extracted. Based on the binary function parameter set of the linear fitting function, the buffer type and delay information under different conditions are calculated, and the engineering repair script files at each module level are generated.

[0004] CN110598235B discloses a method and system for repairing timing violations in chip design, including the following steps: Step 100, after chip placement and routing, timing analysis is performed using a timing analysis tool to obtain the paths of all timing violations; Step 200, the violation values ​​are sorted from largest to smallest, and the path corresponding to the largest violation value is selected as the target repair path; Step 300, all basic units and their corresponding delay values ​​on the data path of the aforementioned target repair path are captured, sorted according to the delay values, and the basic units are selected as target units in sequence according to the sorting; Step 400, it is determined whether the violation of the aforementioned target repair path is an establishment timing violation or a maintenance timing violation, and repaired accordingly; during repair, the target units are replaced sequentially based on the rule of not affecting other timing paths until timing convergence or all target units are completely replaced, and all the above repair operations are obtained. Step 500: Convert the aforementioned repair operation into an operation command that the placement and routing tool can recognize, and perform the above operation on the placement and routing tool based on this version of the placement and routing data; Step 600: Verify whether the timing analysis results after the above operation meet the timing requirements. If not, return to step 200; if they meet, end the repair. In step 400, the method of replacing the target cell based on rules that do not affect other timing paths is as follows: In the case of a setup time violation, determine whether all timing paths passing through the target cell have a hold time margin in the fastest delay environment. If there is a margin, replace the target cell; otherwise, do not replace it. In the case of a hold time violation, determine whether all timing paths passing through the target cell have a setup time margin in the slowest delay environment. If there is a margin, replace the target cell; otherwise, do not replace it.

[0005] As nanometer-scale processes become increasingly prevalent in chip design, the voltage-temperature compensation effect at the FinFET node leads to nonlinear changes in cell delay, necessitating enhanced process characteristic analysis. The number of scenarios that timing analysis needs to cover is growing exponentially. Traditional methods rely on manual selection of critical paths from full-chip timing reports, which is time-consuming and prone to overlooking critical paths, often resulting in insufficient focus in the analysis. Summary of the Invention

[0006] Long-term practical experience has revealed that when chips move to processes below 28nm, especially in FinFET processes below 16nm, 7nm, or 5nm, voltage-temperature compensation effects cause nonlinear changes in cell delay. The number of scenarios that timing analysis needs to cover increases exponentially. If relying on manual screening of critical paths from full-chip timing reports, the average screening time for each critical path exceeds 3 minutes. For designs with tens of millions of gates, complete analysis requires enormous time and human resources. In actual operations, the lack of a unified coordinate system for delay data across multiple scenarios leads to a lack of traceability for cell delay changes and makes it difficult to quantify the correlation between delays in different scenarios. Furthermore, the inability to quickly generate intuitive delay comparison charts impacts the efficiency of timing problem localization.

[0007] In view of this, the present invention provides a critical path filtering method based on chip timing reports, including,

[0008] Step S1: Collect chip timing report data, wherein the chip timing report data includes at least the path start point, path end point, logic unit composition, and interconnect information in the critical path; interconnect delay data, unit delay data, and total delay data on each path; as well as timing indicator data and scenario information data; the timing indicator data includes timing margin, worst-case negative margin, and total negative margin;

[0009] Step S2: Based on the worst-case negative margin, sort from largest to smallest and filter out the top N critical paths from the chip timing report data, where N is a positive integer greater than 2; wherein, the critical path includes at least cell delay, interconnect delay, scenario, worst-case negative margin, and total negative margin;

[0010] Step S3: Establish a three-dimensional data model of path ID-delay type-scenario based on the critical path, and calculate the delay ratio r of unit delay to interconnect delay in each critical path;

[0011] Step S4: Compare the trends of unit delay and interconnect delay under different scenarios to identify the dominant delay type; analyze the correlation between unit delay and interconnect delay under the same scenario to obtain delay characteristic data.

[0012] Preferably, step S4 includes,

[0013] Step S41: In the first N critical paths, under different scenarios, determine the dominant delay type as cell delay or interconnect delay by the rate of change.

[0014] Preferably, step S2 includes adjusting the value of N according to the size of the chip circuit; if the size of the chip circuit reaches a preset condition, then N*P is adjusted, where P is an adjustment coefficient, and the adjustment coefficient is set according to the preset condition.

[0015] Preferably, step S4 includes,

[0016] Step S43: In each critical path, under the signal integrity scenario, calculate the difference between the unit delay and the interconnect delay to obtain RC condition impact comparison data.

[0017] Preferably, in step S2, a data binning algorithm is used to divide all paths into multiple intervals according to the time margin, calculate the statistical value of the delay ratio r of all paths in each interval, and establish a functional relationship model between delay characteristics and path criticality.

[0018] Preferably, the critical path filtering method based on chip timing reports further includes,

[0019] Step S5 involves visualizing and generating a report for each interval in the critical path, including at least the cell delay, interconnect delay, and delay ratio r.

[0020] Preferably, step S4 further includes,

[0021] Step S44: Based on the historical data of the critical path, a machine learning model is used to predict latency characteristic data under different scenarios.

[0022] The present invention also provides a system for performing the above-described critical path filtering method based on chip timing reports, the system comprising:

[0023] The acquisition module is used to acquire chip timing report data, wherein the chip timing report data includes at least the path start point, path end point, logic unit composition, and interconnect information in the critical path; interconnect delay data, unit delay data, and total delay data on each path; as well as timing indicator data and scenario information data; the timing indicator data includes timing margin, worst-case negative margin, and total negative margin;

[0024] The filtering module is used to filter the top N critical paths from the chip timing report data based on the worst-case negative margin in descending order, where N is a positive integer greater than 2; wherein the critical path includes at least cell delay, interconnect delay, scenario, worst-case negative margin, and total negative margin;

[0025] The modeling module is used to establish a three-dimensional data model of path ID-delay type-scene based on the critical path, and calculate the delay ratio r of unit delay to interconnect delay in each critical path;

[0026] The comparison module is used to compare the trends of unit latency and interconnect latency under different scenarios to identify the dominant latency type; it also analyzes the correlation between unit latency and interconnect latency under the same scenario to obtain latency characteristic data.

[0027] The present invention also provides an electronic device, comprising at least one processor; and a memory communicatively connected to said at least one processor; wherein,

[0028] The memory stores instructions that can be executed by the at least one processor, which enables the at least one processor to perform the critical path filtering method based on chip timing reports described above.

[0029] The present invention also provides a machine-readable storage medium storing instructions for causing a machine to execute the critical path filtering method based on chip timing reports as described above.

[0030] Compared to existing technologies, this invention, through steps S1-S4, involves collecting chip timing report data, covering the start and end points of critical paths, logic unit composition, interconnect information, interconnect delays, unit delays, total delays for each path, as well as timing metric data and scenario information data. Based on the timing metric data, the top N critical paths are selected from the above data. These critical paths must include unit delay, interconnect delay, the scenario they belong to, worst-case margin, and total margin. A three-dimensional data model of path ID-delay type-scenario is then established based on the critical paths, and the delay ratio of unit delay to interconnect delay in each critical path is calculated. Finally, single-type delay comparisons, type correlation comparisons, and RC condition impact comparisons are performed for different scenarios to obtain delay characteristic data. This invention discloses a system for performing the above method, which automatically selects the top N critical paths, avoids redundancy of all data, and improves analysis efficiency. By establishing comparisons of unit delay, interconnect delay, and delay ratios in multiple scenarios, the delay variation patterns under different scenarios are quantified. Delay characteristic data can reflect the actual impact of critical path delay on timing, enabling designers to quickly locate the delay bottleneck of the critical path, and providing a basis and reference for targeted optimization of the total chip delay in the later stage.

[0031] Other features and advantages of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0032] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0033] In the attached diagram:

[0034] Figure 1This is a schematic diagram illustrating how, according to one embodiment of the present invention, the top N critical paths are selected from chip timing report data based on the worst-case negative margin sorted from largest to smallest.

[0035] Figure 2 This is a schematic diagram comparing unit delay and interconnect delay in a critical path screening method based on chip timing reports according to one embodiment of the present invention.

[0036] Figure 3 This is a scatter plot of the delay ratio in a critical path screening method based on chip timing reports according to one embodiment of the present invention.

[0037] Figure 4 The delay under the nominal condition of 0.75V TT85C is used as the reference delay for comparison of the line graph. Detailed Implementation

[0038] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustration and explanation only and are not intended to limit the present invention.

[0039] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0040] It should be noted that the terms "first," "second," "third," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of the invention described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0041] In existing technologies, when chips move to processes below 28nm, especially in FinFET (Fin Field-Effect Transistor) processes below 16nm, 7nm, or 5nm, voltage-temperature compensation effects cause nonlinear changes in cell delay. The number of scenarios that timing analysis needs to cover increases exponentially. If relying on manual screening of critical paths from full-chip timing reports, the average screening time for each critical path exceeds 3 minutes. For designs with tens of millions of gates, complete analysis requires enormous time and human resources. In practice, the lack of a unified coordinate system for delay data across multiple scenarios leads to a lack of traceability for cell delay changes and makes it difficult to quantify the correlation between delays in different scenarios. The inability to quickly generate intuitive delay comparison charts also impacts the efficiency of timing problem localization. Fin Field-Effect Transistor

[0042] Interconnect delay (Net Delay) is the delay in signal propagation within chip interconnects. Cell delay (Cell Delay) is the delay of a logic unit, such as a register or buffer. Corner refers to a combination of different process, voltage, temperature, and resistance-capacitance (RC) conditions. RC stands for resistance-capacitance, primarily used to describe the electrical characteristics of interconnects. The resistance R and parasitic capacitance C of an interconnect together constitute the RC delay. Timing margin (Slack) is an indicator used to measure whether the timing of a path meets requirements. Worst Negative Slack (WNS) is the most severe timing violation value in the entire chip. It is one of the key indicators for measuring timing convergence, representing the minimum negative margin among all timing paths, i.e., the most severe timing violation, directly reflecting the greatest timing risk point in the chip design. Total Negative Slack (TNS) is the sum of all timing violations in the entire chip. It measures the cumulative effect of timing violations across all timing paths with inherent negative slack, comprehensively reflecting the overall pressure on the chip design in terms of timing convergence. Unlike WNS, which focuses on the single most severe violation path, TNS prioritizes the overall impact of all violation paths.

[0043] like Figure 1-2 As shown, this invention provides a critical path filtering method based on chip timing reports. The critical path filtering method based on chip timing reports includes...

[0044] Step S1: Collect chip timing report data, wherein the chip timing report data includes at least the path start point, path end point, logic unit composition, and interconnect information in the critical path; interconnect delay data, unit delay data, and total delay data on each path; as well as timing indicator data and scenario information data; the timing indicator data includes timing margin, worst-case negative margin, and total negative margin;

[0045] Step S2: Based on the worst-case negative margin, sort from largest to smallest and filter out the top N critical paths from the chip timing report data, where N is a positive integer greater than 2; wherein, the critical path includes at least cell delay, interconnect delay, scenario, worst-case negative margin, and total negative margin;

[0046] Step S3: Establish a three-dimensional data model of path ID-delay type-scenario based on the critical path, and calculate the delay ratio r of unit delay to interconnect delay in each critical path;

[0047] Step S4: Compare the trends of unit delay and interconnect delay under different scenarios to identify the dominant delay type; analyze the correlation between unit delay and interconnect delay under the same scenario to obtain delay characteristic data.

[0048] This invention, through steps S1-S4, involves collecting chip timing report data, covering the start and end points of critical paths, logic unit composition, interconnect information, interconnect delay, unit delay, total delay for each path, as well as timing metric data and scenario information. Based on the timing metric data, the top N critical paths are selected from the above data. These critical paths must include unit delay, interconnect delay, the scenario they belong to, worst-case margin, and total margin. A three-dimensional data model of path ID-delay type-scenario is then established based on the critical paths, and the delay ratio of unit delay to interconnect delay in each critical path is calculated. Finally, single-type delay comparison, type correlation comparison, and RC condition impact comparison are performed for different scenarios to obtain delay characteristic data. Automated selection of the top N critical paths avoids redundancy of the entire data set, improving analysis efficiency. By establishing a comparison of unit delay, interconnect delay, and delay ratio under multiple scenarios, the delay variation patterns under different scenarios are quantified. Delay characteristic data can reflect the actual impact of critical path delay on timing, enabling designers to quickly locate the delay bottleneck of the critical path, and providing a basis and reference for targeted optimization of the total chip delay in the later stage.

[0049] In step S1, the path start point refers to the starting position of the signal on the critical path, which is usually the timing start unit within the chip. Examples include the output of a clock generator (PLL / MMCM), the output of a clock buffer, and the output of a clock gate. The path end point refers to the ending position of the signal on the critical path, which is usually the timing end unit within the chip. Specifically, this includes flip-flops and the D terminal (data input) of registers, which must meet setup time and hold time constraints. The logic cell composition refers to the sequence and type of all logic functional units on the critical path, and is the core component of path delay. Specifically, it includes basic gate circuits such as AND, OR, NOT, NAND, NOR, and XOR; complex combinational logic units such as MUX, adders, and shift registers; and timing units such as flip-flops and latches. The drive strength, size, and threshold voltage (Vth) level (e.g., high threshold / low threshold) of each unit directly affect the unit delay. The cascading relationship of units from start to finish (e.g., "flip-flop A → NAND gate → multiplexer → flip-flop B") reflects the logical processing flow of the signal. Interconnect information refers to the metal wires and parasitic parameters of each logic unit on the connection path, which determines the magnitude of the interconnect delay. Specifically, this includes: the length, width, thickness of the interconnect, the metal layer it is located on (e.g., Metal 1 to Metal 10), the wiring topology (e.g., straight line, branch type); parasitic parameters such as resistance (R), capacitance (C), and inductance (L, in high-frequency scenarios); the unit pins connected to both ends of the wire, such as NAND gate output → wire → multiplexer input, and the cross-coupling capacitance between the wire and other signal lines, the latter of which may cause signal crosstalk.

[0050] Cell delay data refers to the delay of a single logic cell. The delay of a single logic cell is the delay value of each logic cell in the path, such as a NAND gate, MUX, or flip-flop. This includes the cell's inherent delay, which is the basic delay determined by the switching characteristics of the transistors within the cell. Interconnect delay data is the delay value of each metal wire segment in the path, calculated from the wire's parasitic resistance (R), capacitance (C), and signal transition time. Total delay data is the sum of logic cell delays and interconnect delays, and is the main component of combinational logic path delays. Timing metrics data include at least timing margin (slack), worst-case negative margin (WNS), and total negative margin (TNS). Timing margin (slack) is the difference between the actual delay of the path and the required delay, i.e., Slack = Required Delay - Actual Delay. Worst-case negative margin is the largest absolute value of the negative margin among all paths with negative margins, representing the most severe timing violation. For example, WNS = -50ps means that a certain path needs to reduce latency by at least 50ps to meet the constraint. Total negative margin is the sum of the negative margins of all paths with negative margins, i.e., the cumulative negative margin of all non-compliant paths. Total negative margin reflects the "total amount" of timing violations in the design, comprehensively measuring the overall pressure on timing convergence. For example, TNS = -500ps means that the total latency overrun of all non-compliant paths is 500ps, and this latency needs to be reduced through optimization and amortization.

[0051] The operating voltage of the chip directly affects cell delay; voltage fluctuations increase delay as voltage decreases. The chip's operating temperature range is also crucial; high temperatures reduce transistor carrier mobility, increasing cell delay. Process corners are variations in chip manufacturing processes, such as fast process (FF), slow process (SS), and typical process (TT). Cell and interconnect delays differ significantly across process corners. For example, SS corners have the largest delay, while FF corners have the smallest. Multiple process corner scenarios, such as TT85C, SS0C_CMAX, and SS125C_RXMAX, result in different corner delays.

[0052] Based on the chip timing report data package, in order to more comprehensively and efficiently reflect the timing status of the critical path, timing optimization is performed for the chip design. In a more preferred embodiment of the present invention, step S4 includes step S41, in the first N critical paths, under different scenarios, determining the dominant delay type as cell delay or interconnect delay by the rate of change.

[0053] In scenarios involving voltage variations, process angle variations, temperature variations, and load capacitance variations, the rate of change is used to determine whether the dominant delay type is cell delay or interconnect delay. For example, in voltage variation scenarios, this is used to distinguish between cell delay and interconnect delay. Cell delay is extremely sensitive to voltage; as the voltage decreases, the transistor switching time increases significantly, and the cell delay rises. Interconnect delay is mainly determined by RC and is almost independent of voltage. The total delay T1 at voltage V1 is recorded, including the cell delay T. cell1 Interconnect delay T net1 Reduce the voltage to V2, i.e., V1 = 1.0V → V2 = 0.9V, and record the total delay T2, where T2 includes the unit delay T. cell2 Interconnect delay T net2 .

[0054] ΔT total =T2-T1;

[0055] ΔT cell =T cell2 -T cell1 ;

[0056] ΔT net =T net2 -T net1 (≈0);

[0057] If ΔT total ≈ΔT cell If the total delay variation almost entirely comes from the unit delay, then the unit delay dominates; if ΔT total Very small, ΔT cell If the percentage is less than 50%, then interconnect latency is the dominant factor.

[0058] The scale of the circuit determines the potential number and complexity of critical paths. Larger scale circuits typically require analysis of more critical paths to cover more timing bottlenecks. In a more preferred embodiment of the invention, step S2 includes adjusting the value of N based on the chip circuit scale; if the chip circuit scale reaches a preset condition, then N*P is adjusted, where P is an adjustment coefficient set according to the preset condition. Quantifiable indicators of circuit scale include the number of logic gates, the number of transistors, etc. For example, the number of logic gates is measured in millions of gates, the most intuitive scale indicator, such as 500,000 gates, 5 million gates, 20 million gates. These can be used to determine whether the preset condition has been met. For example, the number of functional modules included in the design, the number of CPU cores, the number of cache modules, the number of I / O interfaces, etc., can also be used to determine this. Based on the quantified circuit scale indicators, a threshold for triggering N value adjustment, i.e., the preset condition, is set. This is usually set according to scale levels. For example, if the circuit scale level is small circuit, with less than 1 million logic gates and less than 50,000 timing paths, an initial N value of N = 1000~2000 is used directly. The circuit size is medium-sized, with 1 million to 5 million logic gates and 50,000 to 300,000 timing paths. The N*P ratio is adjusted to 5,000 to 10,000, with P set to 5. When advancing critical paths, at least cell delay needs to be extracted and categorized by cell type (e.g., REG, COMB, BUF, INV). Net delay should also be categorized by interconnect length, load, and other characteristics. The process corner of the path and its corresponding WNS and TNS values ​​should be recorded. Based on the worst-case margin, the top N critical paths are selected from the chip timing report data, sorted from largest to smallest. Figure 1 As shown.

[0059] In signal integrity scenarios, to better quantify the differential impact of interconnect parasitic resistance R, capacitance C, and crosstalk effects on cell delay and interconnect delay, in a more preferred embodiment of the present invention, step S4 includes:

[0060] Step S43: In each critical path, under the signal integrity scenario, calculate the difference between the cell delay and the interconnect delay to obtain comparative data on the impact of RC conditions. If the difference is positive, it indicates that under the current RC conditions, the cell delay is greater than the interconnect delay, and the RC factor has a more significant impact on the cell delay. If the difference is negative, it indicates that the interconnect delay is dominant, and the RC conditions, especially the crosstalk caused by coupling capacitance, have a more prominent impact on the interconnect delay.

[0061] Parasitic extraction in chip design, such as... Figure 2As shown, the resistance (R), capacitance (C), and inductance (L) of interconnects are key steps in the chip physical design and timing analysis process. Based on the chip's layout data, the resistance (R), capacitance (C), and inductance (L) of interconnects (metal wires, vias, etc.) are calculated using electromagnetic field theory, generating standard files (such as SPEF format) containing these parameters for subsequent timing analysis (STA), signal integrity (SI) analysis, etc.

[0062] For each binning interval, calculating the statistical index of the delay ratio *r* for all paths within that interval allows for a better extraction of the distribution pattern of delay characteristics. In a more preferred embodiment of the invention, in step S2, a data binning algorithm is used to divide all paths into multiple intervals based on timing margins. The statistical value of the delay ratio *r* for all paths within each interval is calculated, establishing a functional relationship model between delay characteristics and path criticality. The cell / net delay ratio *r* for each path is used to quantify the contribution of both to the total delay. Timing margin is a core indicator for measuring path criticality. The larger the absolute value of the negative margin (e.g., negative margin = -100 ps), the more critical the path and the more severe the timing violation. The larger the positive margin (e.g., positive margin = 50 ps), the more lenient the path and the lower its criticality. This model can quantify how path criticality affects delay characteristics, providing direction for timing optimization. For example, the timing margins of all paths can be sorted from the smallest negative margin to the largest positive margin. Divide the path into intervals according to the selected binning method, and label each path with its corresponding bin number, for example, different bins (bin1, bin2…binK). Define the timing margin range for each bin, for example, bin1: [-200ps, -50ps], and the number of paths it contains. If the model shows that the most critical path in bin (bin1) has a mean r = 1.8, indicating cell delay dominance, optimization should prioritize replacing high-latency cells in that interval. If the mean r of an interval is <1, indicating interconnect dominance, optimization should prioritize routing in that interval, such as shortening the length or replacing thicker metal layers. The cell-to-interconnect delay ratio r for each path is... Figure 3 The vertical axis represents 1 / r, which is path delay / cell delay. The horizontal axis represents the time margin (slack). Based on the scatter distribution trend of X and Y, a suitable fitting function is selected. If the variation patterns of different intervals differ significantly, such as the different trends in the negative margin interval and the positive margin interval, the function is defined piecewise according to the interval. For example, a linear function is used for the negative margin interval, and a constant function is used for the positive margin interval.

[0063] The timing slack for all paths must include the quantities of all timing paths across the entire chip, not just the first N critical paths, to ensure complete coverage of the distribution. Timing slack includes positive and negative slack.

[0064] To transform abstract latency data into intuitive visual information and actionable optimization suggestions, intuitive chart types are selected for different data types. The interval trend of the latency ratio r shows the variation of the r value over time margin intervals, reflecting the correlation between path criticality and latency dominance. In a more preferred embodiment of the invention, the critical path screening method based on chip timing reports further includes...

[0065] Step S5 involves visualizing and generating a report for each interval in the critical path, including at least the cell delay, interconnect delay, and delay ratio r. Figure 4 The graph is a line chart that compares the average cell delay and net delay of the first N critical paths under multiple corners. Figure 4 The delay under the nominal condition of 0.75V TT85C is used as the benchmark delay for comparison. "TT85C" is a typical process-temperature (PVT) angle identifier in chip timing analysis; "TT" represents typical process, and "85C" refers to an ambient temperature of 85°C. "Golden delay" refers to the "benchmark delay" used as a reference standard. "COMB BUFINV" in parentheses correspond to combinational logic, buffer, and inverter, respectively, specifying the applicable circuit type for this benchmark delay. Under SSM40C conditions, the cell delay ratio is approximately 1.65-1.8. Note that in "SSM40C," "SS" represents slow-slow process, "M" usually refers to medium voltage (Medium Voltage), and in some scenarios, it is a process subdivision identifier; "40C" refers to a -40°C low-temperature environment; "cell delay ratio" is the ratio of cell delay to interconnect delay, corresponding to the "delay ratio r" mentioned earlier.

[0066] Under SS0C conditions, the cell delay ratio is approximately 1.6-1.7. Note: "SS" in "SS0C" indicates a slow process, and "0C" refers to an ambient temperature of 0°C. Under SS125C conditions, the cell delay ratio is approximately 1.35-1.45. "125C" in "SS125C" refers to a high-temperature environment of 125°C, reflecting the impact of different temperatures on the cell delay ratio under slow process conditions. As the temperature increases, the ratio decreases, consistent with the previous finding that "temperature is more sensitive to cell delay than interconnect delay."

[0067] For RC (resistance-capacitance) process corners, the cell delay ratio satisfies Cmax > RCmin > RCmax > Cmin. "RCcorners" refers to process corners defined based on interconnect parasitic resistance (R) and capacitance (C) parameters, used to evaluate the impact of routing parasitics on delay. "Cmax / Cmin" typically refers to the extreme capacitance process corner (Cmax is the maximum capacitance, Cmin is the minimum capacitance), while "RCmin / RCmax" refers to the extreme resistance-capacitance combination process corner. RCmin represents low RC parasitics, and RCmax represents high RC parasitics. This ranking reflects the changing trend of the cell delay ratio under different RC conditions; the larger the capacitance and the lower the RC parasitics, the higher the relative proportion of cell delay.

[0068] To predict latency characteristics under different scenarios using machine learning models, and by learning patterns from historical data, latency prediction for any scenario can be completed instantly, reducing the analysis cycle from several days to hours, significantly improving design iteration speed. In a more preferred embodiment of the invention, step S4 further includes...

[0069] Step S44: Based on the historical data of the critical path, a machine learning model is used to predict latency characteristics under different scenarios. By replacing traditional scenario enumeration simulation with a machine learning model, latency characteristics under massive scenarios can be predicted quickly, such as under 1000 PVT scenario combinations, significantly shortening the timing analysis cycle. This is particularly suitable for chip designs with complex scenarios and a large number of paths under advanced processes, especially CPU and GPU chip designs at 7nm and below nodes. The trained model can be used to predict the latency characteristics of new critical paths in any scenario. Specific steps: Step S61: Input new path information to obtain the attributes of the critical path to be predicted, such as cell composition, interconnect length, R / C parameters, and target scenario parameters, such as process angle = SS, voltage = 0.9V, temperature = 125℃. Step S62: Feature transformation processes new features according to the rules used during training (such as standardization and one-hot encoding) to ensure the format is consistent with the training set. Step S63: Model prediction: Input the processed features into the model and output the pre-results, for example, cell latency = 1200ps, interconnect latency = 750ps, r = 1.6. Step S64, result calibration: Combine the rapid simulation results of EDA tools to verify the predicted top 10% deviation paths, fine-tune the predicted values, multiply by the correction factor, and improve engineering practicality.

[0070] The present invention also provides a system for performing the above-described critical path filtering method based on chip timing reports, the system comprising:

[0071] The acquisition module is used to acquire chip timing report data, wherein the chip timing report data includes at least the path start point, path end point, logic unit composition, and interconnect information in the critical path; interconnect delay data, unit delay data, and total delay data on each path; as well as timing indicator data and scenario information data; the timing indicator data includes timing margin, worst-case negative margin, and total negative margin;

[0072] The filtering module is used to filter the top N critical paths from the chip timing report data based on the worst-case negative margin in descending order, where N is a positive integer greater than 2; wherein the critical path includes at least cell delay, interconnect delay, scenario, worst-case negative margin, and total negative margin;

[0073] The modeling module is used to establish a three-dimensional data model of path ID-delay type-scene based on the critical path, and calculate the delay ratio r of unit delay to interconnect delay in each critical path;

[0074] The comparison module is used to compare the trends of unit latency and interconnect latency under different scenarios to identify the dominant latency type; it also analyzes the correlation between unit latency and interconnect latency under the same scenario to obtain latency characteristic data.

[0075] The system comprises four core modules: The acquisition module collects chip timing report data, covering the start and end points of critical paths, logic unit composition, interconnect information, interconnect latency, unit latency, and total latency for each path, as well as timing metric data including timing margin, worst-case margin, and total margin, and scenario information data; the filtering module selects the top N (N is a positive integer greater than 2) critical paths from the timing report data based on the worst-case margin in descending order. These paths include unit latency, interconnect latency, their respective scenarios, worst-case margin, and total margin; the modeling module constructs a 3D data model of path ID-latency type-scenario based on the critical paths and calculates the latency ratio r of unit latency to interconnect latency in each critical path; the comparison module identifies the dominant latency type by comparing the changing trends of unit latency and interconnect latency under different scenarios, and analyzes the correlation between the two under the same scenario, ultimately obtaining latency characteristic data. This system avoids redundancy in the entire dataset by automatically filtering the top N critical paths, thus improving analysis efficiency. Establishing a comparative system of interconnect delay (net delay), cell delay, and their ratio across multiple process corners allows for the quantification of delay variation patterns in different scenarios. By combining worst-case negative margin (WNS) and total negative margin (TNS), the actual impact of critical path delay on timing can be verified, guiding targeted optimization. This includes replacing high-speed cells for paths with a high proportion of cell delay and optimizing routing for paths with a high proportion of interconnect delay. Furthermore, through systematic evaluation across multiple process corners, the worst-case sign-off scenarios can be identified in advance, mitigating timing risks and avoiding disruptive modifications later in the project.

[0076] The present invention also provides an electronic device, comprising at least one processor; and

[0077] A memory communicatively connected to the at least one processor; wherein,

[0078] The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the method described above.

[0079] The present invention also provides a machine-readable storage medium storing instructions that cause a machine to perform the methods described above.

[0080] It should be noted that, for the sake of simplicity, the foregoing method embodiments are all described as a series of actions. However, those skilled in the art should understand that the present invention is not limited to the described order of actions, because according to the present invention, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions and modules involved are not necessarily essential to the present invention.

[0081] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0082] In the several embodiments provided by this invention, it should be understood that the disclosed apparatus can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical or other forms.

[0083] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0084] Furthermore, the functional units in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0085] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, mobile terminal, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks.

[0086] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A critical path selection method based on chip timing reports, characterized in that, The critical path filtering method based on chip timing reports includes: Step S1: Collect chip timing report data, wherein the chip timing report data includes at least the path start point, path end point, logic unit composition, and interconnect information in the critical path; interconnect delay data, unit delay data, and total delay data on each path; as well as timing indicator data and scenario information data; the timing indicator data includes timing margin, worst-case negative margin, and total negative margin; Step S2: Based on the worst-case negative margin, sort from largest to smallest and filter out the top N critical paths from the chip timing report data, where N is a positive integer greater than 2; wherein, the critical path includes at least cell delay, interconnect delay, scenario, worst-case negative margin, and total negative margin; Step S3: Establish a three-dimensional data model of path ID-delay type-scenario based on the critical path, and calculate the delay ratio r of unit delay to interconnect delay in each critical path; Step S4: Compare the trends of unit delay and interconnect delay under different scenarios to identify the dominant delay type; analyze the correlation between unit delay and interconnect delay under the same scenario to obtain delay characteristic data.

2. The critical path filtering method based on chip timing reports according to claim 1, characterized in that, In step S4, the following is included: Step S41: In the first N critical paths, under different scenarios, determine the dominant delay type as cell delay or interconnect delay by the rate of change.

3. The critical path filtering method based on chip timing reports according to claim 1, characterized in that, Step S2 includes adjusting the value of N according to the size of the chip circuit; if the size of the chip circuit reaches a preset condition, then N*P is adjusted, where P is an adjustment coefficient, and the adjustment coefficient is set according to the preset condition.

4. The critical path filtering method based on chip timing reports according to claim 1, characterized in that, In step S4, the following is included: Step S43: In each critical path, under the signal integrity scenario, calculate the difference between the unit delay and the interconnect delay to obtain RC condition impact comparison data.

5. The critical path filtering method based on chip timing reports according to any one of claims 1-4, characterized in that, In step S2, a data binning algorithm is used to divide all paths into multiple intervals according to the time margin, calculate the statistical value of the delay ratio r of all paths in each interval, and establish a functional relationship model between delay characteristics and path criticality.

6. The critical path filtering method based on chip timing reports according to claim 5, characterized in that, The critical path filtering method based on chip timing reports also includes... Step S5 involves visualizing and generating a report for each interval in the critical path, including at least the cell delay, interconnect delay, and delay ratio r.

7. The critical path filtering method based on chip timing reports according to claim 6, characterized in that, Step S4 also includes, Step S44: Based on the historical data of the critical path, a machine learning model is used to predict latency characteristic data under different scenarios.

8. A system for executing the critical path screening method based on chip timing reports as described in any one of claims 1-7, characterized in that, The system includes, The acquisition module is used to acquire chip timing report data, wherein the chip timing report data includes at least the path start point, path end point, logic unit composition, and interconnect information in the critical path; interconnect delay data, unit delay data, and total delay data on each path; as well as timing indicator data and scenario information data; the timing indicator data includes timing margin, worst-case negative margin, and total negative margin; The filtering module is used to filter the top N critical paths from the chip timing report data based on the worst-case negative margin in descending order, where N is a positive integer greater than 2; wherein the critical path includes at least cell delay, interconnect delay, scenario, worst-case negative margin, and total negative margin; The modeling module is used to establish a three-dimensional data model of path ID-delay type-scene based on the critical path, and calculate the delay ratio r of unit delay to interconnect delay in each critical path; The comparison module is used to compare the trends of unit latency and interconnect latency under different scenarios to identify the dominant latency type; it also analyzes the correlation between unit latency and interconnect latency under the same scenario to obtain latency characteristic data.

9. An electronic device, characterized in that, At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the critical path filtering method based on chip timing reports as described in any one of claims 1-7.

10. A machine-readable storage medium, characterized in that, The machine-readable storage medium stores instructions for causing the machine to execute the critical path filtering method based on chip timing reports as described in any one of claims 1-7.

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