A low-power high-reliability data verification circuit, method and nonvolatile memory

Abstract

The present application belongs to the technical field of large-scale digital integrated circuit, and particularly relates to a low-power-consumption high-reliability data verification circuit, method and nonvolatile memory. The low-power-consumption high-reliability data verification circuit comprises a verification enable register, a data verification enable control circuit, a state digital logic detection circuit, a verification register and a verification circuit. The data verification enable control circuit is responsible for managing and triggering data verification operation under the control of the verification enable register. The state digital logic detection circuit is used for calculating and storing n-bit binary actual state code values of all nonvolatile memories to be verified according to a verification logic algorithm. The verification register is used for storing n-bit binary ideal state code values under the condition that the stored data of the nonvolatile memories to be verified are all correct. The verification circuit is used for verifying and comparing the actual state code values output by the state digital logic detection circuit with the ideal state code values stored in the verification register. The present application provides a low-power-consumption, small-area, low-cost and high-reliability solution for nonvolatile memory programming and state correctness verification.

Description

Technical Field

[0001] This invention belongs to the field of large-scale digital integrated circuit technology, and specifically relates to a low-power, high-reliability data verification circuit, method, and non-volatile memory. Background Technology

[0002] In high-performance mixed-signal chips, non-volatile memory (NDRAM) is primarily used to store analog tuning values ​​for adjusting capacitors, resistors, and current, as well as digital factory calibration values ​​such as gain and offset calibration values. This helps overcome manufacturing process variations and defects, ensuring optimal performance for each chip before it leaves the factory. Furthermore, for security reasons, NDRAM in high-reliability chips also stores the chip's unique ID and encryption keys. Additionally, for system-on-a-chip (SoC), NDRAM also stores algorithm firmware, protocol stacks, and bootloader code. Therefore, the programming of NDRAM, as the final step before chip delivery, plays a crucial role in the chip's functionality and performance, and is vital for chip and device security.

[0003] However, due to factors such as environmental changes, temperature variations, and aging, data in non-volatile memories may become corrupted. Furthermore, the writing and programming of non-volatile memories, such as One-Time Programmable (OTP), fuses, and Programmable Read Only Memory (PROM), is a one-time, irreversible process. Therefore, to ensure the correctness of data stored in non-volatile memories throughout the entire chip's operating cycle, and to monitor the correctness of stored values ​​after writing to OTP, fuses, PROMs, and other non-volatile memories before shipment, it is crucial to design highly reliable non-volatile memory data verification methods.

[0004] Commonly used data verification algorithms for non-volatile memory include parity check and cyclic redundancy check. While parity check is simple to implement and has low hardware overhead, it can only detect odd-numbered bit errors and therefore does not have high reliability. Cyclic redundancy check, on the other hand, can detect burst errors, but in order to achieve a higher error detection rate, it uses a longer CRC, resulting in relatively large computational resources and transmission overhead. Therefore, it is not suitable for use in situations where hardware resources and bandwidth are limited. Summary of the Invention

[0005] The purpose of this invention is to provide a low-power, high-reliability data verification circuit, method, and non-volatile memory. This invention performs reliability verification on data in non-volatile memory with the lowest possible power consumption, area, and cost, thereby ensuring the functionality, performance, and security of chips and devices.

[0006] To address the aforementioned technical problems, this invention provides a low-power, high-reliability data verification circuit, comprising:

[0007] Verify the enable register;

[0008] The data verification enable control circuit is responsible for managing and triggering data verification operations under the control of the verification enable register.

[0009] A status digital logic detection circuit is used to calculate and store the n-bit binary actual status code value of all non-volatile memories to be verified according to a verification logic algorithm. The verification logic algorithm includes: the status code value output by the status digital logic operation circuit each time the address counter is updated is related to the previous status code value. Thus, after the output of the address counter traverses all register addresses, the n-bit binary actual status code value output by the status digital logic operation circuit can characterize the data characteristics of all non-volatile memories to be verified.

[0010] The check register is used to store the n-bit binary ideal status code value when all the data stored in the non-volatile memory to be checked is correct.

[0011] A verification circuit is used to verify and compare the actual status code value output by the status digital logic detection circuit with the ideal status code value stored in the verification register.

[0012] The verification status identifier register is used to store the comparison results output by the verification circuit.

[0013] Preferably, the state digital logic detection circuit includes:

[0014] An address counter is used to generate the addresses of all registers in the chip that need to be verified.

[0015] The address decoder converts the received register address into the selection signal for the corresponding register;

[0016] Registers are used to store data in non-volatile memory at different addresses that are to be verified.

[0017] A multiplexer, under the control of the address decoder, selects and outputs the stored data in the register corresponding to the address;

[0018] A state digital logic operation circuit is used to perform calculations on the data stored in the register corresponding to the address output by the multiplexer.

[0019] Preferably, when the data verification enable control circuit verifies the data in the non-volatile memory to be verified in the chip, it configures the verification enable register to generate enable and control signals for the state digital logic detection circuit, the verification circuit, and the verification state identifier register to trigger the data verification process.

[0020] Preferably, the verification operation is managed and triggered under the control of the verification enable register, so that the state digital logic detection circuit, the verification circuit and the verification state identifier register only work in the chip data verification mode, and are in a low-power reset state in the chip normal operation mode, i.e., in the non-data verification state.

[0021] Preferably, the n-bit binary actual status code value output by the status digital logic detection circuit has 8 bits.

[0022] Preferably, the state digital logic detection circuit includes:

[0023] Q n <0> The generation circuit includes: XOR gates XOR1~XOR3 and XNOR gates XNOR1~XNOR2; the two inputs of XOR gate XOR1 are respectively connected to signal Q. n-1 <0> and signal M n-1 <0> The two inputs of the XOR gate XOR2 are respectively connected to signal Q. n-1 <6> and signal M n-1 <6> The outputs of XOR gates XOR1 and XOR2 are respectively connected to the two inputs of XNOR gate XNOR2; the two inputs of XNOR gate XNOR1 are respectively connected to signal Q. n-1 <7> and signal M n-1 <7> The outputs of the XNOR gates XNOR1 and XNOR2 are connected to the two inputs of the XOR gate XOR3, and the output of the XOR gate XOR3 outputs signal Q. n <0> ;

[0024] Q n <1> The generation circuit includes: XOR gates XOR4~XOR6 and XNOR gates XNOR3~XNOR4; the two inputs of XOR gate XOR4 are respectively connected to signal Q. n-1 <0> and signal M n-1 <0> The two inputs of the XOR gate XOR5 are respectively connected to signal Q. n-1 <6> and signal M n-1 <6> The outputs of XOR gates XOR4 to XOR5 are connected to the two inputs of XNOR gate XNOR4, respectively; the two inputs of XNOR gate XNOR3 are connected to signal Q. n-1 <1> and signal M n-1<1> The outputs of the XNOR gates XNOR3 to XNOR4 are connected to the two inputs of the XOR gate XOR6, and the output of the XOR gate XOR6 outputs signal Q. n <1> ;

[0025] Q n <2> The generation circuit includes: XOR gates XOR7~XOR9 and XNOR gates XNOR5~XNOR8; the two inputs of XOR gate XOR7 are respectively connected to signal Q. n-1 <0> and signal M n-1 <0> The two inputs of the XOR gate XOR8 are respectively connected to signal Q. n-1 <6> and signal M n-1 <6> The outputs of XOR gates XOR7~XOR8 are connected to the two inputs of XNOR gate XNOR7, respectively; the two inputs of XNOR gate XNOR5 are connected to signal Q. n-1 <2> and signal M n-1 <2> The two inputs of the XNOR gate XNOR6 are respectively connected to signal Q. n-1 <1> and signal M n-1 <1> The outputs of XNOR gates XNOR5~XNOR6 are connected to the two inputs of XOR gate XOR9, respectively; the outputs of XNOR gates XNOR7 and XOR gate XOR9 are connected to the two inputs of XNOR gate XNOR8, respectively; the output of XNOR gate XNOR8 outputs signal Q. n <2> ;

[0026] Q n <3> The generation circuit includes: XOR gates XOR10~XOR12 and XNOR gates XNOR9~XNOR12; the two inputs of the XNOR gate XNOR9 are respectively connected to signal Q. n-1 <3> and signal M n-1 <3> The two inputs of the XNOR gate XNOR10 are respectively connected to signal Q. n-1 <2> and signal M n-1 <2> The outputs of XNOR gates XNOR9~XNOR10 are connected to the two inputs of XOR gate XOR10, respectively; the two inputs of XNOR gate XNOR11 are connected to signal Q, respectively. n-1 <1> and signal M n-1 <1> The two inputs of the XNOR gate XNOR12 are respectively connected to signal Q. n-1 <7> and signal M n-1 <7> The outputs of XNOR gates XNOR11 to XNOR12 are connected to the two inputs of XOR gate XOR11, respectively; the outputs of XOR gates XOR10 to XOR11 are connected to the two inputs of XOR gate XOR12, and the output of XOR gate XOR12 outputs signal Q. n <3> ;

[0027] Q n <4> The generation circuit includes: an XOR gate XOR13 and XNOR gates XNOR13~XNOR16; the two inputs of the XNOR gate XNOR13 are respectively connected to signal Q. n-1 <3> and signal M n-1 <3> The two inputs of the XNOR gate XNOR14 are respectively connected to signal Q. n-1 <4> and signal M n-1 <4> The two inputs of the XNOR15 gate are respectively connected to signal Q. n-1 <2> and signal M n-1 <2> The outputs of XNOR gates XNOR13 to XNOR14 are connected to the two inputs of XNOR gate XNOR16, respectively; the outputs of XNOR gates XNOR15 to XNOR16 are connected to the two inputs of XOR gate XOR13, respectively; the output of XOR gate XOR13 outputs signal Q. n <4> ;

[0028] Q n <5> The generation circuit includes: an XOR gate XOR14 and XNOR gates XNOR17~XNOR20; the two inputs of the XNOR gate XNOR17 are respectively connected to signal Q. n-1 <3> and signal M n-1 <3> The two inputs of the XNOR18 gate are respectively connected to signal Q. n-1 <4> and signal M n-1 <4> The two inputs of the XNOR19 gate are respectively connected to signal Q. n-1 <5> and signal M n-1 <5> The outputs of XNOR gates XNOR17~XNOR18 are connected to the two inputs of XNOR gate XNOR20, respectively; the outputs of XNOR gates XNOR19~XNOR20 are connected to the two inputs of XOR gate XOR14, respectively; the output of XOR gate XOR14 outputs signal Q. n <5> ;

[0029] Q n <6> The generation circuit includes: XOR gates XOR15~XOR17 and XNOR gates XNOR21~XNOR22; the two inputs of XOR gate XOR15 are respectively connected to signal Q. n-1 <6> and signal M n-1 <6> The two inputs of the XNOR21 gate are respectively connected to signal Q. n-1 <5> and signal M n-1 <5> The two inputs of the XNOR22 gate are respectively connected to signal Q. n-1 <4> and signal M n-1<4> The outputs of XOR gate XOR15 and XNOR gate XNOR21 are connected to the two inputs of XOR gate XOR16, respectively; the outputs of XOR gate XOR16 and XNOR gate XNOR22 are connected to the two inputs of XOR gate XOR17, respectively; the output of XOR gate XOR17 outputs signal Q. n <6> ;

[0030] Q n <7> The generation circuit includes: XOR gates XOR18~XOR20 and XNOR gates XNOR23~XNOR24; the two inputs of XOR gate XOR18 are respectively connected to signal Q. n-1 <6> and signal M n-1 <6> The two inputs of the XNOR23 gate are respectively connected to signal Q. n-1 <5> and signal M n-1 <5> The two inputs of the XNOR24 gate are respectively connected to signal Q. n-1 <7> and signal M n-1 <7> The outputs of XOR gate XOR18 and XNOR gate XNOR23 are connected to the two inputs of XOR gate XOR19, respectively; the outputs of XOR gate XOR19 and XNOR gate XNOR24 are connected to the two inputs of XOR gate XOR20, respectively; the output of XOR gate XOR20 outputs signal Q. n <7> .

[0031] Preferably, the verification circuit includes: AND gates AND1~AND5, NAND gates NAND1~NAND2, NOT gates NOT1~NOT7, OR gates OR1~OR4, NOR gates NOR1~NOR4, XOR gates XOR21~XOR22, and XNOR gates XNOR25~XNOR26; the input of NOT gate NOT1 is connected to signal Q. state <2> The output of NOT1 and signal Q ideal <2> Connect the two inputs of AND gate AND1 respectively; connect the signal Q to the input of NOT gate NOT2. state <1> The output of NOT2 and the signal Q ideal <1> The signals are connected to the two inputs of AND gate AND2 respectively; the outputs of AND gates AND1 and AND2 are connected to the two inputs of OR gate OR1 respectively; signal Q state <0> and signal Q ideal <0> Connect the two inputs of the XOR gate 21 to the XOR gate; connect the signal Q to the input of the NOT gate 3. ideal <1> The output of NOT3 and the signal Q state <1> Connect the two inputs of AND gate AND3 respectively; connect the signal Q to the input of NOT gate NOT4. ideal <2> The output of NOT2 and the signal Qstate <2> The outputs of AND gates AND3 through AND4 are connected to the two inputs of OR gate OR2, and the outputs of OR gates OR1 through OR2 and XOR gate XOR1 are connected to the three inputs of NOR gate NOR1. Signal Q... state <3> and signal Q ideal <3> The outputs of the NOR gate (XNOR25), the NOR gate (NOR1), the NOR gate (XNOR25), and the OR gate (OR3) are respectively connected to the three inputs of the NAND gate (NAND1); signal Q... state <5> and signal Q ideal <5> Connect the two inputs of the XOR gate 22 to the XOR gate; connect the signal Q to the input of the NOT gate 5. state <4> , signal Q ideal <4> The output of NOT gate 5 is connected to the two inputs of AND gate 5 and OR gate 3, respectively; the outputs of NAND gate 1, XOR gate 22, and AND gate 5 are connected to the three inputs of NOR gate 2, respectively; signal Q ideal <6> and signal Q state <6> Connect the two inputs of the XNOR26 gate respectively; signal Q state <7> and signal Q ideal <7> Connect the inputs of NOT gates NOT6~NOT7, the output of NOT gate 6, and signal Q respectively. ideal <7> Connect the two inputs of the NOR gate NOR3, the output of the NOT gate NOT7, and the signal Q respectively. state <7> The outputs of NOR gate XNOR26 and NOR gates NOR2~NOR3 are respectively connected to the three inputs of NAND gate NAND2. The outputs of NAND gate NAND1 and NOR gate NOR4 are respectively connected to the two inputs of OR gate OR4. The output of OR gate OR4 outputs signal Q. ver .

[0032] This invention provides a low-power, high-reliability data verification method, employing a low-power, high-reliability data verification circuit as described above, comprising:

[0033] After the non-volatile memory to be verified has been programmed and the binary ideal status code value stored in the verification register has been confirmed to be correct, the verification enable register is configured and the data verification process of the non-volatile memory to be verified begins.

[0034] The address counter first traverses the register addresses of the non-volatile memory to be verified. Then, the address decoder converts the received address into the selection signal of the register of the non-volatile memory to be verified at the corresponding address, and outputs the data stored in the register of the non-volatile memory to be verified at the corresponding address through the multiplexer.

[0035] The status digital logic operation circuit calculates the actual status code value of the non-volatile memory to be verified based on the data output from the multiplex register. This status code value is sent to the verification circuit and compared with the ideal status code value stored in the verification register. Finally, the comparison result is stored in the verification status identifier register.

[0036] This invention provides an application of non-volatile memory, employing a low-power, high-reliability data verification method as described above.

[0037] Preferably, the non-volatile memory is a fuse.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The verification algorithm employed in this invention can completely avoid false positives, as long as the data in the non-volatile memory storing the n-bit binary ideal status code is correct, thus exhibiting extremely high reliability. If the data in the non-volatile memory flips due to non-ideal factors such as temperature or aging, engineers and users can promptly detect this by reading the value of the verification register. Unlike parity checks and CRC checks, the verification algorithm does not require adding redundant bits to the original data for error detection. Therefore, it achieves verification of non-volatile memory data with lower cost, area, and power consumption, ensuring the reliability, functional integrity, and security of the chip. The verification algorithm of this invention is relatively simple, highly reliable, and has a wide range of applications, covering not only all chips using non-volatile memory to store data but also extending to other data verification fields. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of a low-power, high-reliability data verification circuit provided in an embodiment of the present invention.

[0041] Figure 2 A flowchart for non-volatile memory data verification provided in an embodiment of the present invention.

[0042] Figure 3 The logic circuit for the relationship between binary status codes and input data provided in the embodiments of the present invention Figure 1 ; where (a)~(d) are Q respectively. n <0> To Q n <3> Generation circuit.

[0043] Figure 4 The logic circuit for the relationship between binary status codes and input data provided in the embodiments of the present invention Figure 2 ; where (e)~(h) are Q respectively. n <4> To Q n <7> Generation circuit.

[0044] Figure 5 The schematic diagram of the verification circuit provided in the embodiment of the present invention. Detailed Implementation

[0045] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0046] This invention can be applied not only to all chips that use non-volatile memory to store critical data, but also to other data verification fields. To more clearly illustrate the purpose, technical solution, and advantages of this invention, the following description uses a data verification circuit applied to a mixed-signal chip containing fuses storing analog adjustment values ​​and digital calibration data to provide a more detailed explanation.

[0047] like Figure 1 The diagram shows a low-power, high-reliability data verification circuit system block diagram for non-volatile memory. When a user or engineer needs to verify the data stored in the non-volatile memory to be verified, the verification enable register must first be configured. After configuration, the data verification enable control circuit triggers the verification process, generating enable and control signals. Under its control, the address counter in the state digital logic detection circuit sequentially outputs the register addresses of all non-volatile memories to be verified. The address decoder receives the address output by the address counter and converts it into a selection signal for the corresponding register of the non-volatile memory to be verified. The multiplexer, based on the selection signal generated by the decoder, outputs the data stored in the register of the corresponding non-volatile memory to be verified and sends it to the state digital logic operation circuit for calculation.

[0048] As a preferred embodiment of the invention, the non-volatile memory is specifically a fuse.

[0049] Figure 3 and Figure 4The logic circuit diagram showing the relationship between the 8-bit binary code output by the state digital logic operation circuit and the input data (8 bits in this embodiment of the invention, n bits of the non-volatile memory to be verified, n needs to be designed with different numbers of bits according to different application requirements, taking into account hardware overhead and fault tolerance. The more bits of the state code, i.e., the larger n is, the higher the fault tolerance, the more complex the verification logic algorithm, and the larger the circuit scale).

[0050] The data verification enable control circuit, under the control of the verification enable register, manages and triggers the verification operation, ensuring that the state digital logic detection circuit, verification circuit, and verification status flag register of the non-volatile memory to be verified only operate normally in the data verification mode of the non-volatile memory to be verified in the chip, and are in a reset state at other times. It can perform the verification function on the non-volatile memory to be verified in the chip while keeping the power consumption increase during normal chip operation at an extremely low level.

[0051] The status digital logic detection circuit module uses an address counter to traverse all addresses to be verified, eliminating the need for complex calculations. This results in high efficiency when accessing consecutive addresses and a low probability of address errors. The module employs an address decoder to convert the received address into a selection signal for the corresponding non-volatile memory register to be verified. A multiplexer then outputs the data stored in the register of the corresponding non-volatile memory, greatly simplifying complex circuit connections and the system, optimizing hardware resource utilization, and improving overall system efficiency.

[0052] Because the check register stores the ideal value of the n-bit binary status code assuming all data stored in the non-volatile memory to be checked is correct, it reduces the software overhead of checking the non-volatile memory to be checked and effectively prevents software tampering, resulting in high reliability. The check circuit can reliably verify and compare the actual status code of the non-volatile memory to be checked with the ideal status code stored in the check register using relatively simple algorithm logic at the cost of low hardware overhead.

[0053] The verification status register stores the verification results, which allows engineers to promptly obtain the programming status of the non-volatile memory before shipment, and allows users to understand whether the values ​​stored in the non-volatile memory are correct throughout the chip's life cycle, effectively improving the chip's reliability.

[0054] Figure 3 and Figure 4 The relationship between the 8-bit binary code and the input data can be represented by equations (1)-(8) in Table 1 below. Equations (1)-(8) also accurately describe the function of the state logic digital logic operation circuit. In the equations, Q n This indicates the i-th binary bit output by the state digital logic circuit when the nth address is valid, M. n <j>This indicates that when the nth address is valid, the jth bit of the binary code output by the multiplexer is greater than or equal to 1 in equations (1)-(8).

[0055] Table 1

[0056]

[0057] From equations (1) to (8), it can be seen that since the binary status code output by the state digital logic operation circuit when the nth address is valid is related to the status code output when the (n-1)th address is valid, after the address counter output traverses all register addresses of the non-volatile memory to be verified, the 8-bit binary status code output by the state digital logic operation circuit can characterize the actual data stored in the registers of all the non-volatile memory to be verified, thus the verification result has extremely high reliability. In order to ensure that the state digital logic operation circuit can work normally, before it performs state operations, Q... n and M n <j>All require an initial value; in this embodiment of the invention, Q... n initial value Q0 The code is FF, M (8-bit hexadecimal). n <j>initial value M0 <j>It is an 8-bit hexadecimal code C0.

[0058] In addition, such as Figure 3 and Figure 4 As shown, in the data verification mode of the non-volatile memory to be verified, the status digital logic operation circuit calculates the status code in real time when the address counter is updated. However, the operation of the verification circuit is regulated by the data verification enable control circuit. Specifically, after the address counter traverses all register addresses of the non-volatile memory to be verified, the verification circuit compares the final status code calculated by the status digital logic operation circuit with the ideal status code.

[0059] Figure 5 The schematic diagram of the verification circuit is shown. The logic function of the verification circuit can be represented by equation (9) in Table 2 below. Where Q ver Q represents the verification status output by the verification circuit. state <k>This indicates that after the address counter outputs its output through all the register addresses of the non-volatile memory to be verified, the k-th bit of the 8-bit status code output by the status digital logic circuit, Q, is... ideal <m>This represents the m-th bit of the 8-bit binary ideal status code pre-stored in the check register.

[0060] Table 2

[0061]

[0062] like Figure 5 As shown, when the 8-bit binary status code finally output by the state digital logic operation circuit matches the pre-stored binary ideal status code in the verification register, the Q output by the verification circuit... ver A value of 0 indicates that the non-volatile memory was successfully programmed and the data stored in the non-volatile memory is correct; otherwise, Q... ver The value is 1. Finally, after completing the state comparison, Q... ver The data will be stored in the verification status register, allowing engineers to quickly obtain information about the non-volatile memory's programming status before shipment, and enabling users to easily determine whether the values ​​stored in the non-volatile memory are correct. The verification algorithm proposed in this invention does not require adding redundant bits to the original data like parity checks and CRC checks to achieve error detection, offering advantages such as low power consumption, small area, and low cost.

[0063] Figure 2 A flowchart of the verification process for this implementation case is provided. Figure 2 As shown, the verification process is as follows: After the non-volatile memory to be verified is programmed and the binary ideal status code value stored in the verification register is confirmed to be correct, the verification enable register is configured, and the data verification process of the non-volatile memory to be verified begins.

[0064] The address counter first traverses the register addresses of the non-volatile memory to be verified. Then, the address decoder converts the received address into the selection signal of the register of the non-volatile memory to be verified at the corresponding address, and outputs the data stored in the register of the non-volatile memory to be verified at the corresponding address through the multiplexer.

[0065] The status digital logic operation circuit calculates the actual status code value of the non-volatile memory to be verified based on the data output from the multiplex register. This status code value is sent to the verification circuit and compared with the ideal status code value stored in the verification register. Finally, the comparison result is stored in the verification status identifier register.

[0066] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.< / m> < / k> < / j> < / j> < / j> < / j>

Claims

1. A low-power, high-reliability data verification circuit, characterized in that, include: Verify the enable register; The data verification enable control circuit is responsible for managing and triggering data verification operations under the control of the verification enable register. The status digital logic detection circuit is used to calculate and store the n-bit binary actual status code value of all non-volatile memories to be verified according to the verification logic algorithm. The verification logic algorithm includes: the status code value output by the status digital logic operation circuit is related to the previous status code value each time the address counter is updated, so that after the output of the address counter traverses all register addresses, the n-bit binary actual status code value output by the status digital logic operation circuit can characterize the data characteristics of all non-volatile memories to be verified. The check register is used to store the n-bit binary ideal status code value when all the data stored in the non-volatile memory to be checked is correct. A verification circuit is used to verify and compare the actual status code value output by the status digital logic detection circuit with the ideal status code value stored in the verification register. A verification status identifier register is used to store the comparison results output by the verification circuit; The state digital logic detection circuit includes: An address counter is used to generate the addresses of all registers in the chip that need to be verified. The address decoder converts the received register address into the selection signal for the corresponding register; Registers are used to store data in non-volatile memory at different addresses that are to be verified. A multiplexer, under the control of the address decoder, selects and outputs the stored data in the register corresponding to the address; A state digital logic operation circuit is used to perform calculations on the data stored in the register corresponding to the address output by the multiplexer.

2. The low-power, high-reliability data verification circuit as described in claim 1, characterized in that, When the data verification enable control circuit verifies the data in the non-volatile memory to be verified in the chip, it configures the verification enable register to generate enable and control signals for the state digital logic detection circuit, the verification circuit, and the verification state identifier register to trigger the data verification process.

3. The low-power, high-reliability data verification circuit as described in claim 2, characterized in that, Under the control of the verification enable register, the verification operation is managed and triggered so that the state digital logic detection circuit, the verification circuit and the verification state identifier register only work in the chip data verification mode, and are in a low-power reset state in the chip normal operation mode, i.e., in the non-data verification state.

4. The low-power, high-reliability data verification circuit as described in claim 1, characterized in that, The n-bit binary actual status code value output by the state digital logic detection circuit has 8 bits.

5. The low-power, high-reliability data verification circuit as described in claim 1, characterized in that, The state digital logic detection circuit includes: Q n <0> The generation circuit includes: XOR gates (XOR1~XOR3) and XNOR gates (XNOR1~XNOR2); the two inputs of the XOR gate (XOR1) are respectively connected to signal Q. n-1 <0> and signal M n-1 <0> The two inputs of the XOR gate (XOR2) are respectively connected to signal Q. n-1 <6> and signal M n-1 <6> The outputs of the XOR gates (XOR1~XOR2) are connected to the two inputs of the XNOR gate (XNOR2); the two inputs of the XNOR gate (XNOR1) are connected to the signal Q. n-1 <7> and signal M n-1 <7> The outputs of the XNOR gates (XNOR1~XNOR2) are connected to the two inputs of the XOR gate (XOR3), and the output of the XOR gate (XOR3) is the signal Q. n <0> ; Q n <1> The generation circuit includes: XOR gates (XOR4~XOR6) and XNOR gates (XNOR3~XNOR4); the two inputs of the XOR gate (XOR4) are respectively connected to signal Q. n-1 <0> and signal M n-1 <0> The two inputs of the XOR gate (XOR5) are respectively connected to signal Q. n-1 <6> and signal M n-1 <6> The outputs of the XOR gates (XOR4~XOR5) are connected to the two inputs of the XNOR gate (XNOR4); the two inputs of the XNOR gate (XNOR3) are connected to the signal Q. n-1 <1> and signal M n-1 <1> The outputs of the XNOR gates (XNOR3~XNOR4) are connected to the two inputs of the XOR gate (XOR6), and the output of the XOR gate (XOR6) outputs signal Q. n <1> ; Q n <2> The generation circuit includes: XOR gates (XOR7~XOR9) and XNOR gates (XNOR5~XNOR8); the two inputs of the XOR gate (XOR7) are respectively connected to signal Q. n-1 <0> and signal M n-1 <0> The two inputs of the XOR gate (XOR8) are respectively connected to signal Q. n-1 <6> and signal M n-1 <6> The outputs of the XOR gates (XOR7~XOR8) are connected to the two inputs of the XNOR gate (XNOR7); the two inputs of the XNOR gate (XNOR5) are connected to the signal Q. n-1 <2> and signal M n-1 <2> The two inputs of the XNOR gate (XNOR6) are respectively connected to signal Q. n-1 <1> and signal M n-1 <1> The outputs of the XNOR gates (XNOR5~XNOR6) are connected to the two inputs of the XOR gate (XOR9); the outputs of the XNOR gates (XNOR7) and XOR gates (XOR9) are connected to the two inputs of the XNOR gate (XNOR8); the output of the XNOR gate (XNOR8) outputs signal Q. n <2> ; Q n <3> The generation circuit includes: XOR gates (XOR10~XOR12) and XNOR gates (XNOR9~XNOR12); the two inputs of the XNOR gate (XNOR9) are respectively connected to signal Q. n-1 <3> and signal M n-1 <3> The two inputs of the XNOR gate (XNOR10) are respectively connected to signal Q. n-1 <2> and signal M n-1 <2> The outputs of the XNOR gates (XNOR9~XNOR10) are connected to the two inputs of the XOR gate (XOR10); the two inputs of the XNOR gate (XNOR11) are connected to the signal Q. n-1 <1> and signal M n-1 <1> The two inputs of the XNOR gate (XNOR12) are respectively connected to signal Q. n-1 <7> and signal M n-1 <7> The outputs of the XNOR gates (XNOR11~XNOR12) are connected to the two inputs of the XOR gate (XOR11); the outputs of the XOR gates (XOR10~XOR11) are connected to the two inputs of the XOR gate (XOR12); the output of the XOR gate (XOR12) is the signal Q. n <3> ; Q n <4> The generation circuit includes: an XOR gate (XOR13) and a NAND gate (XNOR13~XNOR16); the two inputs of the NAND gate (XNOR13) are respectively connected to signal Q. n-1 <3> and signal M n-1 <3> The two inputs of the XNOR gate (XNOR14) are respectively connected to signal Q. n-1 <4> and signal M n-1 <4> The two inputs of the XNOR gate (XNOR15) are respectively connected to signal Q. n-1 <2> and signal M n-1 <2> The outputs of the XNOR gates (XNOR13~XNOR14) are connected to the two inputs of the XNOR gate (XNOR16); the outputs of the XNOR gates (XNOR15~XNOR16) are connected to the two inputs of the XOR gate (XOR13); the output of the XOR gate (XOR13) is the signal Q. n <4> ; Q n <5> The generation circuit includes: an XOR gate (XOR14) and a NAND gate (XNOR17~XNOR20); the two inputs of the NAND gate (XNOR17) are respectively connected to signal Q. n-1 <3> and signal M n-1 <3> The two inputs of the XNOR gate (XNOR18) are respectively connected to signal Q. n-1 <4> and signal M n-1 <4> The two inputs of the XNOR gate (XNOR19) are respectively connected to signal Q. n-1 <5> and signal M n-1 <5> The outputs of the XNOR gates (XNOR17~XNOR18) are connected to the two inputs of the XNOR gate (XNOR20); the outputs of the XNOR gates (XNOR19~XNOR20) are connected to the two inputs of the XOR gate (XOR14); the output of the XOR gate (XOR14) is the signal Q. n <5> ; Q n <6> The generation circuit includes: XOR gates (XOR15~XOR17) and XNOR gates (XNOR21~XNOR22); the two inputs of the XOR gate (XOR15) are respectively connected to signal Q. n-1 <6> and signal M n-1 <6> The two inputs of the XNOR gate (XNOR21) are respectively connected to signal Q. n-1 <5> and signal M n-1 <5> The two inputs of the XNOR gate (XNOR22) are respectively connected to signal Q. n-1 <4> and signal M n-1 <4> The outputs of the XOR gate (XOR15) and the XNOR gate (XNOR21) are connected to the two inputs of the XOR gate (XOR16); the outputs of the XOR gate (XOR16) and the XNOR gate (XNOR22) are connected to the two inputs of the XOR gate (XOR17); the output of the XOR gate (XOR17) is the signal Q. n <6> ; Q n <7> The generation circuit includes: XOR gates (XOR18~XOR20) and XNOR gates (XNOR23~XNOR24); the two inputs of the XOR gate (XOR18) are respectively connected to signal Q. n-1 <6> and signal M n-1 <6> The two inputs of the XNOR gate (XNOR23) are respectively connected to signal Q. n-1 <5> and signal M n-1 <5> The two inputs of the XNOR gate (XNOR24) are respectively connected to signal Q. n-1 <7> and signal M n-1 <7> The outputs of the XOR gate (XOR18) and the XNOR gate (XNOR23) are connected to the two inputs of the XOR gate (XOR19); the outputs of the XOR gate (XOR19) and the XNOR gate (XNOR24) are connected to the two inputs of the XOR gate (XOR20); the output of the XOR gate (XOR20) is the signal Q. n <7> .

6. The low-power, high-reliability data verification circuit as described in claim 1, characterized in that, The verification circuit includes: AND gates (AND1~AND5), NAND gates (NAND1~NAND2), NOT gates (NOT1~NOT7), OR gates (OR1~OR4), NOR gates (NOR1~NOR4), XOR gates (XOR21~XOR22), and XNOR gates (XNOR25~XNOR26); the input of NOT gate (NOT1) is connected to signal Q. state <2> The output of the NOT1 gate and the signal Q ideal <2> Connect the two inputs of the AND gate (AND1) to the input of the NOT gate (NOT2); connect the signal Q to the input of the NOT gate (NOT2). state <1> The output of the NOT gate (NOT2) and the signal Q ideal <1> Connect the two inputs of AND gate (AND2) respectively; connect the outputs of AND gates (AND1~AND2) to the two inputs of OR gate (OR1) respectively; signal Q state <0> and signal Q ideal <0> Connect the two inputs of the XOR gate (XOR21) respectively; connect the input of the NOT gate (NOT3) to the signal Q. ideal <1> The output of the NOT3 gate and the signal Q state <1> Connect the two inputs of the AND gate (AND3) to the input of the NOT gate (NOT4); connect the signal Q to the input of the NOT gate. ideal <2> The output of the NOT gate (NOT2) and the signal Q state <2> The outputs of AND gates (AND3~AND4) are connected to the two inputs of OR gate (OR2); the outputs of OR gates (OR1~OR2) and XOR gate (XOR21) are connected to the three inputs of NOR gate (NOR1); signal Q state <3> and signal Q ideal <3> The two inputs of the XNOR gate (XNOR25) are connected to the outputs of the NOR gate (NOR1), XNOR gate (XNOR25), and OR gate (OR3), respectively; the three inputs of the NAND gate (NAND1) are connected to the outputs of the NOR gate (NAND1), respectively; signal Q state <5> and signal Q ideal <5> Connect the two inputs of the XOR gate (XOR22) to the inputs of the NOT gate (NOT5); connect the signal Q to the input of the NOT gate. state <4> , signal Q ideal <4> The output of NOT5 is connected to the two inputs of AND5 and OR3, respectively; the outputs of NAND1, XOR22, and AND5 are connected to the three inputs of NOR2, respectively; signal Q ideal <6> and signal Q state <6> Connect the two inputs of the XNOR gate (XNOR26) respectively; signal Q state <7> and signal Q ideal <7> Connect the input terminals of NOT gates (NOT6~NOT7), the output terminal of NOT gate (NOT6), and signal Q respectively. ideal <7> Connect the two inputs of the NOR gate (NOR3), the output of the NOT gate (NOT7), and the signal Q, respectively. state <7> The outputs of the NOR gate (NOR4) and the NOR gate (XNOR26) and the NOR gate (NOR2~NOR3) are respectively connected to the three inputs of the NAND gate (NAND2). The outputs of the NAND gate (NAND1) and the NOR gate (NOR4) are respectively connected to the two inputs of the OR gate (OR4). The output of the OR gate (OR4) outputs signal Q. ver .

7. A low-power, high-reliability data verification method, characterized in that, The low-power, high-reliability data verification circuit as described in any one of claims 1 to 6 includes: After the non-volatile memory to be verified has been programmed and the binary ideal status code value stored in the verification register has been confirmed to be correct, the verification enable register is configured and the data verification process of the non-volatile memory to be verified begins. The address counter first traverses the register addresses of the non-volatile memory to be verified. Then, the address decoder converts the received address into the selection signal of the register of the non-volatile memory to be verified at the corresponding address, and outputs the data stored in the register of the non-volatile memory to be verified at the corresponding address through the multiplexer. The status digital logic operation circuit calculates the actual status code value of the non-volatile memory to be verified based on the data output from the multiplex register. This status code value is sent to the verification circuit and compared with the ideal status code value stored in the verification register. Finally, the comparison result is stored in the verification status identifier register.

8. An application of a non-volatile memory, characterized in that, The low-power, high-reliability data verification method described in claim 7 is adopted.

9. The application of a non-volatile memory as described in claim 8, characterized in that, The non-volatile memory is a fuse.

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