Data programming method and device for flash memory

Abstract

The invention discloses a data programming method and device for a flash memory, and the method comprises the steps: determining the number of invalid logic pages in a physical page according to the original data and the current data of the physical page before the fine programming of any physical page of the flash memory; wherein the original data is data corresponding to the physical page when coarse programming of the physical page is completed, and the current data is data corresponding to the physical page before fine programming of the physical page; when the number of the invalid logic pages is larger than 1 and smaller than the total number of the logic pages, determining a special invalid programming state, a general invalid programming state, a special valid programming state and a general valid programming state in multiple programming states according to the invalid logic pages; when fine programming operation is carried out on the physical page, the verification voltage of the special invalid programming state is converted into the verification voltage of the corresponding special valid programming state, and the verification period of the general invalid programming state is removed.

Description

Technical Field

[0001] This application relates to the field of memory technology, and in particular to a data programming method and apparatus for flash memory. Background Technology

[0002] Flash memory is a commonly used type of memory. Taking 3DQLC NAND flash memory as an example, each storage cell in this flash memory can store 4 bits of binary data, corresponding to 2 to the power of 4, or 16 different programming states. These 16 different programming states will correspond to different distributions from ER to P1516 depending on the Gray code scheme used.

[0003] Two-step coarse-fine programming is a common data programming method for flash memory. In this method, the process of programming data into the flash memory (i.e., writing to the flash memory) can be divided into two stages: coarse programming and fine programming. In coarse programming, the threshold voltage of each cell in each physical page of the flash memory is roughly programmed to a position slightly below the target distribution state. In fine programming, each cell in each physical page of the flash memory is finely programmed, causing the threshold voltage distribution state of each cell to shift further to the right towards the target distribution state, and appropriately narrowing and widening the distribution state. The target distribution state refers to the distribution state corresponding to the programming state to be stored in the cell. For example, if a cell is to store data 1011, the target distribution state of the cell is the distribution state P1 corresponding to the programming state 1011.

[0004] This data programming method may suffer from invalid programming issues. In this method, for each physical page, coarse programming of all storage units within that page must be completed first, followed by coarse programming of the next physical page's storage units. Fine programming of the previous physical page's storage units can only occur during the coarse programming of the next physical page. Therefore, there is a time lag between the completion of coarse programming and the start of fine programming within a physical page (this time lag can be called the programming window). This means that when fine programming a storage unit, the data in that storage unit may be updated compared to the data at the time of coarse programming, causing that data to become invalid. However, since the storage units in the previous physical page have already undergone coarse programming using the original data before the update, the distribution of storage units in the physical page, while slightly lower than the target distribution, is already roughly sized. Therefore, the updated data cannot be directly used for fine programming; the original data must still be used. For the updated data, a "remote update" strategy is adopted, programming is performed in a subsequent new storage location. In the above process, because the original data is still used during fine programming, invalid programming of this invalid data occurs, resulting in a waste of programming time and performance. Summary of the Invention

[0005] Therefore, this application discloses the following technical solution:

[0006] The first aspect of this application provides a data programming method for a flash memory, comprising:

[0007] Before fine programming any physical page of the flash memory, the number of invalid logical pages in the physical page is determined based on the original data and current data of the physical page; wherein, the original data is the data corresponding to the physical page when coarse programming of the physical page is completed, and the current data is the data corresponding to the physical page before fine programming of the physical page;

[0008] When the number of invalid logical pages is greater than 1 and less than the total number of logical pages, a special invalid programming state, a general invalid programming state, a special valid programming state, and a general valid programming state are determined based on the invalid logical pages.

[0009] When performing fine programming on the physical page, the verification voltage of the special invalid programming state is converted into the verification voltage of the corresponding special valid programming state, and the verification cycle of the general invalid programming state is removed.

[0010] Optionally, determining the specific invalid programming state, general invalid programming state, specific valid programming state, and general valid programming state among multiple programming states based on the invalid logical page includes:

[0011] Determine the first read voltage of the invalid logic page;

[0012] The left and right read voltages of each programming state are compared with the first read voltage. Based on the comparison results, each programming state is determined to be a special invalid programming state, a general invalid programming state, a special valid programming state, or a general valid programming state.

[0013] Optional, also includes:

[0014] When the number of invalid logical pages is 1, a special invalid programming state, a special valid programming state, and a general valid programming state are determined from the invalid logical pages.

[0015] Optional, also includes:

[0016] Before fine-programming the physical page, the verification voltage of the special effective programming state is adjusted according to the cold data static data transfer cycle of the flash memory and the correspondence between the data retention time of the flash memory and the threshold voltage offset of different programming states, so as to perform fine-programming based on the adjusted verification voltage.

[0017] Optional, also includes:

[0018] For each programming cycle during fine programming, if the verification cycle from the end of the programming cycle to the beginning of the next programming cycle is a verification cycle in a general invalid programming state, then the programming cycle is removed during fine programming.

[0019] A second aspect of this application provides a data programming device for a flash memory, comprising: a flash conversion layer, a flash interface, a programming module, and a storage module;

[0020] The storage module includes multiple physical pages;

[0021] The programming module includes a charge pump, a controller, and a voltage generator;

[0022] The flash memory conversion layer is connected to the programming module through the flash memory interface;

[0023] The flash memory conversion layer is used for:

[0024] Before fine programming any physical page of the flash memory, the number of invalid logical pages in the physical page is determined based on the original data and current data of the physical page; wherein, the original data is the data corresponding to the physical page when coarse programming of the physical page is completed, and the current data is the data corresponding to the physical page before fine programming of the physical page;

[0025] When the number of invalid logical pages is greater than 1 and less than the total number of logical pages, a special invalid programming state, a general invalid programming state, a special valid programming state, and a general valid programming state are determined based on the invalid logical pages.

[0026] The programming module is used for:

[0027] When performing fine programming on the physical page, the verification voltage of the special invalid programming state is converted into the verification voltage of the corresponding special valid programming state, and the verification cycle of the general invalid programming state is removed.

[0028] Optionally, when the flash memory translation layer determines the special invalid programming state, general invalid programming state, special valid programming state, and general valid programming state among multiple programming states based on the invalid logical page, it is specifically used for:

[0029] Determine the first read voltage of the invalid logic page;

[0030] The left and right read voltages of each programming state are compared with the first read voltage. Based on the comparison results, each programming state is determined to be a special invalid programming state, a general invalid programming state, a special valid programming state, or a general valid programming state.

[0031] Optionally, the flash memory conversion layer is also used for:

[0032] When the number of invalid logical pages is 1, a special invalid programming state, a special valid programming state, and a general valid programming state are determined from the invalid logical pages.

[0033] Optionally, the flash memory conversion layer is also used for:

[0034] Before fine-programming the physical page, the verification voltage of the special effective programming state is adjusted according to the cold data static data transfer cycle of the flash memory and the correspondence between the data retention time of the flash memory and the threshold voltage offset of different programming states, so as to perform fine-programming based on the adjusted verification voltage.

[0035] Optionally, the programming module is also used for:

[0036] For each programming cycle during fine programming, if the verification cycle from the end of the programming cycle to the beginning of the next programming cycle is a verification cycle in a general invalid programming state, then the programming cycle is removed during fine programming.

[0037] The beneficial effects of this application are as follows:

[0038] If data in some logic pages fails after coarse programming, this solution can identify special invalid programming states and general invalid programming states based on the invalid logic pages. It converts the verification voltage of the special invalid programming state to the corresponding verification voltage of the special valid programming state, and removes the verification cycle of the general invalid programming state during fine programming. This saves time verifying the general invalid programming state by removing the verification cycle, improving programming performance. Furthermore, by converting the verification voltage of the special invalid programming state, it prevents the threshold voltage distribution of the special invalid programming state after coarse programming from affecting the data in adjacent special valid programming states, thus improving the reliability of data stored in the flash memory. Attached Figure Description

[0039] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0040] Figure 1 This is a schematic diagram illustrating different programming states provided in an embodiment of this application;

[0041] Figure 2 This is a schematic diagram of a coarse-to-fine two-step programming method provided in an embodiment of this application;

[0042] Figure 3 This is a schematic diagram illustrating the sequence of coarse-to-fine two-step programming provided in an embodiment of this application;

[0043] Figure 4 This is a schematic diagram illustrating an invalid programming method provided in an embodiment of this application;

[0044] Figure 5 This is a schematic diagram illustrating the principle of an ISPP algorithm provided in an embodiment of this application;

[0045] Figure 6 This is a schematic diagram illustrating the functional relationship between threshold voltage offsets of memory cells with different distribution states, provided in an embodiment of this application.

[0046] Figure 7 This is a flowchart illustrating a data programming method for a flash memory provided in an embodiment of this application;

[0047] Figure 8 This is a flowchart of another data programming method for flash memory provided in an embodiment of this application;

[0048] Figure 9 This is a flowchart illustrating a method for determining special invalid programming states and general invalid programming states according to an embodiment of this application;

[0049] Figure 10 This is a schematic diagram of the distribution of an invalid programming state and its corresponding threshold voltage provided in an embodiment of this application;

[0050] Figure 11 This is a timing diagram of fine-grained programming operations based on the ISPP process provided in an embodiment of this application;

[0051] Figure 12 This is another timing diagram for fine-grained programming operations based on the ISPP process provided in this application embodiment;

[0052] Figure 13 This is a schematic diagram illustrating another fine-programming operation based on the converted target effective programming state data provided in this application embodiment;

[0053] Figure 14 This application provides a schematic diagram of adjusting the verification voltage of a target valid programming state;

[0054] Figure 15 This is a schematic diagram of the structure of a data programming device for a flash memory provided in an embodiment of this application. Detailed Implementation

[0055] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0056] The following are definitions of some concepts and symbols that may be involved in this application.

[0057] The programming window is the time window between coarse and fine programming in coarse-to-fine two-step programming.

[0058] Invalid programming state is a high-voltage programming state adjacent to the invalid logic page data read reference voltage. Invalid programming states can be divided into special invalid programming states and general invalid programming states.

[0059] Valid programming states are the remaining programming states after removing invalid programming states. Valid programming states can be divided into general valid programming states and special valid programming states.

[0060] A special invalid programming state is an invalid programming state that is adjacent to the high-voltage direction of the valid programming state. For example, P1 is a valid programming state and P2 is an invalid programming state. P2 is adjacent to P1 in the high-voltage direction, so P2 belongs to a special invalid programming state.

[0061] A general invalid programming state is the invalid programming state remaining after removing the special invalid programming state from all invalid programming states. For example, P1 is a valid programming state, and P2 and P3 are both invalid programming states. P2 is adjacent to the valid programming state P1 in the high voltage direction. P2 belongs to the special invalid programming state, and P3 belongs to the general invalid programming state.

[0062] A special valid programming state, a valid programming state adjacent to a special invalid programming state, or a valid programming state merged from an invalid programming state through data correction. Based on the previous examples, P1 can be considered a special valid programming state.

[0063] All valid programming states except for special valid programming states are generally valid programming states.

[0064] For ease of explanation, the erase state ER is also considered a programming state in this embodiment.

[0065] ΔV_VER is the right shift of the verification voltage for a special effective programming state during fine programming operations.

[0066] T_static is the time period for statically moving cold data in QLC.

[0067] V_VER. Programming verification voltage for a special effective programming state.

[0068] ΔVk, the threshold voltage offset of programmed state k after the data hold time.

[0069] A / B: Parameters related to the properties of flash memory itself.

[0070] L(valid, k): The linear relationship between the threshold voltage offset of the programming state Pk and the special valid programming state valid.

[0071] To facilitate understanding of the technical solution of this application, the relevant technologies of flash memory will be explained first.

[0072] The technical solution of this application can be applied to any flash memory that performs data programming based on a coarse-fine two-step programming method, including but not limited to 3D QLC NAND memory. The following uses 3D QLC NAND memory as an example to illustrate the principle of coarse-fine two-step programming of flash memory.

[0073] 3D QLC NAND memory has multiple physical pages, and each physical page has multiple storage cells (also known as flash memory cells).

[0074] Each storage unit can store 4 bits of binary data, corresponding to the following: Figure 1 The 16 different programming states shown correspond to different Gray code schemes, respectively. Figure 1 The different distribution states ER, P1, P2, ... P15 are shown.

[0075] When programming memory cells, the change in electric field during programming of any cell increases the threshold voltage of adjacent, already programmed cells. This threshold voltage distribution manifests as voltage increases extending towards higher voltage levels and exceeding the read reference voltage RL, affecting data retrieval and reducing data reliability. Therefore, to mitigate the impact of adjacent cell programming on the threshold voltage of already programmed cells, a two-step coarse-fine programming approach can be used. In this approach, the programming operation is divided into two stages: coarse programming and fine programming.

[0076] When performing coarse programming on memory cells within a physical page, the distribution of threshold voltages for each cell is first roughly programmed to a position slightly below the target distribution. For example, after coarse programming, the threshold voltages of each memory cell within a physical page might be at... Figure 2 The coarse-programmed distributions are shown in (1) and (2), where the adjacent dashed lines represent the corresponding target distributions.

[0077] The target distribution state of a storage unit can be understood as the actual distribution state of the data to be stored in that storage unit. For example, if a storage unit is to store data in programming state P2, then the target distribution state of that storage unit could be... Figure 1 The distribution state corresponding to P2 is shown in (1).

[0078] After coarse programming, the distribution of threshold voltages of each memory cell is roughly programmed to a position slightly lower than the target distribution. Even if the distribution shifts to the right due to the influence of coarse programming of neighboring cells, there is still a certain voltage margin between the current distribution and the target position, so each distribution will not exceed the read reference voltage. However, since the distribution is still broadened considerably and has not reached the target position, further fine operations are required.

[0079] After coarse programming is completed, fine programming operations can be performed on the memory cells. When performing fine programming operations on each memory cell in the physical page, based on the original coarse programming, fine programming can be performed on each memory cell in the physical page, so that its threshold distribution state continues to shift to the right to the position of the target distribution state, and the distribution state is appropriately narrowed and widened to ensure a sufficient voltage read window between adjacent distribution states.

[0080] Compared to the traditional one-step programming that directly programs the distribution to the target position, two-step programming can use coarse programming to weaken the programming influence of neighboring units and use fine programming to optimize the position of the distribution, thereby greatly improving the stability of each threshold distribution and ensuring stable and reliable data.

[0081] In actual 3D QLC NAND flash memory programming operations, the coarse programming and fine programming operations of the memory cells need to be performed according to the following... Figure 3 The execution sequence is shown, where each WL represents a physical page.

[0082] Taking the programming operation of the memory cells in WL_i,j (the j-th WL in layer i) as an example, firstly, all WLs in layer i need to be coarsely programmed sequentially, and the corresponding cells in WL_i,j are coarsely programmed to a position slightly below the target distribution state; then, coarse programming begins for the WLs in the next layer. After the coarse programming of the memory cells in WL_i+1,j (the j-th WL in layer i+1) is completed, fine programming can be performed on the cells in WL_i,j, shifting their corresponding threshold voltages to the target position.

[0083] Because coarse programming requires shifting the distributed state from the ER state to each target distributed state, the cell threshold voltage shift is large, which has a significant impact on the distributed states of neighboring cells. In contrast, fine programming only needs to optimize the distributed state position, resulting in a smaller cell threshold voltage shift and less impact on the distributed states of neighboring cells. By adopting the above programming sequence, it can be ensured that after coarse programming of cells WL_i,j, the coarse programming effects of surrounding WL cells are weakened and absorbed.

[0084] After fine-programming the cells WL_i,j, only fine-programming is performed on the surrounding WL cells, which has a minimal impact on the distribution. Therefore, by combining the above programming sequence with two-step programming, the impact of neighboring cell programming on the distribution can be greatly reduced, achieving higher data reliability.

[0085] When programming the physical pages of a 3D QLC NAND memory using the coarse and fine two-step programming method described above, the programming data used for coarse programming and fine programming of the same physical page should be consistent. Specifically, after coarse programming of a physical page cell, the programming data to be stored in the physical page (which can be referred to as the original data) is temporarily stored in the cache. When fine programming of the physical page is performed, the original data is retrieved from the cache for operation.

[0086] There is a time window (called the programming window) between coarse programming and fine programming of the same physical page unit. This time window can be understood as the duration from the completion of coarse programming to the start of fine programming for the same physical page unit. For different workloads, the programming window for some physical page units may be relatively long. During this process, it is highly likely that some logical page data to be stored in that physical page will be updated, causing some logical page data in the original data stored in the cache to become invalid. However, since the storage unit has already completed the coarse programming operation using the original data, the distribution of physical page units, although slightly lower than the target location, has already reached a certain scale. It is impossible to directly use the updated data during fine programming; instead, the original data must still be used for fine programming. For the updated data, a "remote update" strategy is adopted, and programming is performed at a new storage location later. In the above process, since the original data is still used for fine programming, this will result in invalid programming of some invalid logical page data, thus wasting programming time and performance.

[0087] by Figure 4 For example, after coarse programming of the data at level i, due to data updates, logical page data such as 8 and 15 become invalid. The updated logical page data will then be combined with other logical page data at the next level to form new physical page data to complete the data update. However, during fine programming, it is still necessary to operate on the invalid logical page data, which will cause redundant time and power consumption.

[0088] In addition to the above, since a single physical page in QLC contains four logical pages, there may be one to four invalid logical pages in the coarse programming and fine programming windows. The more invalid logical pages there are, the greater the additional overhead will be.

[0089] This is the problem of ineffective programming in the coarse-fine two-step programming approach.

[0090] When fine-programming the memory cells of each physical page in a 3D QLC NAND memory, the Incremental Step Pulse Programming (ISPP) algorithm can be used.

[0091] The following uses a Multi-Level Cell (MLC) memory cell as an example to illustrate the principle of this algorithm. Please refer to [link / reference]. Figure 5 When fine-programming MLC memory cells using the ISPP algorithm, the threshold voltage of the memory cell can be gradually increased by applying a series of voltage pulses Pgm with predetermined amplitude and duration to the gate of the memory cell. After each programming voltage pulse, a verification voltage V for a different programming state is required. VFYThis determines whether the memory cell has reached the target distribution state. If the memory cell has reached the target state, it will be masked in subsequent programming operations; if not, programming voltage pulses will continue to be applied to the memory cell. ISPP programming of a physical page ends when the threshold voltages of all memory cells in the page have reached the target distribution state.

[0092] Figure 5 In the middle, V VFY1 This represents the verification voltage corresponding to programming state P1, V. VFY2 This represents the verification voltage corresponding to programming state P2, V. VFY3 This represents the verification voltage corresponding to the programmed state P3. D1 to D3 represent the distributed states corresponding to programmed states P1 to P3, respectively.

[0093] The ISPP algorithm described above requires verifying different cells using verification voltages from all programming states in each programming-verification cycle. Please refer to [link / reference]. Figure 5 In the initial stage of programming physical page cells, since all cells are initially in the erase state, the threshold voltage of each high-programmability cell is far from reaching the target position after programming. Therefore, using the verification voltage of the high-programmability cell at this point will inevitably fail to verify these cells. Thus, in the initial programming stage, only the low-programmability cells can be verified, omitting the verification cycle of the high-programmability cells. During the programming process, as the programming voltage increases, some low-programmability cells will eventually complete programming, and the verification of these low-programmability cells will inevitably succeed. Therefore, the verification cycle of the low-programmability cells can be omitted as programming progresses. Simultaneously, high-programmability cells will need to be programmed, so verification of the high-programmability cells needs to be added as needed. By using the above method, the number of verification cycles required can be reduced compared to the original ISPP algorithm, thereby improving the overall programming performance.

[0094] Among them, the highly programmable cell refers to a memory cell with a relatively large verification voltage corresponding to the target distributed state, for example... Figure 1 The memory cells corresponding to the P13 and P14 programming states, and the low programming state cells, refer to memory cells with smaller verification voltages for the corresponding target distributed states, for example... Figure 1 The memory units corresponding to programming states P1 and P2.

[0095] After the memory cell is programmed, the electrons stored within it gradually leak out over the data retention time, causing the threshold voltage of the memory cell to gradually decrease. From the perspective of the threshold voltage distribution, each distribution state shifts towards lower voltage to varying degrees as the data retention time increases. When the distribution state exceeds each read reference voltage RL, data reading errors occur, affecting data reliability.

[0096] The offset between the data retention time and the threshold voltage of the storage cell has a functional relationship as shown in Equation (1).

[0097] ΔVk=A×ln(tr)+B(1)

[0098] Where ΔVk represents the threshold voltage offset of the memory cell with distribution state k, tr represents the data retention time after programming the memory cell, and A and B represent parameters related to the properties of the memory itself. Using this formula, the threshold voltage offset of the corresponding distribution state can be calculated for a specific memory after determining the basic parameters and data retention time.

[0099] The electron leakage rate of memory cells in different distribution states varies with data retention time. Cells with higher distribution states have faster electron leakage rates and larger threshold voltage offsets, while cells with lower distribution states have slower electron leakage rates and smaller threshold voltage offsets. Therefore, there is a certain linear functional relationship between the threshold voltage offsets of memory cells in different distribution states. For example, in a triple-level cell (TLC), the threshold voltage offsets of different distribution states and the threshold voltage offset of the P7 state can have the following relationship: Figure 6 The linear function relationship is shown.

[0100] Similarly, in QLC memory, the relationship between the threshold voltage offset of memory cells with different distribution states can be expressed by the following formula (2).

[0101] ΔVi=L(i,k)×ΔVk(2)

[0102] In formula (2), L(i, k) represents the linear relationship between the threshold voltage offset between distribution state i and distribution state k. After obtaining the threshold voltage offset of distribution state k, the threshold voltage offset of distribution state i can be obtained based on this formula.

[0103] To address the invalid programming problem in the aforementioned coarse-to-fine two-step programming scheme, this application provides a data programming method for flash memory. Please refer to [link to relevant documentation]. Figure 7 Here is a flowchart of the method, which may include the following steps.

[0104] S701, before fine-programming any physical page of the flash memory, determines the number of invalid logical pages in the physical page based on the original data and current data of the physical page; wherein, the original data is the data corresponding to the physical page when coarse programming of the physical page is completed, and the current data is the data corresponding to the physical page before fine programming of the physical page.

[0105] The execution entity in this embodiment can be the Flash Translation Layer (FTL) in the memory, or it can be a host computer connected to the memory (e.g., a computer connected to the memory).

[0106] The data programming method provided in this embodiment can be applied when data is first written to the flash memory, or when data is moved from the flash memory.

[0107] In step S701, the original data and the current data can be compared to identify which logical pages have different original data and current data, and those logical pages with different original data and current data can be identified as invalid logical pages.

[0108] Raw data can be obtained from the cache; raw data refers to the logical page data used during coarse programming. Current data refers to the logical page data that will actually be stored in the physical page when fine programming begins. Current data can be provided by the host computer.

[0109] The method provided in this embodiment can be applied to quad-level cell (QLC) memory, as well as the aforementioned MLC or TLC memory.

[0110] S702, when the number of invalid logical pages is greater than 1 and less than the total number of logical pages, determine the special invalid programming state, the general invalid programming state, the special valid programming state, and the general valid programming state among various programming states based on the invalid logical pages.

[0111] In step S702, the principle for determining the invalid and valid programming states can be:

[0112] Determine the first read voltage of the invalid logic page;

[0113] The left and right read voltages of each programming state are compared with the first read voltage. Based on the comparison results, each programming state is determined to be a special invalid programming state, a general invalid programming state, a special valid programming state, or a general valid programming state.

[0114] The first read voltage corresponding to an invalid logic page can be determined based on the invalid logic page in a predetermined correspondence.

[0115] In this embodiment, when the invalid logical page is an LSB, the corresponding first read voltage may include RL2, RL5, and RL11; when the invalid logical page is a CSB, the corresponding first read voltage may include RL1, RL7, RL10, and RL12; when the invalid logical page is an MSB, the corresponding first read voltage may include RL3, RL9, RL13, and RL15; and when the invalid logical page is a TSB, the corresponding first read voltage may include RL4, RL6, RL8, and RL14.

[0116] Specifically, it can be executed as follows: Figure 9The method shown determines which of the following types of programming states each programming state belongs to: special invalid programming state, general invalid programming state, special valid programming state, and general valid programming state.

[0117] S901, set i to the initial value 0.

[0118] S902, determine if i is greater than 15.

[0119] If i is not greater than 15, proceed to step S903; if i is greater than 15, the method ends.

[0120] S903, obtain the left and right read voltages for the i-th programming state.

[0121] The 0th programming state is the erase state ER, and the 15th programming state is the aforementioned P15.

[0122] by Figure 1 For example, for the first programmed state P1, the voltage read on its left side could be Figure 1 As shown in (1), the voltage read on the right side of RL1 can be Figure 1 RL2 is shown in (1).

[0123] S904, determine whether the left read voltage of the i-th programming state belongs to the first read voltage of the invalid logic page.

[0124] If the left-side read voltage of the i-th programming state does not belong to the first read voltage of the invalid logic page, execute step S905.

[0125] If the left-side read voltage of the i-th programming state belongs to the first read voltage of the invalid logic page, execute step S906.

[0126] S905, determine whether the right-side read voltage of the i-th programming state belongs to the first read voltage of the invalid logic page.

[0127] If the right-side read voltage of the i-th programming state does not belong to the first read voltage of the invalid logic page, execute step S9051.

[0128] If the right-side read voltage of the i-th programming state belongs to the first read voltage of the invalid logic page, execute step S9052.

[0129] S9051, determine that the i-th programming state belongs to the general valid programming state.

[0130] S9052, determine that the i-th programming state belongs to the special valid programming state.

[0131] S906, determine whether the previous programming state of the i-th programming state is a special valid programming state.

[0132] The programming state preceding the i-th programming state can be understood as the programming state closest to the i-th programming state in the low-voltage direction. For example, if the i-th programming state is P1, then the programming state preceding the i-th programming state can be ER. If the i-th programming state is P6, then the programming state preceding the i-th programming state can be P5.

[0133] Specifically, when i equals 0, the 0th programming state ER has no previous programming state, so S906 can be omitted when i equals 0.

[0134] If the preceding programming state of the i-th programming state is a special valid programming state, then execute S9061.

[0135] If the preceding programming state of the i-th programming state is not a special valid programming state, then execute S9062.

[0136] S9061, determine that the i-th programming state is a special invalid programming state.

[0137] S9062, determine that the i-th programming state is a general invalid programming state.

[0138] S907 increments i by 1.

[0139] After executing S907, return to execute S902 until i is greater than 15.

[0140] It should be noted that when there are at least two invalid logical pages, there may be a situation where there is no general valid programming state, that is, every valid programming state is a special valid programming state.

[0141] For QLC memory, a physical page can store data from four logical pages: LSB, CSB, MSB, and TSB. These logical pages and the programmed state have the correspondence shown in Table 1.

[0142] Table 1

[0143] ER P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 LSB 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 CSB 1 0 0 0 0 0 0 1 1 1 0 0 1 1 1 1 MSB 1 1 1 0 0 0 0 0 0 1 1 1 1 0 0 1 TSB 1 1 1 1 0 0 1 1 0 0 0 0 0 0 1 1

[0144] In Table 1, each column represents a programming state, and the cell below that column represents the data of each logical page when the programming state is in that state.

[0145] As an example, when the number of invalid logical pages identified in S701 is 1, the method is as follows, depending on the type of invalid logical page: Figure 9 The special invalid programming states and their corresponding special valid programming states determined by the method shown are as shown in Table 2.

[0146] Table 2

[0147]

[0148] As another example, when two invalid logical pages are identified, such as LSB and CSB, the special invalid programming states identified in the above manner may include P1, P5, P7, and P10, the special valid programming states may include ER, P4, P6, and P9, the general invalid programming states may include P2, P11, and P12, and the general valid programming states may include P3, P8, P13, P14, and P15.

[0149] As another example, when three invalid logical pages are identified, such as LSB, CSB and MSB, the special invalid programming states identified in the above manner may include P1, P5, P7, P9 and P15, the special valid programming states may include ER, P4, P6, P8 and P14, the general invalid programming states may include P2, P3, P10, P11, P12 and P13, and there are no general valid programming states.

[0150] In some alternative embodiments, step S702 can also be implemented by looking up a table.

[0151] In this case, it can be done in advance according to Figure 9 The method shown determines the types of invalid programming states (special invalid programming state, general invalid programming state, special valid programming state, and general valid programming state) based on the existence of one, two, or three invalid logical pages. These correspondences are then recorded in a data table, which can be a programming state classification lookup table. During execution of S702, the method can directly look up each programming state in this data table to determine which type it belongs to (special invalid programming state, general invalid programming state, special valid programming state, or general valid programming state).

[0152] Implementing S702 using a lookup table can save on repetitive execution during programming. Figure 9 The method reduces the time consumed, thus improving programming performance.

[0153] S703, when performing fine programming on a physical page, converts the verification voltage of a special invalid programming state to the verification voltage of the corresponding special valid programming state, and removes the verification cycle of a general invalid programming state.

[0154] Step S703 can be implemented by, after the FTL or the host computer determines the special invalid programming state and the general invalid programming state, notifying the voltage generator in memory, which is used to generate the verification voltage during the ISPP process, of the special invalid programming state and the general invalid programming state.

[0155] For the special invalid programming state, the voltage generator modifies the verification voltage corresponding to the special invalid programming state to the verification voltage of the adjacent special valid programming state. During the verification cycle of the special invalid programming state, the verification is performed using the converted verification voltage.

[0156] As an example, a special invalid programming state could be P10, and its left neighboring special valid programming state could be P9. The original verification voltage corresponding to P10 was V. VFY10 The verification voltage corresponding to P9 is V. VFY9 In S703, the voltage generator can convert the verification voltage corresponding to P10 from V VFY10 Change to V VFY9 During the verification cycle of P10, the voltage generator outputs the verification voltage V. VFY9 Verification is required.

[0157] For the general invalid programming state, the voltage generator can directly ignore the verification cycle of the general invalid programming state during the ISPP process, that is, it will not output the verification voltage of the general invalid programming state.

[0158] After converting the verification voltage of the special invalid programming state to the verification voltage of the special valid programming state, during the fine programming operation, when using the verification voltage of the special valid programming state to verify the cell, the cells with the programming state as the special valid programming state and the adjacent special invalid programming state can be identified at the same time and verified together using the verification voltage. This realizes the merging of the verification cycle of the special invalid programming state and the special valid programming state, further shortening the time of the fine programming operation.

[0159] Optional, please see Figure 8 The method in this embodiment may further include:

[0160] S801, when the number of invalid logical pages is 1, determine the special invalid programming state, the special valid programming state, and the general valid programming state among various programming states based on the invalid logical pages.

[0161] The method for determining the special invalid programming state in step S801, the special valid programming state, and the general valid programming state can be found in step S702, and will not be repeated here.

[0162] S802, when performing fine programming on a physical page, converts the verification voltage of a special invalid programming state into the verification voltage of the corresponding special valid programming state.

[0163] The specific implementation of step S802 can be found in the content of converting the verification voltage in step S703, and will not be repeated here.

[0164] The beneficial effects of this embodiment are as follows:

[0165] If data in some logic pages fails after coarse programming, this solution can identify special invalid programming states and general invalid programming states based on the invalid logic pages. It converts the verification voltage of the special invalid programming state to the corresponding verification voltage of the special valid programming state, and removes the verification cycle of the general invalid programming state during fine programming. This saves time verifying the general invalid programming state by removing the verification cycle, improving programming performance. Furthermore, by converting the verification voltage of the special invalid programming state, it prevents the threshold voltage distribution of the special invalid programming state after coarse programming from affecting the data in adjacent special valid programming states, thus improving the reliability of data stored in the flash memory.

[0166] The following example illustrates the beneficial effects of the programming method described in this application.

[0167] Please see Figure 10 This is a schematic diagram of the threshold voltage distribution of memory cells in different programming states in a physical page after coarse programming (coarse programming) and fine programming (fine programming) are performed sequentially according to the method of this embodiment. In this example physical page, programming states P5, P7 and P10 belong to special invalid programming states, programming states P4, P6 and P9 belong to special valid programming states, programming states P11 and P12 belong to general invalid programming states, and other programming states belong to general valid programming states.

[0168] Figure 10 In (1), the solid line represents the threshold voltage distribution state corresponding to each programming state after rough programming, and the dashed line represents the target distribution state of the threshold voltage corresponding to each programming state.

[0169] Figure 10 In (2), the solid line represents the distribution of the threshold voltage corresponding to each programming state after fine programming according to the programming method of step S703.

[0170] See further Figure 11 On the one hand, such as Figure 11 As shown in (1), when fine-programming the physical page of this example according to the ISPP process, the verification voltage of the special invalid programming state is converted into the verification voltage of the left-neighboring special valid programming state. For example, the verification voltage of P5 is converted into the verification voltage of P4, the verification voltage of P7 is converted into the verification voltage of P6, and the verification voltage of P10 is converted into the verification voltage of P9. After the conversion, the verification cycle of the corresponding special invalid programming state, i.e., PV (special invalid), is also merged into the verification cycle of the left-neighboring special valid programming state, i.e., PV (special valid). Therefore, as shown in (1), Figure 11 As shown in (2), by merging the verification cycles of these special invalid programming states, the time used for fine programming according to the ISPP process can be shortened by the corresponding duration, that is, Δt is saved.

[0171] Please also see Figure 10 In (2), curves 1, 2, and 3 are defined. Curve 1 is based on... Figure 11 After fine-tuning using the method, the threshold voltage distribution for the special invalid programming state P5 is shown in curve 2, the threshold voltage distribution for P7 is shown in curve 3, and the threshold voltage distribution for P10 is shown in curve 4. It can be seen that because the verification cycles of these special invalid programming states are not directly removed, but rather merged into the threshold voltage of the adjacent special valid programming state by converting the verification voltage, the threshold voltage distribution of the memory cells corresponding to these special invalid programming states will not be lower than the verification voltage of the adjacent special valid programming state. This ensures that the reading of the memory cells corresponding to the special valid programming states is not affected.

[0172] Therefore, the method in this embodiment can save time in verifying the special invalid programming state by converting the verification voltage of the special invalid programming state, and can also avoid the threshold voltage distribution of the special invalid programming state after coarse programming from affecting the data of the adjacent special valid programming state, thereby improving the reliability of the data stored in the flash memory.

[0173] On the other hand, such as Figure 12 As shown in (1), when fine-programming the physical page of this example according to the ISPP procedure, the verification cycles of general invalid programming states can also be deleted, such as the verification cycles of P11 and P12. After merging the verification cycles of special invalid programming states and removing the verification cycles of general invalid programming states, the timing diagram for fine-programming the physical page according to the ISPP procedure can be as follows: Figure 12 As shown in (2), it can be seen that by removing the verification cycle of the general invalid programming state, the time required for fine programming of the physical page can be further shortened, for example, in Figure 12 In (2), the time required for fine programming of the physical page can be shortened by Δt1.

[0174] Furthermore, after the fine programming process is completed, the threshold voltage distribution state corresponding to the generally invalid programmed states from which these verification cycles are removed can be as follows: Figure 10 As shown in (2), curve 4 is the threshold voltage distribution of the memory cell corresponding to the generally invalid programming state P11 after the corresponding verification cycle is removed, and curve 5 is the threshold voltage distribution of the memory cell corresponding to the generally invalid programming state P12 after the corresponding verification cycle is removed.

[0175] As can be seen, for the general invalid programming state, since its threshold voltage is generally higher than the verification voltage of the special valid programming state on the left after coarse programming, there is no need to adjust its verification voltage. Simply removing the corresponding verification cycle will ensure that the reading of the memory cell corresponding to the special valid programming state is not affected.

[0176] Figure 11 and Figure 12 In this context, Pgm represents a programming cycle in the ISPP process.

[0177] When the number of verification cycles after each programming cycle is limited, there may be a situation where all the verification cycles after a certain programming cycle are invalid programming state cycles. In this case, these invalid programming state verification cycles and the corresponding programming cycles can be omitted together, further saving programming time Δt2.

[0178] Therefore, in some optional embodiments, the above programming method may further include the following steps when performing fine programming operations according to the ISPP process after S702:

[0179] For each programming cycle during fine-tuning, if the verification cycle from the end of the programming cycle to the beginning of the next programming cycle is a verification cycle of a general invalid programming state, then the programming cycle is removed during fine-tuning.

[0180] One way to remove a programming cycle is to remove the programming pulse corresponding to that programming cycle. That is, during fine programming operations, the programming pulse signal corresponding to that programming cycle is no longer generated, and the programming pulse signal corresponding to other subsequent programming cycles is generated directly.

[0181] For example, if the number of verification cycles after a single programming cycle is limited to 3, and the 3 verification cycles between the first programming cycle and the second programming cycle are all verification cycles in the general invalid programming state, then these 3 verification cycles and the first programming cycle can be deleted together, thereby further shortening the time taken for fine programming operations.

[0182] by Figure 13 For example, consider a physical page containing three invalid logical pages, and within these, three generally invalid programming states are adjacent.

[0183] It can be seen that the second programming cycle (i.e., the cycle corresponding to the second Pgm) and the verification cycle that appears after the third programming cycle are both verification cycles of general invalid programming states. Therefore, after eliminating these verification cycles of general invalid programming states, we can further eliminate the programming cycles whose verification cycles have all been eliminated, namely the second and third programming cycles, thereby further reducing the time required for fine-tuning operations. For example, in Figure 13 In the process, by eliminating verification cycles with invalid programming states, the time Δt1 can be reduced. By further eliminating programming cycles whose verification cycles have all been eliminated, the time Δt2 can be reduced even further.

[0184] It should be noted that after the memory is programmed with data according to the programming method provided in this application, the original reading reference voltage is still used when reading data from the memory. In other words, the data programming method of this application does not affect the data reading process, demonstrating good versatility.

[0185] In some optional embodiments, the following steps may also be performed before performing the fine programming operation as described in S703:

[0186] Based on the cold data static data transfer cycle of the flash memory and the correspondence between the data retention time of the flash memory and the threshold voltage offset of different programming states, the verification voltage of the special effective programming state is adjusted so as to perform fine programming according to the adjusted verification voltage.

[0187] Please see Figure 14 In the above steps, the time period T_static for cold data static data transfer in QLC can be determined first. This parameter can be a pre-set fixed value. Then, this time period and parameters A and B related to the properties of the memory itself are substituted into the following formula (3) to calculate the threshold voltage offset ΔVk of the special invalid programming state Pk.

[0188] ΔVk=A×ln(T_static)+B(3)

[0189] Then, according to the special invalid programming state Pk (e.g. Figure 14 The programming state P2) and the special valid programming state valid (e.g. Figure 14 The linear relationship between the threshold voltage offset L(valid, k) of the programming state P1) is used to calculate the right shift ΔV_VER of the verification voltage corresponding to the special valid programming state using the following formula (4).

[0190] ΔV_VER=L(valid,k)×ΔVk(4)

[0191] Finally, by adding the right shift amount to the verification voltage of the special effective programming state, the adjusted verification voltage corresponding to the special effective programming state can be obtained. During fine programming, the adjusted verification voltage can be used to verify whether the threshold voltage of each memory cell reaches the threshold voltage distribution state corresponding to the special effective programming state.

[0192] The purpose of adjusting the verification voltage for the special effective programming state in the above manner is:

[0193] The programming verification voltage of the special effective programming state can be appropriately increased so that the target position of the distribution state shifts to the right by a distance equal to the leftward shift of the threshold distribution state before data transfer, while keeping the reading reference voltage unchanged. This ensures that the leftward shift of the threshold distribution state before data transfer does not exceed the reading reference voltage, thereby improving data reliability.

[0194] This application also provides a data programming device for a flash memory; please refer to [link to relevant documentation]. Figure 15 This is a schematic diagram of the device, which may include: a flash translation layer (FTL) 1501, a flash interface 1502, a programming module 1503, and a storage module 1504.

[0195] Storage module 1504 includes multiple physical pages;

[0196] Programming module 1503 includes a charge pump, a controller, and a voltage generator;

[0197] The flash memory conversion layer 1501 is connected to the programming module via a flash memory interface;

[0198] Flash conversion layer 1501 is used for:

[0199] Before fine programming any physical page of the flash memory, the number of invalid logical pages in the physical page is determined based on the original data and the current data of the physical page; where the original data is the data corresponding to the physical page when the coarse programming of the physical page is completed, and the current data is the data corresponding to the physical page before fine programming of the physical page.

[0200] When the number of invalid logical pages is greater than 0 and less than the total number of logical pages, determine the invalid programming state and the special valid programming state corresponding to the invalid programming state from multiple programming states based on the invalid logical pages;

[0201] Transform the data in the invalid programming state corresponding to the physical page into the corresponding special valid programming state;

[0202] Programming module 1503 is used for:

[0203] When data in an invalid programming state is converted into data in a corresponding special valid programming state, fine-programming of the physical page is performed based on the converted data.

[0204] The data programming device for the flash memory can be a solid-state drive or other data storage device.

[0205] The flash memory conversion layer 1501 can be set in the disk controller of the device. The disk controller can also include a controller cache 1505, which can be used to store a programmable classification lookup table.

[0206] The flash memory conversion layer 1501 may include a programming state classification algorithm module, a special valid programming state and special invalid programming state verification voltage adjustment algorithm module, and a verification cycle and programming pulse omission algorithm module.

[0207] When the data programming device is working, the programming state classification algorithm module can query the programming state classification lookup table based on the determined invalid logical page to find out which special valid programming state, special invalid programming state, general valid programming state, and general invalid programming state correspond to the current invalid logical page.

[0208] For special invalid programming states and special valid programming states, the programming state classification algorithm module calls the special valid programming state and special invalid programming state verification voltage adjustment algorithm module. The special valid programming state and special invalid programming state verification voltage adjustment algorithm module adjusts the verification voltage of the special invalid programming state and special valid programming state according to the aforementioned method.

[0209] For general invalid programming states, the programming state classification algorithm module calls the verification cycle and programming pulse omission algorithm module. The verification cycle and programming pulse omission algorithm module omits the verification cycle corresponding to the general invalid programming state. Furthermore, if any subsequent verification cycle of any programming cycle is a verification cycle of a general invalid programming state, the programming cycle and its corresponding programming pulse are removed.

[0210] The flash translation layer 1501 may also include modules such as address mapping, wear leveling, and garbage collection. The functions and working principles of these modules can be found in relevant existing technologies and will not be elaborated here.

[0211] The data programming device for the flash memory in this embodiment may further include a page cache 1506, which is equivalent to the aforementioned Cache and can be used to store the original data after coarse programming in the coarse and fine two-step programming.

[0212] The storage module may include a single-level cell (SLC) storage unit, as well as a QLC storage unit as described above.

[0213] When the programming module performs fine programming, it can generate pulse voltage Pgm and verification voltage corresponding to different programming states through charge pump and voltage generator. Then, the controller performs programming and verification based on the generated voltage.

[0214] The flash memory's data programming device may also include a host interface 1507 for connecting to a host device. The host device can be an electronic device such as a laptop or desktop computer.

[0215] Optionally, when the flash translation layer 1501 determines a special invalid programming state, a general invalid programming state, a special valid programming state, and a general valid programming state among various programming states based on the invalid logical page, it is specifically used for:

[0216] Determine the first read voltage of the invalid logic page;

[0217] The left and right read voltages of each programming state are compared with the first read voltage. Based on the comparison results, each programming state is determined to be a special invalid programming state, a general invalid programming state, a special valid programming state, or a general valid programming state.

[0218] Optionally, the flash memory conversion layer 1501 is also used for:

[0219] When the number of invalid logical pages is 1, the special invalid programming state, the special valid programming state, and the general valid programming state are determined based on the invalid logical pages.

[0220] Optionally, the flash memory conversion layer 1501 is also used for:

[0221] Before fine-programming the physical pages, the verification voltage for a specific effective programming state is adjusted based on the cold data static data transfer cycle of the flash memory and the relationship between the data retention time of the flash memory and the threshold voltage offset of different programming states, so that fine-programming can be performed according to the adjusted verification voltage.

[0222] Optionally, programming module 1503 is also used for:

[0223] For each programming cycle during fine-tuning, if the verification cycle from the end of the programming cycle to the beginning of the next programming cycle is a verification cycle of a general invalid programming state, then the programming cycle is removed during fine-tuning.

[0224] The specific working principle and beneficial effects of the flash memory data programming device provided in this application embodiment can be found in the relevant steps and beneficial effects of the flash memory data programming method provided in this application embodiment, and will not be repeated here.

[0225] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0226] For ease of description, the above systems or devices are described separately as various modules or units based on their functions. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware components.

[0227] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0228] Finally, it should be noted that in this document, relational terms such as first, second, third, and fourth are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0229] The above description is only a preferred embodiment of this application. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the principle of this application, and these improvements and modifications should also be considered within the scope of protection of this application.

Claims

1. A data programming method for a flash memory, characterized in that, include: Before fine programming any physical page of the flash memory, the number of invalid logical pages in the physical page is determined based on the original data and current data of the physical page; wherein, the original data is the data corresponding to the physical page when coarse programming of the physical page is completed, and the current data is the data corresponding to the physical page before fine programming of the physical page; When the number of invalid logical pages is greater than 1 and less than the total number of logical pages, a special invalid programming state, a general invalid programming state, a special valid programming state, and a general valid programming state are determined based on the invalid logical pages. When performing fine programming on the physical page, the verification voltage of the special invalid programming state is converted into the verification voltage of the corresponding special valid programming state, and the verification cycle of the general invalid programming state is removed.

2. The method according to claim 1, characterized in that, The determination of a special invalid programming state, a general invalid programming state, a special valid programming state, and a general valid programming state among multiple programming states based on the invalid logical page includes: Determine the first read voltage of the invalid logic page; The left and right read voltages of each programming state are compared with the first read voltage. Based on the comparison results, each programming state is determined to be a special invalid programming state, a general invalid programming state, a special valid programming state, or a general valid programming state.

3. The method according to claim 1, characterized in that, Also includes: When the number of invalid logical pages is 1, a special invalid programming state, a special valid programming state, and a general valid programming state are determined from the invalid logical pages.

4. The method according to claim 1, characterized in that, Also includes: Before fine-programming the physical page, the verification voltage of the special effective programming state is adjusted according to the cold data static data transfer cycle of the flash memory and the correspondence between the data retention time of the flash memory and the threshold voltage offset of different programming states, so as to perform fine-programming based on the adjusted verification voltage.

5. The method according to claim 1, characterized in that, Also includes: For each programming cycle during fine programming, if the verification cycle from the end of the programming cycle to the beginning of the next programming cycle is a verification cycle in a general invalid programming state, then the programming cycle is removed during fine programming.

6. A data programming device for a flash memory, characterized in that, include: Flash conversion layer, flash interface, programming module and storage module; The storage module includes multiple physical pages; The programming module includes a charge pump, a controller, and a voltage generator; The flash memory conversion layer is connected to the programming module through the flash memory interface; The flash memory conversion layer is used for: Before fine programming any physical page of the flash memory, the number of invalid logical pages in the physical page is determined based on the original data and current data of the physical page; wherein, the original data is the data corresponding to the physical page when coarse programming of the physical page is completed, and the current data is the data corresponding to the physical page before fine programming of the physical page; When the number of invalid logical pages is greater than 1 and less than the total number of logical pages, a special invalid programming state, a general invalid programming state, a special valid programming state, and a general valid programming state are determined based on the invalid logical pages. The programming module is used for: When performing fine programming on the physical page, the verification voltage of the special invalid programming state is converted into the verification voltage of the corresponding special valid programming state, and the verification cycle of the general invalid programming state is removed.

7. The apparatus according to claim 6, characterized in that, When the flash memory translation layer determines a special invalid programming state, a general invalid programming state, a special valid programming state, and a general valid programming state among multiple programming states based on the invalid logical page, it is specifically used for: Determine the first read voltage of the invalid logic page; The left and right read voltages of each programming state are compared with the first read voltage. Based on the comparison results, each programming state is determined to be a special invalid programming state, a general invalid programming state, a special valid programming state, or a general valid programming state.

8. The apparatus according to claim 6, characterized in that, The flash memory conversion layer is also used for: When the number of invalid logical pages is 1, a special invalid programming state, a special valid programming state, and a general valid programming state are determined from the invalid logical pages.

9. The apparatus according to claim 6, characterized in that, The flash memory conversion layer is also used for: Before fine-programming the physical page, the verification voltage of the special effective programming state is adjusted according to the cold data static data transfer cycle of the flash memory and the correspondence between the data retention time of the flash memory and the threshold voltage offset of different programming states, so as to perform fine-programming based on the adjusted verification voltage.

10. The apparatus according to claim 6, characterized in that, The programming module is also used for: For each programming cycle during fine programming, if the verification cycle from the end of the programming cycle to the beginning of the next programming cycle is a verification cycle in a general invalid programming state, then the programming cycle is removed during fine programming.

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