Memory device and operating method thereof

Abstract

The invention relates to a memory device and an operating method thereof. A memory device includes: a memory cell array including a normal cell block and at least one error correction code (ECC) cell block, the normal cell block and the at least one error correction code (ECC) cell block including a plurality of rows; a cleaning control circuit configured to perform an error checking operation on each of the plurality of rows; and a write back prevention circuit configured to store a serious address of a row where a serious error occurs based on local error signals of the normal cell block and the at least one ECC cell block during the error check operation; and selectively performing a write-back operation on a row corresponding to the stored severe address during an error check operation or a read-modify-write (RMW) operation.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0071590, filed on May 31, 2024, which is incorporated herein by reference in its entirety. Technical Field

[0003] Various embodiments of this disclosure relate to semiconductor design techniques, and more specifically, to memory devices that perform error checking operations and read-modify-write (RMW) operations. Background Technology

[0004] A memory device can store data provided by an external device and provide the stored data to the external device. The memory device may include error correction circuitry to ensure data reliability. Recently, memory devices can store data and error correction codes together in a memory cell array, and the error correction circuitry can use the error correction codes read from the memory cell array to perform error correction operations that detect and correct errors in the data read from the memory cell array.

[0005] When an error correction circuit with single-bit error correction capability attempts to correct a multi-bit error, miscorrection by the error correction circuit occurs. Consequently, the number of erroneous bits increases further, making it impossible for the memory controller's error correction capability to correct the error. Recently, various methods have been proposed to manage such miscorrection when it occurs within defined specification boundaries. Summary of the Invention

[0006] Embodiments of this disclosure relate to a memory device and a method of operating the same, the memory device being able to detect a line that has a serious error causing miscorrection during an error checking operation and prevent a write-back operation on that line during an error checking operation or a read-modify-write (RMW) operation.

[0007] According to embodiments of the present disclosure, a memory device includes: a memory cell array including normal cell blocks and at least one error-correcting code (ECC) cell block, the memory cell array including a plurality of rows; a cleanup control circuit configured to perform an error checking operation on each of the plurality of rows; and a write-back prevention circuit configured to store a critical address of a row in which a critical error has occurred based on local error signals of the normal cell block and at least one ECC cell block during the error checking operation, and to selectively perform a write-back operation on the row corresponding to the stored critical address during the error checking operation or a read-modify-write (RMW) operation.

[0008] According to embodiments of this disclosure, a memory device includes: a plurality of normal cell blocks and at least one error-correcting code (ECC) cell block; a first detection signal generation circuit configured to generate a first detection signal during an error checking operation based on a local error signal of a first normal cell block adjacent to the at least one ECC cell block; a second detection signal generation circuit configured to generate a second detection signal during an error checking operation based on a local error signal of the at least one ECC cell block; a third detection signal generation circuit configured to generate a third detection signal during an error checking operation based on a local error signal of a second normal cell block adjacent to the at least one ECC cell block; a severity determination circuit configured to generate detection signals based on the first to third detection signals; an error storage circuit configured to store a row address based on the detection signals; and a write-back control circuit configured to control a write-back operation of the row corresponding to the stored row address to be skipped.

[0009] According to an embodiment of this disclosure, an operation method for a memory device is provided. The memory device includes a plurality of normal cell blocks and at least one error-correcting code (ECC) cell block. The memory device includes a plurality of rows. The operation method includes: performing an error checking operation on a target row among the plurality of rows; generating a detection signal based on local error signals of the normal cell blocks and at least one ECC cell block during the error checking operation; storing a critical address of the target row in an error storage circuit according to the detection signal; and initializing the detection signal upon completion of the error checking operation. The error checking operation, generating the detection signal, storing the critical address, and initializing the detection signal are repeatedly performed on the plurality of rows.

[0010] Furthermore, according to embodiments of this disclosure, the memory device can skip / omit write-back operations for rows with critical errors, thereby preventing miscorrections caused by critical errors and maximizing its error correction capabilities. Additionally, according to embodiments of this disclosure, the memory device can provide optimized reliability, accessibility, and serviceability (RAS) operations by providing information about critical errors as error log information (which is provided to external devices as a result of error checking operations). Attached Figure Description

[0011] Figure 1 This is a block diagram illustrating a memory device according to an embodiment of the present disclosure.

[0012] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of a storage cell array.

[0013] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 1Block diagram of the error correction circuit.

[0014] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 3 The circuit diagram of the error corrector.

[0015] Figure 5 This illustrates an embodiment according to the present disclosure. Figure 1 The block diagram of the write-back prevention circuit.

[0016] Figure 6 This illustrates an embodiment according to the present disclosure. Figure 5 Block diagram of a critical error detection circuit.

[0017] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 6 Detailed circuit diagram of the initial control circuit.

[0018] Figure 8 This illustrates an embodiment according to the present disclosure. Figure 6 Detailed circuit diagram of the detection circuit.

[0019] Figure 9 It is used to describe embodiments according to this disclosure. Figure 6 The timing diagram for the operation of the critical error detection circuit.

[0020] Figure 10 and Figure 11 This is a flowchart describing error checking operations according to embodiments of the present disclosure.

[0021] Figure 12 This is a flowchart describing a read-modify-write (RMW) operation according to embodiments of the present disclosure.

[0022] Figure 13 This is a block diagram illustrating a storage system according to an embodiment of the present disclosure. Detailed Implementation

[0023] Various embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. However, embodiments of the present disclosure may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that the present disclosure will be comprehensive and complete, and will fully convey the scope of the disclosure to those skilled in the art. Throughout the present disclosure, the same reference numerals refer to the same components in various figures and embodiments.

[0024] It should be understood that when an element is referred to as "coupled" or "connected" to another element, it may mean that the two are directly coupled or that they are electrically connected to each other with another circuit intervening between them. It should also be understood that the terms "comprising," "including," "having," etc., as used in this specification specify the presence of the stated features, numbers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. In this disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0025] In the following description, memory devices are described as semiconductor devices including sampling circuitry. However, embodiments of this disclosure are not limited thereto, and can be applied to all semiconductor devices including sampling circuitry for randomly sampling input addresses or input signals.

[0026] Figure 1 This is a block diagram illustrating a memory device 100 according to an embodiment of the present disclosure. Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram of the storage cell array 110.

[0027] refer to Figure 1 The memory device 100 may include a memory cell array 110, a row control circuit 112, a column control circuit 114, a command / address (CA) receiving circuit 120, a data input / output circuit 130, a command decoder 140, an address generation circuit 150, an error correction circuit 172, an error correction code (ECC) generation circuit 174, an error log circuit 176, a modification circuit 178, a scrub control circuit 180, and a write-back prevention circuit 190.

[0028] The memory cell array 110 may include a plurality of memory cells MC arranged in an array. The plurality of memory cells MC may be coupled to a plurality of word lines WL (hereinafter referred to as "a plurality of row WL") and a plurality of bit lines BL (hereinafter referred to as "a plurality of column BL"). The plurality of row WL may extend along a first direction (e.g., row direction) and may be sequentially arranged in a second direction perpendicular to the first direction (e.g., column direction). The plurality of column BL may extend along the column direction and may be sequentially arranged in the row direction. The plurality of memory cells MC may consist of memory cells that require refresh operations to ensure data retention time. The memory cell array 110 may consist of at least one memory bank. The number of memory banks or the number of memory cells MC may be determined according to the capacity of the memory device 100.

[0029] refer to Figure 2The storage cell array 110 may include multiple cell blocks arranged along the row direction. Each cell block may include multiple storage cells MC connected between multiple rows WL and multiple columns BL. In embodiments of the present invention, a "cell block" may be defined as a group of storage cells that share rows WL and columns BL and are arranged in the same manner.

[0030] The multiple cell blocks may include multiple normal cell blocks (e.g., first normal cell block MB0 to sixteenth normal cell block MB15), and at least one error correction code (ECC) cell block MBECC. The first normal cell block MB0 to sixteenth normal cell block MB15 may store data D0' to D127' (corresponding to...) provided from an external device (e.g., a storage controller) via data input / output circuitry 130. Figure 1 The first normal cell block MB0 to the sixteenth normal cell block MB15 can be areas used to store user data and are storage blocks used to determine the storage capacity of the memory device 100. The ECC cell block MBECC can store error correction codes E0 to E7 (corresponding to) generated by the ECC generation circuit 174 for error correction operations. Figure 1 The error correction codes E0 to E7 may include known parity bits. The first normal cell block MB0 to the sixteenth normal cell block MB15 can be divided into the first normal cell block MB0 to the eighth normal cell block MB7 corresponding to the lower group and the ninth normal cell block MB8 to the sixteenth normal cell block MB15 corresponding to the upper group. In this case, the first normal cell block MB0 to the eighth normal cell block MB7, the ECC cell block MBECC, and the ninth normal cell block MB8 to the sixteenth normal cell block MB15 can be sequentially arranged in the row direction.

[0031] For reference only. Figure 2 The memory device 100 illustrates the case of inputting / outputting data in 8-bit units per cell block during a single write and read operation. That is, Figure 1 The storage cell array 110 can input / output 128-bit data D0' to D127' and use 8-bit error correction codes E0 to E7.

[0032] The rectangle between cell blocks MB0 to MB15 and MBECC can represent the subword line driver SWD, and the lines extending to the left and right of the subword line driver SWD can represent rows WL (i.e., word lines or subword lines). In reality, there are many more subword line drivers and word lines, but only a few are shown here to illustrate a simple structure. Because cell blocks MB0 to MB15 share subword line drivers with adjacent cell regions in MBECC, errors may occur in the cell blocks on either side of the subword line driver when a defect occurs in the subword line driver. For example, since the second normal cell block MB1 and the third normal cell block MB2 share a subword line driver, errors will simultaneously occur in the first normal cell block MB0 to the fourth normal cell block MB3 when a defect occurs in the shared subword line driver.

[0033] See back Figure 1 The CA receiving circuit 120 can receive the command / address signal C / A from the memory controller. Depending on the type of memory device 100, the command and address can be input through the same input terminal, or the command and address can be input through different input terminals, as shown in the illustration where the command and address are input through the same input terminal. The command / address signal C / A can be formed by multiple bits.

[0034] Data input / output circuitry 130 can send data DQ to or receive data DQ from the memory controller. Data input / output circuitry 130 may include data input circuitry 132 and data output circuitry 134. Data input circuitry 132 can receive data DQ provided from the memory controller during a write operation. Data output circuitry 134 can output data DQ read from the memory cell array 110 to the memory controller during a read operation.

[0035] Command decoder 140 can decode the command / address signal C / A received by CA receiving circuit 120 to generate activation command ACT, precharge command PCG, write command WT, read command RD, clean command ECS, error message request command ERR_OUT, and modification signal MODI.

[0036] The activation command ACT is the signal input during an instruction activation operation, the precharge command PCG is the signal input during an instruction precharge operation, the write command WT is the signal input during an instruction write operation, and the read command RD can be the signal input during an instruction read operation. Furthermore, the cleanup command ECS is the signal input during an instruction error checking operation, and the error message request command ERR_OUT is the signal input when requesting error information. For reference, an error checking operation (also known as an error checking and cleanup (ECS) operation) can refer to the operation of reading data DATA' from the memory cell array 110 and checking for errors in the data DATA' using the error correction circuit 172 and selecting regions with many errors. The modification signal MODI is the signal for instruction data modification operations during a read-modify-write (RMW) operation. When the instruction RMW is operated by the command / address signal C / A, the command decoder 140 can sequentially generate the read command RD, the modification signal MODI, and the write command WT.

[0037] The address generation circuit 150 classifies the internal address ICA received from the command decoder 140 into a row address RADD and a column address CADD. The row address RADD can be an address used to select one of multiple rows (WL), and the column address CADD can be an address used to select the column from multiple columns (BL) for performing a read operation. Each of the row address RADD and column address CADD can be formed from multiple bits.

[0038] Error correction circuit 172 can use the error correction code ECC read from memory cell array 110 during a read operation to correct errors in read data DATA', so as to output corrected data DATA. Here, error correction can mean an error checking operation that checks for errors in data DATA' using the error correction code ECC and an error correction operation that corrects errors in data DATA' when an error is detected. Error correction circuit 172 can check and correct errors in both the error correction code ECC and data DATA'. When an error in data DATA' is detected and corrected, the data DATA' input to error correction circuit 172 and the data DATA output from error correction circuit 172 can be different from each other. Error correction circuit 172 can output an error signal ERR that is activated when an error is detected during the error checking operation.

[0039] Furthermore, the error correction circuit 172 can output information about erroneous cell blocks in cell blocks MB0 to MB15 and MBECC as multiple local error signals ERR_#. These multiple local error signals ERR_# correspond to cell blocks MB0 to MB15 and MBECC, respectively. When an error occurs in the corresponding cell block, the corresponding local error signal can be activated. The error correction circuit 172 can activate the error signal ERR when one of the local error signals ERR_# is activated. Both the local error signal ERR_# and the error signal ERR can be activated as logic high levels. Detailed configuration of the error correction circuit 172 will be discussed later. Figure 4 and Figure 5 As described in the text.

[0040] ECC generation circuit 174 can generate error correction code (ECC) using data DATA during a write operation. During the write operation, since the error correction code (ECC) is generated using data DATA and errors in data DATA are not corrected, the data DATA input to ECC generation circuit 174 is the same as the data DATA' output from ECC generation circuit 174.

[0041] Error log circuit 176 can record errors found during error checking operations. More specifically, error log circuit 176 can store error information E_INFO based on the error signal ERR activated during the error checking operation. For example, error log circuit 176 can calculate the number of errors per row, classify rows with errors exceeding a threshold as bad regions, and store the bad regions as error information E_INFO. Since error log circuit 176 receives the cleanup row address RADD_E, the cleanup column address CADD_E, and the error signal ERR, it can check which region of the memory cell array 110 the error was found in. Error log circuit 176 can transmit the stored error information E_INFO to the memory controller via data output circuit 134 of data input / output circuit 130 in response to the error information request command ERR_OUT.

[0042] Modification circuit 178 can be a circuit used to perform data modification operations during RMW operation. Modification circuit 178 can generate partial write data by combining data DQ transmitted from the memory controller with error-corrected data DATA output from error-correction circuit 172 in response to modification signal MODI. During normal write and read operations other than RMW operation, data can bypass modification circuit 178. That is, during normal write operation, the data DQ input to modification circuit 178 is the same as the data DATA output from modification circuit 178. During normal read operation, the data DATA input to modification circuit 178 is the same as the data DQ output from modification circuit 178.

[0043] The cleanup control circuit 180 can generate a cleanup activation signal ACT_E, a cleanup precharge signal PCG_E, a cleanup write signal WT_E, and a cleanup read signal RD_E according to the cleanup command ECS to perform an error checking operation. The cleanup control circuit 180 can sequentially activate the cleanup activation signal ACT_E, the cleanup read signal RD_E, the cleanup write signal WT_E, and the cleanup precharge signal PCG_E according to the cleanup command ECS to control the execution of an error checking operation including an activation operation, a read operation, a write operation, and a precharge operation. For reference, the error checking operation can be performed through the activation operation, the read operation, the write operation, and the precharge operation, but according to an embodiment, the write operation can be omitted.

[0044] Furthermore, the cleanup control circuit 180 can generate the cleanup row address RADD_E and the cleanup column address CADD_E according to the cleanup command ECS. Whenever the cleanup command ECS is input, the cleanup address generation circuit 182 can increment the value of the cleanup column address CADD_E by "+1", and when the value of the cleanup column address CADD_E reaches its maximum value, it can increment the value of the cleanup row address RADD_E by "+1". For example, when the range of the cleanup row address RADD_E is from 0 to 3 and the range of the cleanup column address CADD_E is from 0 to 3, the cleanup control circuit 180 can generate the cleanup addresses (RADD_E, CADD_E) to be changed as follows whenever the cleanup command ECS is input: (0,0)->(0,1)->(0,2)->(0,3)->(1,0)->(1,1)->(1,2)->(1,3)->(2,0)->(2,1)->(2,2)->(2,3)->(3,0)->(3,1)->(3,2)->(3,3).

[0045] Row control circuit 112 can be coupled to memory cell array 110 via multiple row WLs. Row control circuit 112 can perform an activation operation to activate the row selected by row address RADD in response to an activation command ACT, and can perform a precharge operation to precharge the activated row in response to a precharge command PCG. Furthermore, row control circuit 112 can perform an activation operation to activate the row selected by cleanup row address RADD_E in response to a cleanup activation signal ACT_E, and can perform a precharge operation to precharge the activated row in response to a cleanup precharge signal PCG_E.

[0046] Column control circuit 114 can be coupled to memory cell array 110 via multiple columns BL. Column control circuit 114 can select some columns from the multiple columns BL of memory cell array 110 according to column address CADD, and in response to read command RD, perform a read operation to read data DATA' and error correction code ECC from memory cell MC through the selected columns, or in response to write command WT, perform a write operation to write data DATA' and error correction code ECC to memory cell MC through the selected columns. Furthermore, column control circuit 114 can select some columns from the multiple columns BL of memory cell array 110 according to clean column address CADD_E, and in response to clean read signal RD_E, perform a read operation to read data DATA' and error correction code ECC from memory cell MC through the selected columns, or in response to clean write command WT_E, perform a write operation to write data DATA' and error correction code ECC to memory cell MC through the selected columns.

[0047] In embodiments of this disclosure, column control circuit 114 may selectively perform write operations based on masking signal WB_MSK. For example, even if write command WT or clean write signal WT_E is activated, column control circuit 114 may omit write operations when masking signal WB_MSK is activated. Hereinafter, write operations performed during error checking and RMW operations are defined as “write-back operations”.

[0048] The write-back prevention circuit 190 can generate a masking signal WB_MSK based on the cleanup command ECS, the modification signal MODI, the activation command ACT, the cleanup activation signal ACT_E, the cleanup read signal RD_E, the cleanup write signal WT_E, the row address RADD, the cleanup row address RADD_E, and the local error signal ERR_#.

[0049] The write-back prevention circuit 190 can detect critical errors (or significant errors) based on the local error signal ERR_# during the error checking operation of each line, and can store the cleanup line address RADD_E with the detected critical error as the critical address RA_SEV. For example, the write-back prevention circuit 190 can detect critical errors based on the local error signal corresponding to the ECC cell block MBECC in the local error signal ERR_#. Figure 4 The ERR_E signal in the code and the local error signals corresponding to normal cell blocks MB6 to MB9 that share the sub-word line driver with the ECC cell block MBECC. Figure 4 The error check function (ERR_67 and ERR_89) is used to detect critical errors. The write-back prevention circuit 190 can store the cleanup row address RADD_E with the detected critical error as the critical address RA_SEV and generate a masking signal WB_MSK to omit the write-back operation of the row corresponding to the stored critical address RA_SEV during the error checking operation and the RMW operation.

[0050] According to an embodiment, the write-back prevention circuit 190 can provide the stored critical address RA_SEV to the error log circuit 176 (shown as dashed lines). The error log circuit 176 can store the critical address RA_SEV as part of the error information E_INFO and transmit the stored error information E_INFO to the storage controller via the data output circuit 134 of the data input / output circuit 130.

[0051] Even if a defect occurs in the sub-word line driver that drives normal cell blocks MB0 to MB15, the error correction circuit 172 can manage miscorrections within the boundary fault coverage. However, when a defect occurs in the sub-word line driver that drives ECC cell block MBECC, the error correction circuit 172 may cause miscorrections outside the boundary fault coverage.

[0052] In embodiments of this disclosure, during an error checking operation for a specific row, a critical error can be determined to have occurred when errors occur in one or more normal cell blocks (MB6 to MB9) that share a subword line driver with the ECC cell block MBECC. Specifically, a critical error is determined to have occurred when an error occurs in column 0 of the ECC cell block MBECC and column 7 of the 10th normal cell block MB9. When a write-back operation is performed during an error checking operation or an RMW operation while a critical error has occurred, the error propagates to another normal cell block (e.g., MB13) due to the error correction circuit 172, and the number of error bits accumulates and increases as the write-back operation continues.

[0053] According to embodiments of this disclosure, the memory device 100 can detect rows where serious errors have occurred, thus omitting the write-back operation for that row during error checking and RMW operations. Therefore, the memory device 100 can prevent miscorrections caused by serious errors and maximize error correction capabilities.

[0054] Error correction circuit 172 and ECC generation circuit 174 can generate error correction codes using a parity check matrix (also called an H matrix) and use the error correction codes to correct errors. For this purpose, error correction circuit 172 and ECC generation circuit 174 may include multiple parity check matrix calculation circuits (referred to as "code calculation circuits"). According to embodiments, error correction circuit 172 and ECC generation circuit 174 may use a common code calculation circuit, or they may each use separate code calculation circuits. The code calculation circuits can generate error correction codes by applying known BCH codes, Hamming codes, or RS codes. The code calculation circuits can also generate error correction codes by applying another type of parity check code.

[0055] Figure 3 This illustrates an embodiment according to the present disclosure. Figure 1Block diagram of error correction circuit 172.

[0056] refer to Figure 3 The error correction circuit 172 may include a check matrix calculator 310, a corrector calculator 330, and an error corrector 350.

[0057] The parity check matrix calculator 310 can generate preliminary error correction codes E0' to E7' by calculating the parity check matrix and the data D0' to D127' read from the storage cell array 110 during a read operation. The parity check matrix calculator 310 can generate preliminary error correction codes E0' to E7', represented as an 8×1 matrix, by performing matrix product calculations on the 8×128 parity check matrix and the data D0' to D127' represented as a 128×1 matrix.

[0058] The corrector calculator 330 can generate correctors S0 to S7 by adding the error correction codes E0 to E7 read from the storage cell array 110 to the preliminary error correction codes E0' to E7'.

[0059] Error corrector 350 can correct errors in data D0' to D127' read from storage cell array 110 by using correctors S0 to S7, and output corrected data D0 to D127. When the values ​​of correctors S0 to S7 are 0, error corrector 350 can determine that there are no errors in data D0' to D127'. On the other hand, when the values ​​of correctors S0 to S7 are not 0, error corrector 350 can determine that there are errors in data D0' to D127', and activate error signal ERR. In addition, errors in data D0' to D127' can be corrected by reversing the bits in the column vector of the parity check matrix that are the same as the values ​​of correctors S0 to S7.

[0060] In embodiments of this disclosure, when errors occur in data D0' to D127' and error correction codes E0 to E7, the error corrector 350 can generate multiple local error signals ERR_# to specify the cell block to which the erroneous data belongs. For example, when... Figure 2 When 17 cell blocks MB0 to MB15 and MBECC are arranged as shown, the error corrector 350 can generate 9 local error signals ERR_# corresponding to two adjacent normal cell blocks and ECC cell block MBECC, respectively.

[0061] Figure 4 This illustrates an embodiment according to the present disclosure. Figure 3 Circuit diagram of the error corrector 350.

[0062] refer to Figure 4The error corrector 350 may include an error code generator 351, an error corrector 352, a first local error signal generator 353_1 to a ninth local error signal generator 353_9, and an error signal generator 354.

[0063] Error code generator 351 can compare the values ​​of correctors S0 to S7 with pre-stored code values ​​to generate multiple error codes E_D0 to E_D127 and E_E0 to E_E7. Error code generator 351 can store the column vectors of the parity check matrix as multiple code values ​​to output multiple error codes E_D0 to E_D127 and E_E0 to E_E7 corresponding to each code value. Error code generator 351 can set the error code corresponding to the code value matching the values ​​of correctors S0 to S7 from the stored code values ​​to the high bit. That is, error codes E_D0 to E_D127 and E_E0 to E_E7 can be used to define the error positions of data D0' to D127' read from storage cell array 110 and error correction codes E0 to E7.

[0064] Error corrector 352 can output corrected data D0 to D127 by correcting errors in data D0' to D127' and error correction codes E0 to E7 using error codes E_D0 to E_127 and E_E0 to E_E7. Error corrector 352 may include logic gates (e.g., XOR gates) for performing logical XOR operations on the corresponding bits of error codes E_D0 to E_D127 and E_E0 to E_E7, as well as data D0' to D127' and error correction codes E0 to E7.

[0065] The first local error signal generator 353_1 to the ninth local error signal generator 353_9 can correspond to two adjacent normal cell blocks and ECC cell blocks MBECC, respectively, to generate the first to ninth local error signals ERR_01, ERR_23, ERR45, ERR_67, ERR_E, ERR_89, ERR_AB, ERR_CD, and ERR_EF based on error codes E_D0 to E_D127 and E_E0 to E_E7. The first local error signal generator 353_1 to the ninth local error signal generator 353_9 can receive error codes corresponding to the data read from the corresponding cell block, and activate the corresponding local error signal when any received error code is set to a high bit.

[0066] For example, the first local error signal generator 353_1 can receive error codes E_D0 to E_D15 corresponding to data D0' to D15' output from the first normal unit block MB0 and the second normal unit block MB1, so as to activate the first error signal ERR_01 when any one of the error codes E_D0 to E_D15 is set to a high bit. The second local error signal generator 353_2 can receive error codes E_D16 to E_D31 corresponding to data D16' to D31' output from the third normal unit block MB2 and the fourth normal unit block MB3, so as to activate the second error signal ERR_23 when any one of the error codes E_D16 to E_D31 is set to a high bit. The fifth local error signal generator 353_5 can receive error codes E_E0 to E_E7 corresponding to error correction codes E0 to E7 output from the ECC unit block MBECC, so as to activate the fifth error signal ERR_E when any of the error codes E_E0 to E_E7 is set to the high bit.

[0067] The first local error signal generator 353_1 to the ninth local error signal generator 353_9 may each include a logic gate (e.g., an OR gate) for performing a logical OR operation on the corresponding error code.

[0068] When any one of the first to ninth local error signals ERR_01, ERR_23, ERR45, ERR_67, ERR_E, ERR_89, ERR_AB, ERR_CD, and ERR_EF is activated, the error signal generator 354 can activate the error signal ERR. The error signal generator 354 may include logic gates (e.g., OR gates) for performing a logical OR operation on the first to ninth local error signals ERR_01, ERR_23, ERR_E, ERR_89, ERR_AB, ERR_CD, and ERR_EF.

[0069] As described above, in the embodiment, when an error occurs in the data D0' to D127' and the error correction codes E0 to E7, the error corrector 350 can generate multiple error signals ERR_01, ERR_23, ERR45, ERR_67, ERR_E, ERR_89, ERR_AB, ERR_CD and ERR_EF to specify the cell block to which the erroneous data belongs.

[0070] Figure 5 This illustrates an embodiment according to the present disclosure. Figure 1 The block diagram of the write-back prevention circuit 190.

[0071] See Figure 5 The write-back prevention circuit 190 may include a critical error detection circuit 410, an error storage circuit 420, an activation latch 430, and a write-back control circuit 440.

[0072] The critical error detection circuit 410 monitors the error checking operation of the row corresponding to the cleanup row address RADD_E based on the cleanup command ECS, the cleanup activation signal ACT_E, the cleanup read signal RD_E, and the cleanup write signal WT_E. During the error checking operation, the critical error detection circuit 410 can output a detection signal SEV_SUM based on the fourth to sixth local error signals ERR_67, ERR_E, and ERR_89 to detect whether a critical error has occurred in the row corresponding to the cleanup row address RADD_E. The critical error detection circuit 410 can output a logic high-level detection signal SEV_SUM when a critical error occurs in the row corresponding to the cleanup row address RADD_E. The critical error detection circuit 410 can initialize the detection signal SEV_SUM whenever the cleanup row address RADD_E changes.

[0073] The error storage circuit 420 can store the cleanup row address RADD_E as the critical address RA_SEV based on the detection signal SEV_SUM. The error storage circuit 420 may include multiple storage circuits, and each time the detection signal SEV_SUM is activated, it sequentially stores the cleanup row address RADD_E as the critical address RA_SEV.

[0074] The activation latch 430 can store and output the activation address RA_ACT by latching the row address RADD according to the activation command ACT, or latch the cleanup row address RADD_E according to the cleanup activation signal ACT_E.

[0075] The write-back control circuit 440 can be enabled by the cleanup command ECS or the modification signal MODI, and generate a masking signal WB_MSK based on the comparison result between the critical address RA_SEV and the active address RA_ACT. When the critical address RA_SEV and the active address RA_ACT are the same, the write-back control circuit 440 can activate the masking signal WB_MSK to a logic high level.

[0076] With the above configuration, the write-back prevention circuit 190 can detect critical errors based on the local error signal ERR_# during the error checking operation for each row, and store the cleanup row address RADD_E containing the detected critical error as a critical address RA_SEV. When the cleanup row address RADD_E matches the stored critical address RA_SEV during the error checking operation, the write-back prevention circuit 190 can activate the masking signal WB_MSK to omit the write-back operation. Furthermore, when the row address RADD matches the stored critical address RA_SEV during the RMW operation, the write-back prevention circuit 190 can activate the masking signal WB_MSK to omit the write-back operation.

[0077] Figure 6This illustrates an embodiment according to the present disclosure. Figure 5 Block diagram of the critical error detection circuit 410.

[0078] refer to Figure 6 The critical error detection circuit 410 may include an initial control circuit 510 and a detection circuit 520.

[0079] Whenever the row address RADD_E is cleaned up during an error checking operation, according to the cleanup command ECS and the cleanup activation signal ACT_E, the initialization control circuit 510 can activate the initialization signal ECS_RSTB. For example, whenever the least significant bit (LSB) of the row address RADD_E is cleaned up (i.e., RADD_E...), the initialization signal ACT_TB is activated. <0> When the error checking operation is toggled, the initial control circuit 510 can activate the initialization signal ECS_RSTB to a logic low level.

[0080] The detection circuit 520 can detect whether a critical error has occurred during the error checking operation based on the fourth to sixth local error signals ERR_67, ERR_E, and ERR_89, and output a detection signal SEV_SUM. The detection circuit 520 can also detect whether a critical error has occurred based on the fourth to sixth local error signals ERR_67, ERR_E, and ERR_89 according to the cleanup read signal RD_E, and output the detection result as the detection signal SEV_SUM according to the cleanup write signal WT_E. In other words, the detection circuit 520 can detect critical errors during the read operation of the error checking operation and output the detection signal SEV_SUM during the write-back operation of the error checking operation. The detection circuit 520 can be initialized according to the initialization signal ECS_RSTB.

[0081] Figure 7 This illustrates an embodiment according to the present disclosure. Figure 6 Detailed circuit diagram of the initial control circuit 510.

[0082] refer to Figure 7 The initial control circuit 510 may include a first NAND gate ND11 and a second NAND gate ND12, a first inverter INV11 and a second inverter INV12, a flip-flop FF1, a transition detector 512, and a NOR gate NR1.

[0083] The first NAND gate ND11 and the first inverter INV11 can output the clock signal CK by performing a logical AND operation on the cleanup command ECS and the cleanup activation signal ACT_E. That is, the first NAND gate ND11 and the first inverter INV11 can generate the clock signal CK that is activated during the activation operation performed during the error checking operation. The second NAND gate ND12 and the second inverter INV12 can perform a logical AND operation on the cleanup command ECS and the LSB (RADD_E) of the cleanup row address RADD_E. <0> The second NAND gate ND12 and the second inverter INV12 can perform a logical AND operation to output the input signal IN. That is, during the error checking operation, the LSB (RADD_E) of the row address RADD_E is output and cleared. <0> The corresponding input signal IN.

[0084] The flip-flop FF1 can respond to the clock signal CK and output the input signal IN as the output signal OUT.

[0085] The transition detector 512 generates a transition detection signal ED_T by detecting a transition of the output signal OUT from low to high or from high to low. For example, the transition detector 512 may include a delay unit D1 and an XOR gate XR1. The delay unit D1 delays the output signal OUT for a predetermined time, and the XOR gate XR1 generates a logic high transition detection signal ED_T only when the output signal OUT and the output of the delay unit D1 have different values.

[0086] NOR gate NR1 performs a logical OR NOT NOR operation on the transition detection signal ED_T and the global reset signal RST. When either the transition detection signal ED_T or the global reset signal RST is activated to a logic high level, NOR gate NR1 generates an initialization signal ECS_RSTB that is activated to a logic low level. According to an embodiment, NOR gate NR1 may be included in the configuration of transition detector 512. According to an embodiment, a buffer may be provided at the rear end of NOR gate NR1.

[0087] Figure 8 This illustrates an embodiment according to the present disclosure. Figure 6 Detailed circuit diagram of the 520 detection circuit.

[0088] Reference Figure 8 The detection circuit 520 may include a first set signal generation circuit 521 to a third set signal generation circuit 523, a first detection signal generation circuit 524 to a third detection signal generation circuit 526, a severity determination circuit 527, and an output control circuit 528.

[0089] The first set signal generation circuit 521 generates the first set signal S1 by inverting the fourth local error signal ERR_67 based on the cleanup read signal RD_E. The second set signal generation circuit 522 generates the second set signal S2 by inverting the fifth local error signal ERR_E based on the cleanup read signal RD_E. The third set signal generation circuit 523 generates the third set signal S3 by inverting the sixth local error signal ERR_89 based on the cleanup read signal RD_E. For example, each of the first set signal generation circuit 521 to the third set signal generation circuit 523 may include a NAND gate and an even number of inverters.

[0090] The first detection signal generation circuit 524 generates a first detection signal DET1, which is set according to a first set signal S1 and reset according to an initialization signal ECS_RSTB. The first detection signal generation circuit 524 can be implemented using a known SR latch. For example, the first detection signal generation circuit 524 generates a first detection signal DET1 that changes to a logic high level according to a logic low first set signal S1 and changes to a logic low level according to a logic low initialization signal ECS_RSTB. The second detection signal generation circuit 525 generates a second detection signal DET2, which is set according to a second set signal S2 and reset according to an initialization signal ECS_RSTB. The third detection signal generation circuit 526 generates a third detection signal DET3, which is set according to a third set signal S3 and reset according to an initialization signal ECS_RSTB. The second detection signal generation circuit 525 and the third detection signal generation circuit 526 may have essentially the same configuration as the first detection signal generation circuit 524.

[0091] The severity determination circuit 527 can detect the detection result SEV by determining a severity error based on the first detection signal DET1 to the third detection signal DET3. When the second detection signal DET2 is activated and at least one of the first detection signal DET1 and the third detection signal DET3 is activated, the severity determination circuit 527 can output the detection result SEV, which is activated as a logic high level. For example, the severity determination circuit 527 may include a first NAND gate ND21 to a third NAND gate ND23. The first NAND gate ND21 can perform a logical NAND operation on the first detection signal DET1 and the second detection signal DET2. The second NAND gate ND22 can perform a logical NAND operation on the second detection signal DET2 and the third detection signal DET3. The third NAND gate ND23 can perform a logical NAND operation on the outputs of the first NAND gate ND21 and the second NAND gate ND22 to output the detection result SEV.

[0092] The output control circuit 528 can output the detection result SEV as a detection signal SEV_SUM based on the cleanup write signal WT_E. For example, the output control circuit 528 may include a NAND gate and an inverter, and the output control circuit 528 performs a logical AND operation on the cleanup write signal WT_E and the detection result SEV to output the detection signal SEV_SUM.

[0093] The following is for reference. Figure 9 , will describe Figures 6 to 8 The operation of the critical error detection circuit 410 described herein.

[0094] Figure 9 It is used to describe embodiments according to this disclosure. Figure 6 Timing diagram of the operation of the critical error detection circuit 410.

[0095] The cleanup control circuit 180 can sequentially activate the cleanup activation signal ACT_E, the cleanup read signal RD_E, and the cleanup write signal WT_E according to the cleanup command ECS. Whenever the cleanup command ECS is input, the cleanup control circuit 180 increments the value of the cleanup column address CADD_E by "+1", and when the value of the cleanup column address CADD_E reaches its maximum value, it increments the value of the cleanup row address RADD_E by "+1". Whenever the value of the cleanup row address RADD_E is incremented by "+1", the LSB (RADD_E) of the cleanup row address RADD_E is... <0> (Can be flipped)

[0096] During the error checking operation in row n, the error correction circuit 172 can output information about the cell blocks MB0 to MB15 and the cell blocks in MBECC where errors have occurred as a local error signal ERR_#. For example, during the error checking operation in row n and column k, when an error occurs in the seventh normal cell block MB6 or the eighth normal cell block MB7, the fourth local error signal ERR_67 can be activated. Furthermore, during the error checking operation in row n and column m, when an error occurs in the ECC cell block MBECC, the fifth local error signal ERR_E can be activated.

[0097] The detection circuit 520 sets the first detection signal DET1 to a logic high level based on the cleanup read signal RD_E and the fourth partial error signal ERR_67, and sets the second detection signal DET2 to a logic high level based on the cleanup read signal RD_E and the fifth partial error signal ERR_E. When both the first detection signal DET1 and the second detection signal DET2 are at a logic high level, the detection circuit 520 determines that a serious error has occurred, thereby generating a logic high level detection result SEV, and outputting the detection result SEV as a detection signal SEV_SUM based on the cleanup write signal WT_E.

[0098] Subsequently, as the value of the column address CADD_E reaches its maximum value and the LSB (RADD_E) of the row address RADD_E is cleared... <0> When the initial control circuit 510 flips, it can activate the initialization signal ECS_RSTB to a logic low level. Therefore, the detection circuit 520 can initialize the first detection signal DET1 to the third detection signal DET3 to a logic low level.

[0099] As described above, in the embodiments of this disclosure, the critical error detection circuit 410 can output a detection signal SEV_SUM by detecting whether a critical error has occurred in the row corresponding to the cleanup row address RADD_E during the error checking operation, based on the fourth to sixth local error signals ERR_67, ERR_E and ERR_89.

[0100] Figure 10 This is a flowchart describing error checking operations according to embodiments of the present disclosure.

[0101] refer to Figure 10 The cleanup row address RADD_E and the cleanup column address CADD_E can be initialized during power-on (at operation S110).

[0102] When the cleanup command ECS is entered with the instruction to perform an error checking operation, the error checking operation can be executed (at operation S120). Detailed instructions for the error checking operation will be provided in [reference needed]. Figure 11 Describe it.

[0103] like Figure 9 As shown, during the error checking operation on the row corresponding to the cleanup row address RADD_E (hereinafter referred to as the target row), the critical error detection circuit 410 can detect whether a critical error has occurred in the target row based on the fourth to sixth local error signals ERR_67, ERR_E and ERR_89 (at operation S130).

[0104] When a critical error is detected (yes at operation S130), the critical error detection circuit 410 outputs a logic high-level detection signal SEV_SUM, and the error storage circuit 420 stores the cleanup row address RADD_E as the critical address RA_SEV based on the detection signal SEV_SUM (at operation S140). On the other hand, when no critical error is detected (no at operation S130), the error storage circuit 420 does not store the critical address RA_SEV.

[0105] When the value of the cleanup column address CADD_E has not reached the maximum value (no at operation S150), the cleanup control circuit 180 can increase the value of the cleanup column address CADD_E by "+1" (at operation S160), and the above operations S120 to S140 can be repeated.

[0106] Subsequently, when the value of the cleanup column address CADD_E reaches its maximum value (yes at operation S150), the error log circuit 176 can store the error information E_INFO in the target row corresponding to the cleanup row address RADD_E according to the error signal ERR (at operation S170). When the value of the cleanup row address RADD_E has not reached its maximum value (no at operation S180), the cleanup control circuit 180 can increment the value of the cleanup row address RADD_E by "+1". Therefore, the critical error detection circuit 410 can activate the initialization signal ECS_RSTB to initialize the detection signal SEV_SUM (at operation S190). The above operations S120 to S190 can be repeated until the cleanup row address RADD_E reaches its maximum value.

[0107] When the value of the cleanup row address RADD_E reaches its maximum value (Yes at operation S180), the error checking operation for all rows can be terminated.

[0108] After all line error checking operations are completed, the error log circuit 176 can transmit the stored error information E_INFO to the storage controller via the data output circuit 134 according to the error message request command ERR_OUT. According to an embodiment, the write-back prevention circuit 190 can provide the stored critical address RA_SEV to the error log circuit 176, and the critical address RA_SEV can be transmitted to the storage controller as part of the error information E_INFO.

[0109] Figure 11 It is used to describe embodiments according to this disclosure. Figure 10 The flowchart of the error checking operation of S120 is shown.

[0110] See Figure 11 The cleanup control circuit 180 can generate the cleanup row address RADD_E and the cleanup column address CADD_E according to the cleanup command ECS, and sequentially activate the cleanup activation signal ACT_E, the cleanup read signal RD_E, the cleanup write signal WT_E and the cleanup precharge signal PCG_E.

[0111] The row control circuit 112 can perform an activation operation to activate the row selected by the cleanup row address RADD_E according to the cleanup activation signal ACT_E (at operation S121). In this case, the activation latch 430 can latch the cleanup row address RADD_E as the activation address RA_ACT according to the cleanup activation signal ACT_E (at operation S121).

[0112] The column control circuit 114 can perform a read operation according to the cleanup read signal RD_E, that is, read the data DATA' and error correction code ECC from the storage cell MC through the column selected by the cleanup column address CADD_E (at operation S122).

[0113] Error correction circuit 172 can check and correct errors in read data DATA' using the read error correction code ECC (at operation S123). Error correction circuit 172 can output information about the cell blocks MB0 to MB15 and the cell blocks in MBECC where errors have occurred as a local error signal ERR_#, and can activate error signal ERR when any local error signal ERR_# is activated. Error log circuit 176 can store error information E_INFO according to error signal ERR. In this case, Figure 11 The read operation at S122 and the check operation at S123 can be combined with... Figure 10 The operations at S130 are executed almost simultaneously.

[0114] The write-back control circuit 440 can be enabled according to the cleanup command ECS to generate a masking signal WB_MSK (at operation S124) by comparing the critical address RA_SEV previously stored in the error storage circuit 420 with the active address RA_ACT latched in the active latch 430. The write-back control circuit 440 can determine whether the critical address RA_SEV matches the active address RA_ACT based on the comparison result (at operation S125).

[0115] When the critical address RA_SEV matches the active address RA_ACT (yes at operation S125), the write-back control circuit 440 can activate the masking signal WB_MSK to a logic high level.

[0116] Subsequently, the ECC generation circuit 174 can generate an error correction code (ECC) using the error-corrected data. The column control circuit 114 can perform a write-back operation by writing the data DATA' and the error correction code ECC to the memory cell MC based on the column selected by the cleanup write signal WT_E, while omitting the write-back operation when the masking signal WB_MSK is activated. That is, the column control circuit 114 can only perform a write-back operation (at operation S126) when the critical address RA_SEV does not match the active address RA_ACT ("No" at operation S125). Figure 11 The write-back operation at point S126 can be combined with... Figure 10 The operations at S140 are executed almost simultaneously.

[0117] Figure 12 This is a flowchart describing a read-modify-write (RMW) operation according to embodiments of the present disclosure.

[0118] refer to Figure 12 The row address RADD is input from the memory controller along with the activation command ACT (at operation S210). The row control circuit 112 can perform an activation operation to activate the row selected by the row address RADD according to the activation command ACT (at operation S220). In this case, the activation latch 430 can latch the row address RADD as the activation address RA_ACT according to the activation command ACT.

[0119] Subsequently, the column address CADD and the data to be written DQ are input from the memory controller along with the command for the RMW operation (at operation S230). The command decoder 140 can sequentially generate the read command RD, the modification signal MODI, and the write command WT.

[0120] The column control circuit 114 can perform a read operation (at operation S240) to read data DATA' and error correction code ECC from the storage cell MC via the column selected by the column address CADD, according to the read command RD. The error correction circuit 172 can output corrected data DATA by correcting errors in the read data DATA' using the read error correction code ECC (at operation S250).

[0121] Modification circuit 178 can generate partial write data by combining the data DQ transmitted from the memory controller with the error correction data DATA in response to the modification signal MODI (at operation S260). Thereafter, ECC generation circuit 174 can generate error correction code ECC using the partial write data.

[0122] The write-back control circuit 440 can be enabled by the modification signal MODI to generate a masking signal WB_MSK (at operation S270) by comparing the critical address RA_SEV previously stored in the error storage circuit 420 with the active address RA_ACT latched in the active latch 430. The write-back control circuit 440 can determine whether the critical address RA_SEV matches the active address RA_ACT based on the comparison result (at operation S280).

[0123] When the critical address RA_SEV matches the active address RA_ACT ("Yes" at operation S280), the write-back control circuit 440 can activate the masking signal WB_MSK to a logic high level.

[0124] The column control circuit 114 can perform a write-back operation, that is, write the data DATA' and error correction code ECC to the memory cell MC by selecting the column according to the write command WT, and omit the write-back operation when the masking signal WB_MSK is activated. In other words, the column control circuit 114 can only perform a write-back operation (at operation S290) when the critical address RA_SEV does not match the active address RA_ACT ("No" at operation S280).

[0125] Figure 13 This is a block diagram illustrating a storage system 1000 according to an embodiment of the present disclosure.

[0126] refer to Figure 13 The storage system 1000 may include a storage device 100 and a storage controller 200.

[0127] The storage controller 200 can control the overall operation of the storage system 1000 and control data exchange between the host and the memory device 100. The storage controller 200 can generate a command / address signal C / A in response to a request REQ from the host and provide the command / address signal C / A to the memory device 100. According to an embodiment, the storage controller 200 can provide a clock signal along with the command / address signal C / A to the memory device 100. The storage controller 200 can provide data DQ corresponding to the request REQ provided from the host to the memory device 100. The storage controller 200 can provide data DQ read from the memory device 100 to the host. The storage controller 200 can provide the memory device 100 with command / address signals C / A indicating activation operations, precharge operations, read operations, write operations, error checking operations, read-modify-write (RMW) operations, etc.

[0128] The memory device 100 may have the same as Figure 1The memory device 100 has a configuration substantially the same as that of the memory device 100. During the error checking operation for each row, the memory device 100 can detect a critical error that occurs in one or more normal cell blocks that share a subword line driver with the ECC cell block MBECC and normal cell blocks MB6 to MB9, and store the row address of the row with the detected critical error as a critical address RA_SEV. When the row address entered during the error checking operation or RMW operation is the same as the stored critical address RA_SEV, the memory device 100 can omit the write-back operation for the corresponding row. Therefore, the memory device 100 and the memory system 1000 including the memory device 100 can prevent miscorrection caused by critical errors and maximize error correction capability.

[0129] Various embodiments of this disclosure are depicted in the accompanying drawings and specification. Although specific terminology is used herein, it is only for describing embodiments of this disclosure. Therefore, this disclosure is not limited to the embodiments described above, and many variations can be made within the spirit and scope of this disclosure. Those skilled in the art will understand that various modifications can be made based on the technical scope of this disclosure in addition to the embodiments disclosed herein. Embodiments can be combined to form additional embodiments.

[0130] It should be noted that although the technical spirit of this disclosure has been described in conjunction with embodiments thereof, this is for descriptive purposes only and should not be construed as limiting. Those skilled in the art will understand that various modifications can be made without departing from the technical spirit of this disclosure and the appended claims.

[0131] For example, the logic gates and transistors provided as examples in the above embodiments can be implemented in different positions and types according to the polarity of the input signal.

Claims

1. A memory device, comprising: A storage cell array comprising normal cell blocks and at least one ECC cell block, wherein the normal cell block and at least one ECC cell block comprise multiple rows, and ECC refers to error correction code. The cleanup control circuitry performs an error checking operation on each of the plurality of rows; and A write-back prevention circuit, which: stores the critical address of the row where a critical error occurred based on the local error signals of the normal cell block and the at least one ECC cell block during the error checking operation; and selectively performs a write-back operation on the row corresponding to the stored critical address during the error checking operation or RMW operation, where RMW stands for Read-Modify-Write.

2. The memory device according to claim 1, wherein, The write-back prevention circuit detects the critical error when an error occurs in at least one ECC cell block and one or more normal cell blocks adjacent to the ECC cell block.

3. The memory device according to claim 2, wherein, The one or more normal cell blocks adjacent to the at least one ECC cell block share a subword line driver with the at least one ECC cell block.

4. The memory device according to claim 1, wherein, The write-back prevention circuit includes: A critical error detection circuit, which, during the error checking operation, outputs a detection signal by detecting whether a critical error has occurred in the row corresponding to the cleanup row address based on the local error signal; An error storage circuit, wherein: the cleanup line address is stored as the critical address according to the detection signal; and The write-back control circuit compares the stored critical address with the input address to generate a masking signal during the error checking operation or the RMW operation.

5. The memory device according to claim 4, further comprising: The column control circuit performs the write-back operation, which writes data to the normal cell block and the at least one ECC cell block, during the error checking operation or the RMW operation. The write-back operation is skipped based on the masking signal.

6. The memory device according to claim 4, wherein, The critical error detection circuit includes: The initial control circuitry, wherein: during the error checking operation, an initialization signal is activated when the cleanup row address changes; and A detection circuit that is initialized according to the initialization signal and detects whether the serious error has occurred in the row corresponding to the cleanup row address based on the local error signal, and outputs the detection signal.

7. The memory device according to claim 6, wherein, The initial control circuit includes: A trigger that: receives the LSB of the cleanup row address for each error checking operation to output an output signal, where LSB refers to the least significant bit; and A transition detector that outputs the initialization signal by detecting transitions in the output signal.

8. The memory device according to claim 6, wherein, The detection circuit includes: A first detection signal generation circuit generates a first detection signal, which is set according to a local error signal of a first normal cell block adjacent to the at least one ECC cell block in the normal cell block, and is reset according to the initialization signal. The second detection signal generation circuit generates a second detection signal, which is set according to a local error signal of the at least one ECC cell block and reset according to the initialization signal. A third detection signal generation circuit, comprising: generating a third detection signal, the third detection signal being set according to a local error signal of a second normal cell block adjacent to the at least one ECC cell block in the normal cell block, and being reset according to the initialization signal; and The severity determination circuit outputs the detection signal based on the first detection signal to the third detection signal.

9. The memory device according to claim 8, wherein, The severity determination circuit activates the detection signal when the second detection signal is activated and at least one of the first detection signal and the third detection signal is activated.

10. The memory device according to claim 1, in, The normal unit blocks include the first to the 2m normal unit blocks, and The first to the mth normal unit blocks, the at least one ECC unit block, and the (m+1)th to the 2mth normal unit blocks are arranged sequentially in the first direction, where m is a natural number greater than 2.

11. The memory device of claim 1, further comprising: An error correction circuit that, during the error checking operation, generates a local error signal corresponding to one of the at least one ECC cell block and one of the normal cell blocks adjacent to the at least one ECC cell block.

12. The memory device according to claim 1, further comprising: An error log circuit that: stores error information based on the local error signal, and outputs the error information to an external device according to an error information request command, the error information including the stored critical address.

13. A memory device, comprising: Multiple normal cell blocks and at least one ECC cell block, where ECC stands for error correction code; The first detection signal generation circuit generates a first detection signal during the error checking operation based on a local error signal of a first normal cell block that is adjacent to the at least one ECC cell block among the plurality of normal cell blocks. The second detection signal generation circuit generates a second detection signal based on the local error signal of the at least one ECC unit block during the error checking operation. The third detection signal generation circuit generates a third detection signal during the error checking operation based on a local error signal of a second normal cell block adjacent to the at least one ECC cell block among the plurality of normal cell blocks. A severity determination circuit, which generates a detection signal based on the first detection signal to the third detection signal; An error storage circuit, which: stores the row address according to the detection signal; and The write-back control circuit controls the write-back operation of the row corresponding to the stored row address to be skipped.

14. The memory device according to claim 13, wherein, The first normal cell block and the second normal cell block share a subword line driver with the at least one ECC cell block.

15. The memory device according to claim 13, wherein, The severity determination circuit activates the detection signal when the second detection signal is activated and at least one of the first detection signal and the third detection signal is activated.

16. The memory device according to claim 13, wherein, The first detection signal generation circuit to the third detection signal generation circuit initialize the first detection signal to the third detection signal in response to the initialization signal activated when the row address changes.

17. The memory device according to claim 13, wherein, The write-back operation includes a write operation performed during the error checking operation or a write operation performed during the RMW operation, where RMW stands for Read-Modify-Write.

18. A method of operating a memory device, the memory device comprising a plurality of normal cell blocks and at least one ECC cell block, ECC referring to error correction code, the plurality of normal cell blocks and at least one ECC cell block comprising a plurality of rows, the method comprising: Perform error checking on the target row among the plurality of rows; During the error checking operation, a detection signal is generated based on the local error signals of the normal cell block and the at least one ECC cell block; Based on the detection signal, the critical address of the target row is stored in the error storage circuit; as well as The detection signal is initialized when the error checking operation is completed. The steps of performing the error checking operation, generating the detection signal, storing the critical address, and initializing the detection signal are repeated for the multiple lines.

19. The operating method according to claim 18, further comprising: During the error checking operation, a local error signal is generated corresponding to one of the at least one ECC cell block and one of the plurality of normal cell blocks adjacent to the at least one ECC cell block.

20. The operating method according to claim 19, wherein, One of the normal cell blocks adjacent to the at least one ECC cell block shares a subword line driver with the at least one ECC cell block.

21. The operating method according to claim 18, further comprising: The critical address stored in the error storage circuit is compared with the input address to generate a masking signal; as well as A write-back operation is performed during the error checking operation or the RMW operation, wherein the write-back operation is skipped according to the masking signal, and RMW refers to Read-Modify-Write.

22. The operating method according to claim 18, further comprising: Error information is stored based on the local error signal; as well as The error message, including the critical address, is output to an external device according to the error message request command.

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