Slide glass wafer for rapid annealing of SiC wafer, preparation method and application

Abstract

The invention belongs to the technical field of semiconductor device manufacturing processes, and relates to a slide glass wafer for SiC wafer rapid annealing, a preparation method and application, and the method comprises the steps: depositing a silicon dioxide film layer on a first silicon wafer and a second silicon wafer, and forming an etching masking layer; removing the second silicon wafer, performing dry etching on the first silicon wafer, and forming a groove corresponding to the second silicon wafer on the surface of the first silicon wafer; the first silicon wafer subjected to dry etching is put into an HF solution to be corroded so as to remove the etching masking layer, cleaning and drying are carried out, a slide wafer is obtained, the temperature measurement problem of the SiC wafer is solved in a slide wafer machining mode, low-cost machining of rapid annealing of the SiC wafer is achieved, and the temperature measurement efficiency of the SiC wafer is improved. The problems that traditional silicon-based rapid annealing equipment cannot accurately measure the surface temperature of the SiC wafer and rapid annealing of the SiC wafer is difficult to complete are solved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device fabrication technology, and relates to a carrier wafer for rapid annealing of SiC wafers, its preparation method, and its application. Background Technology

[0002] With the development of semiconductor technology, silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, possesses excellent properties such as wide bandgap, high breakdown voltage, high saturation drift velocity, and high thermal conductivity, making its application value under special conditions such as high temperature, high power, and high frequency increasingly prominent. In the manufacturing process of SiC devices, it is usually necessary to deposit specific metals on the device surface and perform rapid annealing to obtain the required metal-semiconductor contacts. However, because SiC wafers are semi-transparent, traditional silicon-based rapid annealing equipment cannot accurately measure the surface temperature of SiC wafers, making it difficult to complete rapid annealing of SiC wafers. Currently, the industry typically uses dedicated rapid annealing equipment for SiC wafer processing, but this is costly. Furthermore, existing rapid annealing methods suffer from low thermal conversion efficiency, rapid heat transfer at contact points, and extremely slow heat transfer at warped areas. Moreover, the heat-absorbing medium is prone to breakage under sudden heating, severely impacting the production efficiency and reliability of SiC devices.

[0003] Chinese invention patent CN112509921A discloses a silicon carbide annealing method, which includes preparing an ohmic contact metal on one side of a silicon carbide wafer, placing the silicon carbide wafer on the side corresponding to the contact metal in a tray, and performing rapid annealing after vacuuming. This method reduces the heating rate during annealing to 2℃ / s, simplifies the annealing process, and solves the problem of tray breakage during rapid annealing in infrared radiation heating furnaces. However, this method still suffers from complex annealing processes and high heating rates without affecting the ohmic contact quality of the silicon carbide chip.

[0004] Chinese invention patent CN115394647A discloses a method for annealing ohmic contacts in silicon carbide semiconductors. By forming polycrystalline structures on the silicon carbide surface, the light transmittance of the silicon carbide wafer is reduced, allowing the wafer to directly absorb the radiant heat from the lamps in the rapid annealing furnace without relying on graphite or other heat-absorbing media, thus improving the uniformity of the ohmic contact annealing. However, this method still has shortcomings in optimizing annealing process parameters, making it difficult to achieve the best ohmic contact effect.

[0005] Therefore, there is an urgent need for a low-cost and efficient rapid annealing process technology for SiC wafers to solve the problems of temperature measurement difficulties, uneven annealing, and high costs in existing technologies, and to achieve high-quality processing of SiC wafers through rapid annealing. Summary of the Invention

[0006] To address the problem that traditional silicon-based rapid annealing equipment cannot accurately measure the surface temperature of SiC wafers, making it difficult to complete rapid annealing of SiC wafers, this invention provides a carrier wafer, a preparation method, and an application for rapid annealing of SiC wafers. By processing the carrier wafer, the temperature measurement problem of SiC wafers is solved, achieving low-cost processing for rapid annealing of SiC wafers.

[0007] This invention is achieved through the following technical solution: A method for preparing a carrier wafer for rapid annealing of SiC wafers includes the following steps: S1. A second silicon wafer is placed in the central region of a first silicon wafer, wherein the size of the first silicon wafer is larger than the size of the second silicon wafer; S2. Deposit silicon dioxide film on the first silicon wafer and the second silicon wafer to form an etching masking layer; S3. Remove the second silicon wafer and perform dry etching on the first silicon wafer to form a groove on its surface corresponding to the second silicon wafer; S4. The first silicon wafer, after dry etching, is placed in an HF solution for etching to remove the etching masking layer, and then cleaned and dried to obtain a carrier wafer.

[0008] Preferably, the first silicon wafer is a 6-inch silicon wafer or a 4-inch silicon wafer.

[0009] Preferably, the thickness of the row of silica film is 8 μm to 10 μm.

[0010] Preferably, the silica film is deposited using a PECVD device.

[0011] Preferably, the dry etching is performed using an ICP etching machine.

[0012] Preferably, the process gases used in the ICP etching machine are SF6 and C4F8.

[0013] Preferably, the dry etching time is 1 hour to 1.5 hours.

[0014] Preferably, the concentration of the hydrofluoric acid solution is in the range of 10% to 20%; and the corrosion time in the HF solution is 30 min to 60 min.

[0015] A method for preparing a carrier wafer for rapid annealing of SiC wafers, the carrier wafer being prepared by the method for rapid annealing of SiC wafers, comprising a carrier wafer having grooves.

[0016] An application of the aforementioned carrier wafer in a SiC wafer rapid annealing process includes: The SiC wafer to be processed is placed in the groove of the carrier wafer; The carrier wafer containing the SiC wafer is placed in a silicon-based rapid annealing apparatus; Perform a rapid annealing process.

[0017] Compared with the prior art, the present invention has the following beneficial technical effects: This invention provides a low-cost rapid annealing process for SiC wafers. By placing a small silicon wafer at the center of a large silicon wafer and using PECVD equipment to deposit a silicon dioxide film as an etching mask layer, rapid annealing of SiC wafers is achieved, avoiding the high cost of dedicated SiC wafer rapid annealing equipment. The mask layer is removed using a combination of dry etching and HF solution etching, which is simple and reliable, overcoming the limitation of traditional silicon-based rapid annealing equipment in accurately measuring the surface temperature of SiC wafers, thus ensuring annealing quality. This invention uses clean carrier wafers for rapid annealing, avoiding the problem of carrier wafers easily breaking under sudden heating, thus improving the production reliability of SiC devices. This invention solves the problem of SiC wafer temperature measurement by processing carrier wafers, achieving low-cost rapid annealing of SiC wafers. Rapid annealing of SiC wafers can be completed using silicon-based rapid annealing equipment. The process method is theoretically simple and easy to understand; different process technicians can adjust it according to different equipment, and following this method can achieve results that meet process requirements, making it widely applicable.

[0018] Furthermore, by optimizing the silicon dioxide film thickness and etching process parameters, this invention achieves precise control of the SiC wafer surface temperature, improves the optimizability of annealing process parameters, and ensures annealing uniformity. Furthermore, the method of the present invention is applicable to different types of silicon-based rapid annealing equipment, and has strong versatility and practicality. It can be flexibly adjusted according to different equipment and is suitable for industrial production. Attached Figure Description

[0019] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a flowchart illustrating a low-cost SiC wafer rapid annealing process technology according to the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0022] The cleaning method for the back side of the wafer before metallization in this invention, such as... Figure 1 As shown, it includes the following steps: S1: A 4-inch silicon wafer is placed at the center of a 6-inch silicon wafer. A silicon dioxide film is deposited as an etching mask using PECVD equipment. The thickness of the silicon dioxide film is 8μm to 10μm. S2. Remove the 4-inch wafer from the 6-inch wafer obtained in S1, and perform dry etching on the 6-inch wafer to form a 4-inch groove on the surface of the 6-inch wafer. Dry etching is performed using an ICP etching machine. Preferably, the process gases used in the ICP etching machine are SF6 and C4F8, and the etching time is 1h to 1h30min; S3. Place the 6-inch wafer obtained in S2 into an HF solution to etch away the silicon dioxide film layer used as a masking layer, and then rinse and spin dry to obtain a clean wafer. Preferably, the concentration of the HF solution used is 10% to 20%, and the corrosion time is 30 min to 60 min.

[0023] S4. Use the 6-inch wafer obtained in S4 as a carrier wafer for rapid annealing of SiC wafers.

[0024] The SiC wafers were rapidly annealed using a silicon-based rapid annealing equipment, with the annealing temperature controlled between 600℃ and 700℃ and the heating rate between 2℃ / s and 5℃ / s.

[0025] This invention enables the rapid annealing of SiC wafers using silicon-based rapid annealing equipment. The process method is theoretically simple and easy to understand. Different process technicians can adjust it according to different equipment. Following this method, results that meet the process requirements can be obtained, making it widely applicable.

[0026] The specific process of using the S1 PECVD equipment to deposit a silicon dioxide film as an etching mask layer is as follows: First, a 6-inch silicon wafer substrate with a 4-inch silicon wafer already placed in the center is loaded into the process chamber of the PECVD equipment, and the chamber is evacuated and the temperature is stabilized.

[0027] Subsequently, precursor gases for the reaction are introduced into the chamber, typically silicon source gases (such as silane-SiH4 or tetraethoxysilane-TEOS) and oxygen source gases (such as nitrous oxide-N2O or oxygen-O2). Under specific radio frequency power excitation, a large number of reactive groups (such as SiH3) are formed in the chamber. + O - The plasma (etc.) reacts with these highly reactive groups on the substrate surface, causing them to chemically react and deposit to form a silicon dioxide (SiO2) thin film.

[0028] By precisely controlling key process parameters such as the flow rate of the reactive gas, chamber pressure, RF power, and substrate temperature, a silicon dioxide film with a thickness of 8μm-10μm was uniformly deposited on the 6-inch wafer in areas not covered by the 4-inch wafer, as well as on the surface of the 4-inch wafer itself. This film is dense, uniform, and exhibits excellent step coverage, completely covering the step edges. After deposition, this silicon dioxide layer will serve as an etching mask to protect the underlying silicon material in subsequent dry etching processes.

[0029] PECVD equipment, short for Plasma Enhanced Chemical Vapor Deposition, is a specialized device that uses plasma technology to deposit various solid thin films (such as silicon dioxide, silicon nitride, amorphous silicon, etc.) on the surface of a substrate (such as a silicon wafer) at relatively low temperatures.

[0030] S2, specifically: After PECVD deposition, the 6-inch wafer is removed from the equipment, and the 4-inch silicon wafer in the center area is carefully removed to expose the circular silicon surface underneath that has not been covered with a silicon dioxide masking layer. The 6-inch wafer is then loaded into the reaction chamber of an inductively coupled plasma etching (ICP) machine and evacuated to the required background pressure for the process.

[0031] At the start of the process, specific etching gases—sulfur hexafluoride (SF6) and octafluorocyclobutane (C4F8)—are introduced into the chamber. Excited by the radio frequency power supply, SF6 dissociates to generate a large number of fluorine radicals. These highly reactive radicals react violently with the exposed silicon surface, producing volatile products such as silicon tetrafluoride (SiF4), thereby achieving high-speed etching of the isotropic silicon material and drilling deep grooves. Simultaneously, the C4F8 gas decomposes and polymerizes in the plasma environment to form a fluorinated carbon polymer film. This film passivates and coats the sidewalls and bottom surface of the etched grooves.

[0032] By precisely alternating the introduction of SF6 and C4F8 gases, a cycle of "etch-passivation-re-etch" is achieved. In each cycle, the SF6 step is responsible for vertically etching the silicon material, while the C4F8 step forms a protective layer on the sidewalls to prevent lateral etching. This cyclic mechanism gives the etching process extremely high anisotropy, enabling the fabrication of high aspect ratio structures with steep sidewalls and a depth much greater than their width.

[0033] Throughout the process, by precisely controlling parameters such as RF power, chamber pressure, gas flow rate ratio, cycle time, and period, and maintaining a total etching time of 1 to 1.5 hours, a circular groove with a regular shape and controllable depth that matches the size of the removed 4-inch wafer is precisely machined on the surface of the 6-inch wafer. After etching, the gas supply and RF power are stopped, the etched wafer is unloaded, and subsequent processes are carried out.

[0034] S3, specifically: The 6-inch wafer, which has been dry-etched and has grooves formed, is removed from the ICP etching machine and immersed in a hydrofluoric acid (HF) aqueous solution of a specific concentration for wet chemical etching.

[0035] The preferred concentration range of the HF solution is 10% to 20% (by weight).

[0036] In this process, the HF solution reacts chemically with the silicon dioxide (SiO2) used as a masking layer to generate water-soluble hexafluorosilicic acid (H2SiF6), thereby selectively dissolving and removing all the silicon dioxide masking layer on the wafer surface. Simultaneously, this chemical etching process exhibits extremely high selectivity towards the underlying silicon substrate material, almost completely avoiding corrosion of the silicon trenches and their surface silicon material, perfectly preserving the trench structure and morphology formed by dry etching.

[0037] To ensure complete removal of the silicon dioxide layer and avoid over-etching, the wafer should be immersed in an HF solution for a preferred time of 30 to 60 minutes. After etching is complete, remove the wafer from the HF solution and immediately rinse thoroughly with plenty of deionized water to completely remove any residual chemical reagents and reaction products from the wafer surface.

[0038] Finally, the rinsed wafer is spun dry at high speed to remove all water from the surface using centrifugal force, resulting in a clean, uncontaminated wafer with no residue, ready for subsequent SiC wafer annealing applications.

[0039] S4, specifically: The 6-inch carrier wafer with 4-inch grooves, prepared in step S3, is placed in the process chamber of a rapid thermal annealing (RTA) apparatus. The 4-inch SiC wafer to be processed is then precisely aligned and embedded into the grooves of the carrier wafer to achieve flat support. After closing the chamber, a vacuum is drawn or an inert protective gas (such as nitrogen) is introduced to create a stable environment. The apparatus rapidly heats the wafer system to the target temperature of 600℃~700℃ at a heating rate of 2℃ / s~5℃ / s, holds it at that temperature briefly, and then rapidly cools it after the annealing process is complete. Finally, the SiC wafer is removed, yielding a finished product with optimized electrical properties and controlled warpage.

[0040] Silicon-based rapid annealing equipment (RTP / RTA) is a semiconductor process equipment that uses a high-intensity light source to perform ultra-fast heating and cooling of wafers.

[0041] Example 1 S1: A 4-inch silicon wafer is placed in the center of a 6-inch silicon wafer. A silicon dioxide film is deposited as an etching mask layer using a PECVD equipment. The thickness of the silicon dioxide film is 8μm. S2. Remove the 4-inch wafer from the 6-inch wafer obtained in S1, perform dry etching on the 6-inch wafer to form a 4-inch groove on the surface of the 6-inch wafer. The dry etching is performed using an ICP etching machine. The process gases used in the ICP etching machine are SF6 and C4F8, and the etching time is 1 hour. S3. Place the 6-inch wafer obtained in S2 into an HF solution to etch away the silicon dioxide film layer used as a masking layer. The concentration of the HF solution used is 10%, and the etching time is 60 minutes. Rinse and spin dry to obtain a clean wafer. S4. The 6-inch wafer obtained in S4 is used as a carrier wafer for the rapid annealing of SiC wafers. A silicon-based rapid annealing apparatus is used for the rapid annealing of the SiC wafers, with the annealing temperature controlled at 600℃ and the heating rate at 2℃ / s.

[0042] Example 2 S1: A 4-inch silicon wafer is placed in the center of a 6-inch silicon wafer. A silicon dioxide film is deposited as an etching mask layer using a PECVD equipment. The silicon dioxide film is 10μm thick. S2. Remove the 4-inch wafer from the 6-inch wafer obtained in S1, and perform dry etching on the 6-inch wafer to form a 4-inch groove on the surface of the 6-inch wafer. The dry etching is performed using an ICP etching machine. The process gases used in the ICP etching machine are SF6 and C4F8, and the etching time is 1 hour and 30 minutes. S3. Place the 6-inch wafer obtained in S2 into an HF solution to etch away the silicon dioxide film layer used as a masking layer. The concentration of the HF solution used is 20%, and the etching time is 30 minutes. Rinse and spin dry to obtain a clean carrier wafer. S4. Use the 6-inch wafer obtained in S4 as a carrier wafer for rapid annealing of SiC wafers.

[0043] The SiC wafers were rapidly annealed using a silicon-based rapid annealing equipment, with the annealing temperature controlled at 650℃ and the heating rate at 4℃ / s.

[0044] Example 3 S1: A 4-inch silicon wafer is placed in the center of a 6-inch silicon wafer. A silicon dioxide film is deposited as an etching mask layer using a PECVD equipment. The silicon dioxide film is 9μm thick. S2. Remove the 4-inch wafer from the 6-inch wafer obtained in S1, perform dry etching on the 6-inch wafer to form a 4-inch groove on the surface of the 6-inch wafer. The dry etching is performed using an ICP etching machine. The process gases used in the ICP etching machine are SF6 and C4F8, and the etching time is 1 hour and 15 minutes. S3. Place the 6-inch wafer obtained in S2 into an HF solution to etch away the silicon dioxide film layer used as a masking layer. The concentration of the HF solution used is 15%, and the etching time is 45 minutes. Rinse and spin dry to obtain a clean carrier wafer. S4. Use the 6-inch wafer obtained in S4 as a carrier wafer for rapid annealing of SiC wafers.

[0045] The SiC wafers were rapidly annealed using a silicon-based rapid annealing equipment, with the annealing temperature controlled at 700℃ and the heating rate at 5℃ / s.

[0046] This invention achieves rapid annealing of SiC wafers by placing a 4-inch silicon wafer at the center of a 6-inch silicon wafer and using PECVD equipment to deposit a silicon dioxide film as an etching mask layer, thus avoiding the high cost of dedicated rapid annealing equipment for SiC wafers. This invention uses a combination of dry etching and HF solution etching to remove the etching masking layer. The operation is simple and reliable, overcoming the shortcomings of traditional silicon-based rapid annealing equipment that cannot accurately measure the surface temperature of SiC wafers, thus ensuring the quality of annealing.

[0047] This invention achieves precise control of the surface temperature of SiC wafers by optimizing the silicon dioxide film thickness and etching process parameters, thereby improving the optimizability of annealing process parameters and ensuring annealing uniformity. This invention uses clean-surfaced carrier wafers for rapid annealing, avoiding the problem that traditional annealed carrier wafers are prone to breakage under rapid heating, thus improving the production reliability of SiC devices. Unless otherwise specified, all embodiments and preferred embodiments mentioned herein can be combined to form new technical solutions.

[0048] Unless otherwise specified, all the technical features and preferred features mentioned herein can be combined to form new technical solutions.

[0049] In this invention, unless otherwise specified, percentage (%) or parts refer to weight percentage or parts relative to the composition.

[0050] Unless otherwise specified, the components or preferred components involved in this invention can be combined with each other to form new technical solutions.

[0051] In this invention, unless otherwise specified, the numerical range "a~b" represents an abbreviation of any combination of real numbers between a and b, where a and b are both real numbers. For example, the numerical range "6~22" means that all real numbers between "6~22" have been listed in this document, and "6~22" is simply an abbreviation of these numerical combinations.

[0052] The "scope" disclosed in this invention can be in the form of a lower limit and an upper limit, and can be one or more lower limits and one or more upper limits, respectively.

[0053] In this invention, the term "and / or" as used herein refers to any combination of one or more of the associated listed items, as well as all possible combinations, and includes such combinations.

[0054] In this invention, unless otherwise stated, the various reactions or operation steps may be performed sequentially or in a particular order. Preferably, the reaction methods described herein are performed sequentially.

[0055] Unless otherwise stated, the technical and scientific terms used herein have the same meanings as those familiar to those skilled in the art. Furthermore, any methods or materials similar to or equivalent to those described herein may also be used in this invention.

[0056] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0057] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0058] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0060] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Those skilled in the art can readily implement the present invention based on the accompanying drawings and the above description. However, any modifications, alterations, or variations made by those skilled in the art without departing from the scope of the present invention, utilizing the disclosed technical content, are equivalent embodiments of the present invention. Furthermore, any modifications, alterations, or variations made to the above embodiments based on the essential technology of the present invention are still within the protection scope of the present invention.

Claims

1. A method for preparing a carrier wafer for rapid annealing of SiC wafers, characterized by, The method comprises the following steps: S1, placing a second silicon wafer in the center region of a first silicon wafer, wherein the size of the first silicon wafer is larger than that of the second silicon wafer; S2, depositing a silicon dioxide film layer on the first silicon wafer and the second silicon wafer to form an etching mask layer; S3, removing the second silicon wafer, and performing dry etching on the first silicon wafer to form a groove corresponding to the second silicon wafer on the surface of the first silicon wafer; S4, placing the first silicon wafer after dry etching into an HF solution for etching, removing the etching mask layer, and performing cleaning and drying to obtain a carrier wafer.

2. The method according to claim 1, wherein the first silicon wafer is a 6-inch silicon wafer, and the second silicon wafer is a 4-inch silicon wafer.

3. The method of claim 1, wherein the carrier wafer is prepared by the steps of: The thickness of the silicon dioxide film layer is 8-10 μm. ​ 4. The method of claim 1, wherein the carrier wafer is prepared by the steps of: The deposition of the silicon dioxide film layer is performed by using a PECVD device. ​ 5. The method of claim 1, wherein the carrier wafer is prepared by the steps of: The dry etching is performed by using an ICP etching machine. ​ 6. The method of claim 5, wherein the carrier wafer is prepared by the steps of: The process gas used by the ICP etching machine is SF6 and C4F8. ​ 7. The method of claim 5, wherein the SiC wafer is a 4H-SiC wafer. The dry etching time is 1-1.5 h.

8. The method of claim 1, wherein the carrier wafer is prepared by the steps of: The concentration of the HF solution is 10-20%, and the etching time in the HF solution is 30-60 min. ​ 9. A method for preparing a carrier wafer for rapid annealing of SiC wafers, characterized by, The carrier wafer is obtained by the method according to any one of claims 1-8. The carrier wafer comprises a groove.

10. Use of a wafer of claim 9 in a rapid annealing process of a SiC wafer, characterized in that, The method comprises the following steps: placing a SiC wafer to be processed in the groove of the carrier wafer; placing the carrier wafer carrying the SiC wafer in a silicon-based rapid annealing device; performing a rapid annealing process.

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