Power semiconductor module and power converter

Abstract

A power semiconductor module may include: a common drain pad; a first power semiconductor device on the first region of the common drain pad; a second power semiconductor device on a second region of the common drain pad; a molding layer surrounding lateral portions of the first power semiconductor device and the second power semiconductor device on a peripheral region of the common drain pad; a common gate pad on the first power semiconductor device and the second power semiconductor device; and a source pad on the first power semiconductor device and the second power semiconductor device. The source pad may surround at least two outer lateral portions of the common gate pad.

Description

Technical Field

[0001] This disclosure relates to power semiconductor modules and power converters. Background Technology

[0002] Unlike system semiconductors or memories that process and store information or signals, power semiconductor devices are the core components that convert, store, distribute, and control the power input to electronic devices, and are widely used in most electronic products.

[0003] Recently, with the global trend of strengthening environmental protection, the replacement of existing fossil fuel vehicles with electric or hydrogen-based environmentally friendly vehicles has become a focus of attention. Many power semiconductor devices are used in these environmentally friendly vehicles. These vehicles include hybrid electric vehicles (HEVs), plug-in hybrid electric vehicles (PHEVs), electric vehicles (EVs), and fuel cell electric vehicles (PCEVs).

[0004] Although Si power semiconductor devices have been widely used in conventional technologies, there is a strong need to develop new power semiconductor devices due to their low power, low insulation breakdown characteristics, and low thermal conductivity.

[0005] Therefore, active research is underway on power semiconductor devices based on semiconductor compounds (such as SiC, GaN, and Ga2O3), which have band gaps approximately three times larger than those of conventional Si power semiconductor devices. Power semiconductor devices based on semiconductor compounds exhibit high power output, high dielectric breakdown characteristics, and high thermal conductivity.

[0006] At the same time, such as Figure 1a and Figure 1b As shown, the inverter includes power semiconductor devices 30 and 40 based on semiconductor compounds. Multiple power semiconductor devices 30 and 40 are mounted between a first substrate 10 and a second substrate 20 using a flip-chip bonding method. Each power semiconductor device 30 and 40 has gate electrodes 30a and 40a and source electrodes 30b and 40b positioned on the same surface. In this configuration, the gate electrodes 30a and 30b of each of some power semiconductor devices 30 are electrically connected to the second substrate 20 facing upwards, and the gate electrodes 40a and 40b of each of the other power semiconductor devices 40 are electrically connected to the first substrate 10 facing downwards.

[0007] The inverter has terminals (or lead frames) 50 disposed between the first substrate 10 and the second substrate 20. Since the thickness of the terminals 50 is greater than the thickness of each of the power semiconductor devices 30 and 40, the upper or lower portion of each of the power semiconductor devices 30 and 40 is spaced apart from the first substrate 10 or the second substrate 20. To compensate for this spacing, spacers 70 and 80 are disposed on the upper and lower portions of the power semiconductor devices 30 and 40, respectively.

[0008] Meanwhile, as each of the power semiconductor devices 30 and 40 requires increasingly higher performance, the die size is reduced. Additionally, to maximize the active region of each power semiconductor device 30 and 40, the size of each gate electrode 30a and 40a is reduced.

[0009] Therefore, the bonding process carries a high risk when power semiconductor devices 30 and 40 are bonded to the first substrate 10 or the second substrate 20. For example, defects such as open gate or short gate-source circuits may occur due to misalignment (such as die misalignment). Furthermore, the power semiconductor devices 30 and 40 may detach due to insufficient bonding strength as the size of the gate electrodes 30a and 40a decreases, thereby reducing reliability.

[0010] When power semiconductor devices 30 and 40 are connected to spacers 70 and 80 without insulation, sparks and other flames can occur during high-voltage (>1200V) testing due to insulation issues, making full testing impossible. When an inverter is implemented using a large number of untested power semiconductor devices 30 and 40, the inverter must be discarded if one of the power semiconductor devices 30 or 40 is defective. Therefore, developing a technology capable of full testing is urgent.

[0011] When power semiconductor devices 30 and 40 connected to spacers 70 and 80 are mounted between the first substrate 10 and the second substrate 20 and EMC filling occurs, an electrical short circuit will occur between the source electrodes 30b and 40b and the gate electrodes 30a and 40a of the power semiconductor devices 30 and 40.

[0012] Due to susceptibility to surface foreign matter or EMC filling defects, production volume is difficult to guarantee. Weak bonding due to the small size of gate electrodes 30a and 40a is difficult to detect through electrical evaluation, and even surface inspection of the bonding area is insufficient to completely eliminate it, resulting in a very high probability of defective products. Delamination of gate electrodes 30a and 40a occurs during reliability assessments in the development phase, and the likelihood of field defects is also very high when subjected to sustained thermal stress. Summary of the Invention

[0013] Technical issues

[0014] Therefore, this disclosure aims to address the above-mentioned problems, as well as other issues.

[0015] This disclosure aims to provide a power semiconductor module and power converter that can improve yield.

[0016] This disclosure aims to provide a power semiconductor module and power converter capable of preventing junction defects.

[0017] This disclosure aims to provide a power semiconductor module and power converter that can ensure reliability.

[0018] This disclosure aims to provide a power semiconductor module and power converter capable of preventing electrical short circuits.

[0019] This disclosure aims to provide a power semiconductor module and power converter capable of high-voltage testing during the manufacturing process.

[0020] This disclosure is not limited to the foregoing description, but includes all that may be understood from the description herein.

[0021] Technical solution

[0022] According to one aspect of achieving the above or other objectives, a power semiconductor module includes: a common drain pad; a first power semiconductor device located on a first region of the common drain pad; a second power semiconductor device located on a second region of the common drain pad; a common gate pad located on the first power semiconductor device and the second power semiconductor device; and a source pad located on the first power semiconductor device and the second power semiconductor device, wherein the common drain pad is configured to be electrically connected to a first drain electrode of the first power semiconductor device and a second drain electrode of the second power semiconductor device, wherein the common gate pad is configured to be electrically connected to a first gate electrode of the first power semiconductor device and a second gate electrode of the second power semiconductor device, wherein the source pad is configured to be electrically connected to a first source electrode of the first power semiconductor device and a second source electrode of the second power semiconductor device, and wherein the source pad is configured to surround at least two outer lateral portions of the common gate pad.

[0023] The source pad may include a common source pad that vertically overlaps with the first power semiconductor device and the second power semiconductor device.

[0024] The common source pad may have an opening, and the common gate pad is positioned within the opening.

[0025] The common gate pad may include a first short lateral portion and a second short lateral portion in one direction, and a first long lateral portion and a second long lateral portion in a direction perpendicular to the one direction.

[0026] The common source pad can be positioned on the first short lateral portion, the second short lateral portion, and the first long lateral portion of the common gate pad.

[0027] The common source pad can be positioned on the second long lateral portion of the common gate pad.

[0028] The first short lateral portion of the common gate pad can be positioned between the first gate electrode and the first source electrode, and the second short lateral portion of the common gate pad can be positioned between the second gate electrode and the second source electrode.

[0029] The source pad may include a first source pad and a second source pad, wherein the first source pad and the second source pad vertically overlap with the first source electrode of the first power semiconductor device and the second source electrode of the second power semiconductor device, respectively.

[0030] The power semiconductor module may further include a Kelvin source pad, which is spaced apart from the source pads on the first power semiconductor device and the second power semiconductor device.

[0031] The size of the common gate pad can be larger than the size of the first gate electrode of the first power semiconductor device or the size of the second gate electrode of the second power semiconductor device.

[0032] According to another aspect, a power semiconductor module includes: a common drain pad; a first power semiconductor device located on a first region of the common drain pad; a second power semiconductor device located on a second region of the common drain pad; a common gate pad located on the first power semiconductor device and the second power semiconductor device; and a source pad located on the first power semiconductor device and the second power semiconductor device, wherein the common drain pad is configured to be electrically connected to a first drain electrode of the first power semiconductor device and a second drain electrode of the second power semiconductor device, wherein the common gate pad is configured to be electrically connected to a first gate electrode of the first power semiconductor device and a second gate electrode of the second power semiconductor device, wherein the source pad is configured to be electrically connected to a first source electrode of the first power semiconductor device and a second source electrode of the second power semiconductor device, and wherein the common gate pad vertically overlaps with at least one of the first source electrode and the second source electrode.

[0033] The common gate pad can be disposed in one direction across the first source electrode and the first gate electrode, as well as the second gate electrode and the second source electrode, in the first region of the common drain pad.

[0034] The source pad may include a common source pad that vertically overlaps with the first power semiconductor device and the second power semiconductor device.

[0035] The common source pad can be disposed on the second region of the common drain pad, spanning the first source electrode and the second source electrode along the one direction.

[0036] The area of ​​the common source pad can be larger than the area of ​​the first source electrode of the first power semiconductor device or the area of ​​the second source electrode of the second power semiconductor device.

[0037] The area of ​​the common drain pad can be greater than the sum of the areas of the common gate pad and the common source pad.

[0038] The source pad may include a first source pad and a second source pad, wherein the first source pad and the second source pad vertically overlap with the first source electrode of the first power semiconductor device and the second source electrode of the second power semiconductor device, respectively.

[0039] The power semiconductor module may further include a Kelvin source pad, which is spaced apart from the source pads on the first power semiconductor device and the second power semiconductor device.

[0040] According to another aspect, a power converter includes: a first substrate; a second substrate; and a plurality of power semiconductor modules located between the first substrate and the second substrate, wherein each of the plurality of power semiconductor modules includes: a common drain pad; a first power semiconductor device located on a first region of the common drain pad; a second power semiconductor device located on a second region of the common drain pad; a common gate pad located on the first power semiconductor device and the second power semiconductor device; and a common source pad. The common source pad is located on the first power semiconductor device and the second power semiconductor device, wherein the common source pad is configured to surround at least two lateral portions of the common gate pad, wherein in some of the plurality of power semiconductor modules, the common drain pad is configured to be electrically connected to the first substrate, and the common gate pad and the common source pad are each electrically connected to the second substrate, and wherein in the remaining of the plurality of power semiconductor modules, the common drain pad is configured to be electrically connected to the second substrate, and the common gate pad and the common source pad are each electrically connected to the first substrate.

[0041] The power converter may also include a plurality of terminals connected to each of the first substrate and the second substrate.

[0042] Beneficial effects

[0043] The effects of the power semiconductor module and power converter according to this disclosure are described below.

[0044] According to at least one aspect, by packaging multiple power semiconductor devices, the common gate pad connecting the gate electrodes of the multiple power semiconductor devices can be expanded as much as possible, thereby preventing bonding defects or detachment defects and increasing yield. Furthermore, since the common gate pad and common source pad can be expanded, the separation distance between the power semiconductor devices can be further increased, and a molding layer can be filled between the power semiconductor devices. Therefore, not only are the power semiconductor devices virtually unaffected by each other's thermal characteristics, but the heat dissipation characteristics generated from each power semiconductor device can also be improved.

[0045] According to at least one aspect, by encapsulating multiple power semiconductor devices, the very thin power semiconductor devices are not exposed to the outside, which prevents electrical short circuits caused by foreign objects or dust, thereby increasing production.

[0046] According to at least one aspect of the present invention, when packaging multiple power semiconductor devices, since the multiple power semiconductor devices are surrounded by a molding layer, the presence or absence of defects can be detected by high-voltage testing at 1200V or higher before installation into a power converter. Therefore, the advantage lies in the early rejection of defective power semiconductor modules through comprehensive testing, thereby fundamentally preventing potential risks such as breakdown due to overvoltage or rating-related faults of each power semiconductor device, thus improving product reliability.

[0047] According to at least one aspect, since the common drain pad is expanded to cover the size of all power semiconductor devices in multiple power semiconductor devices and has excellent thermal characteristics, it has the advantage of obtaining excellent electrode characteristics and excellent heat dissipation characteristics.

[0048] According to at least one aspect, since power semiconductor modules comprising the number of power semiconductor devices required by the customer can be more easily obtained by packaging multiple power semiconductor devices, it has the advantage of maximizing the freedom to manufacture power semiconductor modules.

[0049] According to at least one aspect, each power semiconductor module can be manufactured to have the same thickness as the maximum thickness of the terminal. Therefore, when each power semiconductor module and terminal are mounted between the first substrate and the second substrate, since each power semiconductor module is in contact with the surfaces of the first substrate and the second substrate, separate components such as spacers are not required, which prevents bonding defects between each power semiconductor module and the spacers and facilitates the assembly process of the power converter. Attached Figure Description

[0050] Figure 1a This is a diagram showing multiple power semiconductor devices mounted on a first substrate, and Figure 1b It is shown that... Figure 1a A diagram showing the second substrate bonded to the first substrate.

[0051] Figure 2 This is a circuit diagram showing an inverter according to one aspect of the present disclosure.

[0052] Figure 3 This is a cross-sectional view showing a power converter according to one aspect of the present disclosure.

[0053] Figure 4This is a cross-sectional view showing a power semiconductor module according to a first aspect of the present disclosure.

[0054] Figure 5 It is shown Figure 4 The cross-sectional view of the first power semiconductor device is shown.

[0055] Figure 6 This is a cross-sectional view showing a plurality of power semiconductor devices packaged in the first aspect of this disclosure.

[0056] Figure 7a By cutting Figure 6 The wafer shown is a cross-sectional view of a power semiconductor module with two power semiconductor devices.

[0057] Figure 7b By cutting Figure 6 The wafer shown is a cross-sectional view of a power semiconductor module with a power semiconductor device.

[0058] Figure 8 This is a diagram showing multiple power semiconductor modules mounted on a first substrate.

[0059] Figure 9 This is a first diagram showing the layout of the common gate pad and the common source pad according to this disclosure.

[0060] Figure 10 This is a second figure showing the layout of the common gate pad and the common source pad according to this disclosure.

[0061] Figure 11 This is a third figure showing the layout of the common gate pad and the common source pad according to this disclosure.

[0062] Figure 12 This is a fourth figure showing the layout of a power semiconductor module according to the present disclosure.

[0063] Figures 13a to 13d It is shown Figure 12 Various diagrams showing variations of the common gate pad.

[0064] Figure 14 This is the fifth figure showing the layout of a power semiconductor module according to the present disclosure.

[0065] Figure 15 This is the sixth figure showing the layout of a power semiconductor module according to the present disclosure.

[0066] Figures 16a to 16h It is based on the manufacturing process diagram of the power semiconductor module disclosed herein.

[0067] Figure 17 This is a cross-sectional view showing a power semiconductor module according to the present disclosure.

[0068] Figure 18 This is a cross-sectional view showing a plurality of power semiconductor devices packaged in this disclosure.

[0069] Figure 19a By cutting Figure 18 The wafer shown is a cross-sectional view of a power semiconductor module with two power semiconductor devices.

[0070] Figure 19b By cutting Figure 18 The wafer shown is a cross-sectional view of a power semiconductor module with a power semiconductor device.

[0071] Figure 20 This is the seventh figure showing the layout of the common gate pad and the common source pad according to this disclosure.

[0072] Figure 21 This is the eighth figure showing the layout of the common gate pad and the common source pad according to this disclosure.

[0073] Figure 22 This is the ninth figure showing the layout of the common gate pad and the common source pad according to this disclosure.

[0074] Figure 23 Figure 10 shows the layout of the common gate pad and common source pad according to this disclosure.

[0075] Figure 24 This is Figure 11, which shows the layout of the common gate pad and common source pad according to this disclosure.

[0076] Figures 25a to 25h The manufacturing process of a power semiconductor module according to this disclosure is shown.

[0077] The dimensions, shapes, and values ​​of the components shown in the accompanying drawings may differ from the actual figures. Furthermore, even if the same component is shown with different dimensions, shapes, and values ​​in different drawings, this is merely an example, and the same component may have the same dimensions, shapes, and values ​​in different drawings. Detailed Implementation

[0078] In the following description, the various aspects disclosed in this specification will be described in detail with reference to the accompanying drawings. Regardless of the reference numerals, identical or similar parts will be given the same reference numerals, and redundant descriptions will be omitted. The suffixes “module” and “part” used for parts in the following description are given for ease of writing and are interchangeable, and have no inherent meaning or function. Furthermore, the drawings are intended to facilitate easy understanding of the aspects disclosed in this specification, and the technical concepts disclosed in this specification are not limited to the drawings. Additionally, when referring to an element such as a layer, region, or substrate existing “on” another element, this includes cases where it may be directly on the other element or where other intermediate elements may exist between them.

[0079] Figure 2 This is a circuit diagram showing an inverter according to one aspect of the present disclosure.

[0080] refer to Figure 2 The inverter 1000 according to this disclosure can be applied to applications such as three-phase motors or compressors. The inverter 1000 can output three-phase power. The inverter 1000 can be a power converter, or can be included in a power converter. The inverter 1000 may include switching circuitry. The power converter may also be referred to as a power semiconductor module.

[0081] The inverter 1000 according to this disclosure can convert DC power to AC power and provide the converted AC power to a load 1200 to drive the load 1200. In the inverter 1000 according to this disclosure, a converter can be connected to the input side, enabling the conversion of AC power to DC power. In this case, the DC power converted by the converter can be used to drive the load 1200 after being converted to AC power by the inverter 1000. The load 1200 can be a motor or an electric motor, but is not limited thereto.

[0082] The inverter 1000 according to this disclosure may include, but is not limited to, a three-phase inverter. In this case, a phase difference of 120 degrees may exist between the first, second, and third phases. The inverter 1000 according to this disclosure may include multiple legs 100A, 100B, and 100C. For example, the first leg 100A, the second leg 100B, and the third leg 100C may be connected in parallel with the load 1200 (i.e., the motor) via a first node N1, a second node N2, and a third node N3, respectively. The first leg 100A may include a first arm 100a and a second arm 100b connected in series with each other; the second leg 100B may include a third arm 100c and a fourth arm 100d connected in series with each other; and the third leg 100C may include a fifth arm 100e and a sixth arm 100f connected in series with each other. Here, the first arm 100a, the third arm 100c, and the fifth arm 100e can be referred to as the upper arms, and the second arm 100b, the fourth arm 100d, and the sixth arm 100f can be referred to as the lower arms. Each of the first arms 100a to the sixth arms 100f can be referred to as a switch module, a sub-module, etc.

[0083] The first arm 100a to the sixth arm 100f may each include switching elements Q1 to Q6 and diodes 100a-2 to 100f-2. The switching elements Q1 to Q6 and diodes 100a-2 to 100f-2 can be formed simultaneously using the same semiconductor process. Switching elements Q1 to Q6 may include power semiconductor devices.

[0084] In order to convert DC power to AC power by the inverter 1000 according to this disclosure, the switching elements Q1 to Q6 of the first arm 100a to the sixth arm 100f can be controlled to turn on / off.

[0085] For example, when the first switching element Q1 of the first arm 100a of the first branch 100A is turned on, the fourth switching element Q4 of the fourth arm 100d of the second branch 100B and / or the sixth switching element Q6 of the sixth arm 100f of the third branch 100C can be turned on. Therefore, DC power can be supplied to the first phase inductor of the motor.

[0086] For example, when the third switching element Q3 of the third arm 100c of the second branch 100B is turned on, the sixth switching element Q6 of the sixth arm 100f of the third branch 100C and / or the second switching element Q2 of the second arm 100b of the first branch 100A can be turned on. Therefore, DC power can be supplied to the second-phase inductor of the motor. The second phase can be 120 degrees out of phase with the first phase.

[0087] For example, when the fifth switching element Q5 of the fifth arm 100e of the third branch 100C is turned on, the second switching element Q2 of the second arm 100b of the first branch 100A and / or the fourth switching element Q4 of the fourth arm 100d of the second branch 100B can be turned on. Therefore, DC power can be supplied to the third-phase inductor of the motor. The third phase can be 120 degrees out of phase with the second phase.

[0088] Therefore, AC power can be generated by supplying DC power to each of the first-phase inductor, the second-phase inductor, and the third-phase inductor.

[0089] Meanwhile, although not shown, in order to improve the withstand voltage capability, the switching elements (i.e., power semiconductor devices Q1 to Q6) of the first arm 100a to the sixth arm 100f can be arranged in the form of multiple units connected in series with each other.

[0090] Although not shown, in order to improve current characteristics, the switching elements (i.e., power semiconductor devices Q1 to Q6) of the first arm 100a to the sixth arm 100f can be arranged in the form of multiple units connected in parallel with each other.

[0091] Meanwhile, the switching elements Q1 to Q6 and diodes 100a-2 to 100f-2 constituting the first arm 100a to the sixth arm 100f can be packaged to form a power semiconductor module.

[0092] As an example, the first branch 100A, the second branch 100B, and the third branch 100C can each be configured as a power semiconductor module. That is, the first arm 100a and the second arm 100b of the first branch 100A can be packaged to form a first power semiconductor module. The third arm 100c and the fourth arm 100d of the second branch 100B can be packaged to form a second power semiconductor module. The fifth arm 100e and the sixth arm 100f of the third branch 100C can be packaged to form a third power semiconductor module.

[0093] As another example, the first branch 100A, the second branch 100B, and the third branch 100C can be configured as a single power semiconductor module. That is, the first arm 100a and the second arm 100b of the first branch 100A, the third arm 100c and the fourth arm 100d of the second branch 100B, and the fifth arm 100e and the sixth arm 100f of the third branch 100C can be packaged to form a single power semiconductor module.

[0094] The unexplained symbol VDC represents the input voltage, which can be, for example, a DC voltage. The unexplained symbol CDC represents a capacitor that can be charged by the input voltage VDC.

[0095] Meanwhile, power semiconductor devices are typically referred to as dies when they are manufactured on wafers, and as chips after they are separated by dicing the wafer. In the following text, dies or chips will be collectively referred to as power semiconductor devices.

[0096] Figure 3 This is a cross-sectional view showing a power converter according to one aspect of the present disclosure. Figure 4 This is a cross-sectional view showing a power semiconductor module according to a first aspect of the present disclosure.

[0097] although Figure 4 Multiple power semiconductor modules are shown in the image. Figure 8 The first power semiconductor module 230 (of 230, 240, 260, and 270) may have a structure similar to the second power semiconductor module 240, the third power semiconductor module 260, and the fourth power semiconductor module 270. Figure 4 The structure is the same as that of the first power semiconductor module 230 shown in the figure. Therefore, from Figure 4 The structure of the first power semiconductor module 230 shown can be easily understood to understand the structure of each of the second power semiconductor module 240, the third power semiconductor module 260, and the fourth power semiconductor module 270.

[0098] refer to Figure 3 The power converter 200 according to this disclosure may include a first substrate 210, a second substrate 220, a first power semiconductor module 230, a second power semiconductor module 240, terminals 250, etc.

[0099] The first substrate 210 and the second substrate 220 may respectively include insulating layers 211 and 221, first metal layers 213 and 223, and second metal layers 215 and 225. The insulating layers 211 and 221 may be made of inorganic materials, ceramic materials, alumina materials, plastic materials, glass materials, etc.

[0100] The first metal layers 213 and 223 may include multiple circuit patterns (not shown). These multiple circuit patterns may be electrically connected to the first power semiconductor module 230 and the second power semiconductor module 240. Therefore, the first metal layers 213 and 223 may be formed of a metallic material with excellent conductivity. For example, the first metal layers 213 and 223 may have a single-layer structure or a multi-layer structure made of copper (Cu), gold (Au), aluminum (Al), platinum (Pt), etc.

[0101] The first metal layers 213 and 223 can be formed of materials with excellent electrical conductivity and heat dissipation properties.

[0102] The circuit pattern can be referred to as a heat dissipation pattern. In this case, the first metal layers 213 and 223 may include multiple heat dissipation patterns. The multiple heat dissipation patterns may be electrically connected to the first power semiconductor module 230 and the second power semiconductor module 240.

[0103] The second metal layers 215 and 225 can be used to rapidly dissipate heat generated from the first power semiconductor module 230 and the second power semiconductor module 240 to the outside. Therefore, the second metal layers 215 and 225 can be formed of a material with excellent heat dissipation properties. For example, the second metal layers 215 and 225 can be aluminum (Al) or an aluminum alloy, but are not limited thereto. The second metal layers 215 and 225 can be referred to as a heat sink or radiator.

[0104] The first power semiconductor module 230 and the second power semiconductor module 240 can be installed between the first substrate 210 and the second substrate 220.

[0105] In this disclosure, the first power semiconductor module 230 and the second power semiconductor module 240 may each include at least two or more power semiconductor devices. The two or more power semiconductor devices may be connected in parallel with each other.

[0106] although Figure 3 The diagram shows a first power semiconductor module 230 and a second power semiconductor module 240, but four power semiconductor modules can be provided. Figure 8 The system may contain 230, 240, 260, and 270 or more power semiconductor modules. In this case, the first power semiconductor module 230 and the third power semiconductor module 260 may be connected in parallel with each other, and the second power semiconductor module 240 and the fourth power semiconductor module 270 may be connected in parallel with each other. The first power semiconductor module 230 may be connected in series with the second power semiconductor module 240 or the fourth power semiconductor module 270. The third power semiconductor module 270 may be connected in series with the second power semiconductor module 240 or the fourth power semiconductor module 270.

[0107] exist Figure 8 For example, the first branch 100A shown in Figure 1 can be configured by power semiconductor modules 230, 240, 260, and 270. In this case, the first arm 100a of the first branch 100A can be composed of... Figure 8The first power semiconductor module 230 and the third power semiconductor module 260 are configured, and the second arm 100b of the first branch 100A can be configured by the second power semiconductor module 240 and the fourth power semiconductor module 270. The first switching element Q1 of the first arm 100a can be configured by multiple power semiconductor devices of each of the first power semiconductor module 230 and the third power semiconductor module 260. The second switching element Q2 of the second arm 100b can be formed by multiple power semiconductor devices of each of the second power semiconductor module 240 and the fourth power semiconductor module 270. The second branch 100B and the third branch 100C shown in FIG1 can also be configured by... Figure 8 The power semiconductor modules 230, 240, 260 and 270 are formed in the middle.

[0108] Meanwhile, terminal 250 (or lead frame) can be used to connect external circuitry (or driver) to the first power semiconductor module 230 and the second power semiconductor module 240.

[0109] For example, at least five terminals can be provided, but this is not a limitation. For example, the first terminal and the second terminal can be electrically connected to the first power semiconductor module 230 through corresponding circuit patterns on the first substrate 210. For example, the third terminal can be connected to both the first power semiconductor module 230 and the second power semiconductor module 240 through corresponding circuit patterns on the first substrate 210 or the second substrate 220. Alternatively, the third terminal can be integrally formed with two sub-terminals. In this case, the two sub-terminals can be electrically connected to the first power semiconductor module 230 and the second power semiconductor module 240, respectively.

[0110] For example, the fourth and fifth terminals can be electrically connected to the second power semiconductor module 240 via corresponding circuit patterns on the second substrate 220. In this case, the first and fourth terminals can provide switching signals, gating signals, control signals, etc., to control the on / off state of the first power semiconductor module 230 and the second power semiconductor module 240, respectively.

[0111] The thickness of each of the first power semiconductor module 230 and the second power semiconductor module 240 can be the same as the maximum thickness among the thicknesses of each terminal in the terminals 250. The thickness of each terminal in the terminals 250 can be determined by considering the power, voltage, current, etc., supplied to the first power semiconductor module 230 or the second power semiconductor module 240. Therefore, the first power semiconductor module 230 and the second power semiconductor module 240 can be in direct contact with the first substrate 210 and the second substrate 220, respectively. In this case, no separate component (such as a spacer) is needed to fill the gap between the first power semiconductor module 230 (or the second power semiconductor module 240) and the first substrate 210 or between the first power semiconductor module 230 (or the second power semiconductor module 240) and the second substrate 220, thereby preventing bonding defects between the first power semiconductor module 230 (or the second power semiconductor module 240) and the spacer, and facilitating the assembly process of the power converter.

[0112] refer to Figure 3 The first power semiconductor module 230 and the second power semiconductor module 240 may include common drain pads 231 and 241, common gate pads 237 and 247, common source pads 239 and 249, etc.

[0113] like Figure 4 As shown, the first power semiconductor module 230 may include a first power semiconductor device 232-1, a second power semiconductor device 232-2, a molding layer 233, etc. Although not shown, the second power semiconductor module 240 may also include a first power semiconductor device, a second power semiconductor device, a molding layer, etc. In the second power semiconductor module 240, the first power semiconductor device, the second power semiconductor device, and the molding layer (not shown) may each have the same structure, shape, and / or function as the first power semiconductor device 232-1, the second power semiconductor device 232-2, and the molding layer 233 of the first power semiconductor module 230.

[0114] The common drain pad 231 can be used to support the first power semiconductor device 232-1, the second power semiconductor device 232-2, the molding layer 233, the common gate pad 237, and the common source pad 239. The common drain pad 231 can serve as a common electrode, which together connects the first drain electrode 320 of the first power semiconductor device 232-1 and the second drain electrode 360 ​​of the second power semiconductor device 232-2. The common drain pad 231 can also serve as an electrode pad, which electrically connects each of the first power semiconductor device 232-1 and the second power semiconductor device 232-2 to the first substrate 210 or the second substrate 220. Therefore, the common drain pad 231 can be formed of a metallic material with excellent conductivity. For example, the common drain pad 231 can include copper (Cu). For example, the common drain pad 231 can have a three-layer structure of copper (Cu)-molybdenum (Mo)-copper (Cu). The common drain pad 231 can be referred to as a conductive layer, metal layer, support layer, conductive support layer, support component, heat dissipation component, etc.

[0115] The common drain pad 231 may include a first region 231-1, a second region 231-2, and a remaining region 231-3. The first region 231-1 and the second region 231-2 may be positioned spaced apart from each other, and the remaining region 231-3 may be the region excluding the first region 231-1 and the second region 231-2, i.e., the peripheral region.

[0116] A first power semiconductor device 232-1 and a second power semiconductor device 232-2 can be disposed on a common drain pad 231. The first power semiconductor device 232-1 can be disposed on a first region 231-1 of the common drain pad 231, and the second power semiconductor device 232-2 can be disposed on a second region 231-2 of the common drain pad 231. The first region 231-1 can have dimensions corresponding to the dimensions of the first power semiconductor device 232-1, and the second region 231-2 can have dimensions corresponding to the dimensions of the second power semiconductor device 232-2. Since the first region 231-1 and the second region 231-2 are positioned spaced apart from each other, the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can also be positioned spaced apart from each other.

[0117] Although the first power semiconductor device 232-1 and the second power semiconductor device 232-2 are shown in the accompanying drawings, more power semiconductor devices may be provided.

[0118] Figure 5 It is shown Figure 4 The cross-sectional view of the first power semiconductor device is shown.

[0119] although Figure 5The image shows a power semiconductor device ( Figure 4 The first power semiconductor device 232-1 (232-1 and 232-2) can have the same structure as the first power semiconductor device 232-1. Therefore, from Figure 5 The structure of the first power semiconductor device 232-1 shown can be easily understood to understand the structure of the second power semiconductor device 232-2.

[0120] refer to Figure 4 and Figure 5 The first power semiconductor device 232-1 may include a first semiconductor layer 310, a first drain electrode 320, a first gate electrode 330, a first source electrode 340, etc. The second power semiconductor device 232-2 may include a second semiconductor layer 350, a second drain electrode 360, a second gate electrode 370, and a second source electrode 380.

[0121] The first semiconductor layer 310 and the second semiconductor layer 350 can each be formed on a substrate based on a semiconductor compound such as SiC, GaN or Ga2O3 using semiconductor processes.

[0122] The first drain electrode 320 can be disposed on the lower side of the first semiconductor layer 310, and the first gate electrode 330 and the first source electrode 340 can be disposed on the upper side of the first semiconductor layer 310. Since the first gate electrode 330 and the first source electrode 340 are disposed on the same surface of the first semiconductor layer 310, they can be spaced apart from each other to prevent electrical short circuits between them. Because the first gate electrode 330 and the first source electrode 340 are disposed on the same surface of the first semiconductor layer 310, the first power semiconductor device 232-1 can have a flip-chip structure.

[0123] The second drain electrode 360 ​​can be disposed on the lower side of the second semiconductor layer 350, and the second gate electrode 370 and the second source electrode 380 can be disposed on the upper side of the second semiconductor layer 350. Since the second gate electrode 370 and the second source electrode 380 are disposed on the same surface of the second semiconductor layer 350, they can be spaced apart from each other to prevent electrical short circuits between them. Because the second gate electrode 370 and the second source electrode 380 are disposed on the same surface of the second semiconductor layer 350, the second power semiconductor device 232-2 can have a flip-chip structure.

[0124] A common gate pad 237 can be disposed on the first power semiconductor device 232-1 and the second power semiconductor device 232-2. The common gate pad 237 can be commonly connected to the first gate electrode 330 of the first power semiconductor device 232-1 and the second gate electrode 370 of the second power semiconductor device 232-2. The common gate pad 237 can vertically overlap with and be electrically connected to the first gate electrode 330 of the first power semiconductor device 232-1. The common gate pad 237 can vertically overlap with and be electrically connected to the second gate electrode 370 of the second power semiconductor device 232-2. The common gate pad 237 can extend from the first gate electrode 330 of the first power semiconductor device 232-1 toward the second gate electrode 370 of the second power semiconductor device 232-2.

[0125] Meanwhile, in conventional power converters (or inverters), multiple power semiconductor devices ( Figure 1a and Figure 1b Gate electrodes 30a and 40a are directly bonded to the first substrate 10 or the second substrate 20. To improve performance, the size (or area) of the power semiconductor devices has been progressively reduced. To maximize the active area of ​​each of the reduced power semiconductor devices 30a and 40a, the dimensions of gate electrodes 30a and 40a have been reduced. Therefore, bonding defects occur during the bonding process between the power semiconductor devices 30a and 40a and the first substrate 10 or the second substrate 20, and the bonding strength of gate electrodes 30a and 40a is weak, leading to defects such as detachment of the power semiconductor devices 30a and 40a.

[0126] However, in this disclosure, the size (or area) of the common gate pad 237 can be larger than the size (or area) of the first power semiconductor device 232-1 or the second power semiconductor device 232-2. Therefore, even if the common gate pad 237, larger than the size of the first power semiconductor device 232-1 or the second power semiconductor device 232-2, is bonded to the first substrate 210 or the second substrate 220 to realize the power converter 200, not only will bonding defects not occur, but bonding strength can be greatly improved, thus preventing defects such as detachment. In this way, bonding defects or detachment defects can be prevented, and therefore yield can be increased.

[0127] Meanwhile, the common source pad 239 can be disposed on the first power semiconductor device 232-1 and the second power semiconductor device 232-2. The common source pad 239 can be connected together to the first source electrode 340 of the first power semiconductor device 232-1 and the second source electrode 380 of the second power semiconductor device 232-2.

[0128] The common source pad 239 may vertically overlap with and be electrically connected to the first source electrode 340 of the first power semiconductor device 232-1. The common source pad 239 may vertically overlap with and be electrically connected to the second source electrode 380 of the second power semiconductor device 232-2. The common source pad 239 may extend from the first source electrode 340 of the first power semiconductor device 232-1 toward the second source electrode 380 of the second power semiconductor device 232-2.

[0129] The size of the common source pad 239 may be at least half the sum of the size of the first power semiconductor device 232-1 and the size of the second power semiconductor device 232-2. The outer lateral portion of the common source pad 239 may be disposed on the outer lateral portion of the first power semiconductor device 232-1 and / or the second power semiconductor device 232-2. For example, the common source pad 239 may be positioned closer to the outer lateral portion of the common drain pad 231 than to the outer lateral portion of the first source electrode 340 of the first power semiconductor device 232-1. Similarly, the common source pad 239 may be positioned closer to another outer lateral portion of the common drain pad 231 than to the outer lateral portion of the second source electrode 380 of the second power semiconductor device 232-2.

[0130] The common source pad 239 can be positioned on the same layer as the common gate pad 237. The common source pad 239 can be formed simultaneously with the common gate pad 237 using the same process and material as the common gate pad 237. For example, the common gate pad 237 and the common source pad 239 can each be formed from a metal with excellent conductivity (such as copper (Cu)), but are not limited thereto.

[0131] The common source pad 239 can be positioned spaced apart from the common gate pad 237 to prevent electrical short circuits with the common gate pad 237. The common source pad 239 can surround the common gate pad 237.

[0132] The size (or area) of the common drain pad 231 can be larger than the sum of the size (or area) of the common gate pad 237 and the common source pad 239.

[0133] In this disclosure, since the size of the common gate pad 237 is much larger than the size (or area) of the first gate electrode 330 of the first power semiconductor device 232-1 or the size (or area) of the second gate electrode 370 of the second power semiconductor device 232-2, the common gate pad 237 can be referred to as a scalable gate pad (hereinafter referred to as SGP). In this disclosure, since the size of the common source pad 239 is much larger than the size of the first source electrode 340 of the first power semiconductor device 232-1 or the size of the second source electrode 380 of the second power semiconductor device 232-2, the common source pad 239 can be referred to as a scalable source pad (hereinafter referred to as SSP).

[0134] Simultaneously, the molding layer 233 can be disposed on the peripheral region 231-3 of the common drain pad 231. The molding layer 233 can surround the lateral portion of the first power semiconductor device 232-1 and the lateral portion of the second power semiconductor device 232-2. The first power semiconductor device 232-1 and the second power semiconductor device 232-2 are not exposed to the outside through the molding layer 233. The molding layer 233 can be formed of a resin material with excellent insulating properties. For example, the molding layer 233 can be formed of epoxy molding compound (EMC) material, but is not limited thereto. The EMC material can be a sealing material that protects the first power semiconductor device 232-1 and the second power semiconductor device 232-2 from heat, moisture, impact, insulation breakdown, etc.

[0135] Meanwhile, power semiconductor devices used to implement existing power converters are subjected to high-voltage tests of 1200V or higher without a surrounding molding layer. Therefore, sparking occurs during 1200V or higher high-voltage testing of the power semiconductor devices, making high-voltage testing impossible. Consequently, when power converters are implemented using untested power semiconductor devices, there is always a potential risk of breakdown due to overvoltage or rated failure of the power semiconductor devices, leading to reduced product reliability.

[0136] However, in this disclosure, a power semiconductor module in which the first power semiconductor device 232-1 and the second power semiconductor device 232-2 are surrounded by a molding layer 233 can be manufactured. Figure 4 230). In power semiconductor modules manufactured in this way ( Figure 4 In (230), even if a high-voltage test of 1200V or greater is performed on each of the first power semiconductor device 232-1 and the second power semiconductor device 232-2, a complete test can be performed without sparks. Therefore, the power converter according to this disclosure ( Figure 3The 200) can be implemented using multiple power semiconductor modules 230 that have been fully tested. Therefore, due to the power converter ( ) according to this disclosure Figure 3 The first power semiconductor device 232-1 and the second power semiconductor device 232-2 included in each of the multiple power semiconductor modules 230 and 240 of 200 have been fully tested, so that the potential risks such as breakdown of each of the power semiconductor devices 232-1 and 232-2 due to overvoltage or rated failure can be fundamentally prevented, thereby improving product reliability.

[0137] Additionally, multiple power semiconductor modules in which the first power semiconductor device 232-1 and the second power semiconductor device 232-2 are surrounded by a molding layer 233 are used. Figure 4 The power converter manufactured according to this disclosure (230) Figure 3 When the first power semiconductor device 232-1 and the second power semiconductor device 232-2 are not exposed to the outside, it can prevent electrical short circuits caused by foreign objects or dust, thereby increasing production.

[0138] Meanwhile, existing power converters (or inverters) include multiple power semiconductor devices ( Figure 1a and Figure 1b The gap between the 30 and 40 in the middle is very narrow, which makes the adjacent power semiconductor devices 30 and 40 greatly affected by each other's thermal characteristics, and the heat dissipation characteristics of the heat generated from each power semiconductor device 30 and 40 are poor.

[0139] However, in this disclosure, the separation distance d1 between the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be greater than the separation distance d2 between the common gate pad 237 and the common source pad 239. The separation distance d1 between the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be one-third or greater than the width w1 of the first power semiconductor device 232-1 or the width w2 of the second power semiconductor device 232-2. For example, when the size (or area) of each of the first power semiconductor device 232-1 and the second power semiconductor device 232-2 is at most 5 mm × 5 mm, the separation distance d1 between the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be 4 mm or greater.

[0140] In this way, the separation distance d1 between the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be increased, and a molding layer 233 can be filled between the first power semiconductor device 232-1 and the second power semiconductor device 232-2. This ensures that not only are the first power semiconductor device 232-1 and the second power semiconductor device 232-2 almost unaffected by each other's thermal characteristics, but also that the heat dissipation characteristics of the heat generated in the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be improved. Regarding the separation distances d1 and d2, from... Figures 9 to 11 It is easier to understand in Chinese.

[0141] At the same time, refer to again Figure 4 The first power semiconductor module 230 may include a first gate contact 234-1, a first source contact 234-2, a second gate contact 235-1, a second source contact 235-2, an insulating layer 236, etc.

[0142] The first gate contact 234-1 and the first source contact 234-2 can be respectively disposed on the first gate electrode 330 and the first source electrode 340 of the first power semiconductor device 232-1. The accompanying drawings show that the dimensions of the first gate contact 234-1 are the same as those of the first gate electrode 330, and the dimensions of the first source contact 234-2 are the same as those of the first source electrode 340, but they can be different from each other.

[0143] The second gate contact 235-1 and the second source contact 235-2 can be respectively disposed on the second gate electrode 370 and the second source electrode 380 of the second power semiconductor device 232-2. Although the figures show that the dimensions of the second gate contact 235-1 are the same as those of the second gate electrode 370, and the dimensions of the second source contact 235-2 are the same as those of the second source electrode 380, they can be different from each other.

[0144] An insulating layer 236 may be disposed between a common gate pad 237 and a common source pad 239 to insulate the common gate pad 237 and the common source pad 239.

[0145] like Figure 4 As shown, the outer lateral surface of the common drain pad 231 can be vertically aligned with the outer lateral surface of the molding layer 233. For example... Figure 6 As shown, packages for multiple power semiconductor devices 232-1 to 232-4 can be cut. Figure 6 This enables the manufacture of power semiconductor modules comprising at least two or more power semiconductor devices 232-1 and 232-2. Figure 7a230), or a power semiconductor module including a single power semiconductor device 232-4 can be manufactured. Figure 7b (400). In this way, since power semiconductor modules that can be expanded to a variety of numbers are manufactured, in this disclosure, the first power semiconductor module 230 and the second power semiconductor module 240 can each be named a scalable submodule (SSM).

[0146] Figure 6 This is a cross-sectional view showing a plurality of power semiconductor devices packaged in the first aspect of this disclosure.

[0147] like Figure 6 As shown, multiple power semiconductor devices 232-1 to 232-4 can be packaged on a common drain pad 231'. For example, the common drain pad 231' can be formed on a wafer (not shown), and multiple power semiconductor devices 232-1 to 232-4, a molding layer 233, a common gate pad 237, a common source pad 239, etc., can be formed on the common drain pad 231'. Figure 6 In the diagram, the lateral surface of the molding layer 233 is shown to be aligned with the lateral surface of the common drain pad 231', but is not limited thereto, and the lateral surface of the common drain pad 231' may protrude further to the outer lateral portions on both sides than the lateral surface of the molding layer 233.

[0148] Alternatively, a process opposite to the one described above can be performed. For example, multiple power semiconductor devices 232-1 to 232-4 can be attached to pre-prepared common gate pad 237 and common source pad 239, and a common drain pad 231' can be attached to the multiple power semiconductor devices 232-1 to 232-4. Additionally, a molding layer 233 can be formed around each of the multiple power semiconductor devices 232-1 to 232-4.

[0149] Subsequently, a cutting process can be performed according to the preset sawing channel 2000, thereby manufacturing... Figure 7a and Figure 7b The power semiconductor modules 230 and 400 shown are illustrated. The wafer can be removed by performing processes such as grinding. With the wafer removed, the common drain pad 231 can be exposed to the outside, and the exposed common drain pad 231 can be directly electrically connected to the circuit patterns of the first substrate 210 or the second substrate 220 using an adhesive such as silver (Ag) paste, as shown. Figure 3 As shown.

[0150] Therefore, after multiple power semiconductor devices 232-1 to 232-4 are packaged on a common drain pad 231', they are cut according to a sawing channel 2000 set according to the number of power semiconductor devices 232-1 to 232-4 as desired by the customer, so that power semiconductor modules 230 and 400 can be easily manufactured according to the number of power semiconductor devices 232-1 to 232-4, thereby maximizing the degree of freedom in manufacturing power semiconductor modules 230 and 400.

[0151] Figure 8 A diagram showing multiple power semiconductor modules mounted on a first substrate is shown.

[0152] like Figure 8 As shown, in order to realize the power converter 200 according to the present disclosure, a plurality of power semiconductor modules 230, 240, 260 and 270 can be mounted on the first substrate 210 using a bonding process. For example, an adhesive such as Ag paste can be used to bond the plurality of power semiconductor modules 230, 240, 260 and 270 on the first substrate 210.

[0153] For example, the common drain pad of each of the first power semiconductor module 230 and the third power semiconductor module 260 can be bonded to a first circuit pattern of the first substrate 210. For example, the common gate pad of each of the second power semiconductor module 240 and the fourth power semiconductor module 270 can be bonded to a second circuit pattern of the first substrate 210, and the common source pad of each of the second power semiconductor module 240 and the fourth power semiconductor module 270 can be bonded to a third circuit pattern of the first substrate 210.

[0154] After the second substrate (not shown) is positioned on the first substrate 210, it can be bonded to a plurality of power semiconductor modules 230, 240, 260, and 270. In this case, the common gate pad of each of the first power semiconductor module 230 and the third power semiconductor module 260 can be bonded to a fourth circuit pattern of the second substrate, and the common source pad of each of the first power semiconductor module 230 and the third power semiconductor module 260 can be bonded to a fifth circuit pattern of the second substrate. The common drain pad of each of the second power semiconductor module 240 and the fourth power semiconductor module 270 can be bonded to a sixth circuit pattern of the second substrate. The third and sixth circuit patterns can be connected together to an output terminal.

[0155] Subsequently, an EMC molding process can be performed to form a molding layer (not shown) at least between the first substrate 210 and the second substrate, thereby manufacturing the power converter 200. This is to distinguish it from power semiconductor modules ( Figure 4The molding layer 233 of the power semiconductor module 230 can be referred to as the first molding layer, and the molding layer between the first substrate 210 and the second substrate can be referred to as the second molding layer.

[0156] Figure 9 This is a first diagram showing the layout of the common gate pad and the common source pad according to this disclosure.

[0157] like Figure 9 As shown, the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be disposed on the common drain pad 231.

[0158] The first power semiconductor device 232-1 may include components disposed on the same surface (i.e., disposed on the first semiconductor layer). Figure 4 The first gate electrode 330 and the first source electrode 340 are disposed on the upper surface of the second semiconductor layer 320. The second power semiconductor device 232-2 may include a second gate electrode 370 and a second source electrode 380 disposed on the same surface (i.e., on the upper surface of the second semiconductor layer 350). In this case, the first source electrode 340, the first gate electrode 330, the second gate electrode 370 and the second source electrode 380 may be arranged in a row in this order along one direction (X-axis direction).

[0159] The distance between the first gate electrode 330 of the first power semiconductor device 232-1 and the second gate electrode 370 of the second power semiconductor device 232-2 can be less than the distance between the first source electrode 340 of the first power semiconductor device 232-1 and the second source electrode 380 of the second power semiconductor device 232-2.

[0160] Common gate pad 237 and common source pad 239 can be disposed on the first power semiconductor device 232-1 and the second power semiconductor device 232-2.

[0161] The common gate pad 237 may be disposed in the central region of the common drain pad 231, and the common source pad 239 may surround the common gate pad 237.

[0162] The central region of the common drain pad 231 can be the first region of the common drain pad 231. Figure 4 231-1) and the second region ( Figure 4The area between 231-2). The outer lateral portion of the common gate pad 237 may have a first short lateral portion 237a and a second short lateral portion 237b in one direction (X-axis direction). The outer lateral portion of the common gate pad 237 may have a first long lateral portion 237c and a second long lateral portion 237d in a direction perpendicular to one direction (X-axis direction) (i.e., in the vertical direction (Y-axis direction)). The lengths of the first long lateral portion 237c and the second long lateral portion 237d may be greater than the length of each of the first short lateral portion 237a and the second short lateral portion 237b, respectively. The rectangular shape may be formed by the first short lateral portion 237a, the second short lateral portion 237b, the first long lateral portion 237c, and the second long lateral portion 237d. Although the figures show the common gate pad 237 as having a rectangular shape, it can be modified to another shape.

[0163] The common gate pad 237 can vertically overlap with the first power semiconductor device 232-1. The common gate pad 237 can vertically overlap with the first gate electrode 330 of the first power semiconductor device 232-1. The common gate pad 237 can vertically overlap with the second power semiconductor device 232-2. The common gate pad 237 can vertically overlap with the second gate electrode 370 of the second power semiconductor device 232-2. The size of the common gate pad 237 can be larger than the sum of the sizes of the first gate electrode 330 of the first power semiconductor device 232-1 and the second gate electrode 370 of the second power semiconductor device 232-2.

[0164] A common gate pad 237 may be disposed at a position that overlaps with a common drain pad 231 in a vertical direction, spaced apart from the common drain pad 231, and the common drain pad is exposed between the first power semiconductor device 232-1 and the second power semiconductor device 232-2. A first short lateral portion 237a of the common gate pad 237 may be positioned between the second gate electrode 370 and the second source electrode 380 of the second power semiconductor device 232-2. A second short lateral portion 237b of the common gate pad 237 may be positioned between the first gate electrode 330 and the first source electrode 340 of the first power semiconductor device 232-1.

[0165] The common source pad 239 can vertically overlap with the first power semiconductor device 232-1. The common source pad 239 can vertically overlap with the first source electrode 340 of the first power semiconductor device 232-1. The common source pad 239 can vertically overlap with the second power semiconductor device 232-2. The common source pad 239 can vertically overlap with the second source electrode 380 of the second power semiconductor device 232-2.

[0166] The size of the common gate pad 237 can be larger than the sum of the sizes of the first source electrode 340 of the first power semiconductor device 232-1 and the second source electrode 380 of the second power semiconductor device 232-2. Therefore, even if a common gate pad 237 larger than the size of the first power semiconductor device 232-1 or the second power semiconductor device 232-2 is bonded to the first substrate 210 or the second substrate 220 to realize the power converter 200, not only will bonding defects not occur, but the bonding strength can be significantly improved, thereby preventing defects such as detachment. In this way, bonding defects or detachment defects can be prevented, and yield can be increased.

[0167] Meanwhile, the common source pad 239 may surround at least two outer lateral portions of the common gate pad 237.

[0168] like Figure 9 As shown, the common source pad 239 may have a closed-loop structure surrounding the common gate pad 237. The common source pad 239 has an opening 280, and the common gate pad 237 may be positioned within the opening 280. In this case, the inner lateral portion of the common source pad 239 may be spaced apart from the outer lateral portion of the common gate pad 237.

[0169] A common source pad 239 may be disposed on a first short lateral portion 237a, a second short lateral portion 237b, a first long lateral portion 237c, and a second long lateral portion 237d of a common gate pad 237. The common source pad 239 may be spaced apart from the first short lateral portion 237a, the second short lateral portion 237b, the first long lateral portion 237c, and the second long lateral portion 237d of the common gate pad 237.

[0170] like Figure 9 As shown, the size of the common drain pad 231 can be larger than the sum of the sizes of the common gate pad 237 and the common source pad 239. In this way, due to the significantly increased size of the common drain pad 231, the heat generated from the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be rapidly dissipated to the outside. Therefore, as described above, the common drain pad 231 can be used as a heat dissipation component.

[0171] Figure 10 This is a second figure showing the layout of the common gate pad and the common source pad according to this disclosure.

[0172] Apart from the positions of the first gate electrode 330 of the first power semiconductor device 232-1, the second gate electrode 370 of the second power semiconductor device 232-2, the common gate pad 237, and the common source pad 239. Figure 10 and Figure 9 Identical. Therefore, parts with the same shape, structure and / or function are given the same reference numerals, and detailed descriptions thereof will be omitted thereafter.

[0173] like Figure 10 As shown, the first gate electrode 330 of the first power semiconductor device 232-1 can be positioned in a corner region. The second gate electrode 370 of the second power semiconductor device 232-2 can be positioned in a corner region.

[0174] The common gate pad 237 can be disposed at a distance from one side of the common drain pad 231, at a position that overlaps in space along the vertical direction. The common gate pad 237 can vertically overlap with the first gate electrode 330 of the first power semiconductor device 232-1, and can vertically overlap with the second gate electrode 370 of the second power semiconductor device 232-2.

[0175] like Figure 10 As shown, the common source pad 239 may have an open structure surrounding the common gate pad 237. That is, the common source pad 239 may be disposed on the first short lateral portion 237a, the second short lateral portion 237b, and the first long lateral portion 237c of the common gate pad 237. Alternatively, the common source pad 239 may not be disposed on the second long lateral portion 237d of the common gate pad 237, but is not limited thereto.

[0176] Figure 11 This is a third figure showing the layout of the common gate pad and the common source pad according to this disclosure.

[0177] Apart from Figure 11 In addition to the Kelvin source pad 290, it is related to Figure 10 The same. Therefore, parts with the same shape, structure, and / or function are given the same reference numerals, and detailed descriptions thereof will be omitted thereafter. Kelvin source pad 290 can also be applied to... Figure 9 The arrangement structure of the common gate pad 237 and the common source pad 239 in the middle.

[0178] Typically, a power converter 200 can be driven using a power semiconductor module, which includes a first power semiconductor device 232-1 and a second power semiconductor device 232-2 used as switches. For example, when the first power semiconductor device 232-1 and the second power semiconductor device 232-2 are turned on, the drive current can increase rapidly, and an induced voltage can be generated due to the parasitic capacitance on the source electrode. The induced voltage can flow into the gate electrode, causing a voltage drop. Therefore, the gate-source voltage decreases, slowing down the turn-on speed (i.e., the switching speed). Similarly, the turn-off speed also decreases during turn-off.

[0179] To address this issue, a Kelvin source pad 290 can be provided in this disclosure. The Kelvin source pad 290 can be a pad to be connected to a Kelvin source (or driver) that supplies a voltage separate from the gate voltage supplied to the common gate pad 237. Therefore, the aforementioned problem can be solved by supplying a voltage separate from and different from the gate voltage to the Kelvin source pad 290 via the Kelvin source.

[0180] When implementing the power converter 200 using power semiconductor devices, there is a problem that it is difficult to allocate a portion of the source electrode to the Kelvin source pad 290 because the power semiconductor devices are very small.

[0181] However, in this respect, as described above, the size of the common source pad 239 can be formed to be at least larger than the size of the first power semiconductor device 232-1 or the size of the second power semiconductor device 232-2. Therefore, as... Figure 11 As shown, a portion of the common source pad 239 can be assigned as the Kelvin source pad 290. That is, as Figure 10 As shown, since the common source pad 239 is sufficiently wide, the portion of the common source pad 239 located in the region between the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be configured as a Kelvin source pad 290. Although the Kelvin source pad 290 is shown in the figures as having a square shape, various shapes are also possible. Since the voltage from the Kelvin source is supplied to the Kelvin source pad 290, the generation of induced voltage on the common source pad 239 can be suppressed, and thus a decrease in switching speed can be prevented.

[0182] At the same time, Figures 9 to 11 In the diagram, the first source electrode 340 and the second source electrode 380 are each shown as rectangular, but they may have other shapes, such as those surrounding the first gate electrode 330 and the second gate electrode 370, respectively.

[0183] Figure 12This is a fourth figure showing the layout of a power semiconductor module according to the present disclosure.

[0184] Figure 12 The power semiconductor module 500A shown can be based on the above. Figures 9 to 11 The technical characteristics of power semiconductor modules will be discussed, and the following text will primarily refer to... Figure 12 The technical features of the power semiconductor module 500A shown are described below.

[0185] Figure 12 The power semiconductor module 500A shown is an example in which four power semiconductor devices 511 to 514 are disposed on a common drain pad 531 to form a module, and a common gate pad 530 is disposed on the four power semiconductor devices 511 to 514.

[0186] For example, the first power semiconductor device 511 to the fourth power semiconductor device 514 may each include a first source electrode 541 to a fourth source electrode 544 and a first gate electrode to a fourth gate electrode (not shown).

[0187] In the power semiconductor module 500A, the first power semiconductor device 511 to the fourth power semiconductor device 514 may include a first source pad 540a to a fourth source pad 540d respectively disposed on the first source electrode 541 to the fourth source electrode 544.

[0188] Additionally, the power semiconductor module 500A may include a common gate pad 530 disposed on the first gate electrode to the fourth gate electrode of the first power semiconductor device 511 to the fourth power semiconductor device 514.

[0189] The first source pads 540a to the fourth source pads 540d can surround the common gate pad 530. When the power semiconductor module 500A is divided into a central region and a peripheral region, the common gate pad 530 can be disposed in the central region, and the first source pads 540a to the fourth source pads 540d can be disposed in the peripheral region. The common gate pad 530 can vertically overlap with the first to fourth gate electrodes in the central region. The common gate pad 530 can be disposed not only on the first to fourth gate electrodes in the central region, but also in the region between the first to fourth gate electrodes, so that its size can be maximized.

[0190] Figure 12 The power semiconductor module 500A shown can be manufactured using the following manufacturing process.

[0191] First, a first lead frame including first source pads 540a to fourth source pads 540d and a common gate pad 530 can be provided. Conductive adhesive can be formed on the first lead frame using a paste printing process or a dot coating process, and the adhesive can be used to attach the first power semiconductor device 511 to the fourth power semiconductor device 514 to the first lead frame. Therefore, the first power semiconductor device 511 to the fourth power semiconductor device 514 can be electrically connected to the first source pads 540a to fourth source pads 540d and the common gate pad 530.

[0192] Subsequently, a conductive adhesive can be formed on the second lead frame, including the common drain pad 531, using a paste printing process. Then, the second lead frame can be attached to the first power semiconductor device 511 through the fourth power semiconductor device 514 using a sintering or soldering process. Therefore, the first power semiconductor device 511 through the fourth power semiconductor device 514 can be electrically connected to the common drain pad 531.

[0193] At the same time, such as Figures 13a to 13d As shown, Figure 12 The common gate pad 530 shown can be arranged in various shapes and locations.

[0194] like Figure 13a and Figure 13c As shown, the first common gate pad 530a can be disposed between the first source pad 540a and the fourth source pad 540d, and the second common gate pad 530b can be disposed between the second source pad 540b and the third source pad 540c.

[0195] like Figure 13b and Figure 13d As shown, the common gate pad 530 can be configured to extend from a first region between the first source pad 540a and the fourth source pad 540d to a second region between the second source pad 540b and the third source pad 540c.

[0196] At the same time, with Figure 13c and Figure 13d The difference lies in Figure 13a and Figure 13b In this process, a groove may be formed on one side of each of the first source pads 540a to the fourth source pads 540d, respectively facing the first common gate pad 530a and the second common gate pad 530b.

[0197] Figure 14 This is the fifth figure showing the layout of the power semiconductor module in this aspect.

[0198] Apart from the 550 connection part Figure 14 The power semiconductor module 500B shown can be used with Figure 12 The power semiconductor module shown is the same as the 500A.

[0199] Connection portion 550 can electrically connect the common gate pad 530 to the first substrate. Figure 3 210) or second substrate ( Figure 3 (220). The connection portion 550 may extend from the upper surface of the common gate pad 530 through the space between the first source pad 540a and the fourth source pad 540d. Alternatively, the connection portion 550 may extend from the upper surface of the common gate pad 530 between the first source pad 540a and the second source pad 540b, between the second source pad 540b and the third source pad 540c, or between the third source pad 540c and the fourth source pad 540d.

[0200] Figure 15 This is the sixth figure showing the layout of a power semiconductor module according to the present disclosure. Figure 15 The power semiconductor module 500C shown can be based on the above. Figures 9 to 12 The technical characteristics of power semiconductor modules will be discussed, and the following text will primarily refer to... Figure 12 The technical features of the power semiconductor module 500C shown are described below.

[0201] Figure 15 The power semiconductor module 500C shown is an example in which a common gate pad 530 and a common source pad 540 are disposed on four power semiconductor devices.

[0202] For example, Figure 12 The power semiconductor module 500C shown is an example in which four power semiconductor devices 511 to 514 are disposed on a common drain pad 531 to form a module, and a common gate pad 530 and a common source pad 540 are disposed on the four power semiconductor devices 511 to 514.

[0203] For example, the power semiconductor module 500C may include a common source pad 540 disposed on the first source electrode 541 to the fourth source electrode 544 of the first power semiconductor device 511 to the fourth power semiconductor device 514 and a common gate pad 530 disposed on the first gate electrode to the fourth gate electrode of the first power semiconductor device 511 to the fourth power semiconductor device 514.

[0204] exist Figure 12 In the power semiconductor module 500A shown, the first source pad 540a to the fourth source pad 540d can surround the common gate pad 530, while Figure 15In the power semiconductor module 500C shown, a common source pad 540 may surround a common gate pad 530. When the first source pad 540a to the fourth source pad 540d are integrally formed on... Figure 12 In the power semiconductor module 500A shown, a single common source pad 540 can be formed, as in Figure 15 The power semiconductor module 500C shown is used.

[0205] A connection pad (not shown) may be provided for electrically connecting the common gate pad 530 to an external connection pad. The common source pad 540 may have a separation region that includes at least the provided connection pad to prevent electrical short circuit to the provided connection pad. The separation region may be an area where the common source pad 540 is not formed.

[0206] at the same time, Figure 15 The diagram shows a common gate pad 530 located internally and a common source pad 540 located externally, but is not limited thereto.

[0207] For example, in the additional disclosure, the common gate pad 530 may be located externally, and the common source pad 540 may be located internally.

[0208] Specifically, in the power semiconductor module 500C of this aspect, the first gate electrode to the fourth gate electrode (not shown) of the first power semiconductor device 511 to the fourth power semiconductor device 514 can be respectively positioned at the outer corner, and the first source electrode 541 to the fourth source electrode 544 can be positioned inside.

[0209] Subsequently, the common gate pad 530 can be respectively disposed on the first gate electrode to the fourth gate electrode disposed at the outer corner, and the common source pad 540 can be disposed on the first source electrode 541 to the fourth source electrode 544 located inside.

[0210] The following will refer to Figures 16a to 16h The manufacturing process of the power semiconductor module according to this disclosure is described. However, the manufacturing process of the power semiconductor module according to this disclosure is not limited to... Figures 16a to 16h The process sequence or process content described in the document can be changed, some processes can be omitted, or additional processes can be added.

[0211] First, such as Figure 16aAs shown, multiple power semiconductor devices can be configured, such as a first power semiconductor device 232-1 and a second power semiconductor device 232-2. The first power semiconductor device 232-1 may include a first drain electrode 320, a first semiconductor layer 310, a first gate electrode 330, and a first source electrode 340. The second power semiconductor device 232-2 may include a second drain electrode 360, a second semiconductor layer 350, a second gate electrode 370, and a second source electrode 380.

[0212] In the first power semiconductor device 232-1, a first insulating layer 345 may be provided around each of the first gate electrode 330 and the second source electrode 380 to prevent electrical short circuits between the first gate electrode 330 and the first source electrode 340, and to protect the first semiconductor layer 310 from heat, moisture, impact, etc. In the second power semiconductor device 232-2, a second insulating layer 385 may be provided around each of the second gate electrode 370 and the second source electrode 385 to prevent electrical short circuits between the second gate electrode 370 and the second source electrode 380, and to protect the second semiconductor layer 350 from heat, moisture, impact, etc. The first insulating layer 345 and / or the second insulating layer 385 may be formed of an inorganic insulating material, but are not limited thereto.

[0213] like Figure 16b As shown, the first insulating layer 345 can be used as a mask to perform sputtering and / or electroplating processes, so that the first gate contact 234-1 and the first source contact 234-2 can be formed on the first gate electrode 330 and the first source electrode 340 of the first power semiconductor device 232-1, respectively. The second insulating layer 385 can be used as a mask to perform sputtering and / or electroplating processes, so that the second gate contact 235-1 and the second source contact 235-2 can be formed on the second gate electrode 370 and the second source electrode 380 of the second power semiconductor device 232-2, respectively. Here, the contact can be referred to as a pillar, support, etc.

[0214] At the same time, with Figure 16b Unlike the process shown, the processes for forming the first gate contact 234-1 and the first source contact 234-2 on the first power semiconductor device 232-1 and the processes for forming the first gate contact 235-1 and the first source contact 235-2 on the second power semiconductor device 232-2 can be performed by means of... Figure 16e The overmolding process shown is performed after the process of forming the molding layer 233.

[0215] like Figure 16a and Figure 16bThe process shown can be performed at the wafer level. That is, after forming drain electrodes 320 and 360, semiconductor layers 310 and 350, insulating layers 345 and 385, multiple gate electrodes 330 and 370, multiple source electrodes 340 and 380, multiple gate contacts 234-1 and 235-1, and multiple source contacts 234-2 and 235-2 on a wafer (not shown), a dicing process can be performed. Therefore, the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be formed from the wafer. The wafer can be removed before or after performing the dicing process.

[0216] like Figure 16c As shown, a common drain pad 231 can be provided. The common drain pad 231 can be formed of a metallic material with excellent conductivity. For example, the common drain pad 231 can have a three-layer structure of copper (Cu)-molybdenum (Mo)-copper (Cu).

[0217] like Figure 16d As shown, the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be bonded to a common drain pad 231. For example, the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be bonded to the common drain pad 231 using a sintering process. Adhesives such as Ag paste can be used in a given process, but are not limited thereto.

[0218] like Figure 16e As shown, an EMC molding process can be used to form a molding layer 233 on the first power semiconductor device 232-1 and the second power semiconductor device 232-2. Subsequently, as... Figure 16f As shown, the molding layer 233 on the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be removed using an EMC polishing process. Therefore, the upper surface of the molding layer 233 and the upper surfaces of the first gate contact 234-1, the first source contact 234-2, the second gate contact 235-1, and the second source contact 235-2 can be positioned on the same horizontal line. Meanwhile, as mentioned earlier, with... Figure 16e Unlike the process shown, the processes for forming the first gate contact 234-1 and the first source contact 234-2 on the first power semiconductor device 232-1 and the processes for forming the first gate contact 235-1 and the first source contact 235-2 on the second power semiconductor device 232-2 can be performed by means of... Figure 16e The overmolding process shown is performed after the process of forming the molding layer 233.

[0219] For example, the overmolded layer 233 can be grounded to expose the first gate electrode 330 and the first source electrode 340 of the first power semiconductor device 232-1, and the second gate electrode 370 and the second source electrode 380 of the second power semiconductor device 232-2.

[0220] like Figure 16h As shown, the following processes can then be performed: forming a first gate contact 234-1 and a first source contact 234-2 on the first power semiconductor device 232-1; forming a first gate contact 235-1 and a first source contact 235-2 on the second power semiconductor device 232-2; and forming a common gate pad 237 and a common source pad 239.

[0221] like Figure 16g and Figure 16h As shown, an insulating layer 236, a common gate pad 237, and a common source pad 239 can be formed. For example, after first forming the insulating layer 236, the insulating layer 236 can be used as a mask to perform sputtering and / or electroplating processes to form the common gate pad 237 and the common source pad 239. The insulating layer 236 can be formed on the remaining areas other than the areas where the common gate pad 237 and the common source pad 239 are to be formed. The common gate pad 237 and the common source pad 239 can be surrounded by the insulating layer 236. As described above, the size of each of the common gate pad 237 and the common source pad 239 can be enlarged. The size of each of the common gate pad 237 and the common source pad 239 can be freely adjusted by the layout of the insulating layer 236.

[0222] Meanwhile, the insulating layer 236 can protect the first power semiconductor device 232-1 and the second power semiconductor device 232-2 from heat, moisture, etc., and therefore can be referred to as a passivation layer. The insulating layer 236 can be formed of inorganic insulating materials, but is not limited to this.

[0223] Figure 17 This is a cross-sectional view showing a power semiconductor module according to the present disclosure.

[0224] although Figure 17 Multiple power semiconductor modules are shown. Figure 8 The first power semiconductor module 230 (of 230, 240, 260, and 270) may have a structure similar to the second power semiconductor module 240, the third power semiconductor module 260, and the fourth power semiconductor module 270. Figure 17 The structure of the first power semiconductor module 230 shown is the same. Therefore, from Figure 17The structure of the first power semiconductor module 230 shown can be easily understood to understand the structure of each of the second power semiconductor module 240, the third power semiconductor module 260, and the fourth power semiconductor module 270.

[0225] In addition to each of the common gate pads 237 and 247 being further amplified, the second aspect of this disclosure ( Figure 17 ) and the first aspect of this disclosure ( Figure 4 The same as in the second aspect of this disclosure. Figure 17 In this disclosure, components having the same shape, structure, and / or function are assigned to the first aspect ( Figure 4 The same reference numerals will be used in the accompanying drawings, and their detailed descriptions will be omitted. This can be understood from the first aspect of this disclosure. Figure 4 The second aspect of this disclosure is readily understood from the description of ) Figure 17 Description omitted in ().

[0226] like Figure 17 As shown, the first power semiconductor module 230 may include a first power semiconductor device 232-1, a second power semiconductor device 232-2, a molding layer 233, etc.

[0227] refer to Figure 5 and Figure 17 The first power semiconductor device 232-1 may include a first semiconductor layer 310, a first drain electrode 320, a first gate electrode 330, a first source electrode 340, etc. The second power semiconductor device 232-2 may include a second semiconductor layer 350, a second drain electrode 360, a second gate electrode 370, and a second source electrode 380.

[0228] The common gate pad 237 can be connected to the first gate electrode 330 of the first power semiconductor device 232-1 and the second gate electrode 370 of the second power semiconductor device 232-2. The common gate pad 237 can extend from the first gate electrode 330 of the first power semiconductor device 232-1 toward the second gate electrode 370 of the second power semiconductor device 232-2.

[0229] The common gate pad 237 can be disposed not only on the first power semiconductor device 232-1, but also on the second power semiconductor device 232-2, so that its size (or area) can be maximized.

[0230] The common gate pad 237 can be vertically overlapped with the first gate electrode 330 of the first power semiconductor device 232-1, the first source electrode 340 of the first power semiconductor device 232-1, the first gate electrode 330 of the second power semiconductor device 232-2, and the second source electrode 380 of the second power semiconductor device 232-2.

[0231] The common gate pad 237 can extend from the central region of the common drain pad 231 to the first source electrode 340 via the first gate electrode 330 of the first power semiconductor device 232-1, and can vertically overlap with the first source electrode 340. The common gate pad 237 can extend from the central region of the common drain pad 231 to the second source electrode 380 via the second gate electrode 370 of the second power semiconductor device 232-2, and can vertically overlap with the second source electrode 380. The central region of the common drain pad 231 can be a first region of the common drain pad 231 (…). Figure 17 231-1) and the second region ( Figure 17 The area between 231-2).

[0232] In this way, since the size (or area) of the common gate pad 237 is maximized, bonding defects or detachment defects can be prevented, and thus yield can be increased.

[0233] An insulating layer may be disposed between the common gate pad 237 and the first source electrode 340, and between the common gate pad 237 and the second source electrode 380, so as to prevent electrical short circuits between them.

[0234] Meanwhile, the common source pad 239 can be disposed on the first power semiconductor device 232-1 and the second power semiconductor device 232-2. The common source pad 239 can be connected together to the first source electrode 340 of the first power semiconductor device 232-1 and the second source electrode 380 of the second power semiconductor device 232-2.

[0235] The common source pad 239 may vertically overlap with and be electrically connected to the first source electrode 340 of the first power semiconductor device 232-1. The common source pad 239 may vertically overlap with and be electrically connected to the second source electrode 380 of the second power semiconductor device 232-2. The common source pad 239 may extend from the first source electrode 340 of the first power semiconductor device 232-1 toward the second source electrode 380 of the second power semiconductor device 232-2.

[0236] The size (or area) of the common source pad 239 may be larger than the size (or area) of the first power semiconductor device 232-1 or the second power semiconductor device 232-2. The outer lateral portion of the common source pad 239 may be disposed on the outer lateral portions of the first power semiconductor device 232-1 and / or the second power semiconductor device 232-2. For example, the common source pad 239 may be positioned closer to the outer lateral portion of the common drain pad 231 than to the outer lateral portion of the first source electrode 340 of the first power semiconductor device 232-1. Similarly, the common source pad 239 may be positioned closer to another outer lateral portion of the common drain pad 231 than to the outer lateral portion of the second source electrode 380 of the second power semiconductor device 232-2.

[0237] The common source pad 239 can be positioned spaced apart from the common gate pad 237 to prevent electrical short circuits with the common gate pad 237. The common source pad 239 can surround the common gate pad 237.

[0238] The size (or area) of the common drain pad 231 can be larger than the sum of the size (or area) of the common gate pad 237 and the common source pad 239.

[0239] Figure 18 This is a cross-sectional view showing a plurality of power semiconductor devices packaged in this disclosure.

[0240] In addition to the common gate pad 237 and the common source pad 239 Figure 18 The structure of the package shown is similar to Figure 6 The packaging components shown have the same structure. Therefore, in Figure 18 The structure of the package shown has the same as Figure 6 Components with the same shape, structure, and / or function as the packaged components shown are given the same reference numerals, and detailed descriptions thereof will be omitted. Figure 18 As shown, multiple power semiconductor devices 232-1 to 232-4 can be packaged on a common drain pad 231. For example, the common drain pad 231 can be formed on a wafer (not shown), and multiple power semiconductor devices 232-1 to 232-4, a molding layer 233, a common gate pad 237, a common source pad 239, etc., can be formed on the common drain pad 231.

[0241] Subsequently, a cutting process is performed according to the preset sawing channel 2000, which enables the manufacture of power semiconductor modules 230 and 400.

[0242] Therefore, after multiple power semiconductor devices 232-1 to 232-4 are packaged on a common drain pad 231, they can be cut according to a pre-defined sawing channel 2000 based on the number of power semiconductor devices 232-1 to 232-4 as desired by the customer, such that... Figure 19a and Figure 19b As shown, power semiconductor modules 230 and 400 can be easily manufactured according to the number of power semiconductor devices 232-1 to 232-4. Therefore, the degrees of freedom in manufacturing power semiconductor modules 230 and 400 can be maximized.

[0243] Figure 20 This is the seventh figure showing the layout of the common gate pad and the common source pad according to this disclosure.

[0244] In addition to the common gate pad 237 and the common source pad 239 Figure 20 The structure of the package shown is similar to Figure 9 The packaging components shown have the same structure. Therefore, in Figure 20 The structure of the package shown has the same as Figure 9 Components with the same shape, structure and / or function as the package shown are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0245] like Figure 20 As shown, the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be disposed on the common drain pad 231.

[0246] The first source electrode 340, the first gate electrode 330, the second gate electrode 370, and the second source electrode 380 can be arranged in a row in this order along one direction (X-axis direction).

[0247] Common gate pad 237 and common source pad 239 can be disposed on the first power semiconductor device 232-1 and the second power semiconductor device 232-2.

[0248] The common gate pad 237 may be disposed in the central region of the common drain pad 231, and the common source pad 239 may surround the common gate pad 237.

[0249] The common gate pad 237 can be vertically overlapped with the first power semiconductor device 232-1. The size of the common gate pad 237 can be larger than the sum of the sizes of the first gate electrode 330 of the first power semiconductor device 232-1 and the second gate electrode 370 of the second power semiconductor device 232-2.

[0250] A common gate pad 237 may be disposed at a position that overlaps with a common drain pad 231 in a vertical direction, spaced apart from the common drain pad 231, and the common drain pad is exposed between the first power semiconductor device 232-1 and the second power semiconductor device 232-2. A first short lateral portion 237a of the common gate pad 237 may be positioned on the second source electrode 380 of the second power semiconductor device 232-2. A second short lateral portion 237b of the common gate pad 237 may be positioned on the first source electrode 340 of the first power semiconductor device 232-1.

[0251] The common source pad 239 can be vertically overlapped with the first power semiconductor device 232-1. The common source pad 239 can be vertically overlapped with the second power semiconductor device 232-2.

[0252] like Figure 20 As shown, the size of the common drain pad 231 can be larger than the sum of the sizes of the common gate pad 237 and the common source pad 239. In this way, due to the significantly increased size of the common drain pad 231, the heat generated from the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be rapidly dissipated to the outside. Therefore, as described above, the common drain pad 231 can be used as a heat dissipation component.

[0253] Figure 21 This is Figure 8, illustrating the layout of the common gate pad and common source pad according to this disclosure. Figure 21 In the diagram, the positions of the first gate electrode 330 of the first power semiconductor device 232-1, the second gate electrode 370 of the second power semiconductor device 232-2, the common gate pad 237, and the common source pad 239 are... Figure 20 The same reference numerals are used for parts that have the same shape, structure, and / or function. Therefore, parts that have the same shape, structure, and / or function are given the same reference numerals, and detailed descriptions thereof will be omitted thereafter.

[0254] like Figure 21 As shown, the first gate electrode 330 of the first power semiconductor device 232-1 can be positioned in a corner region. The second gate electrode 370 of the second power semiconductor device 232-2 can be positioned in a corner region.

[0255] The common gate pad 237 and the common source pad 239 can be arranged parallel to each other along one direction (X-axis direction).

[0256] The first short lateral portion 237a of the common gate pad 237 can be positioned between the second source electrode 380 of the second power semiconductor device 232-2 and one side of the common drain pad 231. The first short lateral portion 237a of the common gate pad 237 can be positioned closer to one side of the common drain pad 231 than the outer lateral portion of the second source electrode 380 of the second power semiconductor device 232-2. The outer lateral portion of the second source electrode 380 can be positioned further away from the central region of the common drain pad 231 than the inner lateral portion of the second source electrode 380.

[0257] The second short lateral portion 237b of the common gate pad 237 can be positioned between the first source electrode 340 of the first power semiconductor device 232-1 and the other side of the common drain pad 231. The second short lateral portion 237b of the common gate pad 237 can be positioned closer to the other side of the common drain pad 231 than the outer lateral portion of the first source electrode 340 of the first power semiconductor device 232-1. One side and the other side of the common drain pad 231 can be positioned opposite each other. The outer lateral portion of the first source electrode 340 can be on the side further away from the central region of the common drain pad 231 than the inner lateral portion of the first source electrode 340.

[0258] The size of the common gate pad 237 can be equal to or smaller than the size of the common source pad 239. With this arrangement, due to the further enlargement of the size of the common gate pad 237, bonding defects or debonding defects can be prevented, and higher throughput can be achieved.

[0259] For example, the common gate pad 237 may be disposed on one side of the common drain pad 231 along one direction (X-axis direction) across the first source electrode 340 and the first gate electrode 330 of the first power semiconductor device 232-1, and the second gate electrode 370 and the second source electrode 380 of the second power semiconductor device 232-2. Similarly, the common source pad 239 may be disposed on the other side of the common drain pad 231 along one direction (X-axis direction) across the first source electrode 340 of the first power semiconductor device 232-1 and the second source electrode 380 of the second power semiconductor device 232-2. In the figures, the common gate pad 237 is shown vertically overlapping only a portion of the first gate electrode 330 of the first power semiconductor device 232-1 and only a portion of the second gate electrode 370 of the second power semiconductor device 232-2, but it may also vertically overlap the entire area of ​​the first gate electrode 330 and the entire area of ​​the second gate electrode 370.

[0260] Although not shown, the common source pad 239 may surround at least two outer portions of the common gate pad 237. Figure 22This is a ninth exemplary diagram illustrating the layout of the common gate pad and common source pad according to this disclosure.

[0261] Apart from Figure 22 Apart from the Kelvin source pad 290 in the middle, it is with Figure 21 The same. Therefore, parts with the same shape, structure, and / or function are given the same reference numerals, and detailed descriptions thereof will be omitted thereafter. Kelvin source pad 290 can also be applied to... Figure 20 The arrangement structure of the common gate pad 237 and the common source pad 239 in the middle.

[0262] Typically, a power converter 200 can be driven using a power semiconductor module, which includes a first power semiconductor device 232-1 and a second power semiconductor device 232-2 used as switches. For example, when the first power semiconductor device 232-1 and the second power semiconductor device 232-2 are turned on, the drive current increases rapidly, and an induced voltage can be generated by the parasitic capacitance on the source electrode. This induced voltage can flow into the gate electrode, causing a voltage drop. Therefore, the voltage between the gate and the source can be reduced, and the turn-on speed (i.e., the switching speed) can be slowed down. Similarly, the turn-off speed is also reduced during turn-off.

[0263] To address this issue, a Kelvin source pad 290 can be provided in this disclosure. The Kelvin source pad 290 can be a pad to be connected to a Kelvin source (or driver) that supplies a voltage separate from the gate voltage supplied to the common gate pad 237. Therefore, the aforementioned problem can be solved by supplying a voltage separate from and different from the gate voltage to the Kelvin source pad 290 via the Kelvin source.

[0264] When implementing the power converter 200 using power semiconductor devices, there is a problem that it is difficult to allocate a portion of the source electrode to the Kelvin source pad 290 because the power semiconductor devices are very small.

[0265] However, in this respect, as described above, the size of the common source pad 239 can be formed to be at least larger than the size of the first power semiconductor device 232-1 or the size of the second power semiconductor device 232-2. Therefore, as... Figure 22 As shown, a portion of the common source pad 239 can be assigned to the Kelvin source pad 290. The Kelvin source pad 290 can be integrally formed with the common source pad 239 and can be designated as the area to be connected to the Kelvin source.

[0266] like Figure 21As shown, since the common source pad 239 is wide enough, the portion of the common source pad 239 disposed in the region between the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be designated as the Kelvin source pad 290. That is, because the common source pad 239 is wide enough, sufficient size can be allocated to the Kelvin source pad 290 for connection to the Kelvin source. Although the Kelvin source pad 290 is shown in the figures as having a rectangular shape, various shapes are possible. Since the voltage from the Kelvin source is supplied to the Kelvin source pad 290, induced voltage on the common source pad 239 can be suppressed, and a decrease in switching speed is prevented.

[0267] At the same time, Figures 20 to 22 In the diagram, the first source electrode 340 and the second source electrode 380 are each shown as rectangles, but they may also have other shapes, such as shapes that surround the first gate electrode 330 and the second gate electrode 370, respectively.

[0268] Figure 23 Figure 10 shows the layout of a power semiconductor module according to this disclosure. Figure 23 The power semiconductor module shown can be based on the above. Figures 20 to 22 The technical characteristics of power semiconductor modules will be discussed, and the following text will primarily refer to... Figure 23 The technical features of the power semiconductor module shown are described. Figure 23 The power semiconductor module 600A shown is an example in which four power semiconductor devices 611 to 614 are disposed on a common drain pad 601 to form a module, and a common gate pad 630 is disposed on the four power semiconductor devices 611 to 614.

[0269] For example, the first power semiconductor device 611 to the fourth power semiconductor device 614 may each include a first source electrode 641 to a fourth source electrode 644, and each include a first gate electrode 631 to a fourth gate electrode 634.

[0270] In the power semiconductor module 600A, the first power semiconductor device 611 to the fourth power semiconductor device 614 may each include a first source pad 640a to a fourth source pad 640d disposed on the first source electrode 641 to the fourth source electrode 644.

[0271] Additionally, the power semiconductor module 600A may include a common gate pad 630 disposed on the first gate electrode 631 to the fourth gate electrode 634 of the first common gate pad to the fourth power semiconductor devices 611 to 614.

[0272] Figure 24Figure 11 shows the layout of a power semiconductor module according to this disclosure. Figure 24 The power semiconductor module shown can be based on the above. Figures 20 to 23 The technical characteristics of power semiconductor modules will be discussed, and the following text will primarily refer to... Figure 24 The technical features of the power semiconductor module shown are described.

[0273] Figure 24 The power semiconductor module 600B shown is an example in which a common gate pad 630 and a common source pad 640 are disposed on four power semiconductor devices.

[0274] For example, Figure 23 The power semiconductor module shown is an example in which four power semiconductor devices 611 to 614 are disposed on a common drain pad 601 to form a module, and a common gate pad 630 and a common source pad 640 are disposed on the four power semiconductor devices 611 to 614.

[0275] For example, the power semiconductor module 600B may include a common source pad 640 disposed on the first source electrode 641 to the fourth source electrode 644 of the first power semiconductor device 611 to the fourth power semiconductor device 614, and a common gate pad 630 disposed on the first gate electrode 631 to the fourth gate electrode 634 of the first power semiconductor device 611 to the fourth power semiconductor device 614.

[0276] at the same time, Figure 24 The diagram shows a common gate pad 630 disposed internally and a common source pad 640 disposed externally, but is not limited thereto. For example, in an additional disclosure, the common gate pad 630 may be disposed externally and the common source pad 640 may be disposed internally.

[0277] Specifically, in the power semiconductor module 600B of this aspect, the first gate electrode 631 to the fourth gate electrode 634 of the first power semiconductor device 611 to the fourth power semiconductor device 614 can be respectively positioned at the outer edge, and the first source electrode 641 to the fourth source electrode 644 can be respectively positioned on the inner lateral portion.

[0278] Subsequently, the common gate pad 630 may be disposed on the first gate electrode 631 to the fourth gate electrode 634 respectively disposed on the outer edge, and the common source pad 640 may be disposed on the first source electrode 641 to the fourth source electrode 644 positioned on the inner lateral portion.

[0279] The following will refer to Figures 25a to 25hThe manufacturing process of the power semiconductor module according to this disclosure is described. However, the manufacturing process of the power semiconductor module according to this disclosure is not limited to... Figures 25a to 25h The process sequence or process content described in the document can be changed, some processes can be omitted, or other processes can be added.

[0280] First, such as Figure 25a As shown, multiple power semiconductor devices can be configured, such as a first power semiconductor device 232-1 and a second power semiconductor device 232-2. The first power semiconductor device 232-1 may include a first drain electrode 320, a first semiconductor layer 310, a first gate electrode 330, and a first source electrode 340. The second power semiconductor device 232-2 may include a second drain electrode 360, a second semiconductor layer 350, a second gate electrode 370, and a second source electrode 380.

[0281] In the first power semiconductor device 232-1, a first insulating layer 345 may be provided around each of the first gate electrode 330 and the second source electrode 380 to prevent electrical short circuits between the first gate electrode 330 and the first source electrode 340, and to protect the first semiconductor layer 310 from heat, moisture, impact, etc. In the second power semiconductor device 232-2, a second insulating layer 385 may be provided around each of the second gate electrode 370 and the second source electrode 385 to prevent electrical short circuits between the second gate electrode 370 and the second source electrode 380, and to protect the second semiconductor layer 350 from heat, moisture, impact, etc. The first insulating layer 345 and / or the second insulating layer 385 may be formed of an inorganic insulating material, but are not limited thereto.

[0282] like Figure 25b As shown, the first insulating layer 345 can be used as a mask to perform sputtering and / or electroplating processes, so that the first gate contact 234-1 and the first source contact 234-2 can be formed on the first gate electrode 330 and the first source electrode 340 of the first power semiconductor device 232-1, respectively. The second insulating layer 385 can be used as a mask to perform sputtering and / or electroplating processes, so that the second gate contact 235-1 and the third source contact can be formed on the second gate electrode 370 and the second source electrode 380 of the second power semiconductor device 232-2, respectively. Here, the contact can be referred to as a pillar, support, etc.

[0283] At the same time, with Figure 25b Unlike the process shown, the processes for forming the first gate contact 234-1 and the first source contact 234-2 on the first power semiconductor device 232-1 and the processes for forming the first gate contact 235-1 and the first source contact 235-2 on the second power semiconductor device 232-2 can be performed by means of... Figure 25e The overmolding process shown is performed after the process of forming the molding layer 233.

[0284] like Figure 25a and Figure 25b The process shown can be performed at the wafer level. That is, after forming drain electrodes 320 and 360, semiconductor layers 310 and 350, insulating layers 345 and 385, multiple gate electrodes 330 and 370, multiple source electrodes 340 and 380, multiple gate contacts 234-1 and 235-1, and multiple source contacts 234-2 and 235-2 on a wafer (not shown), a dicing process can be performed. Therefore, the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be formed from the wafer. The wafer can be removed before or after performing the dicing process.

[0285] like Figure 25c As shown, a common drain pad 231 can be provided. The common drain pad 231 can be formed of a metallic material with excellent conductivity. For example, the common drain pad 231 can have a three-layer structure of copper (Cu)-molybdenum (Mo)-copper (Cu).

[0286] like Figure 25d As shown, the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be bonded to a common drain pad 231. For example, the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be bonded to the common drain pad 231 using a sintering process. Adhesives such as Ag paste can be used in a given process, but are not limited thereto.

[0287] like Figure 25e As shown, an EMC molding process can be used to form a molding layer 233 on the first power semiconductor device 232-1 and the second power semiconductor device 232-2. Subsequently, as... Figure 25f As shown, the molding layer 233 on the first power semiconductor device 232-1 and the second power semiconductor device 232-2 can be removed using an EMC polishing process. Therefore, the upper surface of the molding layer 233 and the upper surfaces of the first gate contact 234-1, the first source contact 234-2, the second gate contact 235-1, and the second source contact 235-2 can be positioned on the same horizontal line.

[0288] At the same time, as mentioned above, with Figure 25e Unlike the process shown, the processes for forming the first gate contact 234-1 and the first source contact 234-2 on the first power semiconductor device 232-1 and the processes for forming the first gate contact 235-1 and the first source contact 235-2 on the second power semiconductor device 232-2 can be performed by means of... Figure 25eThe overmolding process shown is performed after the process of forming the molding layer 233.

[0289] For example, the molded layer 233 can be ground to expose the first gate electrode 330 and the first source electrode 340 of the first power semiconductor device 232-1, and the second gate electrode 370 and the second source electrode 380 of the second power semiconductor device 232-2.

[0290] like Figure 25h As shown, the following processes can then be performed: forming a first gate contact 234-1 and a first source contact 234-2 on the first power semiconductor device 232-1; forming a first gate contact 235-1 and a first source contact 235-2 on the second power semiconductor device 232-2; and forming a common gate pad 237 and a common source pad 239.

[0291] like Figure 25g and Figure 25h As shown, an insulating layer 236, a common gate pad 237, and a common source pad 239 can be formed. The insulating layer 236 can be formed such that the common gate pad 237 vertically overlaps with the first gate electrode 330 and the first source electrode 340 of the first power semiconductor device 232-1, and the second gate electrode 370 and the second source electrode 380 of the second power semiconductor device 232-2, respectively.

[0292] Subsequently, sputtering and / or electroplating processes can be performed using the insulating layer 236 as a mask to form the common gate pad 237 and the common source pad 239. The insulating layer 236 can be formed on the remaining areas besides where the common gate pad 237 and the common source pad 239 are to be formed. The common gate pad 237 and the common source pad 239 can be surrounded by the insulating layer 236. As described above, the size of each of the common gate pad 237 and the common source pad 239 can be enlarged. The size of each of the common gate pad 237 and the common source pad 239 can be freely adjusted through the layout of the insulating layer 236.

[0293] Meanwhile, the insulating layer 236 can protect the first power semiconductor device 232-1 and the second power semiconductor device 232-2 from heat, moisture, etc., and therefore can be referred to as a passivation layer. The insulating layer 236 can be formed of inorganic insulating materials, but is not limited to this.

[0294] The above detailed description should not be construed as restrictive in all respects, but rather as illustrative. The scope of each aspect should be determined by a reasonable interpretation of the appended claims, and all modifications within the equivalent scope of these aspects are included within the scope of these aspects.

Claims

1. A power semiconductor module, the power semiconductor module comprising: a common drain pad; a first power semiconductor device on a first region of the common drain pad; a second power semiconductor device on a second region of the common drain pad; a common gate pad on the first power semiconductor device and the second power semiconductor device; and a source pad on the first power semiconductor device and the second power semiconductor device, wherein the common drain pad is configured to be electrically connected to a first drain electrode of the first power semiconductor device and a second drain electrode of the second power semiconductor device, wherein the common gate pad is configured to be electrically connected to a first gate electrode of the first power semiconductor device and a second gate electrode of the second power semiconductor device, wherein the source pad is configured to be electrically connected to a first source electrode of the first power semiconductor device and a second source electrode of the second power semiconductor device, and wherein the source pad is configured to surround at least two outer lateral portions of the common gate pad. The source pad comprises a common source pad vertically overlapping the first power semiconductor device and the second power semiconductor device.

2. The power semiconductor module according to claim 1, wherein, The common source pad has an opening and the common gate pad is positioned in the opening.

3. The power semiconductor module of claim 2, wherein, The common gate pad comprises a first short lateral portion and a second short lateral portion in one direction and a first long lateral portion and a second long lateral portion in a direction perpendicular to the one direction.

4. The power semiconductor module of claim 2, wherein, The common source pad is positioned on the first short lateral portion, the second short lateral portion, and the first long lateral portion of the common gate pad.

5. The power semiconductor module of claim 4, wherein, The common source pad is positioned on the second long lateral portion of the common gate pad.

6. The power semiconductor module of claim 5, wherein, The first short lateral portion of the common gate pad is positioned between the first gate electrode and the first source electrode, and 7. The power semiconductor module of claim 4, wherein, wherein the second short lateral portion of the common gate pad is positioned between the second gate electrode and the second source electrode. The source pad comprises a first source pad and a second source pad vertically overlapping the first source electrode of the first power semiconductor device and the second source electrode of the second power semiconductor device, respectively.

8. The power semiconductor module of claim 1, wherein, 9. The power semiconductor module of claim 1, further comprising: a Kelvin source pad spaced apart from the source pad on the first power semiconductor device and the second power semiconductor device. The common gate pad has a size greater than a size of the first gate electrode of the first power semiconductor device or a size of the second gate electrode of the second power semiconductor device.

10. The power semiconductor module of claim 1, wherein, 11. A power semiconductor module, the power semiconductor module comprising: a common drain pad; a first power semiconductor device on a first region of the common drain pad; a second power semiconductor device on a second region of the common drain pad; a second power semiconductor device on a second region of the common drain pad; a common gate pad on the first power semiconductor device and the second power semiconductor device; and a source pad on the first power semiconductor device and the second power semiconductor device, wherein the common drain pad is configured to be electrically connected to a first drain electrode of the first power semiconductor device and a second drain electrode of the second power semiconductor device, wherein the common gate pad is configured to be electrically connected to a first gate electrode of the first power semiconductor device and a second gate electrode of the second power semiconductor device, wherein the source pad is configured to be electrically connected to a first source electrode of the first power semiconductor device and a second source electrode of the second power semiconductor device, and wherein the common gate pad vertically overlaps at least one of the first source electrode and the second source electrode.

12. The power semiconductor module of claim 11, wherein, The common gate pad is disposed across the first source electrode and the first gate electrode and the second gate electrode and the second source electrode along one direction on the first region of the common drain pad.

13. The power semiconductor module of claim 11, wherein, The source pad includes a common source pad vertically overlapping the first power semiconductor device and the second power semiconductor device.

14. The power semiconductor module of claim 13, wherein, The common source pad is disposed across the first source electrode and the second source electrode along one direction on the second region of the common drain pad.

15. The power semiconductor module of claim 13, wherein, An area of the common source pad is greater than an area of the first source electrode of the first power semiconductor device or an area of the second source electrode of the second power semiconductor device.

16. The power semiconductor module of claim 13, wherein, An area of the common drain pad is greater than a sum of an area of the common gate pad and an area of the common source pad.

17. The power semiconductor module of claim 1, wherein, The source pad includes a first source pad and a second source pad vertically overlapping the first source electrode of the first power semiconductor device and the second source electrode of the second power semiconductor device, respectively.

18. The power semiconductor module of claim 11, further comprising: a Kelvin source pad spaced apart from the source pad on the first power semiconductor device and the second power semiconductor device.

19. A power converter, comprising: a first substrate; a second substrate; and a plurality of power semiconductor modules between the first substrate and the second substrate, wherein the plurality of power semiconductor modules each includes: a common drain pad; a first power semiconductor device on a first region of the common drain pad; a second power semiconductor device on a second region of the common drain pad; a common gate pad on the first power semiconductor device and the second power semiconductor device; and a source pad on the first power semiconductor device and the second power semiconductor device, wherein the common drain pad is configured to be electrically connected to a first drain electrode of the first power semiconductor device and a second drain electrode of the second power semiconductor device, wherein the common gate pad is configured to be electrically connected to a first gate electrode of the first power semiconductor device and a second gate electrode of the second power semiconductor device, wherein the source pad is configured to be electrically connected to a first source electrode of the first power semiconductor device and a second source electrode of the second power semiconductor device, and wherein the common gate pad vertically overlaps at least one of the first source electrode and the second source electrode. a common source pad on the first and second power semiconductor devices, wherein the common source pad is configured to surround at least two lateral portions of the common gate pad, wherein in some of the plurality of power semiconductor modules, the common drain pad is configured to be electrically connected to the first substrate, the common gate pad and the common source pad are each electrically connected to the second substrate, and wherein in remaining ones of the plurality of power semiconductor modules, the common drain pad is configured to be electrically connected to the second substrate, and the common gate pad and the common source pad are each electrically connected to the first substrate.

20. The power converter of claim 19, further comprising: a plurality of terminals connected to each of the first and second substrates.

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