Isolation module for backside power delivery

Abstract

A method of forming a portion of a gate all around field effect transistor (GAA FET) includes forming reserved locations in a recess formed in a portion of a substrate isolated by shallow trench isolation (STI), each reserved location interfacing with an extension region via a cap layer, the recess extending into an interlayer dielectric (ILD) formed on the substrate; selectively removing the reserved location relative to the substrate, the cap layer, and the STI; forming a selective cap layer at the bottom of the groove; performing a substrate removal process to perform isotropic etching on the substrate in the recess; performing a conformal deposition process to form spacer pads on exposed surfaces of the substrate and the selective cap layer within the recess; carving spacing pads on the side walls of the substrate and the STI in the groove; executing a cap layer removal process to remove the cap layer in the groove; and forming a metal contact in the groove.

Description

TECHNICAL FIELD

[0001] This application claims priority to U.S. Provisional Patent Application Serial No. 63 / 529,662, filed July 28, 2023, which is incorporated by reference herein in its entirety.

[0002] Embodiments described herein relate to semiconductor device fabrication, and more particularly, to forming isolation modules for backside power delivery. BACKGROUND

[0003] Conventionally, a wafer is composed of transistors located on the front side of a silicon wafer and all interconnect structures built on top of the transistors to power and transmit data signals for the transistors. One of the key technologies to scale below 3 nm involves delivering power on the backside of the wafer. This way of backside power delivery eliminates the need to share interconnect resources between signal lines and power lines on the front side of the wafer, as power is transferred to the backside of the wafer. Backside power delivery also eliminates the need for power delivery tracks to lower level front side interconnect structures, saving cost. Backside power delivery also allows different metal layers to be fabricated in an optimized way, such as wider lines for operating voltage VDDand common ground voltage VSS, while thinner lines for transmitting signals. dd ss However, backside power delivery comes with new challenges, such as patterning electrical contact patterns isolated from each other by isolation modules in a confined space on the backside of the wafer without impacting the performance of transistors located on the front side of the wafer.

[0004] Therefore, there is a need for related methods to overcome such challenges faced by backside power delivery.

[0005] SUMMARY

[0006] ​​Embodiments of the present disclosure provide a method of forming a portion of a gate-all-around field-effect transistor (GAA FET). The method includes performing a reservation site formation process to form reservation sites in a recess formed in a portion of a substrate isolated by a shallow trench isolation (STI), each reservation site interfacing with an extension region via a cap layer, the recess extending into an inter-layer dielectric (ILD) formed on the substrate; performing a reservation site removal process to selectively remove the reservation sites relative to the substrate, the cap layer, and the STI; performing a selective deposition process to form a selective cap layer at a bottom of the recess; performing a substrate removal process to isotropically etch the substrate within the recess; performing a conformal deposition process to form a spacer pad on the substrate within the recess and an exposed surface of the selective cap layer; performing a spacer pad sculpting process to sculpt the spacer pad on sidewalls of the substrate and the STI within the recess; performing a cap layer removal process to remove the cap layer within the recess; and performing a contact metallization process to form a metal contact within the recess.

[0007] Embodiments of the present disclosure also provide a method of forming a portion of a gate-all-around field-effect transistor (GAA FET). The method includes performing a reservation site formation process to form reservation sites in a recess formed in a portion of a substrate isolated by a shallow trench isolation (STI), each reservation site interfacing with an extension region via a cap layer, the recess extending into an inter-layer dielectric (ILD) formed on the substrate; performing a reservation site removal process to selectively remove the reservation sites relative to the substrate, the cap layer, and the STI; performing a substrate removal process to isotropically etch the substrate within the recess; performing a conformal deposition process to form a spacer pad on the substrate within the recess and an exposed surface of the cap layer; performing a spacer pad sculpting process to sculpt the spacer pad on sidewalls of the substrate and the STI within the recess; performing a cap layer removal process to remove the cap layer within the recess; and performing a contact metallization process to form a metal contact within the recess.

[0008] Embodiments of the present disclosure also provide a semiconductor structure forming a portion of a fully wrapped gate field effect transistor (GAAFET). The method includes a channel layer embedded in an interlayer dielectric (ILD) formed on a substrate, the channel layer extending along a first direction; a metal gate embedded in the ILD, the metal gate extending along the first direction; a source / drain (S / D) contact electrically connected to the channel layer via an extension region and S / D epitaxial layers on both sides of the channel layer; a shallow trench isolation (STI) formed within the substrate; a metal contact formed between the STIs, the metal contact extending along a second direction orthogonal to the first direction, wherein each of the metal contacts is electrically connected to one of the S / D epitaxial layers and surrounded by a spacer pad; and a cap layer formed between the extension region and the spacer pad. BRIEF DESCRIPTION OF DRAWINGS

[0009] For a more complete understanding of the above-described features of the present disclosure, reference is made to the detailed description of the disclosure taken in connection with the accompanying drawings in which certain embodiments are illustrated. However, it is to be noted that the appended drawings are intended solely for purposes of illustration and should not be construed as limiting the scope of the present disclosure, as other embodiments of the present disclosure can be made.

[0010] Figure 1 is a top view schematic of a multi-chamber processing system according to one or more embodiments of the present disclosure.

[0011] Figure 2 is an isometric view of a semiconductor structure forming a portion of a fully wrapped gate field effect transistor (GAAFET) according to one or more embodiments of the present structure.

[0012] Figure 3 A process flow diagram of a method of forming a unit transistor in a semiconductor structure according to one embodiment is described.

[0013] Figure 4A 、 Figure 4A' 、 Figure 4B 、 Figure 4B' 、 Figure 4C 、 Figure 4D 、 Figure 4D' 、 Figure 4E 、 Figure 4E' 、 Figure 4F 、 Figure 4F' 、 Figure 4G 、 Figure 4G' 、 Figure 4H 、 Figure 4H' 、 Figure 4I 、 Figure 4I' 、 Figure 4J 、 Figure 4J' 、 Figure 4K 、 Figure 4K' 、Figure 4L and Figure 4L' are isometric views of portions of a semiconductor structure corresponding to various states of the method in Figure 3

[0014] For purposes of explanation, identical elements and features shown in different figures are identified with the same reference numerals. It is to be noted that the use of identical numbers in different figures is intended to represent similar or identical elements or features. Embodiments can be used in any combination thereof. In the figures and the following description, an orthogonal coordinate system including an X-axis, a Y-axis, and a Z-axis is used. For convenience, the direction indicated by the arrow in the figures is referred to as the positive direction. It is to be noted that elements disclosed in some embodiments can be beneficially used in other embodiments without specific recitation. DETAILED DESCRIPTION

[0015] Embodiments described herein provide methods of forming metal contacts on the backside of a wafer that are isolated from each other by an interlayer dielectric (ILD) while protecting an extended region (e.g., doped silicon (Si) or silicon germanium (SiGe)) on the frontside of the wafer. A selective underlayer (e.g., silicon nitride (Si3N4)) is used when etching the silicon (Si) wafer because the silicon (Si) wafer cannot be selectively patterned from the backside relative to the extended region. The selective underlayer also protects the underlying extended region from any damage during the silicon (Si) wafer etch.

[0016] Figure 1 is a top-down schematic view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 with respective transfer robots 112, 114, holding chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As described in detail herein, substrates in the processing system 100 can be processed in various chambers and transferred between various chambers without exposing the substrates to the ambient environment outside of the processing system 100 (e.g., such as the atmospheric ambient environment that can be present in a wafer fab). For example, substrates can be processed in various chambers and transferred between various chambers that maintain a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment without breaking the low pressure or vacuum environment between various processes performed on the substrates in the processing system 100. Thus, the processing system 100 can provide an integrated solution for certain substrate processing.

[0017] ​Examples of processing systems that can be modified as appropriate in light of the teachings provided herein include Endura®, Producer®, or Centura® integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc. of Santa Clara, California. It is contemplated that other processing systems, including those from other manufacturers, can be adapted to benefit from aspects described herein.

[0018] In Figure 1 In the illustrated example, the factory interface 102 includes a dock station 132 and factory interface robots 134 for transferring substrates. The dock station 132 is configured to accept one or more front opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed at an end of the respective factory interface robot 134 that is used to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0019] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 also has respective ports 148, 150 coupled to the holding chambers 116, 118 and respective ports 152, 154 coupled to the processing chambers 120, 122. Likewise, the transfer chamber 110 has respective ports 156, 158 coupled to the holding chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. For example, the ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be slit valve openings with slit valves for passing substrates therethrough by the transfer robots 112, 114 and providing a seal between chambers to prevent gas from passing between chambers. Generally, any port is opened for transferring a substrate therethrough. In other cases, the ports are in a closed state.

[0020] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 can be fluidly coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo pumps, roughing pumps), gas sources, various valves, and conduits fluidly coupled to the various chambers. In operation, the factory interface robot 134 transfers a substrate from the FOUP 136 to the load lock chamber 104 or 106 through the port 140 or 142. The gas and pressure control system then evacuates the load lock chamber 104 or 106. The gas and pressure control system also maintains the transfer chambers 108, 110 and the holding chambers 116, 118 at an internal low pressure or vacuum environment (which can include an inert gas). Thus, the evacuation of the load lock chamber 104 or 106 facilitates the transfer of the substrate between the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0021] While the substrate is in the load lock chamber 104 or 106 after being evacuated, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 to the transfer chamber 108 through the port 144 or 146. The transfer robot 112 can then transfer the substrate to and / or between any of the processing chambers 120, 122 through respective ports 152, 154 for processing and to and / or between any of the holding chambers 116, 118 through respective ports 148, 150 for further transfer. Likewise, the transfer robot 114 can access a substrate in the holding chamber 116 or 118 through the port 156 or 158 and can transfer the substrate to and / or between any of the processing chambers 124, 126, 128, 130 through respective ports 160, 162, 164, 166 for processing and to and / or between any of the holding chambers 116, 118 through respective ports 156, 158 for further transfer. The transfer and holding of the substrate within and between the various chambers can be performed in the low pressure or vacuum environment provided by the gas and pressure control system.

[0022] The processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chamber for processing a substrate. In some examples, the processing chamber 120 is capable of performing an etch process, the processing chamber 122 is capable of performing a cleaning process, the processing chamber 124 is capable of performing a selective removal process, the processing chamber 126 is capable of performing a chemical vapor deposition (CVD) deposition process, and the processing chambers 128, 130 are capable of performing respective epitaxial growth processes. The processing chamber 120 can be a Selectra™ Etch chamber available from Applied Materials, Inc., located in Santa Clara, Calif. The processing chamber 122 can be a SiCoNi™ pre-clean chamber available from Applied Materials, Inc., located in Santa Clara, Calif. The processing chamber 126 can be a WxZ™ chamber available from Applied Materials, Inc., located in Santa Clara, Calif. The processing chamber 128 or 130 can be a Centura™ Epi chamber available from Applied Materials, Inc., located in Santa Clara, Calif.

[0023] A system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or components thereof. For example, the system controller 168 can control the operation of the processing system 100 using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 can collect data from the various chambers and obtain feedback to coordinate the execution of the processing system 100.

[0024] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuits 174. The CPU 170 can be one of any form of general purpose processor that can be used in an industrial setting. The memory 172, or non-transitory computer readable medium, is accessible by the CPU 170 and can be one or more of a RAM, a ROM, a floppy disk, a hard disk, or any other form of local or remote digital storage. The support circuits 174 are coupled to the CPU 170 and can include cache, clock circuits, input / output subsystems, power supplies, and the like. Under the control of the CPU 170, the various methods disclosed herein can typically be implemented by computer instruction code stored in the memory 172 (or the memory of a particular processing chamber) that is executed by the CPU 170. The CPU 170, when executing the computer instruction code, will control the processing chamber to perform processes in accordance with the various methods.

[0025] Other processing systems can employ other configurations. For example, more or fewer processing chambers can be coupled to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 108, 110 and hold chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer hold chambers (e.g., no hold chambers) can be implemented as a transfer apparatus in a processing system.

[0026] Figure 2 is an isometric view of a portion of a semiconductor structure 200 that can form a full wrap-around gate-all-around field effect transistor (GAAFET) in accordance with one or more embodiments of the present structure. In Figure 2 In, a cross-sectional view of the semiconductor structure 200 along the YZ plane (including the cross-sectional line A-A) is shown, as well as a cross-sectional view of the semiconductor structure 200 along the ZX plane (including the cross-sectional line B-B). The semiconductor structure 200 is formed on a substrate, and in Figure 2 In, the backside of the semiconductor structure 200 is shown facing up.

[0027] As used herein, the term "substrate" refers to a layer of material upon which subsequent processing operations are performed and includes the surface to be cleaned. The substrate can be a silicon-based material or any suitable insulating or conductive material, as desired. The substrate can include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped poly silicon, doped or undoped silicon wafers and patterned or non-patterned wafers, silicon on insulator (SOI), carbon doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, and the like.

[0028] As shown in FIG. 1, a semiconductor structure 100 includes a channel layer 102 and a replacement-metal-gate (RMG) stack 104 extending along a Y-direction, embedded in an interlayer dielectric (ILD) 106. Each of the RMG stacks 104 includes a gate metal 108 and a high-k material 110. The gate metal 108 can be formed of titanium nitride (TiN), titanium aluminum carbide (TiAlC), or tungsten (W). The high-k material 110 can be formed of hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO2), aluminum oxide (Al2O3). Figure 2

[0029] The channel layer 102 can be formed of silicon (Si), germanium (Ge), silicon germanium (SiGe), or indium gallium zinc oxide (IGZO). A surface of the RMG stack 104 can be covered with a spacer pad 112. The spacer pad 112 can be formed of a dielectric material such as silicon oxide (SiO2), silicon oxy-carbide (SiOC), silicon oxy-carbon-nitride (SiOCN), silicon boron carbon nitride (SiBCN), or silicon nitride (Si3N4). The ILD 106 can be formed of silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxy-carbon-nitride (SiOCN), aluminum oxide (Al2O3), or any combination thereof.

[0030] The semiconductor structure 100 further includes source / drain (S / D) contacts 114 electrically connected to the channel layer 102 via extension regions 116 and p-channel S / D epi layers 118P, and via extension regions (not shown) and n-channel S / D epi layers 118N. The p-channel S / D epi layers 118P and the n-channel S / D epi layers 118N are interfaced with the S / D contacts 114 via a contact etch stop layer (CESL) 120 and an interface 122 and a liner 124.

[0031] ​The S / D contacts 214 can be formed of tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), their conductive oxides or nitrides, or any combination thereof.

[0032] The extension region 216 can be formed of silicon germanium (SiGe) with a germanium (Ge) fraction ranging between 0% and 15%, for example, about 10%, lightly doped with a p-type dopant, such as boron (B) or gallium (Ga), at a concentration ranging between about 1 x 1016cm-3and 5 x 1018cm-3, depending on the conductive properties required of the extension region 216. 18 cm −3 The extension region 216 can be formed of silicon germanium (SiGe) with a germanium (Ge) fraction ranging between 0% and 15%, for example, about 10%, lightly doped with a p-type dopant, such as boron (B) or gallium (Ga), at a concentration ranging between about 1 x 1016cm-3and 5 x 1018cm-3, depending on the conductive properties required of the extension region 216. 20 cm −3 The extension region 216 can be formed of silicon germanium (SiGe) with a germanium (Ge) fraction ranging between 0% and 15%, for example, about 10%, lightly doped with a p-type dopant, such as boron (B) or gallium (Ga), at a concentration ranging between about 1 x 1016cm-3and 5 x 1018cm-3, depending on the conductive properties required of the extension region 216.

[0033] The p-channel S / D epitaxial layer 218P can be formed of epitaxially grown silicon germanium (SiGe) with a germanium (Ge) fraction ranging between 25% and 50%, doped with a p-type dopant, such as boron (B) or gallium (Ga), at a concentration ranging between about 10 20 cm −3 The p-channel S / D epitaxial layer 218P can be formed of epitaxially grown silicon germanium (SiGe) with a germanium (Ge) fraction ranging between 25% and 50%, doped with a p-type dopant, such as boron (B) or gallium (Ga), at a concentration ranging between about 10 21 cm −3 The p-channel S / D epitaxial layer 218P can be formed of epitaxially grown silicon germanium (SiGe) with a germanium (Ge) fraction ranging between 25% and 50%, doped with a p-type dopant, such as boron (B) or gallium (Ga), at a concentration ranging between about 10

[0034] The n-channel S / D epitaxial layer 218N can be formed of epitaxially grown silicon (Si) doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb), at a concentration ranging between about 10 20 cm −3 The n-channel S / D epitaxial layer 218N can be formed of epitaxially grown silicon (Si) doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb), at a concentration ranging between about 10 21 cm −3 The n-channel S / D epitaxial layer 218N can be formed of epitaxially grown silicon (Si) doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb), at a concentration ranging between about 10

[0035] The interface 222 can be formed of a metal silicide, such as titanium silicide (TiSi, TiSi2), nickel silicide (NiSi, Ni2Si), molybdenum silicide (MoSi, MoSi2), cobalt silicide (CoSi2), tantalum silicide (TaSi2), or any combination thereof.

[0036] The liner 224 can be formed of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), tungsten (W), lanthanum oxide (La2O3), or aluminum oxide (Al2O3).

[0037] The semiconductor structure 200 also includes shallow trench isolations (STIs) 226 formed within the substrate. The STIs 226 can be formed of silicon oxide (SiO2). The p-channel S / D epitaxial layers 218P and the n-channel S / D epitaxial layers 218N are electrically connected with metal contacts 228, extending in the Z-direction, formed between the STIs 226. The metal contacts 228 can be connected to voltage sources (not shown), respectively. The metal contacts 228 can each be surrounded by a barrier layer 230 and a spacer pad 232, and covered with a contact cap layer 234. The metal contacts 228 on both sides of the channel layer 202 are isolated by an ILD 236. The critical dimensions of the metal contacts 228 in the XY-plane can each be about 10 nm and about 40 nm, and spaced about 20 nm and about 50 nm from each other. The depth of the metal contacts 228 in the Z-direction can be between about 10 nm and 100 nm. The metal contacts 228 can be formed of tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), their conductive oxides or nitrides, or any combination thereof. The barrier layer 230 can be formed of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), or tungsten (W). The spacer pad 232 can be formed of silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), silicon oxycarbonitride (SiOCN), or any combination thereof.

[0038] The contact cap layer 234 can be formed of silicon nitride (Si3N4). The ILD 236 can be formed of silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), silicon oxycarbonitride (SiOCN), or any combination thereof.

[0039] Figure 3 is a process flow diagram of a method 300 for forming a semiconductor structure 400 that can be the semiconductor structure 200 that forms part of a fully wrapped gate all around field effect transistor (GAA FET) according to one or more embodiments of the present disclosure. Figure 4A 、 Figure 4A' 、 Figure 4B 、 Figure 4B' 、 Figure 4C 、 Figure 4D 、 Figure 4D' 、 Figure 4E 、 Figure 4E' 、 Figure 4F 、 Figure 4F' 、 Figure 4G 、 Figure 4G' 、 Figure 4H 、 Figure 4H' 、 Figure 4I 、 Figure 4I' 、Figure 4J 、 Figure 4J' 、 Figure 4K 、 Figure 4K' 、 Figure 4L and Figure 4L' is an isometric view of a portion of semiconductor structure 400, where the cross-section of semiconductor structure 400 along the YZ plane includes a cross-section line A-A, and the cross-section of semiconductor structure 400 along the ZX plane includes a cross-section line B-B, corresponding to various states of method 300. It should be understood that Figure 3 、 Figure 4A 、 Figure 1 、 Figure 4A 、 Figure 1 、 Figure 4B 、 Figure 1 、 Figure 4C 、 Figure 1 、 Figure 4A' 、 Figure 4B' 、 Figure 4D 、 Figure 4D' 、 Figure 1 、 Figure 4D 、 Figure 4D' 、 Figure 4E 、 Figure 4E' 、 Figure 4E 、 Figure 4E' 、 Figure 4F 、 Figure 4F' and Figure 1 only show a partial schematic of semiconductor structure 400, and semiconductor structure 400 can contain any number of transistor portions and additional material having aspects shown in the figures. It should also be noted that while the methods shown are described in a sequential order, other process sequences including one or more operations omitted and / or added and / or rearranged in another ideal order are within the scope of embodiments of the disclosure provided herein. Figure 4F

[0040] Method 300 begins with block 302, where a reservation site formation process is performed to form a reservation site 402 in S / D recess 404 within a portion of substrate 406 isolated by STI 226, as shown in Figure 4G Figure 4G' In a processing chamber, such as processing chamber 120 shown in Figure 1 Figure 4H ​​​In the S / D recess 404 of the substrate 406, the pre-leave locations 402 are formed in the portions of the S / D recess 404 within the processing chamber 126, 128, or 130 using any suitable deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The pre-leave locations 402 are each interfaced with the extension region 216 via the cap layer 408. In the remaining portions of the S / D recess 404 within the ILD 206, the extension region 216, the p-channel S / D epitaxial layer 218P and the n-channel S / D epitaxial layer 218N on both sides of the channel layer 202, and the interface 222 are formed. Subsequently, the S / D contacts 214 are formed.

[0041] The cap layer 408 can be formed of silicon (Si) having a thickness between about 1 nm and 20 nm. In the pre-leave location removal process of block 304, the cap layer 408 can buffer the extension region 216 from the pre-leave locations 402 and can prevent damage to the extension region 216 during etching of the pre-leave locations 402. The pre-leave locations 402 can be formed of a material, such as silicon germanium (SiGe), which can be selectively etched with respect to the substrate 406 (e.g., silicon (Si)), the cap layer 408 (e.g., silicon (Si)), and the STI 226 (e.g., silicon dioxide (SiO2)).

[0042] In block 304, a pre-leave location removal process is performed to selectively remove the pre-leave locations 402 (e.g., silicon germanium (SiGe)) with respect to the substrate 406 (e.g., silicon (Si)), the cap layer 408 (e.g., silicon (Si)), and the STI 226 (e.g., silicon dioxide (SiO2)), as shown in Figure 4H' The pre-leave location removal process can include any suitable dry anisotropic etching or wet etching process performed in a processing chamber, such as the processing chamber 120 shown in Figure 1

[0043] In block 306, a selective deposition process is performed to form a selective cap layer 410 at the bottom of the S / D recess 404, as shown in Figure 4I The selective deposition process can include any suitable deposition process performed in a processing chamber, such as the processing chamber 122 shown in Figure 4I' ​any bottom-up gap fill deposition process performed in a processing chamber 126, 128, or 130 as shown in FIG. 1. The selective cap layer 410 can be formed of any material that is etch selective to silicon (Si), such as silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or amorphous carbon (a-C). The thickness of the selective cap layer 410 can be between about 3 nm and 30 nm, and is used as an etch stop layer in the isotropic etch process in block 308.

[0044] In some other embodiments, in addition to forming the cap layer 408 (e.g., silicon (Si)) in block 302 and the selective cap layer 410 (e.g., silicon nitride (Si3N4) or amorphous carbon (a-C)) in block 306, a thicker cap layer 408' with a thickness between about 5 nm and 30 nm can be formed without forming a selective cap layer on top of it, as shown in FIG. 4. Figure 1 In the pre-void removal process in block 304, the thicker cap layer 408' can be used to selectively remove the pre-voids 402 (e.g., silicon germanium (SiGe)), as shown in FIG. 5. Figure 4J

[0045] In block 308, a substrate removal process is performed to isotropically etch the substrate 406 with the S / D recesses 404, as shown in FIG. 6. Figure 4J' and Figure 1 The substrate removal process can include any appropriate wet isotropic etch process performed in a processing chamber, such as the processing chamber 120 as shown in FIG. 1. Figure 1 In block 308, a substrate removal process is performed to isotropically etch the substrate 406 with the S / D recesses 404, as shown in FIG. 6. Figure 4L In block 308, a substrate removal process is performed to isotropically etch the substrate 406 with the S / D recesses 404, as shown in FIG. 6. Figure 4L' In block 308, a substrate removal process is performed to isotropically etch the substrate 406 with the S / D recesses 404, as shown in FIG. 6.

[0046] In block 310, a conformal deposition process is performed to form the spacer pads 232 on the exposed surfaces of the substrate 406 and the selective cap layer 410 within the S / D recesses 404, as shown in FIG. 7, or on the exposed surfaces of the substrate 406 and the thicker cap layer 408', as shown in FIG. 8. ​ ​ ​​Conformal deposition can include any appropriate deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The spacer pads 232 can be formed of silicon nitride (Si3N4), silicon oxide (Si02), silicon oxynitride (SiON), aluminum oxide (AI2O3), silicon oxycarbonitride (SiOCN), or any combination thereof. The spacer pads 232, the unetched portions 412 of the substrate 406, the selective cap layer 410, and the cap layer 408 (as shown in ​ , as well as the spacer pads 232, the unetched portions 412 of the substrate 406, and the thicker cap layer 408 (as shown in ​ , form a mesh structure to protect the extension regions 216 from the etching process in the block 312.

[0047] In the block 312, a spacer pad etching process is performed to etch the spacer pads 232 on the sidewalls of the substrate 406 and the STI 226 within the S / D recesses 404, as shown in ​ and ​ The selective spacer pad removal process can include any appropriate dry anisotropic etch performed in a processing chamber, such as the processing chamber 120 shown in ​ The spacer pad etching process can remove the spacer pads 232 on the substrate 406 top surface 414 within the S / D recesses 404 and at the bottom of the S / D recesses 404. The selective cap layer 410 at the bottom of the S / D recesses 404 can also be selectively removed with respect to the cap layer 408, as shown in ​ .

[0048] In the block 314, a cap layer removal process is performed to remove the cap layer 408 and 408' within the S / D recesses 404, as shown in ​ and ​ , where the spacer pads 232 protect the extension regions 216 from being etched. The cap layer removal process can include any appropriate dry anisotropic etch performed in a processing chamber, such as the processing chamber 120 shown in ​ .

[0049] In the block 316, a contact metallization process is performed to form metal contacts within the S / D recesses 404, as shown in ​ and ​ The contact metallization process can include any appropriate deposition process performed in a processing chamber, such as the processing chamber 120 shown in ​The S / D recess 404 is filled with a metal fill material, such as tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), scandium (Ta), platinum (Pt), a conductive oxide or nitride, or any combination thereof, by any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), and the like, performed in a processing chamber (such as the processing chambers 126, 128, or 130 shown in FIG. 1C). The contact metallization process can also include forming a barrier layer 230 around the metal contact 228. The barrier layer 230 can be formed from titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), or tungsten (W). The spacer pads 232 can be formed from silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), silicon oxycarbonitride (SiOCN), or any combination thereof.

[0050] In block 318, a contact recessing process is performed to recess the metal contact 228 to form a contact recess 416, as shown in FIGS. 4K and 4K'. ​ and ​ The contact recessing process can include any suitable dry anisotropic etching or wet etching process performed in a processing chamber (such as the processing chamber 120 shown in FIG. 1C). ​

[0051] In block 320, a contact cap formation process is performed to form a contact cap layer 234 in the contact recess 416, as shown in FIGS. 4K and 4K'. ​ and ​ The contact cap formation process can include any suitable deposition process, such as chemical vapor deposition (CVD) or physical vapor deposition (PVD), performed in a processing chamber (such as the processing chambers 126, 128, or 130 shown in FIG. 1C). The contact cap layer 234 can be formed from silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), silicon oxycarbonitride (SiOCN), or any combination thereof. ​

[0052] In block 322, an ILD recessing process is performed to recess the substrate 406 relative to the spacer pads 232 and the contact cap layer 234 from the S / D recess 404 to form an ILD recess 418, as shown in FIGS. 4K and 4K'. The ILD recessing process can include any suitable dry anisotropic etching or wet etching process performed in a processing chamber (such as the processing chamber 120 shown in FIG. 1C). An oxide layer and nitride spacer pad (not shown) can be formed at the bottom of the ILD recess 418 to further protect the extension region 216. ​

[0053] ​​​In block 324, an ILD formation process is performed to form an ILD 236 in the ILD recess 418, as shown in ​ and ​ The ILD 236 can be formed of silicon oxide (Si02), silicon oxynitride (SiON), aluminum oxide (AI2O3), silicon oxycarbonitride (SiOCN), or any combination thereof. The backside of the semiconductor structure 400 can be planarized by a chemical mechanical polishing (CMP) process to remove overfilled material (e.g., silicon oxide (Si02)).

[0054] Embodiments described herein provide methods of forming metal contacts isolated from each other by an interlayer dielectric (ILD) on the backside of a wafer while protecting an extended region (e.g., doped silicon (Si) or silicon germanium (SiGe)) on the frontside of the wafer. In the methods described herein, a selective underlayer (e.g., silicon nitride (Si3N4)) is used when etching a silicon (Si) wafer to provide etch selectivity. The selective underlayer also protects the underlying extended region from any damage during the silicon (Si) wafer etch.

[0055] While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure can be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A method of forming a portion of a fully wrapped gate field effect transistor (GAA FET), comprising the steps of: performing a placeholder formation process to form placeholders in recesses formed in portions of a substrate isolated by shallow trench isolation (STI), each placeholder interfacing with an extension region via a cap layer, the recesses extending into an interlayer dielectric (ILD) formed on the substrate; performing a placeholder removal process to selectively remove the placeholders relative to the substrate, the cap layers, and the STI; performing a selective deposition process to form a selective cap layer at the bottom of the recesses; performing a substrate removal process to isotropically etch the substrate within the recesses; performing a spacer pad formation process to form spacer pads on the substrate within the recesses and exposed surfaces of the selective cap layer; performing a spacer pad sculpting process to sculpt the spacer pads on sidewalls of the substrate and the STI within the recesses; performing a cap layer removal process to remove the cap layers within the recesses; and performing a contact metallization process to form a metal contact within the recesses.

2. The method of claim 1, wherein the placeholders comprise silicon germanium (SiGe), the cap layers comprise silicon (Si), the extension regions comprise lightly doped silicon (Si) or silicon germanium (SiGe), the STI comprises silicon oxide (SiO2), and the ILD comprises silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide, or (Al2O3).

3. The method of claim 2, wherein the cap layers each have a thickness between 1 nm and 30 nm.

4. The method of claim 1, wherein the selective cap layer comprises silicon nitride (Si3N4), silicon oxide (SiO2), silicon oxycarbide (SiOC), silicon oxycarbinitride (SiOCN), or amorphous carbon (a-C).

5. The method of claim 4, wherein the selective cap layer each have a thickness between 2 nm and 30 nm.

6. The method of claim 1, wherein the spacer pads comprise silicon oxide (SiO2), silicon oxycarbide (SiOC), silicon oxycarbinitride (SiOCN), silicon boron carbon nitride (SiBCN), or silicon nitride (Si3N4).

7. The method of claim 1, wherein the metal contact comprises tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), their conductive oxides or nitrides, or any combination thereof.

8. The method of claim 1, further comprising the steps of: performing a contact recessing process to recess the metal contact and form a contact recess; and performing a contact cap formation process to form a contact cap layer in each of the contact recesses.

9. The method of claim 8, further comprising the steps of: performing an ILD recessing process to selectively recess the substrate within the recesses relative to the spacer pads and the contact cap layers, thereby forming an ILD recess; and performing a contact cap formation process to form a contact cap layer in each of the contact recesses. performing an ILD formation process to form an ILD in the ILD recess.

10. A method of forming a portion of a fully wrapped gate field effect transistor (GAA FET), comprising the steps of: performing a reservation site formation process to form reservation sites in recesses formed in portions of a substrate isolated by shallow trench isolation (STI), each reservation site interfacing with an extension region via a cap layer, the recesses extending into an interlayer dielectric (ILD) formed on the substrate; performing a reservation site removal process to selectively remove the reservation sites relative to the substrate, the cap layer, and the STI; performing a substrate removal process to isotropically etch the substrate within the recesses; performing a conformal deposition process to form a spacer pad on exposed surfaces of the substrate and the cap layer within the recesses; performing a spacer pad sculpting process to sculpt the spacer pad on sidewalls of the substrate and the STI within the recesses; performing a cap layer removal process to remove the cap layer within the recesses; and performing a contact metallization process to form a metal contact within the recesses.

11. The method of claim 10, wherein the reservation sites comprise silicon germanium (SiGe), the cap layers comprise silicon (Si), the extension regions comprise lightly doped silicon (Si) or silicon germanium (SiGe), the STI comprises silicon oxide (SiO2), and the ILD comprises silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), or aluminum oxide (Al2O3).

12. The method of claim 11, wherein the cap layers each have a thickness between 2 nm and 30 nm.

13. The method of claim 10, wherein the spacer pads comprise silicon nitride (Si3N4).

14. The method of claim 10, wherein the metal contacts comprise tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), their conductive oxides or nitrides, or any combination thereof.

15. The method of claim 10, further comprising the steps of: performing a contact recessing process to recess the metal contacts to form contact recesses; and performing a contact cap formation process to form a contact cap layer in each of the contact recesses.

16. The method of claim 15, further comprising the steps of: performing an ILD recessing process to recess the substrate within the recesses relative to the spacer pads and the contact cap layers to form ILD recesses; and performing an ILD formation process to form an ILD in the ILD recesses.

17. A semiconductor structure forming a portion of a fully wrapped gate field effect transistor (GAA FET), comprising: a channel layer embedded in an interlayer dielectric (ILD) formed on a substrate, the channel layer extending along a first direction; a metal gate embedded in the ILD, the metal gate extending along the first direction; source / drain (S / D) contacts electrically connected to the channel layer via an extension region and S / D epitaxial layers on both sides of the channel layer; a shallow trench isolation (STI) formed within the substrate; metal contacts formed between the STIs, the metal contacts extending along a second direction orthogonal to the first direction, wherein each of the metal contacts is electrically connected to one of the S / D epitaxial layers and surrounded by a spacer pad; and a cap layer formed between the extension region and the spacer pad.

18. The semiconductor structure of claim 17, wherein a critical dimension of the metal contacts is between 10 nm and 40 nm, a pitch in the plane orthogonal to the second direction is between 20 nm and 50 nm, and a depth in the second direction is between 10 nm and 100 nm.

19. The semiconductor structure of claim 17, wherein the channel layer comprises silicon (Si), germanium (Ge), silicon germanium (SiGe), or indium gallium zinc oxide (IGZO), the metal gate comprises tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), a conductive oxide or nitride thereof, or any combination thereof, the ILD comprises silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), or any combination thereof, and the cap layer comprises silicon (Si).

20. The semiconductor structure of claim 17, wherein the S / D contacts comprise tungsten (W), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), a conductive oxide or nitride thereof, or any combination thereof, the extension region comprises lightly doped silicon (Si) or silicon germanium (SiGe), the S / D epitaxial layers comprise epitaxially grown silicon germanium (SiGe).

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