Holographic monitoring method based on circuit breaker intelligent algorithm

Abstract

The invention relates to the technical field of intelligent circuit breakers, in particular to a holographic monitoring method based on a circuit breaker intelligent algorithm. The method comprises the steps of collecting operation data of a line where the circuit breaker is located; performing data preprocessing on the operation data; performing data processing on the preprocessed operation data to obtain monitoring parameters; holographic monitoring is carried out on an electrical fault according to the monitoring parameters; wherein when the operation data is preprocessed, a dual-frequency injection method is adopted to realize the separation of resistive residual current, a 2kHz high-frequency test signal is superposed on the basis of a fundamental wave frequency, and the resistive residual current is separated; meanwhile, an intelligent algorithm is adopted to carry out de-noising processing on the signal, that is, a dynamic threshold value is adopted to carry out wavelet de-noising processing, and an interlayer correlation coefficient is fused into wavelet threshold value calculation, so that self-adaptive protection of fault features is realized, and subsequent accurate power grid holographic monitoring is facilitated.

Description

Technical Field

[0001] This invention relates to the field of intelligent circuit breaker technology, and in particular to a holographic monitoring method based on intelligent circuit breaker algorithms. Background Technology

[0002] In power systems, circuit breakers, as crucial protection and control devices, are essential for ensuring the safety and stability of the power grid. Traditional circuit breaker monitoring methods often only monitor a limited number of electrical parameters and have limited fault identification capabilities, making it difficult to meet the demands of modern power systems for high reliability and intelligent monitoring. Therefore, developing an intelligent monitoring method capable of comprehensively monitoring electrical and temperature parameters and accurately identifying various electrical faults is of significant practical importance.

[0003] Existing technologies include intelligent monitoring solutions for circuit breakers. For example, Chinese invention patent (CN111474470A) discloses an online monitoring method for intelligent circuit breakers in substations, which includes a monitoring process for circuit breaker opening and closing current signals and a monitoring process for circuit breaker vibration signals. The monitoring process for circuit breaker opening and closing current signals includes the following steps: S1: Collect the coil current of the circuit breaker opening and closing and then determine the type of abnormal fault. The abnormal fault types include coil core jamming fault, low power supply voltage fault, and core idle travel fault. The monitoring process for circuit breaker vibration signals includes the following steps: S100: Install an acceleration sensor on the circuit breaker to measure the opening / closing speed, distance, action time, formation, and vibration spectrum during the circuit breaker's operation. However, in the existing technology, when using circuit breakers to perform holographic monitoring of the power grid, traditional circuit breakers cannot accurately obtain the resistive residual current, resulting in low monitoring accuracy. At the same time, the existing technology uses dynamic thresholds for wavelet noise reduction, which also has the problem of poor noise reduction effect. Summary of the Invention

[0004] The purpose of this invention is to provide a holographic monitoring method based on a circuit breaker intelligent algorithm to solve the problems mentioned in the prior art.

[0005] To address the aforementioned technical problems, the present invention specifically provides the following technical solution: a holographic monitoring method based on a circuit breaker intelligent algorithm, comprising the following steps: S1: Collect the operating data of the line where the circuit breaker is located; S2: Perform data preprocessing on the running data; S3: Process the pre-processed operational data to obtain monitoring parameters; The resistive residual current is separated by using a dual-frequency injection method. A 2kHz high-frequency test signal is superimposed on the fundamental frequency, and the resistive residual current is separated. The specific formula is as follows: ; In the formula, I res For resistive residual current, U test Z is the voltage of the injected high-frequency test signal. line Z represents the line impedance. load R is the load impedance. leak X is the resistive leakage resistance. cap It is a capacitive leakage reactance; S4: Perform holographic monitoring of electrical faults based on the monitoring parameters.

[0006] Preferably, in step S1, the operating data includes voltage data, current data, temperature data, and leakage current data.

[0007] Preferably, in step S2, the preprocessing includes signal denoising and synchronous sampling correction.

[0008] Preferably, the signal denoising specifically includes: S21: Perform multi-scale wavelet decomposition on the running data to obtain the approximation coefficients and detail coefficients of the running data; S22: Perform dynamic threshold denoising on the detail coefficients of the running data; S23: Reconstruct the signal from the denoised detail coefficients and approximation coefficients to obtain the denoised running data.

[0009] Preferably, the process for determining the dynamic threshold is as follows: Calculate the correlation coefficient between the detail coefficients of the i-th layer and the detail coefficients of adjacent layers. ρ i,j The calculation formula is: ; In the formula, i and j represent the wavelet layer number, j = i + 1, D i Let D be the approximation coefficient for the i-th layer. j These are the approximation coefficients for the j-th layer; The dynamic threshold is calculated based on the correlation coefficient between the detail coefficient of the i-th layer and the detail coefficients of adjacent layers; The formula is: ; In the formula, σ i Let be the standard deviation of the detail coefficients in the i-th layer, and N be the total number of detail coefficient layers.

[0010] Preferably, inverse wavelet transform is used for signal reconstruction.

[0011] Preferably, the synchronous sampling correction specifically involves: performing nanosecond-level time synchronization on the running data based on GPS timing or the IEEE 1588 precise time protocol.

[0012] Preferably, in step S3, the monitoring parameters obtained after data processing include: three-phase current, three-phase voltage, frequency, active power, reactive power, apparent power, power factor, number of arcing cycles per second in three phases, resistive residual current, capacitive residual current, active energy, reactive energy, active demand, 2nd-50th harmonics, odd harmonic content, even harmonic content, total harmonic current, voltage THD, phase, and switching status.

[0013] Preferably, the electrical faults include: overload, short circuit, excessive leakage current, arc fault, overvoltage, undervoltage, phase loss, zero-voltage, three-phase imbalance, underfrequency, overfrequency, overtemperature, excessive harmonic current, excessive harmonic voltage, voltage sag, voltage drop, and short circuit exceeding the limit.

[0014] Preferably, the overload fault judgment logic is as follows: the processor calculates the real-time load current I. load , and the preset overload current threshold I overload and overload time threshold t overload In comparison, if I load >I overload And the duration t>t overload If so, it is determined to be an overload fault; The short-circuit fault judgment logic is as follows: the processor monitors the real-time load current amplitude and rate of change in real time; when the amplitude exceeds the short-circuit current threshold I... short Furthermore, if the rate of change of current exceeds the preset threshold for the rate of change of current, it is determined to be a short circuit fault. The logic for determining excessive leakage current is as follows: the processor calculates the resistive residual current I. leak , and the preset leakage current threshold I leak_threshold Comparison. If I leak >I leak_threshold If so, it is determined to be an excessive leakage current. The logic for determining the arc fault is as follows: the processor performs harmonic analysis on the real-time load current to extract high-frequency components; when the amplitude of the high-frequency components exceeds the arc high-frequency threshold I... arc_hf And the cumulative arc energy exceeds the arc energy threshold E arc_threshold Furthermore, if the waveform distortion rate exceeds the set value, it is determined to be an arc fault; The overvoltage judgment logic is as follows: the processor calculates the real-time fundamental voltage U. rms , and the preset overvoltage threshold U overvoltage In contrast, if U rms >U overvoltage And the duration exceeds the overvoltage time threshold toverv If so, it is determined to be an overvoltage; The undervoltage determination logic is as follows: the processor calculates the real-time fundamental voltage U. rms , and the preset undervoltage threshold U undervoltage In contrast, if U rms undervoltage And the duration exceeds the undervoltage time threshold t underv If so, it is determined to be undervoltage; The logic for determining a missing phase is as follows: calculate the positive and negative sequence components of the three-phase current; if a phase current I... phase threshold If the duration exceeds the set value, it is determined to be a phase loss, where I phase These are the positive or negative sequence components of the three-phase current. The logic for determining zero-sequence disconnection is as follows: Calculate the positive and negative sequence components of the three-phase voltage; if the negative sequence voltage ratio is >0.05 and the neutral line current I... N >I N_threshold If I is zero, it is determined to be a zero break. N These are the positive or negative sequence components of the three-phase voltage. The logic for determining the three-phase imbalance fault is as follows: the processor calculates the degree of voltage or current imbalance and compares it with a preset imbalance threshold ϵ. threshold In comparison, if the threshold is exceeded, it is determined to be a three-phase imbalance fault; The logic for determining the underfrequency fault / overfrequency fault is as follows: the processor calculates the real-time frequency f. rms , and the preset underfrequency threshold f under Over-frequency threshold f over In comparison, if f rms <f under or f rms >f over And the duration exceeds the frequency time threshold t freq If so, it is determined to be an underfrequency or overfrequency fault; The judgment logic for the harmonic current / voltage over-limit fault is as follows: the processor performs Fourier transform on the current and voltage signals to extract each harmonic component, calculates THDi, THDu and the amplitude of each harmonic current / voltage, and compares them with the preset harmonic threshold. If any harmonic component or distortion rate exceeds the threshold, it is judged as a harmonic current / voltage over-limit fault. The logic for determining harmonic current / voltage over-limit faults is as follows: the processor tracks the trend of the effective voltage value, and when the effective voltage value rises above the voltage spurt threshold ΔU... swell If the duration is within the voltage rise time range, it is determined to be a voltage rise; when the effective voltage value drops instantaneously beyond the voltage sag threshold ΔU... sag ​​And since the duration is within the voltage sag time range, it is determined to be a voltage sag; The judgment logic for the short-circuit over-level fault is as follows: the processor obtains the short-circuit current detection value and action time information of the upper and lower level protection devices through the communication interface, and combines it with the pre-set protection coordination logic. If the upper level circuit breaker is detected to trip due to the short circuit of the lower level line, and the lower level protection device does not act, it is judged as a short-circuit over-level fault.

[0015] Compared with the prior art, the present invention has the following advantages: This invention collects operational data from the circuit breaker's line; preprocesses the operational data; further processes the preprocessed operational data to obtain monitoring parameters; and performs holographic monitoring of electrical faults based on these monitoring parameters. Specifically, during operational data preprocessing, a dual-frequency injection method is used to separate resistive residual current. A 2kHz high-frequency test signal is superimposed on the fundamental frequency to separate the resistive residual current. This accurately identifies the resistive residual current, improves the reliability of intelligent circuit breaker monitoring, and reduces missed detections or false trips. Its core lies in utilizing frequency-related impedance characteristic differences to decompose the mixed leakage current into independent components, providing a more reliable solution for power system safety protection. Meanwhile, in the data preprocessing step of the operating data, an intelligent algorithm is used to denoise the signal, that is, to use dynamic threshold for wavelet denoising and to incorporate the inter-layer correlation coefficient into the wavelet threshold calculation, thereby realizing adaptive protection of fault characteristics, which is beneficial to subsequent accurate holographic monitoring of the power grid. Attached Figure Description

[0016] To more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely exemplary, and those skilled in the art can derive other embodiments based on the provided drawings without creative effort.

[0017] Figure 1 A flowchart of a holographic monitoring method based on a circuit breaker intelligent algorithm provided in an embodiment of the present invention.

[0018] Figure 2 A flowchart for signal denoising provided in an embodiment of the present invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] The concepts involved in this application will first be described with reference to the accompanying drawings. It should be noted that the following descriptions of various concepts are only for the purpose of making the content of this application easier to understand and do not constitute a limitation on the scope of protection of this application; furthermore, the embodiments and features in the embodiments of this application can be combined with each other unless otherwise specified. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0021] Example 1 As attached Figure 1 As shown, this invention provides a holographic monitoring method based on a circuit breaker intelligent algorithm, comprising the following steps: S1: Collect the operating data of the line where the circuit breaker is located; The operating data includes voltage data, current data, temperature data, and leakage current data; The circuit breaker utilizes a voltage sensor to collect voltage data from the circuit breaker's line, acquiring voltage-related information such as three-phase voltage. This voltage sensor is characterized by high precision and sensitivity, accurately sensing voltage changes and converting them into electrical signals. A current transformer collects current data from the line, obtaining three-phase current data. This current transformer can convert large currents into smaller currents without affecting normal circuit operation, facilitating subsequent processing and analysis. A temperature sensor monitors the temperature of the circuit breaker, specifically the three-phase terminal temperature, the neutral terminal temperature, and the internal temperature of the circuit breaker. This temperature sensor can detect temperature changes in real time and convert them into corresponding electrical signals. A leakage current transformer collects leakage current data for subsequent analysis of resistive residual current (resistive leakage current) and capacitive residual current (harmonic leakage current).

[0022] It is worth emphasizing that the voltage sensor, current transformer, temperature sensor, and leakage current transformer all adopt high-frequency sampling technology with a sampling frequency of 51200Hz, which can more accurately capture the instantaneous changes in electrical and temperature parameters, providing a rich and accurate data foundation for subsequent comprehensive monitoring.

[0023] S2: Perform data preprocessing on the running data; The preprocessing includes signal denoising and synchronous sampling correction. As attached Figure 2 As shown, the signal denoising specifically involves: S21: Perform multi-scale wavelet decomposition on the running data to obtain the approximation coefficients and detail coefficients of the running data; The Daubechies8 (db8) wavelet was selected as the wavelet basis function to perform a 6-level wavelet decomposition on the running data to obtain the approximation coefficients and detail coefficients of the running data. A total of 6 levels of detail coefficients (D1-D6) and 1 level of approximation coefficients (A6) were obtained. S22: Perform dynamic threshold denoising on the detail coefficients of the running data; The process for determining the dynamic threshold is as follows: Calculate the correlation coefficient between the detail coefficients of the i-th layer and the detail coefficients of adjacent layers. ρ i,j The calculation formula is: ; In the formula, i and j represent the wavelet layer number, j = i + 1, D i Let D be the approximation coefficient for the i-th layer. j These are the approximation coefficients for the j-th layer; The dynamic threshold is calculated based on the correlation coefficient between the detail coefficient of the i-th layer and the detail coefficients of adjacent layers; The formula is: ; In the formula, σ i Let N be the standard deviation of the detail coefficients in the i-th layer, and N be the total number of detail coefficient layers. S23: Reconstruct the signal from the denoised detail coefficients and approximation coefficients to obtain the denoised running data; In this process, inverse wavelet transform is used for signal reconstruction.

[0024] In this step, when using dynamic thresholding for wavelet denoising, the inter-layer correlation coefficient is incorporated into the wavelet threshold calculation, thereby achieving adaptive protection of fault characteristics, which is beneficial for subsequent accurate holographic monitoring of the power grid.

[0025] The synchronous sampling correction specifically involves: performing nanosecond-level time synchronization on the running data based on GPS timing or the IEEE 1588 Precise Time Protocol (PTP) to eliminate phase errors caused by asynchronous sampling.

[0026] S3: Process the pre-processed operational data to obtain monitoring parameters; In this step, after data processing, the monitoring parameters obtained include: three-phase current, three-phase voltage, frequency, active power, reactive power, apparent power, power factor, number of arcing cycles per second in three phases, resistive residual current (commonly known as resistive leakage current), capacitive residual current (commonly known as harmonic leakage current), active energy, reactive energy, active demand, 2nd-50th harmonics, odd harmonic content, even harmonic content, total harmonic current, voltage THD, phase, and switch status.

[0027] In response to the problem that traditional circuit breakers cannot accurately obtain resistive residual current, this embodiment uses a dual-frequency injection method to separate the resistive residual current, that is, a 2kHz high-frequency test signal is superimposed on the fundamental frequency (50Hz) and the resistive residual current is separated. The specific formula is as follows: ; In the formula, I res For resistive residual current, U test Z is the voltage of the injected high-frequency test signal. line Z represents the line impedance. load R is the load impedance. leak X is the resistive leakage resistance. cap It is a capacitive leakage reactance; The dual-frequency injection method provided in this embodiment can accurately identify resistive residual current, improve the reliability of circuit breaker intelligent monitoring, and reduce missed detections or false trips. Its core lies in using the frequency-related impedance characteristic differences to decompose the mixed leakage current into independent components, providing a more reliable solution for power system safety protection.

[0028] S4: Perform holographic monitoring of electrical faults based on the monitoring parameters; The electrical faults include: overload, short circuit, excessive leakage current, arc fault, overvoltage, undervoltage, phase loss, zero-voltage, three-phase imbalance, underfrequency, overfrequency, overtemperature, excessive harmonic current, excessive harmonic voltage, voltage sag, voltage drop, and short circuit exceeding the limit.

[0029] The overload fault judgment logic is as follows: the processor calculates the real-time load current I. load , and the preset overload current threshold I overload and overload time threshold t overload Comparison. If I load >I overload And the duration t>t overload If so, it is determined to be an overload fault.

[0030] The short-circuit fault judgment logic is as follows: the processor monitors the real-time load current amplitude and rate of change in real time; when the amplitude exceeds the short-circuit current threshold I... shortIf the rate of change of current exceeds the preset threshold for the rate of change of current, it is determined to be a short circuit fault.

[0031] The short-circuit current threshold is 5-10 times the rated current.

[0032] The logic for determining excessive leakage current is as follows: the processor calculates the resistive residual current I. leak , and the preset leakage current threshold I leak_threshold Comparison. If I leak >I leak_threshold If so, it is determined to be an excessive leakage current.

[0033] The logic for determining the arc fault is as follows: the processor performs harmonic analysis on the real-time load current to extract high-frequency components; when the amplitude of the high-frequency components exceeds the arc high-frequency threshold I... arc_hf And the cumulative arc energy exceeds the arc energy threshold E arc_threshold Furthermore, if the waveform distortion rate exceeds the set value, it is determined to be an arc fault.

[0034] The overvoltage judgment logic is as follows: the processor calculates the real-time fundamental voltage U. rms , and the preset overvoltage threshold U overvoltage In contrast, if U rms >U overvoltage And the duration exceeds the overvoltage time threshold t overv If so, it is determined to be an overvoltage.

[0035] The overvoltage threshold is 110%-120% of the rated voltage.

[0036] The undervoltage determination logic is as follows: the processor calculates the real-time fundamental voltage U. rms , and the preset undervoltage threshold U undervoltage In contrast, if U rm s undervoltage And the duration exceeds the undervoltage time threshold t underv If so, it is determined to be undervoltage.

[0037] The undervoltage threshold is 80%-90% of the rated voltage.

[0038] The logic for determining a missing phase is as follows: calculate the positive and negative sequence components of the three-phase current; if a phase current I... phase threshold If the duration exceeds the set value, it is determined to be a phase loss, where I phase These are the positive or negative sequence components of the three-phase current.

[0039] The logic for determining zero-sequence disconnection is as follows: Calculate the positive and negative sequence components of the three-phase voltage; if the negative sequence voltage ratio is >0.05 and the neutral line current I... N >I​​N_threshold If I is zero, it is determined to be a zero break. N These are the positive or negative sequence components of the three-phase voltage.

[0040] The logic for determining the three-phase imbalance fault is as follows: the processor calculates the degree of voltage or current imbalance and compares it with a preset imbalance threshold ϵ. threshold If the voltage imbalance limit specified in GB / T15543 is 2% (not exceeding 4% for short periods), it is judged as a three-phase imbalance fault if the threshold is exceeded.

[0041] The logic for determining the underfrequency fault / overfrequency fault is as follows: the processor calculates the real-time frequency f. rms , and the preset underfrequency threshold f under (Example, 49.5Hz), over-frequency threshold f over (Example, 50.5Hz) In contrast, if f rms <f under or f rms >f over And the duration exceeds the frequency time threshold t freq If so, it is determined to be an underfrequency or overfrequency fault.

[0042] The judgment logic for the harmonic current / voltage over-limit fault is as follows: the processor performs Fourier transform on the current and voltage signals to extract each harmonic component, calculates THDi, THDu and the amplitude of each harmonic current / voltage, and compares them with the preset harmonic threshold. If any harmonic component or distortion rate exceeds the threshold, it is judged as a harmonic current / voltage over-limit fault.

[0043] The logic for determining harmonic current / voltage over-limit faults is as follows: the processor tracks the trend of the effective voltage value, and when the effective voltage value rises above the voltage spurt threshold ΔU... swell If the duration is within the voltage rise time range, it is determined to be a voltage rise; when the effective voltage value drops instantaneously beyond the voltage sag threshold ΔU... sag Furthermore, if the duration is within the voltage sag time range, it is determined to be a voltage sag.

[0044] The logic for determining a short-circuit over-level fault is as follows: The processor obtains the short-circuit current detection values ​​and action time information of the upper and lower level protection devices through the communication interface, and combines them with the pre-set protection coordination logic (for example, the "selective protection" principle: the lower level protection should act before the upper level protection). If the upper level circuit breaker is detected to have tripped due to a short circuit in the lower level line, and the lower level protection device does not act, it is determined to be a short-circuit over-level fault.

[0045] Example 2 This embodiment includes a computer-readable storage medium storing a data processing program, which is executed by a processor as a holographic monitoring method based on a circuit breaker intelligent algorithm according to Embodiment 1.

[0046] The embodiments and / or implementation methods described above are merely preferred embodiments and / or implementation methods for implementing the technology of the present invention, and are not intended to limit the implementation methods of the technology of the present invention in any way. Any person skilled in the art can make some modifications or alterations to other equivalent embodiments without departing from the scope of the technical means disclosed in the content of the present invention, but they should still be regarded as the technology or embodiments that are substantially the same as the present invention.

[0047] This document uses specific examples to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are only preferred embodiments of this application. It should be noted that due to the limitations of written expression, while there are objectively infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this application, and can also combine the above technical features in an appropriate manner. These improvements, modifications, changes, or combinations, or the direct application of the inventive concept and technical solution to other situations without modification, should all be considered within the scope of protection of this application.

Claims

1. A holographic monitoring method based on a circuit breaker intelligent algorithm, characterized in that, Includes the following steps: S1: Collect the operating data of the line where the circuit breaker is located; S2: Perform data preprocessing on the running data; S3: Process the pre-processed operational data to obtain monitoring parameters; The resistive residual current is separated by using a dual-frequency injection method. A 2kHz high-frequency test signal is superimposed on the fundamental frequency, and the resistive residual current is separated. The specific formula is as follows: ； In the formula, I res For resistive residual current, U test Z is the voltage of the injected high-frequency test signal. line Z represents the line impedance. load R is the load impedance. leak X is the resistive leakage resistance. cap It is a capacitive leakage reactance; S4: Perform holographic monitoring of electrical faults based on the monitoring parameters.

2. The holographic monitoring method based on a circuit breaker intelligent algorithm according to claim 1, characterized in that, In S1, the operating data includes voltage data, current data, temperature data, and leakage current data.

3. The holographic monitoring method based on a circuit breaker intelligent algorithm according to claim 1, characterized in that, In step S2, the preprocessing includes signal denoising and synchronous sampling correction.

4. The holographic monitoring method based on circuit breaker intelligent algorithm according to claim 3, characterized in that, The signal denoising specifically involves: S21: Perform multi-scale wavelet decomposition on the running data to obtain the approximation coefficients and detail coefficients of the running data; S22: Perform dynamic threshold denoising on the detail coefficients of the running data; S23: Reconstruct the signal from the denoised detail coefficients and approximation coefficients to obtain the denoised running data.

5. The holographic monitoring method based on circuit breaker intelligent algorithm according to claim 4, characterized in that, The process for determining the dynamic threshold is as follows: Calculate the correlation coefficient between the detail coefficients of the i-th layer and the detail coefficients of adjacent layers. ρ i,j The calculation formula is: ； In the formula, i and j represent the wavelet layer number, j = i + 1, D i Let D be the approximation coefficient for the i-th layer. j These are the approximation coefficients for the j-th layer; The dynamic threshold is calculated based on the correlation coefficient between the detail coefficient of the i-th layer and the detail coefficients of adjacent layers; The formula is: ； In the formula, σ i Let be the standard deviation of the detail coefficients in the i-th layer, and N be the total number of detail coefficient layers.

6. The holographic monitoring method based on a circuit breaker intelligent algorithm according to claim 4, characterized in that, Signal reconstruction is performed using inverse wavelet transform.

7. The holographic monitoring method based on a circuit breaker intelligent algorithm according to claim 3, characterized in that, The synchronous sampling correction specifically involves performing nanosecond-level time synchronization on the running data based on GPS timing or the IEEE 1588 precise time protocol.

8. The holographic monitoring method based on a circuit breaker intelligent algorithm according to claim 1, characterized in that, In S3, the monitoring parameters obtained after data processing include: three-phase current, three-phase voltage, frequency, active power, reactive power, apparent power, power factor, number of arcing cycles per second in three phases, resistive residual current, capacitive residual current, active energy, reactive energy, active demand, 2nd-50th harmonics, odd harmonic content, even harmonic content, total harmonic current, voltage THD, phase, and switching status.

9. The holographic monitoring method based on a circuit breaker intelligent algorithm according to claim 1, characterized in that, The electrical faults include: overload, short circuit, excessive leakage current, arc fault, overvoltage, undervoltage, phase loss, zero-crossing, three-phase imbalance, underfrequency, overfrequency, overtemperature, excessive harmonic current, excessive harmonic voltage, voltage sag, and short circuit exceeding the limit.

10. The holographic monitoring method based on a circuit breaker intelligent algorithm according to claim 9, characterized in that, The overload fault judgment logic is as follows: the processor calculates the real-time load current I. load , and the preset overload current threshold I overload and overload time threshold t overload In comparison, if I load >I overload And the duration t>t overload If so, it is determined to be an overload fault; The short-circuit fault judgment logic is as follows: the processor monitors the real-time load current amplitude and rate of change in real time; when the amplitude exceeds the short-circuit current threshold I... short Furthermore, if the rate of change of current exceeds the preset threshold for the rate of change of current, it is determined to be a short circuit fault. The logic for determining excessive leakage current is as follows: the processor calculates the resistive residual current I. leak , and the preset leakage current threshold I leak_threshold Comparison. If I leak >I leak_threshold If so, it is determined to be an excessive leakage current. The logic for determining the arc fault is as follows: the processor performs harmonic analysis on the real-time load current to extract high-frequency components; when the amplitude of the high-frequency components exceeds the arc high-frequency threshold I... arc_hf And the cumulative arc energy exceeds the arc energy threshold E arc_threshold Furthermore, if the waveform distortion rate exceeds the set value, it is determined to be an arc fault; The overvoltage judgment logic is as follows: the processor calculates the real-time fundamental voltage U. rms , and the preset overvoltage threshold U overvoltage In contrast, if U rms >U overvoltage And the duration exceeds the overvoltage time threshold t overv If so, it is determined to be an overvoltage; The undervoltage determination logic is as follows: the processor calculates the real-time fundamental voltage U. rms , and the preset undervoltage threshold U undervoltage In contrast, if U rms undervoltage And the duration exceeds the undervoltage time threshold t underv If so, it is determined to be undervoltage;​ The logic for determining a missing phase is as follows: calculate the positive and negative sequence components of the three-phase current; if a phase current I... phase threshold If the duration exceeds the set value, it is determined to be a phase loss, where I phase These are the positive or negative sequence components of the three-phase current;​ The logic for determining zero-sequence disconnection is as follows: Calculate the positive and negative sequence components of the three-phase voltage; if the negative sequence voltage ratio is >0.05 and the neutral line current I... N >I N_threshold If I is zero, it is determined to be a zero break. N These are the positive or negative sequence components of the three-phase voltage. The logic for determining the three-phase imbalance fault is as follows: the processor calculates the degree of voltage or current imbalance and compares it with a preset imbalance threshold ϵ. threshold In comparison, if the threshold is exceeded, it is determined to be a three-phase imbalance fault; The logic for determining the underfrequency fault / overfrequency fault is as follows: the processor calculates the real-time frequency f. rms , and the preset underfrequency threshold f under Over-frequency threshold f over In comparison, if f rms <f under or f rms >f over And the duration exceeds the frequency time threshold t freq If so, it is determined to be an underfrequency or overfrequency fault; The judgment logic for the harmonic current / voltage over-limit fault is as follows: the processor performs Fourier transform on the current and voltage signals to extract each harmonic component, calculates THDi, THDu and the amplitude of each harmonic current / voltage, and compares them with the preset harmonic threshold. If any harmonic component or distortion rate exceeds the threshold, it is judged as a harmonic current / voltage over-limit fault. The logic for determining harmonic current / voltage over-limit faults is as follows: the processor tracks the trend of the effective voltage value, and when the effective voltage value rises above the voltage spurt threshold ΔU... swell If the duration is within the voltage rise time range, it is determined to be a voltage rise; when the effective voltage value drops instantaneously beyond the voltage sag threshold ΔU... sag And since the duration is within the voltage sag time range, it is determined to be a voltage sag; The judgment logic for the short-circuit over-level fault is as follows: the processor obtains the short-circuit current detection value and action time information of the upper and lower level protection devices through the communication interface, and combines it with the pre-set protection coordination logic. If the upper level circuit breaker is detected to trip due to the short circuit of the lower level line, and the lower level protection device does not act, it is judged as a short-circuit over-level fault.

Images