Power module packaging structure

Abstract

The invention discloses a power module packaging structure. According to the chip, a non-linear conductive material coating is arranged at the connecting part of the edge of each metal bonding pad and a chip substrate, and the connecting part of the edge of each metal bonding pad and the chip substrate is the joint of the metal bonding pad, the chip substrate and an insulating encapsulating material, namely the three-phase point. Through the arrangement of the non-linear conductive material coating, the resistivity is high in a normal low field, and electric leakage is prevented; and when the local electric field intensity is increased sharply (terminal at the three-phase junction), the resistivity is reduced sharply, the electric field is uniformly dispersed, and the peak of the local electric field is inhibited, so that the overall dielectric strength and creepage distance of the module are improved. According to the technical scheme, the insulation reliability of the power module under high-voltage, high-frequency and high-temperature working conditions is remarkably improved, particularly, partial discharge is restrained at a three-phase point, the service life of the module is prolonged, and the production and maintenance cost is reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power electronic devices, and particularly relates to a power module packaging structure. BACKGROUND

[0002] With the development of power electronic devices towards high power density, high frequency and wide bandgap semiconductors (SiC, GaN), the module packaging voltage is increasing, and the reliability requirements of the power module on the insulation system are also rising. Under the conditions of high voltage and high-speed switching, the potting insulation material (such as epoxy resin and silicon gel) in the package is prone to partial discharge (PD) under the action of an electric field, which leads to material aging, performance degradation and even insulation breakdown, and becomes one of the main causes of power module failure.

[0003] In the module, the combination interface of the substrate (low-conductive material such as ceramic) and the metal layer and the "three-phase junction" (substrate ceramic-metal-insulation material) of the potting material have extremely strong local electric field enhancement, and this part is prone to form a partial discharge channel, accelerate the degradation of the insulation material, and may trigger secondary failure mechanisms such as electrical treeing and corona discharge.

[0004] Partial discharge often first occurs at the three-phase point and expands along the ceramic-silicon gel interface to form an electrical tree channel, eventually leading to insulation failure. Experiments have shown that when the electric field at the three-phase point exceeds the partial dielectric breakdown threshold, a small discharge pulse can be generated, and the long-term cumulative effect accelerates material aging.

[0005] In the prior art, the above technical problems are generally solved by the following methods: (1) Gradient dielectric material: By applying an alternating current field to the suspension, the inorganic filler is arranged in a chain along the electric field direction, and after solidification, a material with controllable gradient of dielectric constant and electrical conductivity along the thickness direction is formed, which reduces the electric field mutation at the three-phase point and thus suppresses partial discharge.

[0006] (2) Add a field regulation layer: A field regulation structure (epoxy / silicon gel composite layer or nonlinear filler layer) is designed between the direct copper clad ceramic substrate (DBC) substrate and the potting material, the dielectric constant and electrical conductivity distribution of different layers of materials are changed to smooth the electric field gradient at the three-phase point and reduce the local electric field peak value.

[0007] (3) Multi-level filler system: A dual filler system (silicon nitride, aluminum oxide and nano metal particles mixed) of micrometer and nanometer is used to consider thermal conductivity, mechanical strength and electrical performance, which not only improves the packaging heat dissipation performance, but also forms a multi-level charge buffer layer in the high field area, significantly delaying the generation of PD.

[0008] For example, the application with publication number CN110256813A discloses a dielectric gradient material preparation method and a pouring method. The application with publication number CN118398505A discloses an electric field regulation technology in a power electronic module pouring structure.

[0009] However, the main disadvantages of the above prior art are: (1) Many additional process steps: traditional pouring relies only on overall pouring and curing, and cannot perform local processing on the triple point. The step is single and cannot relieve the electric field at the triple point.

[0010] (2) Local electric field concentration: no silicon gel is pre-coated at the triple point, resulting in excessive electric field strength at the metal / ceramic / pouring glue junction, causing partial discharge (PD) problems.

[0011] (3) Bubble and interface delamination risk: the overall pouring process cannot fully remove the bubbles in the triple point micro-cracks, and the curing shrinkage easily causes interface cracking at the triple point.

[0012] (4) Thermal stress concentration: there is no flexible buffer layer at the triple point, and the difference in thermal expansion coefficients between the ceramic and the pouring glue causes interface stress concentration during thermal cycling, reducing the reliability of the module. SUMMARY

[0013] The present application provides a power module packaging structure to solve the above technical problems in the prior art.

[0014] A power module packaging structure, comprising: a chip array comprising a plurality of chips, each chip comprising a chip substrate and a metal pad disposed on the chip substrate; a low-voltage molybdenum layer disposed above the chip array; a high-voltage copper layer disposed below the chip array; a packaging shell, the chip array is packaged in the packaging shell; an insulating pouring material poured in the packaging shell, the chip is provided with a non-linear conductive material coating at the edge of each metal pad and the chip substrate connection part, and then the insulating pouring material is poured, the non-linear conductive material coating exhibits non-linear conductive properties when an electric field is applied.

[0015] Preferably, the non-linear conductive material coating has a jump in electrical conductivity in the range of 5-10 kV / mm of electric field.

[0016] Preferably, the non-linear conductive material in the non-linear conductive material coating is SiC nanoparticles and ZnO semiconductor particles added to a base, and the base is a silicone gel, polyurethane or acrylic acid.

[0017] More preferably, the average particle size of the SiC nanoparticles is 20-100 nm; and the particle size of the ZnO semiconductor particles is 1-5 μm.

[0018] More preferably, the nonlinear conductive material further comprises a curing agent, and the mass ratio of the matrix, the curing agent, the SiC nanoparticles and the ZnO semiconductor particles is 100:30:20-50:30-50.

[0019] In the preparation of the nonlinear conductive material coating, the SiC nanoparticles with an average particle size of 20-100 nm and the ZnO semiconductor particles with a particle size of 1-5 μm are treated at 80°C for 6 hours under vacuum drying conditions to remove moisture, and then the SiC nanoparticles and the ZnO semiconductor particles are added into the matrix in the mass fraction and uniformly mixed, vacuum mechanically stirred for 1 hour, and ultrasonically treated for 30 minutes to achieve uniform dispersion, and then the silicon gel and the curing agent are added and stirred for 30 minutes, and the mixed product is heated to 90-120°C, and after the rheological property decreases, it is poured into a mold preheated to 60°C; after curing at room temperature for 24 hours, heat treatment at 120°C for 2-4 hours is performed to complete the crosslinking and curing. The obtained composite material exhibits nonlinear conductive characteristics when an electric field is applied: the conductivity suddenly jumps around the electric field of 5-10 kV / mm, and the semiconductive property of SiC and the nonlinear effect of ZnO synergistically act to make the material have a low threshold and enhanced conductive capacity at a high field while maintaining an insulating state at a low field.

[0020] Preferably, the nonlinear conductive material coating is formed by in-situ spot gluing, spraying or dip coating and curing, or is preformed into a film piece and then assembled.

[0021] More preferably, the nonlinear conductive material coating is formed by in-situ spot gluing, spraying or dip coating and curing, and is degassed by negative pressure before curing, and the negative pressure is-0.095~-0.08 MPa. The vacuum degassing process makes the nonlinear conductive material fully penetrate into the micro gap, eliminates bubbles and enhances the interface bonding.

[0022] Preferably, the thickness of the nonlinear conductive material coating is 0.01-0.1 mm.

[0023] Preferably, the chips in the chip array are bonded by metal wires; a first sintered layer formed by sintering of solder paste is arranged between one side of the chip substrate of each chip and the high-voltage copper layer; and a low-voltage molybdenum layer extends a molybdenum column corresponding to each chip, and a second sintered layer formed by sintering of solder paste is arranged between the molybdenum column and the metal pad of the chip.

[0024] The low-voltage molybdenum layer is a ground molybdenum conductor for heat dissipation and ground connection, and provides a reliable electrical ground and heat dissipation path, and is welded and fixed with an external base or heat sink.

[0025] High-voltage copper layer, i.e. high-voltage copper conductor, can use pure copper foil, which is patterned and etched to form a power lead. The function is to bear high-voltage output of semiconductor devices such as switching tubes or diodes, and to form a high potential difference between three phases and ground.

[0026] The chip substrate in the chip can use a ceramic substrate, which is a low-conductivity material layer, and the specific material can be aluminum nitride or aluminum oxide, with a thickness of 0.4-1.0 mm, high thermal conductivity (>170 W / (m·K)) and high dielectric strength (>10 kV / mm). The function is electrical insulation, mechanical support and pin pad base of semiconductor devices.

[0027] The insulating potting material uses the material commonly used in the prior art, and generally uses silicone gel. The use of the insulating potting material plays the role of overall sealing, buffering mechanical stress, and blocking moisture and contaminants.

[0028] In the present application, the chip is provided with a non-linear conductive material coating at the edge of each metal pad and the chip substrate connection part, i.e. the intersection of the metal pad, the chip substrate and the insulating potting material, i.e. the triple point. By providing the non-linear conductive material coating, the resistivity is high in normal low field to prevent electric leakage; when the local electric field strength increases sharply (the "terminal" at the triple junction), the resistivity decreases sharply, uniformly disperses the electric field, and suppresses the local electric field peak, thereby improving the overall dielectric strength and creepage distance of the module.

[0029] Advantages of the present application: (1) Gradual release of electric field: by locally setting a non-linear conductive material coating at the triple point, the electric field gradient is smoothed, and the risk of partial discharge is reduced.

[0030] (2) Flexible buffer design: by the flexible properties of the non-linear conductive material coating, the stress caused by thermal expansion difference is absorbed, preventing delamination and crack generation at the triple point.

[0031] (3) Process compatibility: the non-linear conductive material coating application step can be seamlessly integrated into the existing potting production line, without the need for additional equipment modification, simplifying the process flow.

[0032] Through the above technical solutions, the present application aims to significantly improve the insulation reliability of the power module under high-voltage, high-frequency and high-temperature working conditions, especially to suppress the occurrence of partial discharge at the triple point, prolong the service life of the module and reduce the production and maintenance costs. BRIEF DESCRIPTION OF DRAWINGS

[0033] Figure 1 is a schematic diagram of the three-dimensional structure of the power module packaging structure of the present application.

[0034] Figure 2This is a side view of the power module packaging structure of the present invention.

[0035] Figure 3 for Figure 2 Sectional view along the middle AA.

[0036] Figure 4 This is a schematic diagram of the structure of a chip.

[0037] Figure 5 for Figure 4 Enlarged view of part B in the middle.

[0038] Figure 6 This is a schematic diagram of the three-dimensional structure of the low-pressure molybdenum layer.

[0039] Figure 7 This is a three-dimensional structural diagram of the encapsulation shell.

[0040] Figure 8 This is a three-dimensional structural diagram of an insulating potting material.

[0041] Figure 9 This is a schematic diagram of the three-dimensional structure of the high-voltage copper layer.

[0042] Figure 10 This is a schematic diagram of the three-dimensional structure of the chip array.

[0043] Figure 11 This is a schematic diagram of the three-dimensional structure of the chip array on a high-voltage copper layer.

[0044] Figure 12 This is a top view of the chip array structure on a high-voltage copper layer.

[0045] Figure 13 This is a schematic diagram of the location structure of a nonlinear conductive material coating on a chip.

[0046] Figure 14 The image shows the simulation results. Among them, Figure 14 In this context, A represents the application of a nonlinear conductive material coating. Figure 14 In this context, B represents the absence of a nonlinear conductivity material coating.

[0047] Reference numerals: Chip 1, Chip substrate 11, Metal pad 12, Metal wire 13, Terminal 14, Low-voltage molybdenum layer 2, Molybdenum pillar 21, High-voltage copper layer 3, Copper pillar 31, Encapsulation shell 4, Heat sink fin 41, Insulating potting material 5, Nonlinear conductive material coating 6, First sintered layer 7, Second sintered layer 8. Detailed Implementation

[0048] like Figures 1 to 13As shown in the figure, a power module packaging structure includes a chip array, the chip array includes a plurality of chips 1, the structure shown in the figure includes two groups of chip arrays, each group of chip arrays includes five chips 1, and each group of chip arrays further includes a terminal 14; each chip 1 includes a chip substrate 11 and a metal pad 12 arranged on the chip substrate 11; the metal pads 12 in the five chips 1 in each group of chip arrays are bonded to the terminal 14 through a metal wire 13, and the terminal 14 is used for connecting an external circuit.

[0049] The chip substrate 11 in the chip 1 can use a ceramic substrate, which is a low-conductivity material layer, and the specific material can be aluminum nitride or aluminum oxide, with a thickness of 0.4-1.0 mm, high thermal conductivity (>170 W / (m·K)) and high dielectric strength (>10 kV / mm). The function is to provide electrical insulation, mechanical support and pin pad base for semiconductor devices.

[0050] Above the chip array, that is, on the side where the metal pad 12 is located, a low-voltage molybdenum layer 2 is also arranged, that is, a ground molybdenum conductor, which is used for heat dissipation and ground connection, provides a reliable electrical ground, a heat dissipation path, and is welded and fixed with an external base or a heat dissipation fin. The bottom surface of the low-voltage molybdenum layer 2 is provided with a molybdenum column 21 opposite the position of the metal pad 12 of each chip 1, and the molybdenum column 21 protrudes downward and extends to near the metal pad 12.

[0051] Below the chip array, that is, on the side where the chip substrate 11 is located, a high-voltage copper layer 3 is also arranged, that is, a high-voltage copper conductor, which can use a pure copper foil and is etched into a power lead after patterning. The function is to bear the high-voltage output of semiconductor devices such as switching tubes or diodes, and form a high potential difference between three phases and ground. The top surface of the high-voltage copper layer 3 is provided with a copper column 31 opposite the position of the chip substrate 11 of each chip 1, and the copper column 31 protrudes upward and extends to near the chip substrate 11.

[0052] A first sintering layer 7 formed by sintering of solder paste is arranged between the side of the chip substrate 11 of each chip 1 and the copper column 31 of the high-voltage copper layer 3; and a second sintering layer 8 formed by sintering of solder paste is arranged between the side of the metal pad 12 of each chip 1 and the molybdenum column 21 of the low-voltage molybdenum layer 2.

[0053] The power module packaging structure further includes a packaging shell 4, and the chip array is packaged in the packaging shell 4. The packaging shell 4 is composed of a plurality of layers of insulating substrates, which not only realizes mechanical support and environmental protection of the module, but also forms heat dissipation fins 41 on the side.

[0054] The bottom end of the high-voltage copper layer 3 protrudes downward from the package shell 4, the top end of the low-voltage molybdenum layer 2 protrudes upward from the package shell 4, and the chip array is located in the space enclosed by the package shell 4, the low-voltage molybdenum layer 2 and the high-voltage copper layer. The space is filled with an insulating potting material 5 in the gap. The insulating potting material can use the material commonly used in the prior art, and generally can use a silicone gel, i.e. a two-component (AB two components) silicone gel. The use of the insulating potting material plays a role in overall sealing, buffering mechanical stress, and blocking moisture and contaminants.

[0055] Before the insulating potting material 5 is filled, a non-linear conductive material coating 6 is arranged at the edge of each metal pad 12 of the chip 1 and the connection part of the chip substrate 11, and then the insulating potting material 5 is filled. The non-linear conductive material coating 6 exhibits a non-linear conductive characteristic when an electric field is applied. The specific position of the non-linear conductive material coating 6 is shown in Figure 13 Figure 13 In the above figure, the metal pads 12 on one chip 1 are divided into multiple blocks, and each block of metal pads 12 has a gap between them, Figure 13 The area enclosed by the dashed line in the above figure is the position where the non-linear conductive material coating 6 is arranged.

[0056] The non-linear conductive material coating 6 has a jump in conductivity in the range of 5-10 kV / mm of electric field. The non-linear conductive material in the non-linear conductive material coating 6 is SiC nanoparticles and ZnO semiconductor particles added to the matrix, and the matrix is silicone gel, polyurethane or acrylic. The average particle size of the SiC nanoparticles is 20-100 nm; the particle size of the ZnO semiconductor particles is 1-5 μm. The non-linear conductive material also includes a curing agent. By weight, the matrix: curing agent: SiC nanoparticles: ZnO semiconductor particles is 100:30:20-50:30-50.

[0057] When using a two-component silicone gel, the silicone gel AB component is a two-component room temperature curing silicone material, which is formed into an elastic solid by cross-linking reaction after mixing A component (base polymer, i.e. matrix in this application) and B component (curing agent) in proportion. The A component contains vinyl polysiloxane, which provides a three-dimensional network skeleton; the B component contains hydrogen-containing silicone oil and platinum catalyst, which forms a cross-linked structure through silicon-hydrogen addition reaction.

[0058] The matrix material used in the non-linear conductive material coating is the same as the insulating potting material.

[0059] ​The non-linear conductive material coating is prepared by mixing the SiC nanoparticles with an average particle size of 20-100 nm and the ZnO semiconductor particles with a particle size of 1-5 μm in a mass ratio in a base, uniformly stirring for 1 hour in vacuum, uniformly dispersing by ultrasonic treatment for 30 minutes, gradually adding a curing agent, continuously stirring for 30 minutes, heating the mixed product to 90-120°C, pouring the product into a mold preheated to 60°C after the rheological property is reduced, and completing cross-linking and curing by heat treatment at 120°C for 2-4 hours after solidification at room temperature for 24 hours.

[0060] The non-linear conductive material coating 6 is formed by in-situ spot gluing, spraying or dip coating and curing, or is preformed into a film and then assembled. The non-linear conductive material coating 6 is arranged to have a thickness of 0.01-0.1 mm. The width of the non-linear conductive material coating 6 has no effect on the result, and generally only needs to cover the three-phase junction.

[0061] The non-linear conductive material coating is formed by in-situ spot gluing, spraying or dip coating and curing, and is degassed by negative pressure before curing. The negative pressure is-0.095~-0.08 MPa, and the negative pressure time can be 13-15 minutes. The vacuum degassing process is used to make the non-linear conductive material fully penetrate the micro-cracks, eliminate bubbles and enhance the interface bonding.

[0062] In the present application, the non-linear conductive material coating is arranged at the edge of each metal pad and the chip substrate connecting part, that is, the three-phase point. By arranging the non-linear conductive material coating, the resistivity is high at normal low field to prevent electric leakage, and the resistivity sharply decreases when the local electric field strength sharply increases (at the "terminal" of the three-phase junction), the electric field is uniformly dispersed, the local electric field peak is suppressed, and thus the overall dielectric strength and creepage distance of the module are improved.

[0063] Example 1: Comparison of the effect of the non-linear conductive material coating on the power module packaging structure (1) Model of the module is established. The model is constructed and simulated by using the software comsol. The specific parameters of the materials of the components are shown in Table 1. In Table 1, the conductivity of the non-linear material is described as 1.3×10 -12 ×[1+(E / 15) 7 ], wherein 1.3×10-12 denoted as the electrical conductivity of the matrix material, E as the applied voltage, 15 as the switching electric field (i.e., the threshold voltage), and 7 as the value of the nonlinear coefficient α.

[0064] Furthermore, the terminals and the package housing have no effect on the electric field at the three-phase point, so they are all outside the solution domain during simulation. The thickness and width of the nonlinear conductive material coating are both 0.05 mm.

[0065] Table 1. Specific parameters of the simulation

[0066] (2) Apply a load, wherein the top surface of the low-voltage molybdenum layer is grounded and the bottom surface of the high-voltage copper layer is connected to a voltage of 6500V.

[0067] (3) After calculation and simulation, the electric field intensity distribution results are as follows: Figure 14 As shown, Figure 14 In this context, A represents the application of a nonlinear conductive material coating. Figure 14 In the figure, B represents the absence of a nonlinear conductive material coating. It can be seen that the addition of a nonlinear conductive material coating can significantly reduce the electric field strength at the three-phase interface, effectively weakening the electric field.

Claims

1. A power module packaging structure, characterized in that, include: A chip array, comprising several chips, each chip including a chip substrate and metal pads disposed on the chip substrate; A low-pressure molybdenum layer is disposed above the chip array; A high-voltage copper layer is disposed below the chip array; The chip array is encapsulated within the packaging housing. An insulating potting material is encapsulated within the package housing. After a nonlinear conductive material coating is applied to the edge of each metal pad where the chip connects to the chip substrate, the insulating potting material is then encapsulated. The nonlinear conductive material coating exhibits nonlinear conductive characteristics when an electric field is applied.

2. The power module packaging structure according to claim 1, characterized in that, The nonlinear conductive material coating exhibits a rapid increase in conductivity within an electric field range of 5-10 kV / mm.

3. The power module packaging structure according to claim 1, characterized in that, The nonlinear conductive material coating consists of SiC nanoparticles and ZnO semiconductor particles added to a matrix, which is a silica gel, polyurethane, or acrylic acid.

4. The power module packaging structure according to claim 3, characterized in that, The average particle size of SiC nanoparticles is 20-100 nm; the particle size of ZnO semiconductor particles is 1-5 μm.

5. The power module packaging structure according to claim 3, characterized in that, The nonlinear conductive material also includes a curing agent, and by weight, the ratio of matrix:curing agent:SiC nanoparticles:ZnO semiconductor particles is 100:30:20-50:30-50.

6. The power module packaging structure according to claim 1, characterized in that, The nonlinear conductive material coating is formed by in-situ adhesive coating, spraying, or dipping followed by curing, or by prefabricating a film before assembly.

7. The power module packaging structure according to claim 6, characterized in that, The nonlinear conductive material coating is formed by in-situ adhesive coating, spraying, or dipping followed by curing. Before curing, it is degassed under negative pressure, with the negative pressure being -0.095 to -0.08 MPa.

8. The power module packaging structure according to claim 1, characterized in that, The thickness of the nonlinear conductive material coating is set to 0.01-0.1 mm.

9. The power module packaging structure according to claim 1, characterized in that, In the chip array, each chip is bonded by a metal wire; a first sintering layer formed by solder paste is provided between the chip substrate side of each chip and the high-voltage copper layer; a low-voltage molybdenum layer extends out a molybdenum pillar for each chip, and a second sintering layer formed by solder paste is provided between the molybdenum pillar and the metal pad of the chip.

Images