Chip heat dissipation layout optimization method based on improved Transform model

Abstract

The invention provides a chip heat dissipation layout optimization method based on an improved Transform model, and the method employs the improved Transform model to carry out the preprocessing of training data, strengthens the analysis capability of a model for the temperature intensity under a spatial position relation for the structured spatial data of a chip position coordinate, can effectively capture an interconnection relation during the processing of the structured sequence data, and achieves the optimization of the heat dissipation layout of a chip. The complex relationship between different data sequences can be accurately represented and predicted; and meanwhile, a nonlinear feature enhancement layer is added into the network model, so that the defect of mining a nonlinear feature relationship by a Transform model feed-forward network is made up, and the ability of the network model to learn the relationship between the layout of the chip position and the heat influence temperature is enhanced. According to the method, the limitation of a traditional chip based on human experience is broken through, the design process can be accelerated, the effective heat dissipation control of the optimal layout of the circuit board chip position can be improved through accurate layout optimization, the service life of electronic equipment is finally prolonged, and the maintenance cost of an electronic equipment system is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of electric digital data processing, and in particular to a chip heat dissipation layout optimization method based on an improved Transformer model. BACKGROUND

[0002] With the continuous progress of science and technology and the popularization of electronic equipment, as the core component of various electronic equipment, when designing the layout of the circuit board, the close distance between multiple chips makes the heat dissipation problem complex, the temperature influences each other, the heat dissipation space is limited, the thermal coupling effect is intensified, under high temperature environment, the thermal expansion between chips will restrict each other to generate thermal stress, causing chip deformation and even rupture, resulting in various consequences such as performance degradation of equipment, damage to system stability, shortening of electronic equipment life and increase of maintenance cost.

[0003] Optimizing the position layout of multiple chips in electronic equipment is an important means to improve the overall system performance of electronic equipment. With the development of electronic equipment towards high performance and miniaturization, how to reasonably arrange the layout position of chips in limited space under the background of optimal heat dissipation has become the key to ensure the efficient operation of electronic equipment.

[0004] Therefore, there is a need for a chip heat dissipation layout position optimization method. SUMMARY

[0005] The present application is to solve the problem of intensified thermal coupling effect, increased mechanical stress, decreased system reliability, damaged equipment stability and other problems caused by high temperature between multiple chips, and provides a chip heat dissipation layout optimization method based on an improved Transformer model. In order to ensure the stable operation and long-term reliability of electronic equipment, the chip position of the circuit design in the actual electronic engineering is optimized, the optimal distance between chips is adjusted to provide sufficient heat dissipation space and reduce the thermal coupling effect, so that the heat dissipation condition of the circuit board card is optimal as the precondition, the chip layout is optimized based on the finite element simulation iteration which is seriously dependent on the experience of designers in the design process is reduced, the effective heat dissipation control of the optimal layout of the chip position of the circuit board is improved, and the research and development efficiency is improved.

[0006] The present application provides a chip heat dissipation layout optimization method based on an improved Transformer model, comprising the following steps:

[0007] S1, data set preparation, generating N groups of chip coordinate combinations meeting the chip layout requirements, two coordinates in each group: (x1, y1), (x2, y2), and simulating the highest board temperature z corresponding to each group of coordinates;

[0008] S2, data set preprocessing, calculating the Euclidean distance d, angle r and coordinate difference Δ of two chips in the coordinate combinations We obtain N preprocessed datasets, where the preprocessed data is: ((x1,y1,x2,y2,d,r,Δ) s ),z);

[0009] S3. Build an improved Transformer network model. Add a spatial distance attenuation factor and modify the weights of multi-head attention to focus on regions with high thermal interference temperatures when chips are close together. Add a nonlinear feature enhancement layer after the feedforward layer of the Transformer network model to highlight the relationship between temperature and chip coordinates. The nonlinear feature enhancement module includes a sequentially connected input feature encoding module, a multi-scale spatial enhancement module, a nonlinear activation association module, a spatial feature and temperature feature cross-coupling module, and an output feature encoding module. The input features of the nonlinear feature enhancement module are the feature vectors output from the feedforward layer, which include chip coordinates, temperature, and self-attention weighting information. Configure the hyperparameters of the improved Transformer network model.

[0010] S4. Divide the dataset into training set, test set and validation set, and input them into the improved Transformer network model for training;

[0011] S5. Use the loss function to evaluate the model. Once the evaluation is successful, the trained model is obtained.

[0012] S6. Use the trained model to predict the maximum temperature under different chip layouts.

[0013] The chip heat dissipation layout optimization method based on an improved Transformer model described in this invention, as a preferred method, in step S3, the nonlinear feature enhancement module performs deep cross-combination and nonlinear information mining on the spatial characteristics of the chip layout to obtain continuous value features. After the splicing layer splices the features, they are sent to the fully connected layer MLP module for combined prediction tasks. By mining the spatial regularity information of the structured list data in the dataset, the maximum temperature value corresponding to different chip layouts is predicted.

[0014] The chip heat dissipation layout optimization method based on an improved Transformer model described in this invention, as a preferred embodiment, has the spatial distance attenuation factor f(d) in step S3 as follows:

[0015]

[0016] Where f(d) represents the degree of temperature attenuation caused by the distance between the two chips, and f(d) is a coefficient with a value range of (0, 1]; α is the learning attenuation coefficient, which controls the speed of distance attenuation and adapts to different chip layout characteristics.

[0017] The chip heat dissipation layout optimization method based on the improved Transformer model described in this invention, as a preferred method, is that when the chip positions in the chip group are close, d approaches 0, then f(d) approaches 1, indicating that the thermal coupling effect is high and the temperature mutual influence is strongest.

[0018] When the chip is furthest away, f(d) approaches 0, indicating that the thermal coupling effect is low and the temperature interaction is weakest.

[0019] The chip heat dissipation layout optimization method based on an improved Transformer model described in this invention, as a preferred embodiment, involves the input feature encoding module performing relative relationship transformation and feature separation processing on the input feature vector information in step S3: For the input features ((x1,y1,x2,y2,d,r,Δ... s Feature separation is performed using z), resulting in location features and temperature features;

[0020] The multi-scale spatial enhancement module includes small-scale branches, large-scale branches, and a gated attention fusion layer connected to both small-scale and large-scale branches. The small-scale branch convolution mines the thermal relationships of local regions at a single chip location, while the large-scale branch mines the global temperature and thermal relationships between chips at long distances. The gated attention fusion layer performs weighted fusion.

[0021] The nonlinear activation correlation module performs nonlinear activation and spatial relationship mapping to simulate the nonlinear decay law of temperature changing with distance, and strengthens the exponential decay nonlinear transformation calculation for relative distance features;

[0022] The spatial and temperature feature cross-coupling module takes the chip coordinate difference as input and uses a multilayer perceptron (MLP) to calculate the spatial correlation matrix of the thermal effects between the two chips, thereby mining and capturing the coordinate cross-relationship.

[0023] The output feature encoding module directly uses the enhanced feature encoding for structured spatial relationship features in reverse reasoning and forward prediction. The output features include local relationships, global relationships, and nonlinear mapping relationships.

[0024] The chip heat dissipation layout optimization method based on an improved Transformer model described in this invention, as a preferred method, uses a 3×3 convolution kernel for small-scale branches and a 5×5 convolution kernel for large-scale branches;

[0025] The thermal influence weights calculated by the spatial and temperature feature cross-coupling module are as follows:

[0026] ω 热 =σ(W·[Δ x ,Δ y ,Δ x ·Δ y ,|Δx -Δ y |]+b);

[0027] Where σ is the sigmoid activation, W is the model weight, b is the bias, Δx is the x-axis coordinate difference between chipsets, and Δy is the y-axis coordinate difference between chipsets.

[0028] The local relationships are the relative positions of the chip and its neighboring chips, and the weights of temperature influence. The global relationships are the features of global pooling through the large-scale branches of the multi-scale spatial enhancement module. The features of the nonlinear mapping relationships include nonlinear function parameters that convert coordinate differences into temperature influences, which can support the conversion of temperature influences into coordinate differences for reverse reasoning.

[0029] The chip heat dissipation layout optimization method based on the improved Transformer model described in this invention, as a preferred method, involves using Matlab software to generate N sets of chip coordinate combinations in step S1, and using finite element simulation software to obtain the highest board temperature z corresponding to each set of coordinate combinations.

[0030] The chip heat dissipation layout optimization method based on an improved Transformer model described in this invention, as a preferred embodiment, includes step S2,

[0031]

[0032] The chip heat dissipation layout optimization method based on the improved Transformer model described in this invention, as a preferred embodiment, further includes cleaning the preprocessed training set dataset in step S2. The data cleaning method is as follows: distinguishing numerical types, normalizing different numerical features, defining and dividing input features and target fields, using pandas to read input data into a dataframe for data cleaning, and removing invalid data examples from the first row.

[0033] In the chip heat dissipation layout optimization method based on the improved Transformer model described in this invention, as a preferred method, in step S5, the Adam optimizer is used to update the model parameters.

[0034] This invention meets the need for intelligent calculation of the optimal position coordinates of chip placement under optimal heat dissipation conditions in practical electronic engineering PCB layout design.

[0035] The technical solution of this invention is as follows: This invention is a spatial location prediction model framework based on an improved Transformer network algorithm. 5000 and 1000 sets of data, each containing the coordinates of two chip center points and the corresponding actual maximum temperature value (set to z), are converted into structured spatial data. This data is then used as the training and testing sets of the network and input into the improved Transformer module. By modifying the model's self-attention weight factor and adding a "nonlinear feature enhancement layer" after the feedforward layer to adapt to the spatial characteristics of the chip layout, deep cross-combination and nonlinear information mining are performed. Continuous value features are obtained and then concatenated before being fed into the fully connected MLP module for combined prediction tasks. This effectively mines spatial regularity information within the structured list data, predicting the maximum temperature value corresponding to different chip layouts. Furthermore, the optimal chip placement can be calculated by setting the maximum temperature value.

[0036] Ultimately, a general algorithm system for predicting optimal chip placement with intelligence and high precision was established, demonstrating its versatility in the field of circuit optimization design technology. The specific steps are as follows:

[0037] (1) Training set data preparation: First, use Matlab software to generate 5000 sets of chip center point coordinate combinations that meet the board layout requirements, and use finite element simulation software to simulate and obtain the highest temperature corresponding to each set of coordinates.

[0038] (2) Training Dataset Preprocessing: The temperature values ​​corresponding to the chip center point coordinate dataset above are converted into structured spatial data. Preprocessing is performed on the input training data to calculate the absolute position features, relative position features, and corresponding temperature values ​​of the two chips as input data ((x1, y1, x2, y2, d, r, Δ). s ),z);

[0039] (3) Self-attention weight factor modification: An improved version of the Transformer network model was built, and a "spatial distance decay factor" was added to the attention of the network model to correct the weight. When the chip is closer (d is smaller), the attention weight decay is smaller, so that the network model pays more attention to the chip interaction area with strong thermal interference temperature. Through the multi-head attention layer of the multi-head attention mechanism in the network model, the model can simultaneously consider the relationship between chip data and all cells corresponding to the temperature, learn the interaction relationship between cell data features in parallel, and strengthen the context relationship of the structured data after the entire input dataset is transformed.

[0040] (4) Adding a "Nonlinear Feature Enhancement Layer": Since the temperature value resulting from the thermal impact of chip position and its layout is nonlinear, this method adds a nonlinear feature enhancement layer after the feedforward layer of the Transformer model network. Its input features are the feature vector output by the feedforward layer (chip coordinates, temperature, and self-attention weighted information). Adding this module allows for the output of enhanced spatial relationships, enabling targeted capture of the influence of chip position and temperature. Its architecture consists of five modules: an input feature encoding module, a multi-scale spatial enhancement module, a nonlinear activation correlation module, a spatial feature and temperature feature cross-coupling module, and an output feature encoding module. The enhancement method is as follows:

[0041] ① Input Feature Encoding Module

[0042] a) Perform relative relation transformation and feature separation processing on the input feature vector information:

[0043] Perform relative spatial feature transformation on the input features (convert absolute spatial position information into relative spatial features): calculate the Euclidean distance, angle and coordinate difference between two chips on the board to reflect the spatial position interaction relationship between the two chips.

[0044] For input features ((x1,y1,x2,y2,d,r,Δ) s Feature separation is performed using z): it is divided into location features and temperature features, which serve as the basis for cross-enhancing of network model data.

[0045] ② Multi-scale spatial enhancement module

[0046] Spatial relationship enhancement is performed on the input feature vector information. To enable the model to capture the influence of chip temperature at different distances, parallel convolutional branches are used to simultaneously learn the spatial temperature influence of the chip at different distances. The multi-scale spatial enhancement module mainly consists of small-scale branch 3×3 convolutional kernels, large-scale branch 5×5 convolutional kernels, and a fusion layer (gated attention weighted fusion).

[0047] First, 3×3 convolution is used to mine the thermal relationships in local areas of a single chip location. Then, 5×5 convolution is used to mine the global temperature and thermal relationships between distant chips. Finally, gated attention is used to weight the above feature results to complete the fusion.

[0048] ③ Nonlinear activation association module

[0049] To simulate the nonlinear decay law of temperature variation with distance, nonlinear activation and spatial relationship mapping can be used to enhance the calculation of exponential decay nonlinear transformation of relative distance features, thereby improving the mining of the sensitivity relationship of these features to spatial distance.

[0050] ④ Spatial and temperature characteristics cross-coupling module

[0051] Using the chip coordinate difference as input, a multilayer perceptron (MLP) is used to calculate the spatial correlation matrix of the thermal impact between the two chips. The thermal impact weights are then calculated.

[0052] ω 热 =σ(W·[Δ x ,Δ y ,Δ x ·Δ y ,|Δ x -Δ y |]+b)

[0053] Where σ is the sigmoid activation, W is the model weight, and b is the bias, which can be used to capture coordinate intersection relationships.

[0054] ⑤ Output Feature Encoding Module

[0055] To enable the enhanced feature encoding to be directly used for structured spatial relationship features in both backward reasoning and forward prediction, the output features include three types of key spatial relationships:

[0056] a) Local relationships: relative position of the chip to its neighboring chips and the weight of temperature influence.

[0057] b) Global Relationship: Feature global pooling through 5×5 convolutional kernels of multi-scale fusion layers.

[0058] c) Nonlinear mapping relationship: The feature contains nonlinear function parameters that convert coordinate differences into temperature effects, which can support the conversion of temperature effects into coordinate differences for reverse reasoning.

[0059] During network model training and optimization, the Adam optimizer is used to update model parameters and adaptively adjust the learning rate to accelerate network model convergence. By learning the discrete and continuous features of the data, the data patterns are accurately mined. A "spatial feature enhancement module" is added after the encoder of the model to highlight the nonlinear relationship between temperature and chip coordinate position, which makes up for the deficiency of the feedforward network of the Transformer model in mining nonlinear feature relationships and enhances the network model's ability to learn the relationship between chip position layout and thermally affected temperature.

[0060] (5) Model prediction and forecasting: After network training, various features and dependencies of the data are obtained to complete the prediction task; the chip layout coordinates under a specific temperature value are accurately predicted by learning the discrete and continuous features of the data, and the chip layout temperature under the optimal heat dissipation conditions is predicted.

[0061] (6) Finally, the error between the chip position coordinates generated by the test and the chip position coordinates under actual simulation conditions is calculated to measure the difference between the predicted value and the actual value, and to comprehensively evaluate the prediction accuracy of the optimization algorithm. This technology can be applied to the circuit optimization component layout design technology in the field of semiconductor design.

[0062] The present invention has the following advantages:

[0063] (1) High prediction accuracy of the system: First, the improved Transformer model preprocesses the training data and enhances the model’s ability to analyze the temperature intensity under spatial positional relationships by processing the structured spatial data of chip position coordinates. When processing structured sequence data, it can effectively capture interconnection relationships and accurately represent and predict complex relationships between different data sequences. At the same time, a nonlinear feature enhancement layer is added to the network model to make up for the defects of the feedforward network of the Transformer model in mining nonlinear feature relationships and enhance the network model’s ability to learn the relationship between chip position layout and thermally affected temperature.

[0064] Finally, the last 1000 sets of data were selected as the test set. The pre-trained model can estimate the corresponding temperature. After multiple tests, the optimal average absolute error of the predicted chip temperature value was about 0.84°.

[0065] (2) Improved design efficiency and accelerated chip design cycle: Parallel computing is achieved through this network model, which improves training and inference efficiency, significantly shortens the chip heat dissipation layout design cycle, and improves system design and testing speed;

[0066] (3) Reduced energy consumption and labor costs: Optimizing chip heat dissipation layout can reduce the risks of chip performance degradation and device failure, and reduce manufacturing costs. Automated model prediction methods can significantly reduce the manufacturing costs of traditional manual design.

[0067] (4) Strong system generalization ability: Compared with traditional methods, this model can learn experience and rules from historical lists / structured data and use them to predict future samples of a certain parameter. As the number of training samples / classes increases, this method can quickly adapt to other similar design tasks and generate corresponding optimized performance solutions.

[0068] In summary, the method of predicting the optimal heat dissipation layout of chips using an improved version of the Transformer network overcomes the limitations of traditional chip design based on human factors experience. It can not only accelerate the design process and improve the effective heat dissipation control of the optimal chip placement on the circuit board through precise layout optimization, but also ultimately extend the service life of electronic devices and reduce the maintenance costs of electronic device systems. Attached Figure Description

[0069] Fig. 1This is a flowchart of a chip heat dissipation layout optimization method based on an improved Transformer model;

[0070] Fig. 2 This is a schematic diagram of the basic structure of an improved Transformer network model, which is a chip heat dissipation layout optimization method based on an improved Transformer model.

[0071] Fig. 3 This is a schematic diagram of the nonlinear feature enhancement layer structure of a chip heat dissipation layout optimization method based on an improved Transformer model.

[0072] Fig. 4 The graph shows the LOSS value change during the training process of a chip heat dissipation optimal layout algorithm framework based on an improved Transformer model.

[0073] Fig. 5 This is a comparison of predicted and actual temperature values ​​from 1000 test sets in a test experiment of a chip heat dissipation layout optimization method based on an improved Transformer model.

[0074] Fig. 6 This is the error result of the predicted and actual temperature values ​​after 250 training iterations for a chip heat dissipation layout optimization method based on an improved Transformer model. Detailed Implementation

[0075] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0076] Example 1

[0077] like Figs. 1-3 As shown, a chip heat dissipation layout optimization method based on an improved Transformer model includes the following steps:

[0078] S1. MATLAB software generates 5000 coordinate combinations that meet the board layout requirements. Finite element simulation software is used to obtain the highest temperature corresponding to each coordinate combination. Two chips (x1, y1) and (x2, y2) are used as the network input dataset, and the temperature value z is set as the training label. Since Transformer network models are mostly used for sequential data, but the chip coordinates in this system are structured spatial data, the "spatial relationship" of the input data needs to be represented during dataset preprocessing. This representation is then input into the corresponding improved Transformer model.

[0079] S2. Dataset Preprocessing: 5000 sets of two-chip coordinate combinations and corresponding temperature values ​​are represented as a matrix. The features of the input chip center point coordinates (x1, y1) and (x2, y2) are decomposed into "absolute position" and "relative position" to provide the core correlation feature for the model to learn that the closer the two chips are, the stronger the thermal interference. This data serves as the input data for the network model.

[0080] ① Absolute position characteristics of the chip: In order to directly reflect the absolute position of the chip on the board, (x1,y1) and (x2,y2) are changed to (x1,y1,x2,y2).

[0081] ② Relative position characteristics of chips: Calculate the Euclidean distance, angle and coordinate difference between two chips on the board to reflect the spatial position interaction between the two chips.

[0082]

[0083] Δ s = (x1-x2, y1-y2)

[0084] Define dataset metadata: differentiate the numerical types of the above data fields and normalize the different numerical features; define and divide the input features and target fields; use pandas to read the input data into a dataframe for data cleaning, removing invalid data examples from the first row ((x1,y1,x2,y2,d,r,Δ)). s ),z), save 5000 training sets and 1000 test sets back to each CSV file;

[0085] S3. Configure network model hyperparameters: Set the learning rate of the improved Transformer network to 0.00005, batch size to 265, epochs to 250, number of Transformer modules to 3, number of attention heads to 4, num_embeddings to 4000 rows, categorical embedding dimension embeddings_dim to 5, and number of hidden units in MLP (Multilayer Perceptron) to 2.

[0086] Model Construction: Import the training and validation sets, define the optimizer as Adam, call the model code to train the model, convert 5000 and 1000 sets of data with the coordinates of the two chip center points and the corresponding actual maximum temperature value (Temperature set to z) into structured spatial data, and use them as the training and test sets of the network to input into the improved Transformer module; after continuous features (chip position and corresponding temperature) are normalized by layers, they are input into the multi-head attention layer of the Transformer, after the first residual connection and layer normalization, they are input into the feedforward layer; the result of continuous feature layer normalization is also input into the first residual connection and layer normalization module;

[0087] By modifying the model's self-attention weights and adding a "nonlinear feature enhancement layer" after the feedforward layer to adapt to the spatial characteristics of chip layout, this method performs deep cross-combination and nonlinear information mining. After residual connection and layer normalization, continuous value features are obtained and then concatenated before being fed into the fully connected MLP module for combined prediction. Simultaneously, categorical features (number of chips) are column-embedded and input into the concatenation layer. This method effectively mines spatial regularity information within structured list data and can predict the maximum temperature value corresponding to different chip layouts. This method adds a nonlinear feature enhancement layer after the feedforward layer of the Transformer model. The nonlinear feature enhancement layer consists of five modules: an input feature encoding module, a multi-scale spatial enhancement module, a nonlinear activation association module, a spatial feature and temperature feature cross-coupling module, and an output feature encoding module. Adding this module can output the spatial relationship after feature enhancement, which can specifically capture the influence of chip position and temperature.

[0088] S4. Model Fine-tuning: First, the weights of multi-head attention are modified by adding a spatial distance attenuation factor to the transformer model to focus on regions with high thermal interference temperatures when chips are close together; at the same time, a "spatial feature enhancement module" is added after the encoder of the model to highlight the relationship between temperature and chip coordinate position.

[0089] ① Spatial distance attenuation factor: Regarding the multi-head attention mechanism of the transformer model mentioned above, since the standard self-attention of the model assigns equal weight to all positions, but the thermal impact of the chip is stronger in the actual chip layout, in order to make the model pay attention to the areas with high thermal interference temperature when the chip positions are close together during training, this method modifies the weights of the multi-head attention by adding a spatial distance attenuation factor:

[0090]

[0091] Where f(d) is the distance attenuation factor, which represents the degree to which the distance between two chips attenuates the effect of temperature, and its value ranges from (0, 1). d is the Euclidean distance between the chips, and α is the learning attenuation coefficient, which controls the rate of distance attenuation (adapting to different chip layout characteristics).

[0092] When the chip positions are close and the positional distance d approaches 0, then f(d) approaches 1, indicating a high thermal coupling effect and the strongest temperature interaction.

[0093] When the chip is located far away, f(d) approaches 0, indicating that the thermal coupling effect is low and the temperature interaction is weakest.

[0094] ② Nonlinear Feature Enhancement Layer: Since the thermal impact temperature values ​​resulting from the chip's location and layout have a nonlinear relationship, this module enhances the output of the spatial relationship. The nonlinear feature enhancement module consists of an input feature encoding module, a multi-scale spatial enhancement module, a nonlinear activation correlation module, a spatial feature and temperature feature cross-coupling module, and an output feature encoding module. It takes the feature vector output from the preceding Transformer model as input, compensating for the Transformer model's feedforward network's shortcomings in mining nonlinear feature relationships and enhancing the network model's ability to learn the relationship between the chip's location layout and its thermal impact temperature.

[0095] S5. Model Evaluation: During training, the network retains error information from the training process. This invention introduces loss value prediction data processing to assess the regression model performance, calculates the error between the actual and predicted temperature values, and evaluates the prediction accuracy of the optimized algorithm network. The test results of the improved Transformer model in this invention show excellent performance. Through optimization of the network's self-attention weights and the design of nonlinear feature enhancement layers, the nonlinear correlation between chip coordinates and temperature is accurately discovered. In two sets of typical chip layout tests (see Table 2), the absolute errors between the predicted and actual temperatures are 0.8787℃ and 0.8396℃, respectively, both controlled within 0.9℃. In practical terms, an error ≤0.9℃ can effectively guide chip layout optimization and reduce physical testing costs; stable performance ensures reliability under different heat dissipation scenarios, providing a precise tool for high-density board thermal management.

[0096] S6. Use the trained model to predict the maximum temperature under different chip layouts.

[0097] Table 1 shows the input training set and test set data formats for the chip heat dissipation layout optimization framework in this embodiment.

[0098] Table 1

[0099] x1 x2 y1 y2 temperature 8.049658 4.723812 5.820529 3.341657 70.17099 3.317436 7.877631 4.945888 9.033498 69.90516 7.121235 1.861336 9.1591 4.933812 71.98534 9.406176 2.987714 0.782782 9.096491 74.80563 3.478561 9.276793 5.225178 8.365374 69.8045 8.679749 1.922094 5.102199 2.354764 70.49821 8.931931 1.552699 5.239545 8.317714 70.79719 6.641113 1.929889 5.723788 8.575553 69.88544 8.198668 3.653441 9.350161 3.273941 73.08755 6.038356 2.928787 5.543029 7.864101 69.91575 2.558409 8.526237 6.059907 3.567235 69.97072 6.301923 1.957049 6.886124 3.146229 69.91094 … … … … …

[0100] Table 2 shows examples of the absolute error results between the lowest actual temperature and the predicted temperature under the same coordinates.

[0101] Table 2

[0102]

[0103]

[0104] The LOSS value variation curve of this embodiment is shown below. Fig. 4 As shown in the figure, the comparison results between the predicted and actual temperature values ​​of 1000 test sets are as follows: Fig. 5 As shown, the error results between the predicted and actual temperature values ​​after 250 training iterations are as follows: Fig. 6 As shown, the goal has been achieved.

[0105] The above description is only a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A chip heat dissipation layout optimization method based on an improved Transformer model, characterized in that: Includes the following steps: S1. Dataset preparation: Generate N sets of chip coordinate combinations that meet the chip layout requirements. Each set has two coordinates: (x1, y1) and (x2, y2). Simulate to obtain the highest board temperature z corresponding to each set of coordinate combinations. S2. Perform dataset preprocessing, and calculate the Euclidean distance d, angle r, and coordinate difference Δ between the two chips in the coordinate combination. s We obtain N preprocessed datasets, where the preprocessed data is: ((x1,y1,x2,y2,d,r,Δ) s ),z); S3. Construct an improved Transformer network model by adding a spatial distance attenuation factor and modifying the weights of multi-head attention to focus on regions with high thermal interference temperatures when chips are close together. Add a nonlinear feature enhancement layer after the feedforward layer of the Transformer network model to highlight the relationship between temperature and chip coordinates. The nonlinear feature enhancement module includes, in sequence, an input feature encoding module, a multi-scale spatial enhancement module, a nonlinear activation association module, a spatial feature and temperature feature cross-coupling module, and an output feature encoding module. The input feature of the nonlinear feature enhancement module is the feature vector output by the feedforward layer, which includes chip coordinates, temperature, and self-attention weighted information. Configure the hyperparameters of the improved Transformer network model. S4. Divide the dataset into training set, test set and validation set, and input them into the improved Transformer network model for training; S5. Use the loss function to evaluate the model. Once the evaluation is successful, the trained model is obtained. S6. Use the trained model to predict the maximum temperature under different chip layouts.

2. The chip heat dissipation layout optimization method based on an improved Transformer model according to claim 1, characterized in that: In step S3, the nonlinear feature enhancement module performs deep cross-combination and nonlinear information mining on the spatial characteristics of the chip layout to obtain continuous value features. After the splicing layer splices the features, they are sent to the fully connected layer MLP module for combined prediction tasks. By mining the spatial regularity information of the structured list data in the dataset, the highest temperature value corresponding to different chip layouts is predicted.

3. The chip heat dissipation layout optimization method based on an improved Transformer model according to claim 1, characterized in that: In step S3, the spatial distance attenuation factor f(d) is: Where f(d) represents the degree of temperature attenuation caused by the distance between the two chips, and f(d) is a coefficient with a value range of (0, 1]; α is the learning attenuation coefficient, which controls the speed of distance attenuation and adapts to different chip layout characteristics.

4. The chip heat dissipation layout optimization method based on an improved Transformer model according to claim 3, characterized in that: When the chips in the chipset are close together, d approaches 0, then f(d) approaches 1, indicating a high thermal coupling effect and the strongest temperature interaction. When the chip is furthest away, f(d) approaches 0, indicating that the thermal coupling effect is low and the temperature interaction is weakest.

5. The chip heat dissipation layout optimization method based on an improved Transformer model according to claim 1, characterized in that: In step S3, the input feature encoding module performs relative relation transformation and feature separation processing on the input feature vector information: for the input features ((x1,y1,x2,y2,d,r,Δ...)... s Feature separation is performed using z), resulting in location features and temperature features; The multi-scale spatial enhancement module includes a small-scale branch, a large-scale branch, and a gated attention fusion layer connected to both the small-scale branch and the large-scale branch. The small-scale branch convolution mines the thermal relationships of local regions at a single chip location, the large-scale branch mines the global temperature and thermal relationships between chips at long distances, and the gated attention fusion layer performs weighted fusion. The nonlinear activation association module performs nonlinear activation and spatial relationship mapping to simulate the nonlinear decay law of temperature changing with distance, and strengthens the exponential decay nonlinear transformation calculation for relative distance features. The spatial and temperature feature cross-coupling module takes the chip coordinate difference as input and uses a multi-layer perceptron (MLP) to calculate the spatial correlation matrix of the thermal influence between the two chips, thereby mining and capturing the coordinate cross-relationship. The output feature encoding module directly uses the enhanced feature encoding for structured spatial relationship features in reverse reasoning and forward prediction. The output features include local relationships, global relationships, and nonlinear mapping relationships.

6. The chip heat dissipation layout optimization method based on an improved Transformer model according to claim 5, characterized in that: The small-scale branch is a 3×3 convolution kernel, and the large-scale branch is a 5×5 convolution kernel; The thermal influence weight value calculated by the cross-coupling module of spatial and temperature characteristics is: oh 热 =σ(W·[Δ x ,D y ,D x ·D y ,|D x -D y |]+b); Where σ is the sigmoid activation, W is the model weight, b is the bias, Δx is the x-axis coordinate difference between chipsets, and Δy is the y-axis coordinate difference between chipsets. The local relationship is the relative position of the chip and its neighboring chips, and the weight of temperature influence. The global relationship is the feature global pooling of the large-scale branch through the multi-scale spatial enhancement module. The features of the nonlinear mapping relationship include nonlinear function parameters that convert coordinate differences into temperature influence, which can support the conversion of temperature influence into coordinate differences for reverse reasoning.

7. The chip heat dissipation layout optimization method based on an improved Transformer model according to claim 1, characterized in that: In step S1, N sets of chip coordinate combinations are generated using Matlab software, and the highest plate temperature z corresponding to each set of coordinate combinations is obtained using finite element simulation software.

8. The chip heat dissipation layout optimization method based on an improved Transformer model according to claim 1, characterized in that: In step S2, Δ s =(x1-x2,y1-y2)。 9. The chip heat dissipation layout optimization method based on an improved Transformer model according to claim 1, characterized in that: Step S2 also includes cleaning the preprocessed training set dataset. The data cleaning method is as follows: distinguishing numerical data, normalizing different numerical features, defining and dividing input features and target fields, using pandas to read input data into a dataframe for data cleaning, and removing invalid data examples from the first row.

10. The chip heat dissipation layout optimization method based on an improved Transformer model according to claim 1, characterized in that: In step S5, the Adam optimizer is used to update the model parameters.

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