A method for manufacturing a silicon nanowire

Abstract

The application relates to a silicon nanowire manufacturing method and belongs to the technical field of MEMS. The steps comprise the following: S1, providing an SOI substrate; S2, forming a mask layer on the SOI substrate; S3, patterning the mask layer to form an etching window; S4, performing isotropic etching on the SOI substrate through the etching window to form a cavity and a silicon nanocolumn; S5, oxidizing the silicon nanocolumn to form an oxide layer and a silicon nanowire; and S6, removing the buried oxygen layer and the oxide layer to obtain a suspended silicon nanowire. The application solves the problems of the prior art, such as complex preparation method of the silicon nanowire, high requirement for equipment and poor batch consistency.

Description

TECHNICAL FIELD

[0001] The application relates to a silicon nanowire manufacturing method and belongs to the technical field of MEMS. BACKGROUND

[0002] The silicon nanowire has excellent semiconductor characteristics and unique effects under nanometer scale, and thus has significant application value in the fields of nanoelectronics, biosensors and energy storage, and controllable preparation technology thereof is a core bottleneck for industrialization in the related fields. Current silicon nanowire preparation methods are divided into two categories: a top-down method and a bottom-up method, and both have the problems of complex process and poor controllability.

[0003] 1. The top-down method: a photolithography-etching method depends on expensive and precise equipment (such as a silicon nanowire manufacturing method disclosed in Chinese patent document CN106783618A, which needs to use a high-precision electron beam lithography machine), the process is long, and the nanowire diameter and sidewall roughness are difficult to control; a metal-assisted chemical etching method (MACE) has low equipment requirements, but the distribution of metal particles and the etching rate are easily disturbed, resulting in uneven nanowire size and high defect rate.

[0004] 2. The bottom-up method: a chemical vapor deposition method (CVD) needs high temperature, high vacuum and toxic silicon source, and has high process risk and uncontrollable nanowire growth direction; a thermal evaporation method depends on an ultrahigh vacuum environment, and the nanowire diameter and length distribution are wide, and the nanowire is easy to agglomerate and difficult to be directly used for device integration.

[0005] In summary, the existing silicon nanowire preparation technology generally has the problems of low-cost mass production, difficult structure parameter control and difficulty in compatibility with mature manufacturing systems, and therefore, a simple process and parameter controllable silicon nanowire manufacturing method is urgently needed to break through the limitations of the existing technology. SUMMARY

[0006] In view of the deficiencies of the prior art, the application provides a silicon nanowire manufacturing method to solve the problems of complex preparation method, high equipment requirement and poor batch consistency of the silicon nanowire in the prior art.

[0007] The technical scheme of the application is as follows:

[0008] A silicon nanowire manufacturing method has the following steps:

[0009] S1. Providing an SOI substrate;

[0010] S2. Forming a mask layer on the SOI substrate;

[0011] S3. Patternizing the mask layer to form an etching window;

[0012] S4, isotropically etching the SOI substrate through the etching windows to form cavities and silicon nanorods;

[0013] S5, performing thermal oxidation on the silicon nanorods to form an oxide layer and silicon nanowires; a high-temperature and wet-oxygen thermal oxidation scheme is adopted, and since under microscale, when the buried oxygen layer grows to a limit thickness, the oxygen diffusion to the silicon-buried oxygen layer interface is hindered, and the further oxidation reaction cannot be carried out, thus the oxidation reaction is'self-stopped', and the silicon nanowires are formed in the interior of the silicon nanorods.

[0014] S6, removing the oxide layer and part of the buried oxygen layer to obtain the suspended silicon nanowires.

[0015] According to the application, preferably, in step S1, the SOI substrate comprises substrate silicon, a buried oxygen layer and top layer silicon from bottom to top.

[0016] According to the application, further preferably, the substrate silicon and the top layer silicon are P-type doped silicon wafers, the buried oxygen layer is silicon dioxide, and the thickness of the top layer silicon is 500 nm.

[0017] According to the application, preferably, in step S2, a mask layer is formed on the top layer silicon, and the material of the mask layer is silicon nitride with a thickness of 100-500 nm.

[0018] According to the application, further preferably, the silicon nitride is formed by an LPCVD method.

[0019] According to the application, preferably, in step S3, specifically:

[0020] S3-1, coating photoresist on the mask layer;

[0021] S3-2, based on a prefabricated photoetching plate, exposing and developing the photoresist by a photoetching process to obtain a window pattern;

[0022] S3-3, patterning the mask layer by an etching process to transfer the window pattern on the photoresist to the mask layer to obtain etching windows;

[0023] S3-4, removing the photoresist.

[0024] According to the application, further preferably, in step S3-3, the etching process adopted is RIE;

[0025] The etching windows are rectangular windows arranged at equal intervals, and the number is at least two.

[0026] According to the application, further preferably, the interval between the etching windows is about 2 times the thickness of the top layer silicon.

[0027] According to the application, preferably, in step S4, isotropic etching technology of XeF2 is used to etch the top layer of silicon, which uses the pure chemical reaction between XeF2 gas and silicon material to realize the 'hollowing' etching from the surface window to the inside of silicon, and has good material selectivity and low process cost. When the isotropic etching of XeF2 is performed, a pulse process (for example, XeF2 gas is introduced for 10 s, and vacuum is pumped for 5 s in a cycle) is used to avoid excessive etching caused by too high local XeF2 concentration, and the formed silicon nanocolumn is located on the upper side of the buried oxygen layer and has no contact with the mask layer.

[0028] According to the application, preferably, the characteristic size of the silicon nanocolumn is 200-500 nm.

[0029] According to the application, preferably, in step S6, the buried oxygen layer and the oxide layer are removed by a wet etching method, and a BOE solution is used as the etching solution.

[0030] A method for manufacturing a silicon nanowire, comprising the following steps:

[0031] Steps S1-S3 are as shown above, and no additional improvement is made;

[0032] S4, isotropic etching technology of XeF2 is used to etch the top layer of silicon through the etching window, to form a cavity and a silicon thin wall, and the silicon thin wall is located between the buried oxygen layer and the mask layer;

[0033] S5, the silicon thin wall is subjected to thermal oxidation to obtain a silicon nanowire close to the mask layer and an oxide layer wrapping the silicon nanowire;

[0034] S6, the oxide layer is removed to obtain a silicon nanowire attached to the lower surface of the mask layer.

[0035] The application has the following advantages:

[0036] The method for manufacturing a silicon nanowire of the application is based on the isotropic etching technology of silicon, has no substrate crystal direction limitation, and uses the standard MEMS process, so that high-precision photolithography equipment is not needed, and the method has the advantages of simple process, controllable parameters, batch processing, etc. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 The figure is a flowchart of the application;

[0038] Figure 2 The figure is a schematic diagram of the substrate structure of the application;

[0039] Figure 3 The figure is a schematic diagram of the mask layer preparation of the application;

[0040] Figure 4 The figure is a schematic diagram of the etching window formation of the application;

[0041] Figure 5 This is a schematic diagram of the product structure in step S4 of Embodiment 1 of the present invention;

[0042] Figure 6 This is a schematic diagram of the product structure in step S5 of Embodiment 1 of the present invention;

[0043] Figure 7 This is a schematic diagram of the product structure in step S6 of Embodiment 1 of the present invention;

[0044] Figure 8 This is a schematic diagram of the product structure in step S4 of embodiment 2 of the present invention;

[0045] Figure 9 This is a schematic diagram of the product structure in step S5 of embodiment 2 of the present invention;

[0046] Figure 10 This is a schematic diagram of the product structure for step S6 of embodiment 2 of the present invention;

[0047] Among them: 1. SOI substrate; 2. Mask layer;

[0048] 11. Substrate silicon; 12. Buried oxide layer; 13. Top silicon layer;

[0049] 131. Cavity; 132. Silicon nanopillar; 133. Silicon thin-walled structure;

[0050] 1321, Oxide layer; 1322, Silicon nanowires;

[0051] 21. Corrosion window. Detailed Implementation

[0052] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.

[0053] Example 1:

[0054] like Figures 1-7 As shown, this embodiment provides a method for fabricating silicon nanowires, the steps of which are as follows:

[0055] S1. Provide an SOI substrate 1, such as Figure 2 As shown, the SOI substrate, from bottom to top, includes substrate silicon 11, buried oxide layer 12, and top silicon layer 13. Substrate silicon 11 and top silicon layer 13 are P-type doped silicon wafers, buried oxide layer 12 is silicon dioxide, and the thickness of top silicon layer 13 is 500 nm. It should be understood that the P-type doped silicon wafer and 500 nm here are only examples and not limitations; in fact, other thicknesses and doping types, or intrinsic silicon wafers, are also applicable.

[0056] S2. Form a mask layer 2 on the SOI substrate 1, such as Figure 3As shown, a mask layer 2 is formed on the top layer of silicon 13, the material of the mask layer 2 is silicon nitride, which is formed by the LPCVD method, and the thickness is 100-500 nm. It should be understood that the silicon nitride and its thickness here are only examples and are not limited. In this embodiment, since part of the top layer of silicon 13 is removed by the method of isotropic etching later, and the buried oxide layer is removed by the method of wet etching, the material of the mask layer 2 does not react with the above-mentioned methods;

[0057] S3, the mask layer 2 is patterned to form an etching window 21, as shown in Figure 4 Specifically, as shown in

[0058] S3-1, photoresist is coated on the mask layer 2;

[0059] S3-2, based on the pre-prepared photoetching plate, the photoresist is exposed and developed by the photoetching process to obtain a window pattern;

[0060] S3-3, the mask layer is patterned by the RIE process to transfer the window pattern on the photoresist to the mask layer to obtain the etching window 21, the etching window is a rectangular window arranged at equal intervals, the number is 4. It should be understood that in the subsequent operation, a silicon nanowire will be formed between every two etching windows 21. Therefore, the number of etching windows 21 can be set as needed, and the interval between the etching windows is 2 times the thickness of the top layer of silicon. It should be understood that the interval is a key parameter for forming the silicon nanowire, which is designed by considering both theory and experimental results. In this embodiment, the interval is 1.2 μm;

[0061] S3-4, the photoresist is removed;

[0062] S4, isotropic etching is performed on the SOI substrate through the etching window 21 to form a cavity 131 and a silicon nanocolumn 132, as shown in Figure 5 ;

[0063] XeF2 isotropic etching technology is used to etch the top layer of silicon. This technology uses the pure chemical reaction between XeF2 gas and silicon material to perform "hollowing" etching from the surface window to the inside of the silicon, and has good material selectivity and low process cost. Since the etching rate of the top layer of silicon 13 is the same in all directions, the cross-sectional shape of the cavity 131 under a single etching window 21 is "semi-circular" or "bowl-shaped". By size setting and process control, a silicon nanocolumn 132 can be formed near the buried oxide layer 12. When XeF2 isotropic etching is performed, a pulse process (for example, XeF2 gas is introduced for 10 s, and vacuum is pumped for 5 s in a cycle) is used to avoid excessive etching caused by too high local XeF2 concentration. The formed silicon nanocolumn is located on the upper side of the buried oxide layer and does not contact the mask layer. The characteristic size of the silicon nanocolumn is 200-500 nm;

[0064] S5. Thermally oxidize the silicon nanopillars 132 to form an oxide layer 1321 and silicon nanowires 1322, such as Figure 6 As shown, a high-temperature, moist oxygen thermal oxidation scheme is used. At the microscale, when the buried oxide layer grows to its limit thickness, it will hinder the diffusion of oxygen to the silicon-buried oxide layer interface, causing further oxidation reactions to be unable to proceed. Therefore, the oxidation reaction will "self-stop," and silicon nanowires will be formed inside the silicon nanopillars. The thermal oxidation scheme is only an example and not a limitation. Since the limit thickness of the buried oxide layer is affected by the oxidation temperature and oxidation atmosphere, a low-temperature, dry oxygen thermal oxidation scheme can be used when the feature size of the silicon nanopillars is small or the feature size of the target silicon nanowires is large.

[0065] S6. The oxide layer 1321 and part of the buried oxide layer 12 are removed by wet etching using a BOE solution to obtain suspended silicon nanowires, such as... Figure 7 As shown.

[0066] Example 2:

[0067] This embodiment provides a method for fabricating silicon nanowires, the steps of which are as follows:

[0068] Steps S1-S3 are as shown in Example 1;

[0069] S4. Using XeF2 isotropic etching technology, the top silicon 13 is etched through an etching window. Compared to Example 1, this shortens the etching time and forms a cavity 131 and a silicon thin wall 133. The silicon thin wall 133 is located between the buried oxide layer and the mask layer. Figure 8 As shown; the feature size of silicon thin-walled 133 is 200~500nm;

[0070] S5. Oxidize the silicon thin-walled layer 133 to obtain silicon nanowires 1322 close to the mask layer and an oxide layer encapsulating the silicon nanowires, as shown below. Figure 9 As shown;

[0071] S6. Remove the oxide layer to obtain silicon nanowires attached to the lower surface of the mask layer, such as... Figure 10 As shown.

[0072] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating silicon nanowires, characterized in that, The steps are as follows: S1. Provide an SOI substrate, the SOI substrate comprising, from bottom to top, a substrate silicon, a buried oxide layer and a top silicon layer; S2. Form a mask layer on the SOI substrate; S3, a patterned mask layer, forming an etch window; S4. Through the etching window, the top silicon layer is etched using XeF2 isotropic etching technology to form cavities and silicon nanopillars. When performing XeF2 isotropic etching, a pulsed process is used. The formed silicon nanopillars are located on the upper side of the buried oxide layer and have no contact with the mask layer. S5. Thermal oxidation of silicon nanopillars to form an oxide layer and silicon nanowires; S6. Remove the oxide layer and part of the buried oxide layer to obtain suspended silicon nanowires.

2. The method for fabricating silicon nanowires as described in claim 1, characterized in that, The substrate silicon and the top silicon are P-type doped silicon wafers, the buried oxide layer is silicon dioxide, and the thickness of the top silicon is 500nm.

3. The method for fabricating silicon nanowires as described in claim 2, characterized in that, In step S2, a mask layer is formed on the top silicon layer. The mask layer is made of silicon nitride and has a thickness of 100~500nm.

4. The method for fabricating silicon nanowires as described in claim 3, characterized in that, In step S3, specifically: S3-1. Coat the mask layer with photoresist; S3-2. Based on the pre-made photomask, the photoresist is exposed and developed through photolithography to obtain a window pattern; S3-3. Pattern the mask layer through etching process, transfer the window pattern on the photoresist onto the mask layer, and obtain the etched window. S3-4, Remove photoresist.

5. The method for fabricating silicon nanowires as described in claim 4, characterized in that, In step S3-3, the etching process used is RIE; The erosion windows are rectangular windows arranged at equal intervals, and there are at least two of them.

6. The method for fabricating silicon nanowires as described in claim 5, characterized in that, The spacing between the etched windows is twice the thickness of the top silicon layer.

7. The method for fabricating silicon nanowires as described in claim 6, characterized in that, In step S6, the buried oxide layer and oxide layer are removed by wet etching, and the etching solution used is BOE solution.

8. A method for fabricating silicon nanowires, characterized in that, The steps are as follows: S1. Provide an SOI substrate, the SOI substrate comprising, from bottom to top, a substrate silicon, a buried oxide layer and a top silicon layer; S2. Form a mask layer on the SOI substrate; S3, a patterned mask layer, forming an etch window; S4. The top silicon layer is etched through the etching window using XeF2 isotropic etching technology to form cavities and silicon thin walls. The silicon thin walls are located between the buried oxide layer and the mask layer. S5. Oxidize the silicon thin-walled layer to obtain silicon nanowires close to the mask layer and an oxide layer encapsulating the silicon nanowires. S6. Remove the oxide layer to obtain silicon nanowires attached to the lower surface of the mask layer.

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