A method and apparatus for generating a sine signal and a cosine signal.

Abstract

This application provides a method and apparatus for generating sine and cosine signals. Based on trigonometric and angle formulas, it generates sine signals by pre-configured base values ​​and pipelined multiply-accumulate iterations to generate iterative values, thus avoiding the complex logic of DDS data cache management and Cordic multi-round iterative calculations. Furthermore, the m-stage pipelined multiply-accumulate module breaks down the logical combination of multiplication and addition operations in the multiply-accumulate operation into m clock cycles, thereby optimizing the FPGA's operating frequency. This embodiment relies only on common logic operations such as accumulation counting, data selection, and basic multiply-accumulate, eliminating the need for the large amount of BRAM required in the DDS scheme to store complete sine wave data. It also avoids the large-scale parallel iterative logic required by the Cordic scheme to ensure accuracy and throughput. In actual implementation, only a small number of LUT tables and DSP resources are needed, significantly reducing the FPGA's hardware resource consumption.

Description

Technical Field

[0001] This application relates to the field of FPGA technology, and more specifically, to a method and apparatus for generating sine signals and cosine signals. Background Technology

[0002] In modern mobile communication systems, frequency offset pre-compensation is often required for baseband signals entering the digital domain to correct frequency deviations introduced by analog devices such as crystal oscillators. Sine and cosine signal generators produce I_offset and Q_offset signals at specific frequencies based on externally configured frequencies. Traditional sine and cosine signal generators are implemented using direct digital synthesizers (DDS) or Cordic schemes.

[0003] In FPGA implementation, both approaches have their drawbacks. The DDS approach uses BRAM to store data from sin0 to sin2π. The higher the required precision and resolution, the larger the required BRAM block storage space. In mobile communication systems, resolutions as high as 1Hz are often needed, requiring a large number of BRAM blocks. The Cordic approach uses the Cordic iterative algorithm to generate sin and cos signals. However, calculating a sin or cos value that meets the system's precision requirements requires more than 10 iterations, and the throughput cannot meet the system requirements. The parallel Cordic implementation method requires a large amount of LUT table resources to simultaneously meet the system's precision and throughput requirements. Summary of the Invention

[0004] The purpose of this application is to provide a sine signal generation method, a cosine signal generation method, and an apparatus to solve the technical problem that existing sine and cosine signal generators consume a large amount of LUT table resources and BRAM resources.

[0005] This application provides a method for generating a sinusoidal signal, comprising:

[0006] Obtain m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], and m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and fix the rotation step size sin(mθ) and cos(mθ). Configure the m fundamental sine values ​​and the m fundamental cosine values ​​in the selector, and configure sin(mθ) and cos(mθ) in the multiply-accumulate operation module; where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1.

[0007] After receiving the start signal pulse, the counter starts from 0 and increments clock cycle by clock cycle to m and then remains constant;

[0008] When the output of the counter is from 0 to m-1, the selector selects a sinusoidal base value that corresponds one-to-one with the output of the counter, and uses this sinusoidal base value as the final output of the sinusoidal signal after a delay of m clock cycles.

[0009] When the output of the counter is m, the corresponding value in the selector is input into the multiply-accumulate operation module for m-stage pipelined calculation to obtain the sine iteration value; the sine iteration value is configured into the selector; after a delay of m clock cycles, the selector outputs the sine iteration value as the final sine signal after a delay of m clock cycles.

[0010] In the above technical solution, based on trigonometric and angle formulas, a sine signal is generated by pre-configured basic values ​​and pipelined multiply-accumulate iterations, avoiding the complex logic of DDS data cache management and Cordic multi-round iterative calculations. Furthermore, the m-stage pipelined multiply-accumulate module breaks down the logical combination of multiplication and addition operations in the multiply-accumulate operation into m clock cycles, thereby optimizing the FPGA's operating frequency. This embodiment only relies on common logic operations such as accumulation counting, data selection, and basic multiply-accumulate, eliminating the need for the large amount of BRAM required to store the complete sine wave data in the DDS solution. It also avoids the large-scale parallel iterative logic (and corresponding large LUT resources) required by the Cordic solution to ensure accuracy and throughput. In actual implementation, only a small number of LUT tables and DSP resources are needed, significantly reducing the FPGA's hardware resource consumption.

[0011] In some optional implementations, obtaining m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and fixing the rotation step sizes sin(mθ) and cos(mθ) includes:

[0012] Configure the valid signals of sin(θ), cos(θ), sin(r), and cos(r) and their parameters into the preprocessing module;

[0013] The preprocessing module generates the m fundamental sine values, m fundamental cosine values, sin(mθ), and cos(mθ) in a serial manner based on sin(θ), cos(θ), sin(r), and cos(r).

[0014] In the above technical solution, the basic values ​​required for generating the sinusoidal signal are generated by the preprocessing module. Specifically, the effective signal of the parameter determines the effective window of sin(θ), cos(θ), sin(r), and cos(r). Based on sin(θ), cos(θ), sin(r), and cos(r), the preprocessing module generates m basic sine values ​​sequentially in a serial manner, generates m basic cosine values ​​sequentially in a serial manner, and iteratively generates sin(mθ) and cos(mθ) in a serial manner. This preprocessing stage does not require parallel computing units and can complete the generation of all basic values ​​only through serial iteration in time, avoiding the additional resource consumption caused by parallel processing.

[0015] In some optional implementations, after configuring sin(θ), cos(θ), sin(r), and cos(r) and the valid parameter signals into the preprocessing module, the method further includes:

[0016] The preprocessing module generates a start signal to the counter after a certain delay.

[0017] In the above technical solution, after sin(θ), cos(θ), sin(r), and cos(r) and the parameter valid signals are configured into the preprocessing module, the preprocessing module serially generates m sine fundamental values, m cosine fundamental values, sin(mθ), and cos(mθ), and configures these values ​​into the selector or multiply-accumulate operation module. After the configuration is completed, the preprocessing module generates a start signal to the counter to trigger the counter to start working.

[0018] In some optional implementations, the preprocessing module generates the m fundamental sine values ​​using the following formula:

[0019] sin(r+nθ)=sin[r+(n-1)θ+θ]=sin[r+(n-1)θ]cos(θ)+cos[r+(n-1)θ]sin(θ);

[0020] The preprocessing module generates the m fundamental cosine values ​​using the following formula:

[0021] cos(r+nθ)= cos [r+(n-1)θ+θ]= cos [r+(n-1)θ]cos(θ)-sin[r+(n-1)θ]sin(θ);

[0022] The preprocessing module generates sin(mθ) using the following formula:

[0023] sin(mθ)=sin[(m-1)θ+θ]=sin[(m-1)θ]cos(θ)+cos[(m-1)θ]sin(θ);

[0024] The preprocessing module generates cos(mθ) using the following formula:

[0025] cos(mθ)=cos[(m-1)θ+θ]=cos[(m-1)θ]cos(θ)-sin[(m-1)θ]sin(θ);

[0026] Where n is time, and 0 ≤ n ≤ m-1.

[0027] In some optional implementations, the multiply-accumulate module performs m-stage pipelined calculations using the following formula to obtain the sine iteration value:

[0028] sin(r+nθ)=sin[r+(nm)θ+mθ]=sin[r+(nm)θ]cos(mθ)+cos[r+(nm)θ]sin(mθ);

[0029] Where n is time, and m ≤ n.

[0030] In the above technical solution, the formula used by the multiply-accumulate operation module cannot have a negative value nm, meaning the minimum value of time n is m. At this time, the corresponding sine iteration value calculated by the multiply-accumulate operation module is sin(r+mθ). Before this timing, the multiply-accumulate operation module cannot be used to calculate the output value. However, the selector is pre-configured with the required basic sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ] for 0≤n≤m-1. The selector only needs to select the corresponding basic sine value for output at the corresponding timing.

[0031] This application provides a method for generating a cosine signal, comprising:

[0032] Obtain m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], and m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and fix the rotation step size sin(mθ) and cos(mθ). Configure the m fundamental sine values ​​and the m fundamental cosine values ​​in the selector, and configure sin(mθ) and cos(mθ) in the multiply-accumulate operation module; where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1.

[0033] After receiving the start signal pulse, the counter starts from 0 and increments clock cycle by clock cycle to m and then remains constant;

[0034] When the output of the counter is from 0 to m-1, the selector selects a cosine base value that corresponds one-to-one with the output of the counter, and uses this cosine base value as the final output of the cosine signal after a delay of m clock cycles.

[0035] When the output of the counter is m, the corresponding value in the selector is input into the multiply-accumulate operation module for m-stage pipelined calculation to obtain the cosine iteration value; the cosine iteration value is configured into the selector; after a delay of m clock cycles, the selector outputs the cosine iteration value as the final cosine signal after a delay of m clock cycles.

[0036] In the above technical solution, based on trigonometric and angle formulas, a cosine signal is generated by pre-configured basic values ​​and pipelined multiply-accumulate iterations, avoiding the complex logic of DDS data cache management and Cordic multi-round iterative calculations. Furthermore, the m-stage pipelined multiply-accumulate module breaks down the logical combination of multiplication and addition operations in the multiply-accumulate operation into m clock cycles, thereby optimizing the FPGA's operating frequency. This embodiment only relies on common logic operations such as accumulation counting, data selection, and basic multiply-accumulate, eliminating the need for the large amount of BRAM required to store the complete cosine wave data in the DDS solution. It also avoids the large-scale parallel iterative logic (and corresponding large LUT resources) required by the Cordic solution to ensure accuracy and throughput. In actual implementation, only a small number of LUT tables and DSP resources are needed, significantly reducing the FPGA's hardware resource consumption.

[0037] In some optional implementations, obtaining m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and fixing the rotation step sizes sin(mθ) and cos(mθ) includes:

[0038] Configure the valid signals of sin(θ), cos(θ), sin(r), and cos(r) and their parameters into the preprocessing module;

[0039] The preprocessing module generates the m fundamental sine values, m fundamental cosine values, sin(mθ), and cos(mθ) in a serial manner based on sin(θ), cos(θ), sin(r), and cos(r).

[0040] In the above technical solution, the basic values ​​required for generating the cosine signal are generated by the preprocessing module. Specifically, the effective signal of the parameter determines the effective window of sin(θ), cos(θ), sin(r), and cos(r). Based on sin(θ), cos(θ), sin(r), and cos(r), the preprocessing module generates m basic sine values ​​sequentially in a serial manner, generates m basic cosine values ​​sequentially in a serial manner, and iteratively generates sin(mθ) and cos(mθ) in a serial manner. This preprocessing stage does not require parallel computing units and can complete the generation of all basic values ​​only through serial iteration in time, avoiding the additional resource consumption caused by parallel processing.

[0041] In some optional implementations, after configuring sin(θ), cos(θ), sin(r), and cos(r) and the valid parameter signals into the preprocessing module, the method further includes:

[0042] The preprocessing module generates a start signal to the counter after a certain delay.

[0043] In the above technical solution, after sin(θ), cos(θ), sin(r), and cos(r) and the parameter valid signals are configured into the preprocessing module, the preprocessing module serially generates m sine fundamental values, m cosine fundamental values, cos(mθ), and sin(mθ), and configures these values ​​into the selector or multiply-accumulate operation module. After the configuration is completed, the preprocessing module generates a start signal to the counter to trigger the counter to start working.

[0044] In some optional implementations, the preprocessing module generates the m fundamental sine values ​​using the following formula:

[0045] sin(r+nθ)=sin[r+(n-1)θ+θ]=sin[r+(n-1)θ]cos(θ)+cos[r+(n-1)θ]sin(θ);

[0046] The preprocessing module generates the m fundamental cosine values ​​using the following formula:

[0047] cos(r+nθ)= cos [r+(n-1)θ+θ]= cos [r+(n-1)θ]cos(θ)-sin[r+(n-1)θ]sin(θ);

[0048] The preprocessing module generates sin(mθ) using the following formula:

[0049] sin(mθ)=sin[(m-1)θ+θ]=sin[(m-1)θ]cos(θ)+cos[(m-1)θ]sin(θ);

[0050] The preprocessing module generates cos(mθ) using the following formula:

[0051] cos(mθ)=cos[(m-1)θ+θ]=cos[(m-1)θ]cos(θ)-sin[(m-1)θ]sin(θ);

[0052] Where n is time, and 0 ≤ n ≤ m-1.

[0053] In some optional implementations, the multiply-accumulate module performs m-stage pipelined calculations using the following formula to obtain the cosine iteration value:

[0054] cos(r+nθ)=cos[r+(nm)θ+mθ]=cos[r+(nm)θ]cos(mθ)-sin[r+(nm)θ]sin(mθ);

[0055] Where n is time, and m ≤ n.

[0056] In the above technical solution, the formula used by the multiply-accumulate module cannot have a negative value nm, meaning the minimum value of time n is m. At this time, the corresponding cosine iteration value calculated by the multiply-accumulate module is cos(r+mθ). Before this timing, the multiply-accumulate module cannot be used to calculate the output value. However, the selector is pre-configured with the required cosine base values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ] for 0≤n≤m-1. The selector only needs to select the corresponding cosine base value for output at the corresponding timing.

[0057] This application provides a sinusoidal signal generating device, comprising:

[0058] The preprocessing module is used to: acquire m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and sin(mθ) and cos(mθ), and configure the m fundamental sine values ​​and the m fundamental cosine values ​​into a selector, and configure sin(mθ) and cos(mθ) into a multiply-accumulate operation module; where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1;

[0059] A counter, used to: upon receiving a start signal pulse, increment the counter from 0 clock cycles to m and then keep it constant;

[0060] The selector is used to: when the output of the counter is 0 to m-1, select a sinusoidal base value that corresponds one-to-one with the output of the counter, and use the sinusoidal base value as the final output of the sinusoidal signal after a delay of m clock cycles;

[0061] The multiply-accumulate operation module is used to: when the output of the counter is m, input the corresponding value in the selector into the multiply-accumulate operation module to perform m-stage pipelined calculations to obtain a sine iteration value; configure the sine iteration value into the selector; and the selector outputs the sine iteration value as the final sine signal after a delay of m clock cycles.

[0062] This application provides a cosine signal generating device, comprising:

[0063] The preprocessing module is used to: acquire m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and sin(mθ) and cos(mθ), and configure the m fundamental sine values ​​and the m fundamental cosine values ​​into a selector, and configure sin(mθ) and cos(mθ) into a multiply-accumulate operation module; where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1;

[0064] A counter, used to: upon receiving a start signal pulse, increment the counter from 0 clock cycles to m and then keep it constant;

[0065] The selector is used to: when the output of the counter is 0 to m-1, select a cosine base value that corresponds one-to-one with the output of the counter, and use the cosine base value as the final output of the cosine signal after a delay of m clock cycles;

[0066] The multiply-accumulate operation module is used to: when the output of the counter is m, input the corresponding value in the selector into the multiply-accumulate operation module to perform m-stage pipelined calculations to obtain a cosine iteration value; configure the cosine iteration value into the selector; and the selector outputs the cosine iteration value as the final cosine signal after a delay of m clock cycles. Attached Figure Description

[0067] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0068] Figure 1 A flowchart illustrating the steps of a sine wave signal generation method provided in this application embodiment;

[0069] Figure 2 A flowchart illustrating the steps of a cosine signal generation method provided in this application embodiment;

[0070] Figure 3 A flowchart illustrating the steps of a method for generating sine and cosine signals provided in this application embodiment;

[0071] Figure 4 This is a schematic diagram of the timing of sine and cosine signal generation provided in an embodiment of this application. Detailed Implementation

[0072] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.

[0073] Please refer to Figure 1 , Figure 1 A flowchart of a method for generating a sinusoidal signal provided in this application embodiment includes:

[0074] Step S1: Obtain m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], and m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ]. Fix the rotation step size sin(mθ) and cos(mθ), and configure the m fundamental sine and m fundamental cosine values ​​into the selector, and configure sin(mθ) and cos(mθ) into the multiply-accumulate operation module; where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1.

[0075] The selector's ports 0 to m-1 are configured with sin(r) and cos(r), sin(r+θ) and cos(r+θ), sin(r+2θ) and cos(r+2θ), sin(r+3θ) and cos(r+3θ), ..., sin[r+(m-1)θ] and cos[r+(m-1)θ], respectively. The selector's else port is configured with the sine and cosine iteration values ​​calculated by the multiply-accumulate module. The selector can be a multiplexer or a multiplexer, etc.

[0076] Step S2: After receiving the start signal pulse, the counter starts from 0 and increments clock cycle by clock cycle to m and then remains constant;

[0077] Step S3: When the output of the counter is 0 to m-1, the selector selects the sine base value that corresponds one-to-one with the output of the counter, and uses the sine base value as the final output of the sine signal after a delay of m clock cycles.

[0078] The delay of m clock cycles is achieved through synchronization using a counter, eliminating the need for additional delay units.

[0079] Step S4: When the counter output is m, input the corresponding value in the selector into the multiply-accumulate operation module for m-stage pipelined calculation to obtain the sine iteration value; configure the sine iteration value into the selector; after a delay of m clock cycles, the selector uses the sine iteration value as the final output of the sine signal after a delay of m clock cycles.

[0080] The corresponding values ​​in the selector may be the sine base value and the cosine base value, or they may be the sine iteration value and the cosine iteration value.

[0081] An m-stage pipeline breaks down multiply-accumulate operations into m clock cycles for sequential completion, optimizing FPGA timing and resource utilization. The following is a detailed explanation:

[0082] Pipelining is a technique that breaks down a task into multiple stages for parallel processing. Ideally, each stage performs a single multiplication or addition operation. In FPGAs, pipelining can increase operating frequency, as each stage only needs to complete a portion of the computation, shortening the critical path and allowing for higher clock frequencies. For example, for sin[r+(nm)θ]×cos(mθ)+cos[r+(nm)θ]×sin(mθ), the pipeline breakdown is as follows: the multiplication and addition operation is broken down into m steps, with each clock cycle completing a portion of the computation. For example, if m=4, then: Stage 1: Calculate part of the multiplication (e.g., multiplying the higher digits); Stage 2: Calculate the other part of the multiplication (e.g., multiplying the lower digits); Stage 3: Accumulate the multiplication results; Stage 4: Perform the final addition and output the result.

[0083] In this embodiment, a sine signal is generated based on trigonometric and angle formulas. It is generated by pre-configured base values ​​and pipelined multiply-accumulate iterations, avoiding the complex logic of DDS data cache management and Cordic multi-round iterative calculations. Furthermore, the m-stage pipelined multiply-accumulate module breaks down the logical combination of multiplication and addition operations into m clock cycles, thereby optimizing the FPGA's operating frequency. This embodiment relies only on common logic operations such as accumulation counting, data selection, and basic multiply-accumulate, eliminating the need for the large amount of BRAM required to store complete sine wave data in the DDS solution. It also avoids the large-scale parallel iterative logic (and corresponding large LUT resources) required by the Cordic solution to ensure accuracy and throughput. In actual implementation, only a small number of LUT tables and DSP resources are needed, significantly reducing the FPGA's hardware resource consumption.

[0084] In some optional implementations, obtaining m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and fixing the rotation step sizes sin(mθ) and cos(mθ), includes:

[0085] Configure the valid signals of sin(θ), cos(θ), sin(r), and cos(r) and their parameters into the preprocessing module;

[0086] The preprocessing module generates m fundamental sine values, m fundamental cosine values, sin(mθ), and cos(mθ) in a serial manner based on sin(θ), cos(θ), sin(r), and cos(r).

[0087] The preprocessing module can be controlled by a state machine.

[0088] In the above technical solution, the basic values ​​required for generating the sinusoidal signal are generated by the preprocessing module. Specifically, the effective signal of the parameter determines the effective window of sin(θ), cos(θ), sin(r), and cos(r). Based on sin(θ), cos(θ), sin(r), and cos(r), the preprocessing module generates m basic sine values ​​sequentially in a serial manner, generates m basic cosine values ​​sequentially in a serial manner, and iteratively generates sin(mθ) and cos(mθ) in a serial manner. This preprocessing stage does not require parallel computing units and can complete the generation of all basic values ​​only through serial iteration in time, avoiding the additional resource consumption caused by parallel processing.

[0089] In some optional implementations, after configuring sin(θ), cos(θ), sin(r), and cos(r) and the valid signals of the parameters into the preprocessing module, the method further includes:

[0090] The preprocessing module generates a start signal to the counter after a certain delay.

[0091] In the above technical solution, after sin(θ), cos(θ), sin(r), and cos(r) and the parameter valid signals are configured into the preprocessing module, the preprocessing module serially generates m sine fundamental values, m cosine fundamental values, sin(mθ), and cos(mθ), and configures these values ​​into the selector or multiply-accumulate operation module. After the configuration is completed, the preprocessing module generates a start signal to the counter to trigger the counter to start working.

[0092] In some optional implementations, the preprocessing module generates m fundamental sine values ​​using the following formula:

[0093] sin(r+nθ)=sin[r+(n-1)θ+θ]=sin[r+(n-1)θ]cos(θ)+cos[r+(n-1)θ]sin(θ);

[0094] The preprocessing module generates m fundamental cosine values ​​using the following formula:

[0095] cos(r+nθ)= cos [r+(n-1)θ+θ]= cos [r+(n-1)θ]cos(θ)-sin[r+(n-1)θ]sin(θ);

[0096] The preprocessing module generates sin(mθ) using the following formula:

[0097] sin(mθ)=sin[(m-1)θ+θ]=sin[(m-1)θ]cos(θ)+cos[(m-1)θ]sin(θ);

[0098] The preprocessing module generates cos(mθ) using the following formula:

[0099] cos(mθ)=cos[(m-1)θ+θ]=cos[(m-1)θ]cos(θ)-sin[(m-1)θ]sin(θ);

[0100] Where n is time, and 0 ≤ n ≤ m-1.

[0101] In some optional implementations, the multiply-accumulate module performs m-stage pipelined calculations using the following formula to obtain the sine iteration value:

[0102] sin(r+nθ)=sin[r+(nm)θ+mθ]=sin[r+(nm)θ]cos(mθ)+cos[r+(nm)θ]sin(mθ);

[0103] Where n is time, and m ≤ n.

[0104] In the above technical solution, the formula used by the multiply-accumulate operation module cannot have a negative value nm, meaning the minimum value of time n is m. At this time, the corresponding sine iteration value calculated by the multiply-accumulate operation module is sin(r+mθ). Before this timing, the multiply-accumulate operation module cannot be used to calculate the output value. However, the selector is pre-configured with the required basic sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ] for 0≤n≤m-1. The selector only needs to select the corresponding basic sine value for output at the corresponding timing.

[0105] In one specific embodiment, assume m=2 and n is 0-4:

[0106] The selector is configured with the basic values ​​sin(r), sin(r+θ), cos(r), and cos(r+θ), and the multiply-accumulate module is configured with sin(2θ) and cos(2θ).

[0107] When the counter is 0, the selector selects the output sin(r) after 2 clock cycles.

[0108] When the counter is 1, the selector selects the output sin(r+θ) after 2 clock cycles.

[0109] When the counter is 2, the multiply-accumulate operation module calculates the iterative values ​​sin(r+2θ)=sin(r)cos(2θ)+cos(r)sin(2θ) and cos(r)=cos(r)cos(2θ) based on sin(2θ), cos(2θ) and the basic values ​​sin(r)cos(r). The module then configures sin(r+2θ) and cos(r+2θ) to the else port of the selector and determines the output sin(r+2θ) after 2 clock cycles.

[0110] When the counter is 3, the multiply-accumulate module calculates the iterative values ​​sin(r+3θ)=sin(r+θ)cos(2θ)+cos(r+θ)sin(2θ) and cos(r+θ)=cos(r+θ)cos(2θ)-sin(r+θ)sin(2θ) based on sin(2θ), cos(2θ) and the basic values ​​sin(r+θ)cos(2θ). The iterative values ​​cos(r+3θ)cos(2θ) are then configured to the else port of the selector, and the selector selects the output sin(r+3θ) after 2 clock cycles.

[0111] When the counter is 4, the multiply-accumulate module calculates the iterative values ​​sin(r+4θ) = sin(r+2θ)cos(2θ) + cos(r+2θ)sin(2θ) and cos(r+4θ) = cos(r+2θ)cos(2θ) - sin(r+2θ)sin(2θ) based on sin(2θ), cos(2θ) and the iterative values ​​cos(r+4θ) = cos(r+2θ)cos(2θ) - sin(r+2θ)sin(2θ) according to sin(2θ) and cos(r+4θ) according to cos(2θ) and cos(r+4θ) according to cos(2θ) and cos(r+4θ) according to cos(2θ) and cos(2θ) according to cos(r+ ...

[0112] Please refer to Figure 2 , Figure 2 A method for generating a cosine signal provided in this application includes:

[0113] Step S5: Obtain m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and fix the rotation step size sin(mθ) and cos(mθ). Configure the m fundamental sine values ​​and m fundamental cosine values ​​in the selector, and configure sin(mθ) and cos(mθ) in the multiply-accumulate operation module. Where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1.

[0114] Step S6: After receiving the start signal pulse, the counter starts from 0 and increments clock cycle by clock cycle until it reaches m and then remains constant;

[0115] Step S7: When the output of the counter is 0 to m-1, the selector selects the cosine base value that corresponds one-to-one with the output of the counter, and uses the cosine base value as the final output of the cosine signal after a delay of m clock cycles.

[0116] Step S8: When the counter output is m, the corresponding value in the selector is input into the multiply-accumulate operation module for m-stage pipelined calculation to obtain the cosine iteration value; the cosine iteration value is configured into the selector; after a delay of m clock cycles, the selector uses the cosine iteration value as the final output of the cosine signal after a delay of m clock cycles.

[0117] In this embodiment, the cosine signal is generated based on trigonometric and angle formulas. It is achieved through a pre-configured base value and pipelined multiply-accumulate iteration to generate iterative values, thus avoiding the complex logic of DDS data cache management and Cordic multi-round iterative calculations. Furthermore, the m-stage pipelined multiply-accumulate module breaks down the logical combination of multiplication and addition operations in the multiply-accumulate operation into m clock cycles, thereby optimizing the FPGA's operating frequency. This embodiment relies only on common logic operations such as accumulation counting, data selection, and basic multiply-accumulate, eliminating the need for the large amount of BRAM required to store the complete cosine wave data in the DDS solution. It also avoids the large-scale parallel iterative logic (and corresponding large LUT resources) required by the Cordic solution to ensure accuracy and throughput. In actual implementation, only a small number of LUT tables and DSP resources are needed, significantly reducing the FPGA's hardware resource consumption.

[0118] In some optional implementations, obtaining m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and fixing the rotation step sizes sin(mθ) and cos(mθ), includes:

[0119] Configure the valid signals of sin(θ), cos(θ), sin(r), and cos(r) and their parameters into the preprocessing module;

[0120] The preprocessing module generates m fundamental sine values, m fundamental cosine values, sin(mθ), and cos(mθ) in a serial manner based on sin(θ), cos(θ), sin(r), and cos(r).

[0121] In the above technical solution, the basic values ​​required for generating the cosine signal are generated by the preprocessing module. Specifically, the effective signal of the parameter determines the effective window of sin(θ), cos(θ), sin(r), and cos(r). Based on sin(θ), cos(θ), sin(r), and cos(r), the preprocessing module generates m basic sine values ​​sequentially in a serial manner, generates m basic cosine values ​​sequentially in a serial manner, and iteratively generates sin(mθ) and cos(mθ) in a serial manner. This preprocessing stage does not require parallel computing units and can complete the generation of all basic values ​​only through serial iteration in time, avoiding the additional resource consumption caused by parallel processing.

[0122] In some optional implementations, after configuring sin(θ), cos(θ), sin(r), and cos(r) and the valid signals of the parameters into the preprocessing module, the method further includes:

[0123] The preprocessing module generates a start signal to the counter after a certain delay.

[0124] In the above technical solution, after sin(θ), cos(θ), sin(r), and cos(r) and the parameter valid signals are configured into the preprocessing module, the preprocessing module serially generates m sine fundamental values, m cosine fundamental values, cos(mθ), and sin(mθ), and configures these values ​​into the selector or multiply-accumulate operation module. After the configuration is completed, the preprocessing module generates a start signal to the counter to trigger the counter to start working.

[0125] In some optional implementations, the preprocessing module generates m fundamental sine values ​​using the following formula:

[0126] sin(r+nθ)=sin[r+(n-1)θ+θ]=sin[r+(n-1)θ]cos(θ)+cos[r+(n-1)θ]sin(θ);

[0127] The preprocessing module generates m fundamental cosine values ​​using the following formula:

[0128] cos(r+nθ)= cos [r+(n-1)θ+θ]= cos [r+(n-1)θ]cos(θ)-sin[r+(n-1)θ]sin(θ);

[0129] The preprocessing module generates sin(mθ) using the following formula:

[0130] sin(mθ)=sin[(m-1)θ+θ]=sin[(m-1)θ]cos(θ)+cos[(m-1)θ]sin(θ);

[0131] The preprocessing module generates cos(mθ) using the following formula:

[0132] cos(mθ)=cos[(m-1)θ+θ]=cos[(m-1)θ]cos(θ)-sin[(m-1)θ]sin(θ);

[0133] Where n is time, and 0 ≤ n ≤ m-1.

[0134] In some optional implementations, the multiply-accumulate module performs m-stage pipelined calculations using the following formula to obtain the cosine iteration value:

[0135] cos(r+nθ)=cos[r+(nm)θ+mθ]=cos[r+(nm)θ]cos(mθ)-sin[r+(nm)θ]sin(mθ);

[0136] Where n is time, and m ≤ n.

[0137] In the above technical solution, the formula used by the multiply-accumulate operation module cannot have a negative value nm, that is, the minimum value of time n is m. At this time, the corresponding cosine iteration value calculated by the multiply-accumulate operation module is cos(r+mθ). Before this timing, the multiply-accumulate operation module cannot be used to calculate the output value. However, the selector is pre-configured with the required cosine basic values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ] for 0≤n≤m-1. The selector only needs to select the corresponding cosine basic value for output at the corresponding timing. An embodiment of this application provides a sine signal generating device, including:

[0138] The preprocessing module is used to: acquire m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and sin(mθ) and cos(mθ), and configure the m fundamental sine values ​​and the m fundamental cosine values ​​into a selector, and configure sin(mθ) and cos(mθ) into a multiply-accumulate operation module; where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1;

[0139] A counter is used to: upon receiving a start signal pulse, the counter starts from 0 and increments clock cycle by clock cycle to m, then remains constant;

[0140] The selector is used when the output of the counter is from 0 to m-1. The selector selects the sinusoidal base value that corresponds one-to-one with the output of the counter, and uses the sinusoidal base value as the final output of the sinusoidal signal after a delay of m clock cycles.

[0141] The multiply-accumulate module is used to: input the corresponding value in the selector into the multiply-accumulate module to perform m-stage pipelined calculations when the output of the counter is m, to obtain a sine iteration value; configure the sine iteration value into the selector; and the selector outputs the sine iteration value as the final sine signal after a delay of m clock cycles.

[0142] This application provides a cosine signal generating device, comprising:

[0143] The preprocessing module is used to: acquire m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and sin(mθ) and cos(mθ), and configure the m fundamental sine values ​​and the m fundamental cosine values ​​into a selector, and configure sin(mθ) and cos(mθ) into a multiply-accumulate operation module; where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1;

[0144] A counter is used to: upon receiving a start signal pulse, the counter starts from 0 and increments clock cycle by clock cycle to m, then remains constant;

[0145] A selector is used to: when the output of the counter is 0 to m-1, the selector selects a cosine base value that corresponds one-to-one with the output of the counter, and uses the cosine base value as the final output of the cosine signal after a delay of m clock cycles;

[0146] The multiply-accumulate module is used to: input the corresponding value in the selector into the multiply-accumulate module to perform m-stage pipelined calculations when the output of the counter is m; configure the cosine iteration value into the selector; and output the cosine iteration value as the final cosine signal after a delay of m clock cycles.

[0147] In one specific embodiment, assume m=2 and n is 0-4:

[0148] The selector is configured with the basic values ​​sin(r), sin(r+θ), cos(r), and cos(r+θ), and the multiply-accumulate module is configured with sin(2θ) and cos(2θ).

[0149] When the counter is 0, the selector selects the output cos(r) after 2 clock cycles.

[0150] When the counter is 1, the selector selects the output cos(r+θ) after 2 clock cycles.

[0151] When the counter is 2, the multiply-accumulate module calculates the iterative values ​​sin(r+2θ)=sin(r)cos(2θ)+cos(r)sin(2θ) and cos(r)=cos(r)cos(2θ) based on sin(2θ), cos(2θ) and the basic values ​​sin(r) and cos(r). The iterative values ​​cos(r+2θ)=cos(r)cos(2θ)-sin(r)sin(2θ) are then configured to the else port of the selector. After two clock cycles, the selector selects the output cos(r+2θ).

[0152] When the counter is 3, the multiply-accumulate module calculates the iterative values ​​sin(r+3θ)=sin(r+θ)cos(2θ)+cos(r+θ)sin(2θ) and cos(r+θ)=cos(r+θ)cos(2θ)-sin(r+θ)sin(2θ) based on sin(2θ), cos(2θ) and the basic values ​​sin(r+θ)cos(2θ). The iterative values ​​cos(r+3θ)cos(2θ) are then configured to the else port of the selector, and the selector selects the output cos(r+3θ) after 2 clock cycles.

[0153] When the counter is 4, the multiply-accumulate module calculates the iterative values ​​sin(r+4θ) = sin(r+2θ)cos(2θ) + cos(r+2θ)sin(2θ) and cos(r+4θ) = cos(r+2θ)cos(2θ) - sin(r+2θ)sin(2θ) based on sin(2θ), cos(2θ) and the iterative values ​​cos(r+4θ) = cos(r+2θ)cos(2θ) - sin(r+2θ)sin(2θ) according to sin(2θ), cos(2θ) and cos(r+4θ) according to cos(2θ), and configures sin(r+4θ) and cos(r+4θ) to the else port of the selector. After two clock cycles, the selector selects the output cos(r+4θ).

[0154] In some optional embodiments, sine and cosine signals can be generated simultaneously, as follows:

[0155] Please refer to Figure 3 Figure 3 This is a flowchart illustrating the steps of a method for generating sine and cosine signals, as provided in an embodiment of this application.

[0156] The preprocessing module receives external parameters sin(θ), cos(θ), sin(r), cos(r), and a valid parameter signal. Based on these, it generates sin(r), cos(r), sin(r+θ), cos(r+θ), sin(r+2θ), cos(r+2θ), sin(r+3θ), cos(r+3θ), ..., sin[r+(m-1)θ], cos[r+(m-1)θ], sin(mθ), cos(mθ), and a start control signal. The start control signal is a pulse signal for one clock cycle, indicating that subsequent modules can start working. All of the above signals are sent together to the back-end counter, selector, and multiply-accumulate operation module.

[0157] The counter, controlled by the start signal, starts counting from 0 until it counts to m, and then holds at m. The output signal cnt of the counter has a value range of [0, m], and this cnt signal will be input to the selector.

[0158] The selector receives sin(r), cos(r), sin(r+θ), cos(r+θ), sin(r+2θ), cos(r+2θ), sin(r+3θ), cos(r+3θ), ..., sin[r+(m-1)θ], cos[r+(m-1)θ] from the preprocessing module and sin(r+nθ) and cos(r+nθ) from the multiply-accumulate module. Under the control of the cnt signal output by the counter, it outputs sin(r+nθ) and cos(r+nθ) as the final output.

[0159] The multiply-accumulate module receives sin(mθ) and cos(mθ) from the preprocessing module and sin[r+(nm)θ] and cos[r+(nm)θ] from the selector. It then calculates sin(r+nθ) and cos(r+nθ) using an m-stage pipeline and outputs the counting results to the selector.

[0160] Please refer to Figure 4 , Figure 4 The timing diagram for generating sine and cosine signals provided in the embodiments of this application includes:

[0161] 1. After the external module configures the valid signal to the preprocessing module, the preprocessing module generates the start control signal after a delay of several clock cycles.

[0162] 2. After the external module configures sin(θ), cos(θ), sin(r), and cos(r) to the preprocessing module, the preprocessing module generates and outputs sin(r), cos(r), sin(r+θ), cos(r+θ), sin(r+2θ), cos(r+2θ), sin(r+3θ), cos(r+3θ), ..., sin[r+(m-1)θ], cos[r+(m-1)θ], sin(mθ), and cos(mθ).

[0163] 3. After receiving the start signal pulse, the counter starts counting from 0 until cnt outputs m, and then remains unchanged.

[0164] 4. The selector selects an output from cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ] based on the value of cnt. When cnt is 0 to m-1, the output is cos(r), cos(r+θ) to cos[r+(m-1)θ].

[0165] 5. The selector selects an output from sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ] based on the value of cnt. When cnt is 0 to m-1, the output is sin(r), sin(r+θ) to sin[r+(m-1)θ].

[0166] 6. Multiply-accumulate module: Based on sin[r+(nm)θ], cos[r+(nm)θ] and sin(mθ), cos(mθ), calculate sin(r+nθ) and cos(r+nθ) using an m-stage pipeline.

[0167] 7. When cnt is m, the selector outputs sin(r+nθ) and cos(r+nθ) with fixed values.

[0168] In the embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the displayed or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0169] Furthermore, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0170] Furthermore, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0171] In this document, relational terms such as first and second are used only to distinguish one entity or operation from another entity or operation, without necessarily requiring or implying any such actual relationship or order between these entities or operations.

[0172] The above description is merely an embodiment of this application and is not intended to limit the scope of protection of this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A method of generating a sinusoidal signal, characterized by, include: Obtain m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], and m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and fix the rotation step size sin(mθ) and cos(mθ). Configure the m fundamental sine values ​​and the m fundamental cosine values ​​in the selector, and configure sin(mθ) and cos(mθ) in the multiply-accumulate operation module; where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1. After receiving the start signal pulse, the counter starts from 0 and increments clock cycle by clock cycle to m and then remains constant; When the output of the counter is from 0 to m-1, the selector selects a sinusoidal base value that corresponds one-to-one with the output of the counter, and uses this sinusoidal base value as the final output of the sinusoidal signal after a delay of m clock cycles. When the output of the counter is m, the corresponding value in the selector is input into the multiply-accumulate operation module for m-stage pipelined calculation to obtain the sine iteration value; the sine iteration value is configured into the selector; the selector uses the sine iteration value as the final output of the sine signal after a delay of m clock cycles.

2. The method as described in claim 1, characterized in that, The acquisition of m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and the fixed rotation step sizes sin(mθ) and cos(mθ) include: Configure the valid signals of sin(θ), cos(θ), sin(r), and cos(r) and their parameters into the preprocessing module; The preprocessing module generates the m fundamental sine values, m fundamental cosine values, sin(mθ), and cos(mθ) in a serial manner based on sin(θ), cos(θ), sin(r), and cos(r).

3. The method as described in claim 2, characterized in that, After configuring sin(θ), cos(θ), sin(r), and cos(r) and the valid signals of the parameters into the preprocessing module, the process further includes: The preprocessing module generates a start signal to the counter after a certain delay.

4. The method as described in claim 2, characterized in that, The preprocessing module generates the m fundamental sine values ​​using the following formula: sin(r+nθ)=sin[r+(n-1)θ+θ]=sin[r+(n-1)θ]cos(θ)+cos[r+(n-1)θ]sin(θ); The preprocessing module generates the m fundamental cosine values ​​using the following formula: cos(r+nθ)= cos [r+(n-1)θ+θ]= cos [r+(n-1)θ]cos(θ)-sin[r+(n-1)θ]sin(θ); The preprocessing module generates sin(mθ) using the following formula: sin(mθ)=sin[(m-1)θ+θ]=sin[(m-1)θ]cos(θ)+cos[(m-1)θ]sin(θ); The preprocessing module generates cos(mθ) using the following formula: cos(mθ)=cos[(m-1)θ+θ]=cos[(m-1)θ]cos(θ)-sin[(m-1)θ]sin(θ); Where n is time, and 0 ≤ n ≤ m-1.

5. The method as described in claim 1, characterized in that, The multiply-accumulate module uses the following formula to perform m-stage pipeline calculations to obtain the sine iteration value: sin(r+nθ)=sin[r+(nm)θ+mθ]=sin[r+(nm)θ]cos(mθ)+cos[r+(nm)θ]sin(mθ); Where n is time, and m≤n.

6. A method for generating a cosine signal, characterized in that, include: Obtain m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], and m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and fix the rotation step size sin(mθ) and cos(mθ). Configure the m fundamental sine values ​​and the m fundamental cosine values ​​in the selector, and configure sin(mθ) and cos(mθ) in the multiply-accumulate operation module; where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1. After receiving the start signal pulse, the counter starts from 0 and increments clock cycle by clock cycle to m and then remains constant; When the output of the counter is from 0 to m-1, the selector selects a cosine base value that corresponds one-to-one with the output of the counter, and uses this cosine base value as the final output of the cosine signal after a delay of m clock cycles. When the output of the counter is m, the corresponding value in the selector is input into the multiply-accumulate operation module for m-stage pipelined calculation to obtain the cosine iteration value; the cosine iteration value is configured into the selector; the selector uses the cosine iteration value as the final output of the cosine signal after a delay of m clock cycles.

7. The method as described in claim 6, characterized in that, The acquisition of m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and the fixed rotation step sizes sin(mθ) and cos(mθ) include: Configure the valid signals of sin(θ), cos(θ), sin(r), and cos(r) and their parameters into the preprocessing module; The preprocessing module generates the m fundamental sine values, m fundamental cosine values, sin(mθ), and cos(mθ) in a serial manner based on sin(θ), cos(θ), sin(r), and cos(r).

8. The method as described in claim 7, characterized in that, After configuring sin(θ), cos(θ), sin(r), and cos(r) and the valid signals of the parameters into the preprocessing module, the process further includes: The preprocessing module generates a start signal to the counter after a certain delay.

9. The method as described in claim 7, characterized in that, The preprocessing module generates the m fundamental sine values ​​using the following formula: sin(r+nθ)=sin[r+(n-1)θ+θ]=sin[r+(n-1)θ]cos(θ)+cos[r+(n-1)θ]sin(θ); The preprocessing module generates the m fundamental cosine values ​​using the following formula: cos(r+nθ)= cos [r+(n-1)θ+θ]= cos [r+(n-1)θ]cos(θ)-sin[r+(n-1)θ]sin(θ); The preprocessing module generates sin(mθ) using the following formula: sin(mθ)=sin[(m-1)θ+θ]=sin[(m-1)θ]cos(θ)+cos[(m-1)θ]sin(θ); The preprocessing module generates cos(mθ) using the following formula: cos(mθ)=cos[(m-1)θ+θ]=cos[(m-1)θ]cos(θ)-sin[(m-1)θ]sin(θ); Where n is time, and 0 ≤ n ≤ m-1.

10. The method as described in claim 6, characterized in that, The multiply-accumulate module uses the following formula to perform m-stage pipelined calculations to obtain the cosine iteration value: cos(r+nθ)=cos[r+(nm)θ+mθ]=cos[r+(nm)θ]cos(mθ)-sin[r+(nm)θ]sin(mθ); Where n is time, and m≤n.

11. A sinusoidal signal generating device, characterized in that, include: The preprocessing module is used to: acquire m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and fix the rotation step size sin(mθ) and cos(mθ), and configure the m fundamental sine values ​​and the m fundamental cosine values ​​into a selector, and configure sin(mθ) and cos(mθ) into the multiply-accumulate operation module; where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1; A counter, used to: upon receiving a start signal pulse, increment the counter from 0 to m clock cycles and then keep it constant; The selector is used to: when the output of the counter is 0 to m-1, select a sinusoidal base value that corresponds one-to-one with the output of the counter, and use the sinusoidal base value as the final output of the sinusoidal signal after a delay of m clock cycles; The multiply-accumulate operation module is used for: when the output of the counter is m, inputting the corresponding value in the selector into the multiply-accumulate operation module to perform m-stage pipelined calculations to obtain a sine iteration value; configuring the sine iteration value into the selector; and after a delay of m clock cycles, the selector outputs the sine iteration value as the final sine signal after a delay of m clock cycles.

12. A cosine signal generating device, characterized in that, include: The preprocessing module is used to: acquire m fundamental sine values ​​sin(r), sin(r+θ), sin(r+2θ), sin(r+3θ), ..., sin[r+(m-1)θ], m fundamental cosine values ​​cos(r), cos(r+θ), cos(r+2θ), cos(r+3θ), ..., cos[r+(m-1)θ], and fix the rotation step size sin(mθ) and cos(mθ), and configure the m fundamental sine values ​​and the m fundamental cosine values ​​into a selector, and configure sin(mθ) and cos(mθ) into the multiply-accumulate operation module; where r is the initial phase value, 0≤r<2π; θ is the angular frequency, θ=2πfo / fs, fo is the offset frequency, fs is the sampling rate; m is the pipeline stage of the multiply-accumulate operation module and is not less than 1; A counter, used to: upon receiving a start signal pulse, increment the counter from 0 to m clock cycles and then keep it constant; A selector is used to: when the output of the counter is 0 to m-1, the selector selects a cosine base value that corresponds one-to-one with the output of the counter, and uses the cosine base value as the final output of the cosine signal after a delay of m clock cycles; The multiply-accumulate module is used to: input the corresponding value in the selector into the multiply-accumulate module for m-stage pipelined calculation when the output of the counter is m, to obtain the cosine iteration value; configure the cosine iteration value into the selector; and after a delay of m clock cycles, the selector outputs the cosine iteration value as the final cosine signal after a delay of m clock cycles.

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