A method of clock tree synthesis, computer readable storage medium

Abstract

A method for clock tree synthesis and a computer-readable storage medium are disclosed. The method includes: acquiring a global clock tree of a target circuit, the global clock tree comprising multiple timing skew groups; determining sub-clock trees corresponding to each timing skew group based on each timing skew group, wherein each sub-clock tree includes a common path and several non-common paths branching from the common path, and the common and non-common paths each include several components; for each sub-clock tree: determining a drive object to be processed based on the common path of the sub-clock tree; calculating the load center location based on the several non-common paths; inserting a load center component at the load center location; when the components on the common path where the inserted load center component is located, and the components adjacent to the load center component in each of the non-common paths connected to the inserted load center component, do not meet preset design constraints, setting several signal conditioning units between the drive object to be processed and the inserted load center component.

Description

Technical Field

[0001] This invention relates to the field of digital chip timing optimization technology, specifically to a method for clock tree synthesis and a computer-readable storage medium. Background Technology

[0002] Clock tree synthesis is fundamental to data transmission in digital integrated circuit design. The performance of the clock tree determines the maximum operating frequency and signal stability of the entire system, with far-reaching and extensive implications. Ideally, the clock signal arrives simultaneously from the source node at all flip-flops and memories within the circuit. However, timing deviations are unavoidable in real-world scenarios. Therefore, the clock signal must ensure that critical timing requirements are met even under worst-case conditions; otherwise, uncontrollable and unknown errors may occur. With rapid technological advancements, the demand for integrated circuits with higher integration density, smaller process dimensions, and lower power consumption is increasing, posing greater challenges to clock tree synthesis performance. The continuous shrinking of process dimensions further complicates achieving minimal timing deviations after clock tree synthesis.

[0003] Currently, commonly used clock tree synthesis methods mainly reduce timing deviations by selecting the clock tree structure and using buffer or inverter insertion strategies.

[0004] Commonly used physical structures for clock tree synthesis include H-trees, fishbone structures, and mesh structures. H-trees are simple fractal structures, easy to implement, and their symmetrical structure effectively reduces timing skew, making them suitable for high-frequency circuits. However, this simple symmetrical structure has high routing requirements (horizontal and vertical connections can only be on adjacent routing layers), low flexibility, and is unsuitable for circuits with keep-out areas on the clock path. Furthermore, large-scale complex circuits often suffer from excessive clock delays. Fishbone trees significantly reduce clock delays by utilizing multiple shorter paths, but due to their asymmetrical structure and lack of adjustment for timing skew within branches, their overall timing performance is inferior to H-trees. Mesh clock trees, with their symmetrical mesh structure, can achieve smaller timing skews, but the mesh contains redundant structures consuming significant line length and power, making them unsuitable for power-sensitive designs and circuits with keep-out areas.

[0005] The insertion strategy for buffers or inverters is not only a method for local fine-tuning timing deviations in the aforementioned clock tree physical structure, but also a commonly used method in clock tree synthesis to reduce timing deviations. The timing deviation grouping method groups the clock tree according to different user requirements such as process timing, and then sorts the clock paths according to clock delay. It inserts buffers or inverters at each level along the shortest / longest path using algorithms such as clustering and CCOPT (Clook Concurrent Optimization) to reduce timing deviations or time delays. It also supplements this with fine-tuning of buffer position, size, load, etc., until all clock paths meet the timing requirements.

[0006] This method has no requirements on the clock tree structure to be synthesized, making it more flexible and suitable for large and complex circuits. However, since there is no physical structure to guarantee small timing deviations, it can only rely on theoretical calculations. Due to the mutual influence and constraints of clock delay, timing deviations, and overall size, a lot of experience is needed to find a suitable strategy. Finding a general, globally optimal strategy applicable to most circuits is a challenge. Research has found that for circuit structures that are complex and asymmetrical overall but locally symmetrical, the buffer or inverter strategies used along the shortest / longest paths in the locally symmetrical parts are similar. In other words, the same buffer or inverter is repeatedly added to the locally symmetrical parts in each path, resulting in redundant calculations and structural redundancy. Summary of the Invention

[0007] The main technical problem solved by this invention is a clock tree synthesis method for global optimization of timing deviations in common paths.

[0008] According to the first aspect, one embodiment provides a method for clock tree synthesis, comprising:

[0009] Obtain the global clock tree of the target circuit. The global clock tree includes multiple timing skew groups. Determine the sub-clock tree corresponding to each timing skew group based on each timing skew group. Each sub-clock tree includes a common path and several non-common paths branching from the common path. The common path and non-common paths include several components.

[0010] For each sub-clock tree:

[0011] The driving object to be processed is determined based on the common path of the sub-clock tree;

[0012] Calculate the load center location based on several non-common paths;

[0013] In the case where the drive object to be processed is not a load center element:

[0014] Insert a load center element at the load center location;

[0015] When the elements in the common path where the inserted load center element is located, and the elements adjacent to the load center element in each non-common path connected to the inserted load center element, do not meet the preset design constraints, several signal conditioning units are set between the driving object to be processed and the inserted load center element to optimize the sub-clock tree.

[0016] In one embodiment, determining the driving object to be processed based on the common path of the sub-clock tree includes:

[0017] Along the direction of clock signal transmission, the path from the root node of the sub-clock tree to a designated output pin is determined as a common path; wherein, the designated output pin is the first output pin that connects multiple next-level components in the direction of clock signal transmission.

[0018] The first output pin that connects to multiple next-level components is identified as the driving object to be processed.

[0019] In one embodiment, calculating the load center location based on several non-common paths includes:

[0020] Select the load from each non-public path;

[0021] Calculate the load center location based on the selected load location coordinates.

[0022] In one embodiment, selecting the load from each non-common path includes:

[0023] Select the element that is directly connected to the driver object to be processed from each non-common path, and determine the element that is directly connected to the driver object to be processed as the load.

[0024] In one embodiment, selecting the load from each non-common path includes:

[0025] Select the last element in the clock signal transmission direction of each non-common path connected to the driving object to be processed, and determine the last element on each non-common path as the load.

[0026] In one embodiment, the clock tree synthesis method further includes: determining the module to which the inserted load center element belongs, for determining the electrical characteristic parameters of the inserted load center element and the connection relationship between the load center element to be inserted and the selected load;

[0027] The module to which the inserted load center element belongs is either the module to which the driver object to be processed belongs, or the smallest common module of the next-level element connected to the inserted driver object to be processed belongs, or the module calculated by setting a calculation method.

[0028] In one embodiment, when the elements in the common path where the inserted load center element is located, and the elements adjacent to the load center element in each non-common path connected to the inserted load center element, do not meet the preset design constraints, a plurality of signal conditioning units are provided between the driving object to be processed and the load center element to be inserted, including:

[0029] The maximum number of signal conditioning units set between the driving object to be processed and the inserted load center element is calculated based on preset physical constraints.

[0030] Between the drive object to be processed and the inserted load center element, the number of signal conditioning units is increased or decreased sequentially according to a set quantity change condition;

[0031] The timing of the sub-clock tree is calculated for each change in the number of signal conditioning units;

[0032] When determining the number of signal conditioning units each time, whether the elements in the common path where the inserted load center element is located, and the elements adjacent to the load center element in each non-common path connected to the inserted load center element, meet the preset design constraints; if they meet the constraints, the number of signal conditioning units is determined to be the number of signal conditioning units for the current time; if they do not meet the constraints, the number of signal conditioning units is increased or decreased successively according to the set quantity change conditions until all signal conditioning units participate in the determination.

[0033] If, during each change in the number of signal conditioning units, the elements in the common path where the inserted load center element is located, and the elements adjacent to the load center element in each non-common path connected to the inserted load center element, do not meet the preset design constraints, then the number of signal conditioning units is determined to be the number of signal conditioning units corresponding to the optimal timing of the sub-clock tree in each change in the number of signal conditioning units.

[0034] In one embodiment, each signal conditioning unit is placed at equal intervals according to the winding path from the drive object to be processed to the inserted load center element.

[0035] In one embodiment, the clock tree synthesis method further includes:

[0036] When the load center position is the coordinate position of the driving object to be processed, the driving object to be processed is determined as the load center element.

[0037] According to a second aspect, one embodiment provides a computer-readable storage medium storing a computer program that can be executed by a processor to implement the methods described in any of the above embodiments.

[0038] According to the above embodiments, a clock tree synthesis method and a computer-readable storage medium are provided. The method obtains the global clock tree of the target circuit and determines sub-clock trees corresponding to each timing deviation group based on multiple timing deviation groups in the global clock tree. In each sub-clock tree, a driver to be processed is determined based on the common path of the sub-clock tree, and the load center position is calculated based on the non-common paths in the sub-clock tree. A load center element is then inserted at the calculated load center position. When the elements on the common path where the load center element is located, and the elements adjacent to the load center element in each non-common path connected to the inserted load center element, do not meet preset design constraints, several signal conditioning units are set between the driver to be processed and the load center element to optimize the sub-clock tree. This application divides the corresponding sub-clock trees according to timing deviation groups, enabling local optimization for each type of timing deviation group, thereby improving the overall synchronization accuracy. Furthermore, this application directly inserts signal conditioning units on the common path, which avoids introducing new timing deviations while also reducing the chip design cycle and chip size. Attached Figure Description

[0039] Figure 1 This is a flowchart illustrating the overall process of clock tree synthesis in one embodiment.

[0040] Figure 2 This is a schematic diagram of a root node as the driving object to be processed in one embodiment;

[0041] Figure 3 This is a schematic diagram illustrating the determination of the driving object to be processed in a simple transmission path in one embodiment;

[0042] Figure 4 This is a schematic diagram illustrating the determination of the driving object to be processed in a complex transmission path in one embodiment.

[0043] Figure 5 This is a flowchart of step S300 of a clock tree synthesis method in one embodiment;

[0044] Figure 6 This is a flowchart illustrating one implementation of step S310 of the clock tree synthesis method in one embodiment;

[0045] Figure 7 This is a flowchart illustrating another implementation of step S310 of the clock tree synthesis method in one embodiment;

[0046] Figure 8 This is a schematic diagram illustrating a first method for determining the module to which the load center element belongs in one embodiment;

[0047] Figure 9 This is a schematic diagram illustrating a second method for determining the module to which the load center element belongs in one embodiment;

[0048] Figure 10 This is a schematic diagram illustrating a third method for determining the module to which the load center element belongs in one embodiment;

[0049] Figure 11 This is a schematic diagram illustrating a scenario where an incorrectly selected module belonging to the load center element results in a through-module error.

[0050] Figure 12 This is a flowchart of step S500 in one embodiment. Detailed Implementation

[0051] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0052] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0053] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages).

[0054] In commonly used clock tree synthesis methods, since there is no limit to the number of inserted components, adding a buffer or inverter along each clock path to correct design rule violations can easily introduce new timing deviations and may also lead to over-insertion of buffers or inverters, thereby increasing chip area. This application provides a clock tree synthesis method that prioritizes inserting buffers based on common paths and inserts components at equal intervals along the routing path to improve maximum transition time. This solves the problems of long runtime and excessive chip area associated with the traditional method of traversing clock paths to insert, move, delete, and adjust loads to reduce timing deviations. It helps to shorten the design cycle of ultra-large-scale complex high-frequency circuit products and reduce chip size, which will be described in detail below.

[0055] Please refer to Figure 1 One embodiment provides a method for clock tree synthesis, comprising the following steps.

[0056] Step S100: Obtain the global clock tree of the target circuit to determine the sub-clock tree of each timing deviation group in the global clock tree.

[0057] In one embodiment, a global clock tree refers to a complete distributed network structure in the target circuit used to transmit clock signals. This structure starts from a clock source (such as a phase-locked loop (PLL), an external clock input port, etc.) and distributes the clock signal to various registers or logic modules in the circuit step by step through a series of driving units (such as buffers, inverters, clock distribution units, etc.), thereby ensuring that each register operates under a unified clock signal.

[0058] In one embodiment, the global clock tree typically consists of multiple branches, each corresponding to a portion of the synchronous logic units in the circuit. As the clock signal is distributed hierarchically in the network, differences in signal propagation delay may occur between different distributions, resulting in timing deviations. To facilitate analysis and optimization, the global clock tree is divided into several timing deviation groups according to the timing deviation situation, with each timing deviation group corresponding to a set of clock paths with similar delay characteristics.

[0059] In one embodiment, preliminary work is required before partitioning the clock tree. This includes: reading the netlist information of the target circuit to obtain the components and their connections; reading the optional component library for selecting and matching parameters of buffers, inverters, or other signal conditioning units that may be inserted later; and reading the physical library information related to the layout implementation to obtain the physical dimensions, pin locations, and electrical characteristics of each component. Additionally, a set of design constraint parameters, including maximum load capacitance, maximum signal transition time, clock arrival time constraints, and path timing deviation thresholds, can be imported for further timing analysis and configuration of signal conditioning units.

[0060] In one embodiment, after the configuration is completed, a corresponding clock tree structure, i.e. a sub-clock tree, is generated for each timing deviation group according to the division results of each timing deviation group.

[0061] In one embodiment, each sub-clock tree includes a common path and several non-common paths branching off from the common path. The common path typically represents a shared signal transmission path from the clock source to several next-level driven objects, while the non-common paths represent the path from the branching point of the common path to the end point of the clock tree. Each common path includes several components, and each non-common path also includes several components; the number of components on the common path and each non-common path can be set according to actual engineering needs.

[0062] Step S200: Determine the driving object to be processed based on the common path of each sub-clock tree.

[0063] In one embodiment, starting from the root node of the sub-clock tree corresponding to each timing deviation group, all component pins and their connections in the sub-clock tree are traversed and analyzed according to the transmission direction of the clock signal. During the traversal, the output pins of the current node and the information of the next-level components they are connected to are identified sequentially.

[0064] Please refer to Figure 2 , Figure 3 and Figure 4 In one embodiment, during the initial traversal, the clock signal is transmitted step-by-step from the root node to the next level node. At this stage, the signal path is a single path, meaning the output pin connects to only one next-level component. As the traversal progresses, when the number of next-level components connected to a particular output pin is greater than one, it indicates that the output pin is the first branching point of the clock signal. At this point, the path from the root node to the output pin is determined as the common path of the sub-clock tree, because this path is the signal transmission path shared by all subsequent clock branches. Simultaneously, the output pin that first exhibits a multi-fan-out connection is determined as the driver object to be processed; this driver object is the boundary node between the common path and several non-common paths.

[0065] It's important to note that the root node refers to the source node of the clock signal, i.e., the starting point where the clock signal enters the clock tree structure in the target circuit. Typically, the root node corresponds to the clock signal generation unit or input port, such as a signal source output from a phase-locked loop, clock generator, or external clock input. To accommodate the design requirements of different circuit structures, the root node can also be specified by the user based on design goals or optimization strategies. The root node is the starting point for clock signal distribution in the global clock tree. Starting from the root node, the clock signal passes through several levels of buffers, branches, and adjustment units, and is transmitted step-by-step to each trigger unit (such as registers, flip-flops, latches, etc.). In terms of topology, there is only a single output path between the root node and the other nodes of the clock tree; that is, the root node has only one output pin, and its output signal serves as the input reference for the entire clock network.

[0066] In the actual implementation, the root node can be identified by parsing the circuit netlist or clock constraint file. For example, if the signal source type of a node is identified as "master clock source" or "external input clock port" and there is no upper-level driving unit, then it can be determined as the root node of the global clock tree.

[0067] For each timing skew group, its corresponding sub-clock tree also has an independent root node. This root node is not necessarily the same as the root node of the global clock tree; it is usually an intermediate node in the global clock tree or the first common driver node in the timing path of that group.

[0068] Step S300: Calculate the load center location based on several non-common paths.

[0069] Please refer to Figure 5 In one embodiment, the execution step S300, which calculates the load center location based on several non-common paths, includes the following steps.

[0070] Step S310: Select the load from each non-common path.

[0071] In one embodiment, selecting the load in each non-common path during step S310 can be done in the following two ways.

[0072] Please refer to Figure 6 The first method includes the following steps.

[0073] Step S311: Select the component that is directly connected to the driving object to be processed from each non-common path.

[0074] Step S313: Identify the components directly connected to the driving object to be processed as loads.

[0075] In one embodiment, for each sub-clock tree, in order to determine the location of the subsequent load center, it is necessary to first determine the load in each non-common path.

[0076] In one embodiment, the load typically refers to a circuit unit that receives the clock signal, such as a register, flip-flop, latch, or other logic unit that requires a clock signal to trigger. On each non-common path, the circuit unit directly connected to the output of the object being processed, i.e., the first-stage receiving unit of that path, is selected as the corresponding load. This load is typically the first receiver of the clock signal and can reflect the actual delay and fan-out characteristics of that non-common path.

[0077] Please refer to Figure 7 The second method includes the following steps.

[0078] Step S312: Select the last element in the clock signal transmission direction of each non-common path connected to the driving object to be processed.

[0079] Step S314: Identify the last element on each non-common path as a load.

[0080] In one embodiment, starting from the output of the driver object to be processed, all non-common paths connected to the driver object are traversed along the direction of clock signal transmission until the end node of each path. If the end node of the path is an input port of a component, and the node does not branch downwards, then the component is determined to be the final load of the non-common path. This component is also a leaf node of the path; therefore, the leaf nodes on each non-common path can be identified as loads. The components serving as leaf nodes are generally registers or latches.

[0081] Step S320: Calculate the load center location based on the selected load location coordinates.

[0082] In one embodiment, in order to more accurately determine the load center location of each sub-clock tree and thus improve the balance of clock signal distribution, different algorithms can be used to calculate the load center location based on the selected load location coordinates.

[0083] Specifically, the location coordinates of each load are first obtained, including the coordinates of each load in the horizontal direction (x-axis) and the vertical direction (y-axis). Depending on the load distribution characteristics, timing constraints, and layout complexity, several algorithms can be used.

[0084] Arithmetic mean method: Calculate the arithmetic mean of the x and y coordinates of all load nodes to obtain the horizontal and vertical positions of the load center, which is the load center position.

[0085] Geometric center algorithm: Obtain the coordinates of all load nodes, determine the geometric shape formed by all loads based on the coordinates of all load nodes, and calculate the center point of the geometric image, which is the load center position.

[0086] Weighted average algorithm: Based on parameters such as the importance of the load node, the size of the load capacitance, the number of fan-outs or timing deviations, a weight coefficient is set for each load, and the coordinates of each load are weighted and averaged based on the weight coefficient to obtain the load center location.

[0087] Step S400: Insert the load center element at the load center position.

[0088] In one embodiment, to reduce clock skew caused by load imbalance, a load center element for signal redistribution needs to be inserted after the drive object to be processed. This load center element can be a buffer or an inverter.

[0089] In one embodiment, during the insertion process, it is first determined whether the spatial location of the driver object to be processed coincides with the calculated load center location or is within the allowable deviation threshold. If this condition is met, no new component needs to be added, and the driver object to be processed is directly marked as a load center component. If there is a significant difference between the spatial location of the driver object to be processed and the load center location, then the driver object to be processed is not a load center component. In this case, a new load center component is inserted along the signal direction from the driver object to be processed on the clock signal transmission path, making its position close to or equal to the load center location. Since the physical wiring space and signal trace delay are taken into account during insertion, as long as it is within a suitable threshold error, it is considered that a load center component has been inserted at the load center location.

[0090] It should be noted that if the driving object to be processed is marked as a load center element, it is not necessary to determine the module to which the subsequent load center element belongs or whether it meets the preset design constraints.

[0091] In one embodiment, in addition to determining the load center location based on the above calculations, the module to which the inserted load center element belongs also needs to be further determined. By determining the module to which the inserted load center element belongs, the electrical characteristic parameters of the inserted load center element and the connection relationship between the inserted load center element and the selected load can be clarified. The electrical characteristic parameters include the type and size of the inserted load center element.

[0092] In one embodiment, the module to which the driving object to be processed belongs can be directly determined as the module to which the inserted load center element belongs. For example... Figure 8 As shown, the driving object to be processed is in module A, therefore the inserted load center element also belongs to module A.

[0093] In one embodiment, when multiple downstream components connected to the driving object belong to different modules, to avoid complex circuit structures caused by cross-module connections, the least common module of the modules to which the downstream components belong can be selected as the module to which the inserted load center component belongs. For example... Figure 9 As shown, the next-level components connected to the driver object to be processed are registers, AND gates, and latches. The smallest common module of registers, AND gates, and latches is module B. Therefore, the module to which the inserted load center component belongs is module B.

[0094] In one embodiment, in a complex hierarchical structure, a suitable module can be calculated using a defined calculation method, and this module is determined as the module to which the inserted load center element belongs. Specifically, a comprehensive evaluation can be performed based on the module to which the driven object to be processed and its connected next-level components belong, their location, connection relationships, and other design parameters. Factors such as module area, signal path length, clock delay, and layout density are balanced to determine the module that optimizes timing performance. This module with optimal timing performance is then determined as the module to which the inserted load center element belongs. Figure 10 As shown, the optimal module calculated according to the set calculation method is the top-level module. Therefore, the module to which the inserted load center element belongs is determined to be the top-level module.

[0095] It should be noted that if multiple ports within the same module are simultaneously connected to the drive object being processed, this module cannot be selected as an optional module for load center component insertion. This is because directly inserting components into this module can easily lead to multiple penetrations, which not only disrupts the integrity of the module's internal layout but may also cause signal routing conflicts or timing abnormalities. Figure 11 As shown, module B contains both a load (registers, AND gates, and latches) and a submodule (module C). Module B has two input ports connected to the object to be processed in module A. One input port connects to the load in module B, and the other input port connects to module C within module B. If the inserted load center element is placed in module B, to ensure the circuit structure remains unchanged, the output port of module B needs to be connected to its own input port, resulting in module B being repeatedly penetrated.

[0096] In one embodiment, when inserting a load center component, the type and size of the load center component are selected primarily based on user settings. That is, before inserting the load center component, it is first determined whether the user-specified component type and size parameters exist. If the user has specified the target component type and size through a configuration file, design instructions, or graphical interface, that specified component will be directly used as the inserted load center component. If the user has not specified these parameters, a suitable component type and size can be automatically selected from the available component library based on the load of the object to be processed and the module information of the module to which the previously selected inserted load center component belongs.

[0097] Step S500: Determine whether the components in the common path where the inserted load center component is located, and the components adjacent to the load center component in each non-common path connected to the inserted load center component, satisfy the preset design constraints.

[0098] In one embodiment, after inserting the load center element, it is necessary to further determine whether the elements in the common path where the inserted load center element is located, as well as the elements adjacent to the load center element in each non-common path connected to the inserted load center element, satisfy preset design constraints. These preset design constraints include, but are not limited to, layout constraints, timing constraints, electrical constraints, and power consumption constraints related to Design Rule Checks (DRVs). For example, component spacing, wiring density, clock skew, signal integrity, power distribution, and temperature rise parameters are all within the scope of the design rule constraint assessment.

[0099] It should be noted that since the load center component belongs to the common path, the judgment of whether the components on the common path meet the preset design constraints must include the load center component.

[0100] In one embodiment, when the elements in the common path where the inserted load center element is located, as well as the elements adjacent to the load center element in each non-common path connected to the inserted load center element, satisfy a preset design constraint, the load center element is fixed at its final insertion position, and that part of the sub-clock tree is no longer adjusted. At this time, the load center element serves as an anchor element for the common path, supporting the balance and signal distribution of the subsequent clock tree.

[0101] In one embodiment, when the elements in the common path where the inserted load center element is located and the elements adjacent to the load center element in each non-common path connected to the inserted load center element do not meet the preset design constraints, several signal conditioning units are set between the driving object to be processed and the inserted load center element to optimize the sub-clock tree.

[0102] Please refer to Figure 12 Specifically, it includes the following steps.

[0103] Step S510: Calculate the maximum number of signal conditioning units set between the drive object to be processed and the inserted load center element.

[0104] In one embodiment, the maximum number of signal conditioning units set between the driving object to be processed and the inserted load center element is calculated based on physical constraints such as load conditions, maximum load capacitance, and maximum signal transition time.

[0105] For example, based on the selected module, component type, and size of the inserted load center component in the above steps, the parasitic capacitance parameter `maxTransCap` is retrieved from the component's technology library according to the maximum transition time specified in the preset design constraints. The maximum parasitic capacitance parameter `unitCap` on a unit winding path is estimated based on the drive position and load conditions of the signal conditioning unit, combined with the winding process and rules. The shortest winding length is calculated using the parasitic capacitance parameter `maxTransCap` and the maximum parasitic capacitance parameter `unitCap` on a unit winding path: `netLength = maxTransCap / unitCap`. Then, the longest winding length `maxLength` is calculated based on the drive position and load conditions of the signal conditioning unit. Therefore, the maximum number of signal conditioning units, N = `maxLength / netLength`.

[0106] It should be noted that the signal conditioning unit refers to a circuit unit inserted between the driven object to be processed and the load center element to adjust the signal propagation characteristics, which may include a buffer and / or an inverter.

[0107] Step S520: Between the drive object to be processed and the inserted load center element, the signal conditioning unit is increased or decreased sequentially according to the set quantity change conditions.

[0108] In one embodiment, after determining the maximum number N of signal conditioning units, in order to achieve timing balance and signal quality optimization of the sub-clock tree, the number of signal conditioning units inserted is increased or decreased sequentially according to a set quantity change between the driving object to be processed and the inserted load center element.

[0109] Specifically, by setting quantity change conditions, the number of signal conditioning units can be gradually increased from 1 to N, with each increase being 1, 2, or 3 units. Alternatively, the number of signal conditioning units can be gradually decreased from N to 1, with each decrease also being 1, 2, or 3 units.

[0110] It should be noted that the inserted signal conditioning units do not use a direct, equidistant placement method between two points. This is because if there are areas between the two points where components cannot be placed, equidistant placement becomes impossible, resulting in excessively long distances between some components and causing new local design rule violations. Therefore, in this application, each signal conditioning unit is placed equidistantly along the winding path from the driven object to the inserted load center component, effectively avoiding this problem.

[0111] Step S530: Determine whether the elements in the common path where the inserted load center element is located and the elements adjacent to the load center element in each non-common path connected to the inserted load center element meet the preset design constraints when the number of signal conditioning units changes each time.

[0112] In one embodiment, the following is performed in each attempt to change the number of signal conditioning units.

[0113] In one embodiment, given the current number of signal conditioning units being attempted, the timing of the sub-clock tree is calculated, including signal propagation delay, timing margin, signal transition time, load distribution, etc. It is then determined whether, given the current number of signal conditioning units, the components in the common path where the inserted load center element is located, and the components adjacent to the load center element in each non-common path connected to the inserted load center element, meet preset design constraints. These preset design constraints include, but are not limited to: maximum signal delay not exceeding an allowable threshold, maximum signal transition time less than a target specification, signal integrity meeting noise and crosstalk tolerance limits, and cumulative capacitance and resistance values ​​not exceeding rule limits.

[0114] If the current number of signal conditioning units meets the preset design constraints, then stop trying and determine the current number of signal conditioning units as the final number.

[0115] If the current number of signal conditioning units does not meet the preset design constraints, the number of signal conditioning units will continue to be increased or decreased successively according to the set quantity change conditions until all signal conditioning units participate in the judgment. When all signal conditioning units participate in the judgment, and in each change of the number of signal conditioning units, the elements in the common path where the inserted load center element is located, as well as the elements adjacent to the load center element in each non-common path connected to the inserted load center element, still cannot meet the preset design constraints, then the timing calculated in each change of the number of signal conditioning units is compared, and the number of signal conditioning units corresponding to the optimal timing is selected as the final number.

[0116] It should be noted that when the inserted load center element is an inverter, the polarity change in the signal transmission path needs to be considered during the insertion of signal conditioning units for the driven object. Since an inverter itself inverts the polarity of the input signal (i.e., a high input level results in a low output level, and a low input level results in a high output level), if the signal conditioning unit inserted between the driven object and the inverter contains inverter-type elements, the signal polarity will change with the number of inserted elements. When the number of inserted inverters is odd, the signal polarity reverses once; when the number of inserted inverters is even, the signal polarity remains unchanged. Failure to correct this polarity change may lead to inconsistencies between the inverter output logic direction and the original design logic, thus affecting the correctness of the circuit function. Therefore, when inserting several signal conditioning units between the driven object and the inserted load center element, the overall polarity change of the signal chain needs to be monitored in real time. If the final output polarity is detected to be inconsistent with expectations, polarity can be corrected by adding or removing an inverter to ensure that the signal polarity at the inverter input is consistent with the circuit design requirements.

[0117] In summary, after completing the optimization design between the driver object to be processed and the inserted load center element, the finally determined load center element is marked. This involves tagging the optimized load center element to ensure that the path from the root node of the clock tree to the load center element is a common path, there are no branches before the load center element, and the load center element is always in the load center position. After marking, conventional clock tree synthesis methods can be used to further adjust and optimize the global clock tree structure to achieve better timing consistency, power consumption control, and routing feasibility globally.

[0118] Therefore, the clock tree synthesis method provided in this application finds the end point of the common path as the driving object to be processed during the clock signal transmission process from the root node of each timing deviation group. A load center element located at the load center position is inserted at the end of the common path. Then, with the constraint of design rules, several signal conditioning units are inserted at equal intervals along the winding path between the driving object to be processed and the load center element to ensure that the maximum transition time of the common path is as small as possible on the basis of low offset. Finally, traditional clock tree synthesis methods such as adjusting the load and adjusting the buffer size are used to achieve low skew with the chip area as small as possible, which is more suitable for clock tree synthesis design of high-performance integrated circuits.

[0119] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0120] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A method of clock tree synthesis, the method comprising: The method comprises the following steps: obtaining a global clock tree of a target circuit, the global clock tree comprising a plurality of timing skew groups, and determining a sub-clock tree corresponding to each timing skew group according to each timing skew group, wherein each sub-clock tree comprises a common path and a plurality of non-common paths branched from the common path, and the common path and the non-common paths comprise a plurality of elements; for each sub-clock tree: determining, in a transmission direction of a clock signal, a path between a root node of the sub-clock tree and a set output pin as the common path, wherein the set output pin is the first output pin connected to a plurality of next-level elements in the transmission direction of the clock signal, and determining the first output pin connected to the plurality of next-level elements as a to-be-processed driving object; selecting a load in each non-common path and calculating a load center position according to a position coordinate of the selected load; in a case where the to-be-processed driving object is not a load center element: inserting a load center element at the load center position; when elements of the common path where the inserted load center element is located and elements adjacent to the inserted load center element in each non-common path connected to the inserted load center element do not satisfy a preset design constraint, setting a plurality of signal adjusting units between the to-be-processed driving object and the inserted load center element to optimize the sub-clock tree; wherein the number of the signal adjusting units is increased or decreased successively according to a set number change condition between the to-be-processed driving object and the inserted load center element, and the timing of the sub-clock tree is calculated each time the number of the signal adjusting units changes; if the elements of the common path where the inserted load center element is located and the elements adjacent to the inserted load center element in each non-common path connected to the inserted load center element do not satisfy the preset design constraint each time the number of the signal adjusting units changes, the number of the signal adjusting units is determined as the number of the signal adjusting units corresponding to the optimal timing of the sub-clock tree in each time the number of the signal adjusting units changes; and the signal adjusting unit comprises a buffer and / or an inverter.

2. The method of clock tree synthesis of claim 1, wherein, The selecting a load in each non-common path comprises: selecting an element directly connected to the to-be-processed driving object in each non-common path, and determining the element directly connected to the to-be-processed driving object as the load.

3. The method of clock tree synthesis of claim 1, wherein, The selecting a load in each non-common path comprises: selecting a last element in the transmission direction of the clock signal of each non-common path connected to the to-be-processed driving object, and determining the last element in each non-common path as the load.

4. The method of clock tree synthesis of claim 1, wherein, The method further comprises determining a module to which the inserted load center element belongs, for determining an electrical characteristic parameter of the inserted load center element and a connection relationship between the inserted load center element and the selected load. The module to which the inserted load center element belongs is the module of the to-be-processed driving object, or the least common module of the module to which the inserted to-be-processed driving object is connected, or a module calculated by setting a calculation mode.

5. The method of clock tree synthesis of claim 4, wherein, When the elements on the common path where the inserted load center element is located and the elements adjacent to the load center element in each non-common path connected with the load center element do not satisfy the preset design constraint, a plurality of signal conditioning units are arranged between the to-be-processed driving object and the inserted load center element, and the method further comprises: calculating the maximum number of signal conditioning units arranged between the to-be-processed driving object and the inserted load center element according to a preset physical constraint condition; judging whether the elements on the common path where the inserted load center element is located and the elements adjacent to the load center element in each non-common path connected with the load center element satisfy the preset design constraint when the number of signal conditioning units changes each time; if yes, the number of signal conditioning units is determined as the number of signal conditioning units of the current time; if no, the signal conditioning units are increased or decreased one by one according to a set number change condition until all the signal conditioning units participate in the judgment.

6. The method of clock tree synthesis of claim 5, wherein, Each signal conditioning unit is placed equidistantly according to a wiring path of the to-be-processed driving object to the inserted load center element.

7. The method of clock tree synthesis of claim 1, wherein, The method of clock tree synthesis further comprises: When the load center position is the coordinate position of the to-be-processed driving object, the to-be-processed driving object is determined as a load center element.

8. A computer-readable storage medium, characterized in that, The medium has stored thereon a computer program, and the computer program can be executed by a processor to implement the method according to any one of claims 1-7.

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