Modular multilevel converter sub-module fault-tolerant operation method and system

Abstract

The embodiment of the application discloses a modular multilevel converter submodule fault tolerance operation method and system. The method comprises the following steps: identifying and processing the submodule fault in the MMC system, adjusting the capacitor voltage of the remaining submodules to ensure the stability of the DC side voltage when the submodule fault occurs; under the condition that the DC side voltage is stable, the AC current tracking is set as the highest priority, the optimal switching sequence is found in the limited control set by establishing a mathematical model and designing a value function; after the current tracking is completed, the interphase circulating current suppression is selected as the secondary target, and the discrete processing and voltage compensation technology are used to minimize the circulating current influence; after the secondary target optimization, the sorting voltage sharing algorithm is implemented, and the input or bypass state of each submodule is monitored and dynamically adjusted in real time. Through the implementation of the method of the embodiment of the application, not only the operation speed is improved, but also an efficient fault tolerance operation scheme is provided for the MMC submodule fault, and the reliability and performance of the system are significantly improved.

Description

Technical Field

[0001] This invention relates to the technical field of modular multilevel converters, and more particularly to a fault-tolerant operation method and system for modular multilevel converter submodules. Background Technology

[0002] Modular multilevel converters (MMCs) are widely used in flexible DC transmission due to their low harmonic distortion, flexible control performance, low energy loss, and ease of voltage and power expansion. However, as the number of submodules in an MMC system increases, the likelihood of failure also rises. In particular, if a submodule failure is not detected and isolated in a timely manner, it will severely impact the reliability of the entire MMC system.

[0003] When an MMC system encounters a single-phase asymmetrical fault, an odd number of circulating currents, especially at the fundamental frequency, will be generated within the faulty phase. These asymmetrical circulating currents not only cause fluctuations in both DC-side and AC-side output currents, affecting power transmission efficiency, but also cause additional fluctuations in the capacitor voltage within the faulty arm, disrupting capacitor voltage balance and reducing system stability and reliability. Therefore, to ensure the stable operation of the MMC system after a submodule failure, it is essential to achieve accurate diagnosis and location of the submodule fault and take measures to disconnect and isolate the faulty submodule to support uninterrupted system operation and enhance system stability and reliability.

[0004] Currently, fault-tolerant operation strategies for MMC systems after submodule failures are mainly divided into two categories: hardware-based methods and software-based correction methods. Hardware methods include techniques such as using redundant submodules or introducing new submodules into the system, but this approach may reduce the versatility of the MMC system. On the other hand, software correction methods mainly maintain the stability of the output line voltage by adjusting the modulation waveform to keep the line voltage constant, modifying the submodule capacitor voltage setting to suppress fault circulating current, or injecting zero-sequence voltage. However, these software methods typically focus only on a single control objective, neglecting the adjustment of other system parameters, which may lead to further system deterioration or even shutdown risks.

[0005] Therefore, it is necessary to design a new method that not only improves the computing speed but also provides an efficient fault-tolerant operation scheme for MMC submodule failures, significantly improving the reliability and performance of the system. Summary of the Invention

[0006] The purpose of this invention is to overcome the shortcomings of the prior art and provide a fault-tolerant operation method and system for modular multilevel converter submodules.

[0007] To achieve the above objectives, the present invention adopts the following technical solution: a fault-tolerant operation method for a modular multilevel converter submodule, comprising:

[0008] Identify and handle submodule faults in the MMC system, and adjust the capacitor voltages of the remaining submodules to ensure the stability of the DC side voltage when a submodule fault occurs;

[0009] With the DC side voltage stable, AC current tracking is set as the highest priority. By establishing a mathematical model and designing a value function, the optimal switching sequence is found within a finite control set.

[0010] After completing current tracking, phase-to-phase circulating current suppression is selected as a secondary objective. Discretization and voltage compensation techniques are used to minimize the impact of circulating current without interfering with current performance.

[0011] After optimizing the secondary objectives, a sorting and equalizing voltage algorithm is implemented to monitor and dynamically adjust the input or bypass status of each submodule in real time to ensure balanced capacitor voltage within the bridge arm.

[0012] The further technical solution is as follows: Identifying and handling submodule faults in the MMC system, and adjusting the capacitor voltages of the remaining submodules to ensure the stability of the DC-side voltage when a submodule fault occurs, includes:

[0013] Identify and handle submodule faults in the MMC system, according to Adjust the rated capacitor voltage of the remaining sub-modules, and adjust the total number of sub-modules to be put into the upper and lower bridge arms of the sub-modules according to the rated capacitor voltage, so that they are no longer equal to the original set value.

[0014] Among them, U cref_pj The voltage of the upper arm submodule is N; the number of upper arm fault submodules is N. fault_pj U cref_nj The voltage of the lower bridge arm submodule is N; the number of faulty lower bridge arm submodules is N. fault_nj U dc This represents the DC power supply voltage, and N represents the number of submodules in each bridge arm. The number of operable submodules in the upper bridge arm becomes NN. fault_pj The number of operable submodules in the lower bridge arm becomes N. fault_nj When N fault_pj =N fault_nj At that time, the maximum number of output levels on the AC side is 2 (NN). fault_pj +1; when N fault_pj ≠N fault_nj At that time, the maximum number of output levels on the AC side is (NN) fault_pj +1) (NN fault_nj +1)-1.

[0015] Its further technical solution is: the mathematical model is The value objective function is ;in, i j_phase [ k +1] indicates the first j Xiangzai k Predicted current at time +1 i j_phase [ k ] is the first j Xiangzai k The actual current at any given moment; T s To control the periodic sampling time; L arm This refers to the inductance value of the bridge arm; u arm_pj [ k +1] indicates the first j The upper bridge arm is k The sum of the voltages of all sub-modules at time +1; u arm_nj [ k +1] indicates the first j The lower bridge arm is k The sum of the voltages of all sub-modules at time +1; u j_phase [ k +1] is the first j Xiangzai k The output phase voltage at time +1; its corresponding objective function Indicates the first j Xiangzai k The reference value of the current at time +1. For the first j Xiangzai k The predicted current value obtained from the prediction model at time +1.

[0016] Its further technical solution is as follows: Under the condition of stable DC-side voltage, AC current tracking is set as the highest priority. By establishing a mathematical model and designing a value function, the optimal switching sequence is found within a finite control set, including:

[0017] When the DC side voltage is stable, set AC current tracking to the highest priority;

[0018] A mathematical model of the output AC current is established using the backward Euler method, and a value objective function is constructed based on this model. The reference value of the AC current is determined by the reference values ​​of active power and reactive power.

[0019] Based on the mathematical model and the value objective function, hierarchical optimization FCS-MPC is implemented to obtain the optimal switching sequence.

[0020] The further technical solution is as follows: the hierarchical optimization FCS-MPC based on the mathematical model and the value objective function to obtain the optimal switching sequence includes:

[0021] Set the weight coefficient of the most important control objective to 1, and the weight coefficient of the rest to 0;

[0022] Based on the mathematical model and the value objective function, optimize the most important objective until the optimal switching sequence is found.

[0023] Its further technical solution is: the optimization of the most important objective based on the mathematical model and the value objective function until the optimal switch sequence is found includes:

[0024] When in a stable fault-tolerant operating state, assuming that the circulating current is completely suppressed, the voltage of the submodule capacitors is equal to the rated value; the reference values ​​of the upper and lower bridge arm voltages are calculated using the reference and predicted values ​​of the AC current.

[0025] Divide the reference voltage values ​​of the upper and lower bridge arms by the rated voltage values ​​of the capacitors of the sub-modules within each bridge arm and round down to obtain the number of sub-modules that should be put into operation.

[0026] Based on the number of sub-modules to be deployed, the relationship between the voltage difference between the upper and lower bridge arms and the capacitor voltage of the sub-modules under different conditions is analyzed to determine the value of the corresponding objective function, and the optimal switching sequence is determined based on the value.

[0027] The further technical solution is as follows: After completing current tracking, interphase circulating current suppression is selected as a secondary objective, and discretization processing and voltage compensation techniques are used to minimize the impact of circulating current without interfering with current performance, including:

[0028] After determining the optimal switching sequence, the next most important targets are selected in sequence according to the set priority order, and further optimization is carried out in the neighborhood of the optimal switching sequence until all targets have been optimized.

[0029] The further technical solution is as follows: After determining the optimal switching sequence, the next most important targets are selected sequentially according to a set priority order, and further optimization is performed within the neighborhood of the optimal switching sequence until all targets have been optimized, including:

[0030] The interphase circulation is discretized by backward Euler and its objective value function is constructed to obtain the mathematical model of the interphase circulation and the objective value function.

[0031] Using the interphase circulating current reference value, the interphase circulating current mathematical model is used to calculate the predicted value of the circulating current at a specified time, and the deviation between the bridge arm voltage and the DC side voltage is calculated.

[0032] Circulating current is suppressed by applying the same voltage compensation to the upper and lower bridge arms, without affecting the AC current value.

[0033] The number of sub-modules to be deployed in the upper and lower bridge arms is determined based on the voltage deviation range in order to optimize system performance.

[0034] The further technical solution is as follows: After secondary objective optimization, a sorting and voltage equalization algorithm is implemented to monitor and dynamically adjust the input or bypass status of each submodule in real time to ensure voltage balance of the capacitors within the bridge arm, including:

[0035] After optimizing the secondary objective, the voltage difference between each submodule is monitored and analyzed in real time using a sorting and equalizing voltage algorithm.

[0036] Prioritize selecting switching operation sequences that help optimize voltage distribution for adjustment;

[0037] Dynamic voltage balance of capacitors is achieved by bypassing high voltage and connecting low voltage submodules.

[0038] The voltage equalization process is synchronized with the control cycle of FCS-MPC.

[0039] This invention also provides a fault-tolerant operation system for modular multilevel converter submodules, including:

[0040] The adjustment unit is used to identify and handle submodule faults in the MMC system, and adjust the capacitor voltage of the remaining submodules to ensure the stability of the DC side voltage when a submodule fault occurs.

[0041] The main objective optimization unit is used to set AC current tracking as the highest priority when the DC side voltage is stable. It finds the optimal switching sequence within a finite control set by establishing a mathematical model and designing a value function.

[0042] The secondary optimization unit is used to select interphase circulating current suppression as a secondary objective after current tracking is completed, and to minimize the impact of circulating current without interfering with current performance by using discretization and voltage compensation techniques.

[0043] The voltage balancing unit is used to implement a sorting and equalizing voltage algorithm after secondary target optimization, monitor and dynamically adjust the input or bypass status of each submodule in real time, and ensure the voltage balance of the capacitors in the bridge arm.

[0044] The advantages of this invention compared to existing technologies are as follows: This invention identifies and handles submodule faults, adjusts the capacitor voltages of remaining submodules to maintain DC-side voltage stability, sets AC current tracking as the highest priority, and uses mathematical models and value functions to quickly find the optimal switching sequence within a finite control set. Subsequently, with phase-to-phase circulating current suppression as a secondary objective, discretization and voltage compensation techniques are used to minimize the impact of circulating current. Finally, a sorting and voltage equalization algorithm is implemented to monitor and dynamically adjust the state of each submodule in real time to ensure balanced capacitor voltages within the bridge arms. This method not only significantly improves computational speed and control efficiency but also effectively achieves efficient fault-tolerant operation for MMC submodule faults, thereby greatly improving the system's reliability and overall performance.

[0045] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. Attached Figure Description

[0046] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the following description of the embodiments will be briefly introduced. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0047] Figure 1 This is a flowchart illustrating the fault-tolerant operation method for a modular multilevel converter submodule provided in an embodiment of the present invention.

[0048] Figure 2 This is a schematic diagram of the FCS-MPC process provided in an embodiment of the present invention;

[0049] Figure 3 This is a topology diagram of an MMC system provided in an embodiment of the present invention;

[0050] Figure 4 The three-phase AC side voltage waveform diagram provided in the embodiment of the present invention;

[0051] Figure 5 Three-phase AC side current waveform diagram provided for embodiments of the present invention

[0052] Figure 6 The three-phase interphase circulating waveform diagram provided in the embodiment of the present invention;

[0053] Figure 7 DC-side current waveform diagram provided for embodiments of the present invention;

[0054] Figure 8 The three-phase bridge arm current waveform diagram provided in the embodiment of the present invention;

[0055] Figure 9 This is a schematic diagram of the Fourier decomposition of the A-phase circulation provided in an embodiment of the present invention;

[0056] Figure 10 This is a schematic diagram of the Fourier decomposition of the B-phase circulation provided in an embodiment of the present invention;

[0057] Figure 11 A schematic diagram of the Fourier decomposition of the C-phase circulation provided in an embodiment of the present invention;

[0058] Figure 12 A schematic diagram of the Fourier decomposition of the DC-side current provided in an embodiment of the present invention;

[0059] Figure 13 A schematic diagram showing the actual and reference values ​​of the three-phase alternating current provided in an embodiment of the present invention;

[0060] Figure 14 A schematic diagram showing the actual and reference values ​​of the submodule capacitor voltage provided in an embodiment of the present invention;

[0061] Figure 15 A schematic diagram of the Fourier decomposition of interphase circulation provided in an embodiment of the present invention;

[0062] Figure 16 A schematic diagram of three-phase interphase circulation provided in an embodiment of the present invention.

[0063] Figure 17 This is a schematic block diagram of a modular multilevel converter submodule fault-tolerant operation system provided in an embodiment of the present invention.

[0064] Figure 18 A schematic block diagram of a computer device provided for an embodiment of the present invention. Detailed Implementation

[0065] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0066] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0067] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0068] It should also be further understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0069] Please see Figure 1 , Figure 1 This is a schematic flowchart illustrating the fault-tolerant operation method for modular multilevel converter (MMC) submodules provided in this invention. This method is applied in a server. By identifying and handling submodule faults, the capacitor voltages of the remaining modules are adjusted to ensure DC-side voltage stability. Based on this stability, AC current tracking is prioritized, followed by interphase circulating current suppression. Finally, a sorting voltage equalization algorithm is implemented to dynamically balance the operational or bypassed states of each submodule. This method utilizes hierarchical optimization FCS-MPC technology combined with a backward Euler method discrete mathematical model and a value objective function to quickly find the optimal switching sequence. Simultaneously, it synchronizes with the control cycle during voltage equalization, significantly improving computational speed and providing an efficient and stable fault-tolerant operation scheme for the MMC system, greatly enhancing system reliability and performance.

[0070] The method in this embodiment aims to improve system reliability, reduce computational burden, and accelerate multi-objective optimization. This scheme introduces an advanced strategy of Finite Control Set Model Predictive Control (FCS-MPC) to achieve an efficient, fault-tolerant operation method.

[0071] The implementation of this method follows four main steps: First, fault modeling is performed and submodule voltages are corrected to ensure that the system can maintain DC-side voltage stability in the event of a fault. Next, AC current tracking is optimized as the primary objective by establishing a mathematical model and designing a value function to find the optimal switching sequence. Then, based on the current tracking, interphase circulating current suppression is set as a secondary objective, and the impact of circulating current is minimized by using discretization processing and voltage compensation techniques. The final step is submodule voltage equalization control, which uses a sorting voltage equalization algorithm to monitor and dynamically adjust the state of each submodule in real time to ensure the balance of capacitor voltages within the bridge arm.

[0072] The fundamental principle of FCS-MPC is based on Model Predictive Control (MPC), a control strategy that combines predictive models, rolling optimization, reference trajectories, and feedback correction. Its core lies in solving the optimal control problem within a finite time frame in real time, generating the best control action at the current moment, and re-optimizing at the next moment to form a closed-loop control. FCS-MPC further optimizes the control set, reducing computational load. Compared to traditional MPC, FCS-MPC uses discrete switching states as control variables, directly enumerating all possible control combinations during optimization to find the optimal control scheme. The entire process includes three key steps: establishing the predictive model, designing the value function, and rolling optimization. The flowchart above is shown below. Figure 2 The diagram illustrates the basic implementation framework of FCS-MPC. This approach not only improves the system's response speed and efficiency but also significantly enhances its reliability and performance.

[0073] Figure 1 This is a flowchart illustrating the fault-tolerant operation method for a modular multilevel converter submodule provided in an embodiment of the present invention. Figure 1 As shown, the method includes the following steps S110 to S140.

[0074] S110. Identify and handle submodule faults in the MMC system, and adjust the capacitor voltages of the remaining submodules to ensure the stability of the DC side voltage when a submodule fault occurs.

[0075] In this embodiment, submodule faults in the MMC system are identified and handled according to... Adjust the rated capacitor voltage of the remaining sub-modules, and adjust the total number of sub-modules to be put into the upper and lower bridge arms of the sub-modules according to the rated capacitor voltage, so that they are no longer equal to the original set value.

[0076] Among them, U cref_pj The voltage of the upper arm submodule is N, and the number of faulty upper arm submodules is N. fault_pj U cref_nj The voltage of the lower bridge arm submodule is N, and the number of faulty lower bridge arm submodules is N. fault_nj The number of operable submodules on the upper bridge arm becomes N. fault_pj The number of operable submodules in the lower bridge arm becomes N. fault_nj U dc This represents the DC bus voltage, and N represents the number of submodules in each bridge arm. When N... fault_pj =N fault_nj At that time, the maximum number of output levels on the AC side is 2 (NN). fault_pj +1; when N fault_pj ≠N fault_nj At that time, the maximum number of output levels on the AC side is (NN) fault_pj +1) (NN fault_nj +1)-1.

[0077] Please see Figure 3 In a three-phase MMC system topology, each phase contains two arms (denoted by p and n respectively), and each arm consists of N sub-modules. arm_xj and i arm_xj These represent the sum of the submodule voltages and the arm current on the j-th phase x-th bridge arm, respectively, where x = p or n, p represents the upper bridge arm, and n represents the lower bridge arm. phase_j Udc represents the phase voltage of the j-th phase output, while Udc is the DC bus voltage.

[0078] When a submodule failure occurs in the MMC system, assuming the number of faulty upper arm submodules is N fault_pj The number of fault submodules in the lower arm is N. fault_nj Accordingly, the number of operable submodules in the upper bridge arm becomes N. fault_pj The lower bridge arm is NN fault_nj To ensure stable DC-side voltage, the voltage ratings of the remaining submodule capacitors need to be adjusted to a specific level. This adjustment is crucial for maintaining the normal operation of the entire system, especially after a submodule failure.

[0079] In this scenario, the total number of upper and lower bridge arm submodules in use will no longer equal the initially set N value. This means that, after considering the impact of faulty submodules, the system needs to dynamically adjust the number of submodules participating in operation in each bridge arm to ensure the system operates as efficiently and stably as possible. This process involves not only the effective management of the remaining healthy submodules but also precise control to compensate for performance degradation caused by faults, thereby achieving fault-tolerant operation of the system. Such a strategy helps improve the overall reliability and stability of the MMC system when facing submodule failures.

[0080] S120. When the DC side voltage is stable, set the AC current tracking as the highest priority, and find the optimal switching sequence within a finite control set by establishing a mathematical model and designing a value function.

[0081] In this embodiment, the optimal switching sequence refers to the set of operation instructions calculated by the hierarchical optimization FCS-MPC method, which guides the engagement sequence of the upper and lower bridge arm sub-modules of the MMC system, based on ensuring the achievement of the primary control objective. It aims to efficiently respond to and meet the dynamic control requirements of the system.

[0082] In MMC (Modular Multilevel Converter) systems, a hierarchical optimization FCS-MPC (Finite Control Set Model Predictive Control) method is employed to achieve effective tracking control of the AC current and ensure the stability of the DC-side voltage. This method simplifies the complex multi-objective optimization problem by setting different priority objective functions, focusing first on the most important control objective and then progressively addressing the less important objectives.

[0083] Specifically, the mathematical model is as follows: The value objective function is .

[0084] in, i j_phase [ k +1] indicates the first j Xiangzai k Predicted current at time +1 i j_phase [ k ] is the first j Xiangzai k The actual current at any given moment; T s To control the periodic sampling time; L arm This represents the inductance value of the bridge arm. u arm_pj [ k +1] indicates the first j The upper bridge arm is k The sum of the voltages of all sub-modules at time +1; u arm_nj [ k +1] indicates the first j The lower bridge arm is k The sum of the voltages of all submodules at time +1. u j_phase [ k +1] is the first j Xiangzai k The output phase voltage at time +1. Its corresponding objective function... Indicates the first j Xiangzai k The reference value of the current at time +1. For the first j Xiangzai k The predicted current value obtained from the prediction model at time +1.

[0085] In one embodiment, step S120 described above may include steps S121 to S123.

[0086] S121. When the DC side voltage is stable, set AC current tracking to the highest priority.

[0087] First, while ensuring DC-side voltage stability, AC current tracking is the highest priority objective in the control system. This means that the main task of the system is to match the actual AC current with the reference value as accurately as possible to meet the system's performance requirements.

[0088] S122. Use the backward Euler method to establish a mathematical model of the output AC current, and construct a value objective function based on it. The reference value of the AC current is determined by the reference values ​​of active power and reactive power.

[0089] Next, a mathematical model of the output AC current is established using the backward Euler method, and a value objective function is constructed based on this model. This value objective function is used to quantify the degree to which the control objective is achieved, where the reference value of the AC current is determined based on the reference values ​​of active and reactive power. This process lays the foundation for subsequent optimization steps.

[0090] S123. Based on the mathematical model and the value objective function, implement hierarchical optimization FCS-MPC to obtain the optimal switching sequence.

[0091] In one embodiment, step S123 described above may include steps S1231 to S1232.

[0092] S1231. Set the weight coefficient of the most important control objective to 1, and the others to 0.

[0093] In this embodiment, the weight coefficient of the most important control objective at the current stage is set to 1, while the weight coefficients of all other control objectives are set to 0. The purpose of this is to concentrate resources on solving the most pressing problem.

[0094] S1232. Based on the mathematical model and the value objective function, optimize the most important objective until the optimal switch sequence is found.

[0095] In one embodiment, step S1232 described above may include steps S12321 to S12323.

[0096] S12321. When in a stable fault-tolerant operating state, assuming that the circulating current is completely suppressed, the voltage of the submodule capacitors is equal to the rated value; calculate the reference values ​​of the voltage of the upper and lower bridge arms using the reference and predicted values ​​of the AC current.

[0097] Assuming the system is in a stable and fault-tolerant operating state, circulating current is completely suppressed, and the voltages of the submodule capacitors are equal to their rated values. Using these conditions, combined with the reference and predicted values ​​of the AC current, the reference values ​​of the voltages of the upper and lower bridge arms can be calculated.

[0098] S12322. Divide the reference voltage values ​​of the upper and lower bridge arms by the rated voltage values ​​of the capacitors of the sub-modules within each bridge arm, and round down to obtain the number of sub-modules to be deployed.

[0099] By dividing the reference voltage values ​​of the upper and lower bridge arms by the rated values ​​of their respective submodule capacitor voltages and rounding down, the number of submodules that should be put into operation for each bridge arm can be obtained.

[0100] S12323. Based on the number of sub-modules to be deployed, analyze the relationship between the voltage difference between the upper and lower bridge arms and the capacitor voltage of the sub-modules under different conditions, so as to determine the value of the corresponding objective function, and determine the optimal switching sequence based on the value.

[0101] Based on the number of submodules to be deployed, the relationship between the voltage difference between the upper and lower bridge arms and the capacitor voltage of the submodules is analyzed under different conditions, thereby determining the optimal switching sequence corresponding to a specific value objective function. This step involves meticulous analysis and calculation to ensure that the primary control objective is met while also considering the needs of other secondary objectives.

[0102] This hierarchical optimization method not only significantly reduces computational burden and improves response speed, but also effectively handles various complex situations that may arise in the system, such as submodule failures. Although this method seeks an approximate optimal solution rather than a globally optimal solution, its effectiveness has been proven in many practical applications.

[0103] Specifically, the hierarchical optimization FCS-MPC control isolates each objective function. First, it selects the most important control objective, setting its weight coefficient to 1, and setting the weight coefficients of the others to 0. Then, after optimizing the most important objective, it obtains the optimal switching sequence. Subsequent control objectives are selected according to priority, and the optimal switching sequence for the next highest priority objective is found within the neighborhood of the optimal switching sequence. This process continues until all objective function values ​​have been optimized. Hierarchical optimization FCS-MPC seeks an approximate optimal solution, not a globally optimal solution, but it significantly reduces computational workload and improves response speed.

[0104] Set the AC current control target to the highest control priority, and use the backward Euler method to obtain the mathematical model of the output AC current as shown in equation (2).

[0105] (2)

[0106] in, i j_phase [ k +1] indicates the first j Xiangzai k Predicted current at time +1 i j_phase [ k] is the first j Xiangzai k The actual current at any given moment; T s To control the periodic sampling time; L arm This represents the inductance value of the bridge arm. u arm_pj [ k +1] indicates the first j The upper bridge arm is k The sum of the voltages of all sub-modules at time +1; u arm_nj [ k +1] indicates the first j The lower bridge arm is k The sum of the voltages of all sub-modules at time +1; u j_phase [ k +1] is the first j Xiangzai k Output phase voltage at time +1.

[0107] Its value objective function is given by equation (3).

[0108] (3)

[0109] in, Indicates the first j Xiangzai k The reference value of the current at time +1. For the first j Xiangzai k The predicted current value obtained from the prediction model at time +1.

[0110] The reference value of the alternating current is derived from the active power reference value P. and reactive power reference value Q Sure.

[0111] (4)

[0112] in, and They represent in k +1 moment α , β Reference values ​​for phase current in the coordinate system; and They represent in k +1 moment α , β The components of phase voltage in the coordinate system; for k A reference value for active power at all times. for kReference value for reactive power at any given time.

[0113] When the system is operating stably and with fault tolerance, it can be assumed that the circulating current is completely suppressed, the capacitor voltages of the submodules on the same bridge arm are equal and equal to the rated value (1), and the DC voltage Udc is equal to the sum of the voltages of the upper and lower bridge arms, that is:

[0114] (5)

[0115] in, U arm_pj [ k ] indicates in k Time of the first j The sum of the voltages of all submodules in the upper bridge arm; U arm_nj [ k ] respectively represent in k Time of the first j The sum of the voltages of all submodules in the lower bridge arm. U dc This represents the DC bus voltage, which is equal to the sum of the voltages of the upper and lower bridge arms. U arm_pj [ k +1] indicates that in k +1 moment j The sum of the voltages of all submodules in the upper bridge arm; U arm_nj [ k +1] indicates that in k +1 moment j The sum of the voltages of all submodules in the lower bridge arm.

[0116] Substituting the AC current reference value at time k (Equation (4)) into the AC current prediction value at time k+1, we can obtain Equation (6) from Equation (2):

[0117] (6)

[0118] in, u arm_pj [ k +1] indicates the first j The upper bridge arm is k The sum of the voltages of all sub-modules at time +1; u arm_nj [ k +1] indicates the first j The lower bridge arm is k The sum of the voltages of all submodules at time +1. L arm This refers to the inductance value of the bridge arm; T s To control the periodic sampling time. ij_phase [ k ] is the first j Xiangzai k The actual current at any given moment; Indicates the first j Xiangzai k Reference value of current at time +1; u j_phase [ k +1] is the first j Xiangzai k Output phase voltage at +1 time; U dc This indicates the DC bus voltage.

[0119] This formula indicates the reference values ​​of the upper and lower bridge arm voltages at time k. When the switching frequency is much greater than the AC power frequency cycle, it is assumed that uj_phase[k+1] = uj_phase[k]. Divide formula (6) by the rated value of the capacitor voltage of each submodule in the respective bridge arm and round down to obtain the number of submodules that should be put into operation.

[0120] (7)

[0121] in, N pj Indicates the first j The number of sub-modules deployed on the upper bridge arm; N nj Indicates the first j The number of sub-modules deployed in the lower bridge arm. u arm_pj [ k +1] indicates the first j The upper bridge arm is k The sum of the voltages of all sub-modules at time +1; u arm_nj [ k +1] indicates the first j The lower bridge arm is k The sum of the voltages of all sub-modules at time +1; U cref_pj Indicates the first j Reference voltage of the capacitor in the upper bridge arm submodule; U cref_nj Indicates the first j The reference voltage of the capacitor in the lower bridge arm submodule.

[0122] The following relationship exists at this point:

[0123] (8)

[0124] in, N pj Indicates the first jThe number of sub-modules deployed on the upper bridge arm; N nj Indicates the first j The number of sub-modules deployed in the lower bridge arm; N Indicates the number of each bridge arm submodule; N fault_pj Indicates the first j Number of faulty submodules in the upper bridge arm; N fault_nj Indicates the first j Number of faulty submodules in the lower bridge arm. u arm_pj Indicates the first j The sum of the voltages of all submodules in the upper bridge arm; u arm_nj Indicates the first j The sum of the voltages of all submodules in the lower bridge arm; U cref_pj Indicates the first j Reference voltage of the capacitor in the upper bridge arm submodule; U cref_nj Indicates the first j The reference voltage of the capacitor in the lower bridge arm submodule.

[0125] It's worth noting:

[0126] (9)

[0127] in, n pj For the first j Normalized voltage scaling factor of the upper bridge arm; n nj For the first j Normalized voltage scaling factor of the lower bridge arm. u arm_pj [ k +1] indicates the first j The upper bridge arm is k The sum of the voltages of all sub-modules at time +1; u arm_nj [ k +1] indicates the first j The lower bridge arm is k The sum of the voltages of all submodules at time +1. N pj Indicates the first j The number of sub-modules deployed on the upper bridge arm; N nj Indicates the first j The number of sub-modules deployed in the lower bridge arm.

[0128] From formula (7), we can see that 0 <n pj <1, 0 <nnj <1.

[0129] At this point, the voltage difference between the upper and lower bridge arms in the MMC system is:

[0130] (10)

[0131] in, u arm_pj [ k +1] indicates the first j The upper bridge arm is k The sum of the voltages of all sub-modules at time +1; u arm_nj [ k +1] indicates the first j The lower bridge arm is k The sum of the voltages of all submodules at time +1. N pj Indicates the first j The number of sub-modules deployed on the upper bridge arm; N nj Indicates the first j The number of sub-modules deployed in the lower bridge arm; n pj For the first j Normalized voltage scaling factor of the upper bridge arm; n nj For the first j Normalized voltage scaling factor of the lower bridge arm. U cref_pj Indicates the first j Reference voltage of the capacitor in the upper bridge arm submodule; U cref_nj Indicates the first j The reference voltage of the capacitor in the lower bridge arm submodule.

[0132] When U cref_nj cref_pj When, if (n nj U cref_nj -n pj U cref_pj > 0.5 U cref_nj At this time, the upper bridge arm should be engaged with N. pj Each sub-module, the lower bridge arm should be equipped with N... nj+1 Sub-modules.

[0133] If 0.5 (U cref_nj - U cref_pj )<(n nj U cref_nj -n pj U cref_pj < 0.5​ U cref_nj At this time, the upper bridge arm should be engaged with N. pj Each sub-module, the lower bridge arm should be equipped with N... nj Sub-modules.

[0134] If 0.5 U cref_nj -U cref_pj <(n nj U cref_nj- n pj U cref_pj <0.5 (U cref_nj -Ucref_pj), at this time the upper bridge arm should be engaged with N. pj +1 submodule, N should be deployed in the lower bridge arm. nj +1 submodule.

[0135] If -U cref_nj <(n nj U cref_nj -n p U cref_pj <0.5 U cref_nj -U cref_pj At this point, the upper bridge arm should have Npj+1 sub-modules and the lower bridge arm should have Nnj sub-modules.

[0136] The summary is shown in Table 1. Similarly, the result when U... cref_nj >U cref_pj At that time, the number of sub-modules that should be put into each bridge arm.

[0137] Table 1. Number of sub-modules to be deployed in the upper and lower bridge arms under the primary priority objective.

[0138]

[0139] in, n pj For the first j Normalized voltage scaling factor of the upper bridge arm; n nj For the first j Normalized voltage scaling factor of the lower bridge arm. U cref_pj Indicates the first j Reference voltage of the capacitor in the upper bridge arm submodule; U cref_nj Indicates the first j Reference voltage of the capacitor in the lower bridge arm submodule; U cref_cn This indicates the rated reference value of the capacitor voltage in the submodule. N pj Indicates the first jThe number of sub-modules deployed on the upper bridge arm; N nj Indicates the first j The number of sub-modules deployed in the lower bridge arm.

[0140] S130. After completing current tracking, phase-to-phase circulating current suppression is selected as a secondary objective. Discretization and voltage compensation techniques are used to minimize the impact of circulating current without interfering with current performance.

[0141] In this embodiment, after determining the optimal switching sequence, the next most important targets are selected in sequence according to the set priority order, and further optimization is performed in the neighborhood of the optimal switching sequence until all targets have been optimized.

[0142] After completing current tracking and ensuring the achievement of the primary control objective, step S130 selects the suppression of interphase circulating current as a secondary optimization objective. This process utilizes discretization and voltage compensation techniques to minimize the impact of circulating current without interfering with the system's current performance.

[0143] In one embodiment, step S130 described above may include steps S131 to S134.

[0144] S131. Perform backward Euler discretization on the interphase circulation and construct its objective value function to obtain the mathematical model of the interphase circulation and the objective value function.

[0145] First, the interphase circulation is discretized using the backward Euler method to construct its objective value function, thereby establishing an accurate mathematical model of the interphase circulation. This step provides a theoretical foundation for subsequent calculations and yields reference values ​​for the interphase circulation.

[0146] S132. Using the interphase circulating current reference value, calculate the predicted circulating current value at a specified time using the interphase circulating current mathematical model, and calculate the deviation between the bridge arm voltage and the DC side voltage.

[0147] In this embodiment, based on the reference value of the interphase circulating current and the corresponding mathematical model, the predicted value of the circulating current at a specified time is calculated (substituting the circulating current reference value at time k to time k+1). Subsequently, the deviation between the bridge arm voltage and the DC side voltage is calculated. This deviation is one of the main reasons for the generation of circulating current within the system.

[0148] S133. Circulating current is suppressed by applying the same voltage compensation to the upper and lower bridge arms without affecting the AC current value.

[0149] In this embodiment, to effectively suppress circulating current without affecting the performance of the alternating current, the same voltage compensation is applied to both the upper and lower bridge arms. This method can significantly reduce or eliminate circulating current without affecting the alternating current.

[0150] S134. Determine the number of sub-modules to be put into the upper and lower bridge arms based on the voltage deviation range to optimize system performance.

[0151] Finally, based on the voltage deviation ranges calculated in the previous step, as shown in Table 2, the number of submodules to be deployed in the upper and lower bridge arms is determined. This strategy not only optimizes system performance but also ensures that voltage deviation is minimized. For example, different submodule deployment strategies are adopted for the upper and lower bridge arms in different voltage deviation ranges to achieve the best system response.

[0152] Through steps S131 to S134, the dynamic response characteristics of the system were further optimized based on the optimal switching sequence. In particular, the influence of interphase circulating current was effectively suppressed, improving the stability and efficiency of the entire system. This process emphasizes the importance of multi-objective optimization and demonstrates how to balance multiple interrelated control objectives in a complex system.

[0153] Specifically, after obtaining the switching sequence that optimizes the objective function of alternating current value, the interphase circulating current is selected as the secondary priority objective. Similarly, backward Euler discretization of the interphase circulating current yields:

[0154] (11)

[0155] in, i cirj [ k +1] indicates the first j Xiangzai k Predicted circulation value at time +1 i cirj [ k ] is the first j Xiangzai k The actual value of the circulation at any given time. T s To control the periodic sampling time; L arm For bridge arm inductance. U dc Indicates the DC bus voltage; u arm_pj [ k +1] indicates the first j The upper bridge arm is k The sum of the voltages of all sub-modules at time +1; u arm_nj [ k +1] indicates the first j The lower bridge arm is k The sum of the voltages of all submodules at time +1.

[0156] Its interphase circulation target value function is given by equation (12).

[0157] (12)

[0158] in, Indicates the first j Xiangzai k The reference circulation value at time +1, For the first j Xiangzai k The circulation prediction value obtained by the prediction model at time +1.

[0159] The reference value of the interphase circulation is calculated using equation (13).

[0160] (13)

[0161] in, This is a reference value for active power. U dc It is a DC voltage.

[0162] Substituting the circulating current reference value at time k (Equation (13)) into the circulating current prediction value at time k+1, the deviation between the bridge arm voltage and the DC side voltage is calculated as follows:

[0163] (14)

[0164] in, u arm_pj [ k +1] indicates the first j The upper bridge arm is k The sum of the voltages of all sub-modules at time +1; u arm_nj [ k +1] indicates the first j The lower bridge arm is k The sum of the voltages of all sub-modules at time +1; U dc It is a DC voltage. i cirj [ k ] indicates the first j Xiangzai k Predicted circulation values ​​at time 10:00. i cirj [ k ] is the first j Xiangzai k The actual value of the circulation at any given time. L arm For bridge arm inductance; T s To control the periodic sampling time.

[0165] The deviation between the bridge arm voltage and the DC side voltage causes circulating current. At the same time, adding the same voltage deviation to the upper and lower bridge arms will not change the AC current value. Therefore, voltage compensation can be applied to the upper and lower bridge arms simultaneously to suppress circulating current.

[0166] (15)

[0167] Where, Δ N pj Indicates the first j The change in the number of submodules that need to be compensated for in the upper bridge arm; Δ N nj Indicates the first j The change in the number of submodules requiring compensation in the lower bridge arm. Δ U Err This indicates the deviation between the sum of the voltages of the upper and lower bridge arms and the DC side voltage; U cref_pj Indicates the first j Reference voltage of the capacitor in the upper bridge arm submodule; U cref_nj Indicates the first j The reference voltage of the capacitor in the lower bridge arm submodule. `floor` represents the floor function.

[0168] Similarly, let

[0169] (16)

[0170] Where, Δ n pj This represents the normalized voltage scaling factor of the upper bridge arm after voltage compensation; Δ n nj This represents the normalized voltage scaling factor of the lower bridge arm after voltage compensation. Δ U Err This indicates the deviation between the sum of the voltages of the upper and lower bridge arms and the DC side voltage; U cref_pj Indicates the first j Reference voltage of the capacitor in the upper bridge arm submodule; U cref_nj Indicates the first j The reference voltage for the capacitor of the lower bridge arm submodule. Δ N pj Indicates the first j The change in the number of submodules for phase upper arm compensation; Δ N nj Indicates the first j The change in the number of sub-modules for the lower bridge arm compensation.

[0171] From formula (15), we can see that, .

[0172] At this point, the deviation between the sum of the voltages of the upper and lower bridge arms and the DC side voltage is:

[0173] (17)

[0174] Where, Δ N pj Indicates the first j The change in the number of submodules for phase upper arm compensation; Δ N nj Indicates the first j The change in the number of submodules for phase lower arm compensation; Δ n pj This represents the normalized voltage scaling factor of the upper bridge arm after voltage compensation; Δ n nj This represents the normalized voltage scaling factor of the lower bridge arm after voltage compensation. U cref_pj Indicates the first j Reference voltage of the capacitor in the upper bridge arm submodule; U cref_nj Indicates the first j Reference voltage of the capacitor in the lower bridge arm submodule; U dc This is the DC bus voltage.

[0175] In order to To reach the minimum, when U cref_nj cref_pj hour:

[0176] If 0.5 U cref_nj + U cref_pj < cref_nj + U cref_pj At this time, the upper bridge arm should be engaged with N. pj +1 submodule, N bridge arm deployed nj +1 submodule.

[0177] If 0.5 (U cref_nj +U cref_pj )< <0.5 U cref_nj +U cref_pj At this time, the upper bridge arm should be engaged with N. pj +1 submodule, N should be deployed in the lower bridge arm. nj Sub-modules.

[0178] If 0.5 U cref_nj < <0.5​​ (U) cref_nj +U cref_pj At this point, the upper bridge arm should be engaged with N. pj Each sub-module, the lower bridge arm should be equipped with N... nj +1 submodule.

[0179] If 0 < <0.5 U cref_nj At this time, the upper bridge arm should be engaged with N. pj Each sub-module, the lower bridge arm should be equipped with N... nj Sub-modules.

[0180] The summary is shown in Table 2. Similarly, the result when U... cref_nj >U cref_pj At that time, the number of sub-modules that should be put into each bridge arm.

[0181] Table 2. Number of sub-modules to be deployed in the upper and lower bridge arms after the secondary priority target is revised

[0182]

[0183] Where, Δ n pj This represents the normalized voltage scaling factor of the upper bridge arm after voltage compensation; Δ n nj This represents the normalized voltage scaling factor of the lower bridge arm after voltage compensation. U cref_pj Indicates the first j Reference voltage of the capacitor in the upper bridge arm submodule; U cref_nj Indicates the first j The reference voltage of the capacitor in the lower bridge arm submodule.

[0184] S140. After optimizing the secondary objective, implement the sorting and equalizing voltage algorithm, monitor and dynamically adjust the input or bypass status of each submodule in real time, and ensure the voltage balance of the capacitors in the bridge arm.

[0185] In one embodiment, step S140 described above may include steps S141 to S144.

[0186] S141. After optimizing the secondary objective, the voltage difference of each submodule is monitored and analyzed in real time using the sorting and equalization algorithm.

[0187] S142. Prioritize selecting switching operation sequences that help optimize voltage distribution for adjustment;

[0188] S143. Dynamic balance of capacitor voltage is achieved by bypassing the high voltage and connecting the low voltage submodule.

[0189] S144. Synchronize the voltage equalization process with the control cycle of FCS-MPC.

[0190] After determining the number of submodules to be deployed in each bridge arm, to further improve the stability and reliability of the system operation, it is necessary to balance the capacitor voltages of the submodules within the bridge arm. This invention employs a traditional sorting voltage equalization algorithm, which collects voltage data from each submodule in real time, determines voltage differences, and prioritizes the selection of switching sequences that can improve voltage distribution. The specific implementation is as follows:

[0191] High voltage bypass, low voltage input: Submodules with higher voltage are bypassed first to avoid overvoltage damage; submodules with lower voltage are input first to ensure that the capacitor voltage of all submodules is kept within a reasonable range.

[0192] Synchronous execution of FCS-MPC control cycle: This balancing process can be executed synchronously with the FCS-MPC (Finite Control Set - Model Predictive Control) control cycle, thereby achieving fast response and simple implementation, while not affecting the fault-tolerant operation control performance of the system.

[0193] The method in this embodiment comprehensively considers multiple objectives such as AC current tracking, interphase circulating current suppression, and submodule capacitor voltage equalization, aiming to achieve the MMC (Modular Multilevel Converter) system operating in a multi-objective optimal asymmetric operating state from a macroscopic perspective.

[0194] Compared to traditional MPC control strategies, the finite number of control sets significantly reduces computational complexity. Each rolling optimization search for the optimal solution only requires traversing the finite control set, eliminating the need to solve complex quadratic programming problems. The hierarchical optimization FCS-MPC strategy avoids the complex design issues of weights among multiple objectives; each rolling optimization only requires traversing eight switch combinations to find the optimal switch sequence, simplifying computation.

[0195] The method in this embodiment employs a hierarchically optimized FCS-MPC algorithm, which significantly reduces the computational load. This method not only improves the computational speed but also significantly enhances the system's fault-tolerant operation capability after a submodule failure.

[0196] The innovative application of the FCS-MPC method solves the problem of insufficient fault-tolerant operation capability of existing MMC systems after submodule failure, and provides a highly efficient, optimized, and computationally simple system fault-tolerant operation solution. This provides strong support for fault-tolerant operation of MMC systems after fault diagnosis, and promotes the development and application of modular multilevel converter technology.

[0197] In summary, the method presented in this embodiment comprehensively considers multiple key indicators of the MMC system, achieving overall optimal control. By employing hierarchical optimization and the application of finite control sets, the calculation process is greatly simplified, and computational efficiency is improved. This provides a novel solution that helps improve the reliability and performance of MMC systems, while also offering new ideas and methods for research and applications in related fields.

[0198] For example, a simulation case of fault-tolerant operation of an MMC system submodule after failure was built based on the Simulink simulation environment. The simulation parameters are shown in Table 3.

[0199] Table 3 MMC Simulation Model Parameters

[0200]

[0201] like Figures 4 to 8 The figure shows the simulation waveforms of the MMC system under normal operation and after a submodule failure and submodule disconnection, where the number of submodules N=22 and the number of hot-standby submodules N0 hot =0, at 0.7s, a submodule of the upper arm of phase A malfunctions and is disconnected, N fault_pa =1, N fault_na =0.

[0202] like Figure 4 and Figure 5 The output voltage and current waveforms are shown for the three-phase AC side. Figure 6 The waveform diagram shows the three-phase interphase circulating current. Before the fault time of 0.7s, the circulating current is dominated by the second harmonic component. After the fault occurs and the submodule is disconnected, the three phases are no longer balanced, and the upper and lower bridge arms in the fault phase are also no longer balanced, resulting in a large fundamental frequency circulating current. A certain fundamental frequency circulating current component also appears in the non-faulty phases (phase B and phase C).

[0203] Figure 7 The waveform of the DC side current is shown. After the fault occurs in 0.7s, due to the imbalance of the MMC system, the fundamental frequency component of the bridge arm current will also flow through the DC side, which will cause the DC side current to fluctuate at the fundamental frequency. Figure 8 For the three-phase bridge arm current, the fundamental frequency component also appears in the faulty phase.

[0204] Figures 9 to 12 The Fourier decompositions of the three-phase interphase circulating current and DC-side current in the MMC flexible DC converter valve system before and after a submodule failure are shown. It can be observed that after the failure, the fundamental frequency components of all variables increase significantly, consistent with the aforementioned theoretical analysis.

[0205] like Figure 13The actual and reference values ​​of the three-phase AC current are given. At 0.8s, the active power suddenly increases from 0.6MW to 1MW. The simulation shows that the three-phase AC current tracking effect is very good, and it can also track well when the reference current changes abruptly.

[0206] like Figure 14 The voltage value of the submodule capacitor is shown in the simulation. It can be seen that the voltage equalization effect is good. When the power increases, the voltage fluctuation of the submodule capacitor also increases.

[0207] like Figure 15 The Fourier decomposition of the interphase circulation is mainly composed of second harmonic waves.

[0208] like Figure 16 The diagram shows the interphase circulating current when a single-phase asymmetrical fault occurs. The system experiences a fault at 0.7s and performs FCS-MPC fault-tolerant control at 0.9s. The simulation shows that the circulating current THD of the MMC system during fault-tolerant operation is 1.71%, which is very effective in suppressing the circulating current.

[0209] The aforementioned fault-tolerant operation method for modular multilevel converter (MMC) submodules identifies and handles submodule faults, adjusts the capacitor voltages of remaining submodules to maintain DC-side voltage stability, and prioritizes AC current tracking. It then uses mathematical models and value functions to quickly find the optimal switching sequence within a finite control set. Subsequently, with phase-to-phase circulating current suppression as a secondary objective, it minimizes the impact of circulating current using discretization and voltage compensation techniques. Finally, it implements a sorting and voltage equalization algorithm to monitor and dynamically adjust the state of each submodule in real time to ensure balanced capacitor voltages within the bridge arms. This method not only significantly improves computational speed and control efficiency but also effectively achieves efficient fault-tolerant operation for MMC submodule faults, thereby greatly enhancing system reliability and overall performance.

[0210] Figure 17 This is a schematic block diagram of a modular multilevel converter submodule fault-tolerant operation system 300 provided in an embodiment of the present invention. Figure 17 As shown, corresponding to the above-described modular multilevel converter submodule fault-tolerant operation method, this invention also provides a modular multilevel converter submodule fault-tolerant operation system 300. This modular multilevel converter submodule fault-tolerant operation system 300 includes a unit for executing the above-described modular multilevel converter submodule fault-tolerant operation method, and this system can be configured in a server. Specifically, please refer to... Figure 17 The modular multilevel converter submodule fault-tolerant operation system 300 includes an adjustment unit 301, a primary target optimization unit 302, a secondary optimization unit 303, and a voltage balancing unit 304.

[0211] The adjustment unit 301 is used to identify and handle submodule faults in the MMC system, and adjust the capacitor voltages of the remaining submodules to ensure the stability of the DC-side voltage when a submodule fault occurs. The main objective optimization unit 302 is used to set AC current tracking as the highest priority when the DC-side voltage is stable, and to find the optimal switching sequence within a finite control set by establishing a mathematical model and designing a value function. The secondary optimization unit 303 is used to select interphase circulating current suppression as a secondary objective after completing current tracking, and to minimize the impact of circulating current without interfering with current performance by using discretization processing and voltage compensation technology. The voltage balancing unit 304 is used to implement a sorting voltage equalization algorithm after the secondary objective optimization, and to monitor and dynamically adjust the on or off status of each submodule in real time to ensure the capacitor voltage balance within the bridge arm.

[0212] In one embodiment, the adjustment unit 301 is used to identify and handle submodule faults in the MMC system, according to... Adjust the rated capacitor voltage of the remaining sub-modules, and adjust the total number of sub-modules to be put into the upper and lower bridge arms of the sub-modules according to the rated capacitor voltage, so that they are no longer equal to the original set value.

[0213] Among them, U cref_pj The voltage of the upper arm submodule is N; the number of upper arm fault submodules is N. fault_pj U cref_nj The voltage of the lower bridge arm submodule is N; the number of faulty lower bridge arm submodules is N. fault_nj U dc This represents the DC power supply voltage, and N represents the number of submodules in each bridge arm. The number of operable submodules in the upper bridge arm becomes NN. fault_pj The number of operable submodules in the lower bridge arm becomes N. fault_nj When N fault_pj =N fault_nj At that time, the maximum number of output levels on the AC side is 2 (NN). fault_pj +1; when N fault_pj ≠N fault_nj At that time, the maximum number of output levels on the AC side is (NN) fault_pj +1) (NN fault_nj +1)-1.

[0214] In one embodiment, the main objective optimization unit 302 includes:

[0215] The system includes a setting subunit for setting AC current tracking as the highest priority when the DC side voltage is stable; a first establishment subunit for establishing a mathematical model of the output AC current using the backward Euler method and constructing a value objective function based on this model, wherein the reference value of the AC current is determined by the reference values ​​of active power and reactive power; and a first optimization subunit for implementing hierarchical optimization FCS-MPC based on the mathematical model and the value objective function to obtain the optimal switching sequence.

[0216] In one embodiment, the first optimization subunit is used to set the weight coefficient of the most important control objective to 1 and the rest to 0; based on the mathematical model and the value objective function, the most important objective is optimized until the optimal switching sequence is found.

[0217] In one embodiment, the first optimization subunit includes:

[0218] The first calculation module is used to calculate the reference values ​​of the upper and lower bridge arm voltages under stable fault-tolerant operation, assuming that the circulating current is completely suppressed and the submodule capacitor voltages are equal and equal to the rated values. The second calculation module is used to divide the reference values ​​of the upper and lower bridge arm voltages by the rated values ​​of the submodule capacitor voltages in their respective bridge arms and then round down to obtain the number of submodules that should be put into operation. The third calculation module is used to analyze the relationship between the voltage difference between the upper and lower bridge arms and the submodule capacitor voltages under different conditions based on the number of submodules that should be put into operation, in order to determine the value of the corresponding objective function, and to determine the optimal switching sequence based on the value.

[0219] In one embodiment, the secondary optimization unit 303 is used to select the next most important target in sequence according to a set priority order after determining the optimal switching sequence, and perform further optimization in the neighborhood of the optimal switching sequence until all targets have been optimized.

[0220] In one embodiment, the secondary optimization unit 303 includes:

[0221] The second construction subunit is used to perform backward Euler discretization on the interphase circulating current and construct its objective value function to obtain the interphase circulating current mathematical model and the objective value function; the deviation calculation subunit is used to calculate the predicted value of the circulating current at a specified time using the interphase circulating current reference value and the interphase circulating current mathematical model, and to calculate the deviation between the bridge arm voltage and the DC side voltage; the compensation subunit is used to suppress the circulating current by applying the same amount of voltage compensation to the upper and lower bridge arms without affecting the AC current value; the optimization subunit is used to determine the number of sub-modules to be put into the upper and lower bridge arms according to the voltage deviation range to optimize the system performance.

[0222] In one embodiment, the voltage equalization unit 304 includes:

[0223] The sorting and equalizing subunit is used to monitor and analyze the voltage differences of each submodule in real time using the sorting and equalizing algorithm after secondary objective optimization; the adjustment subunit is used to prioritize the selection of switching operation sequences that help optimize voltage distribution for adjustment; the balancing subunit is used to achieve dynamic balance of capacitor voltage by bypassing high-voltage and connecting low-voltage submodules; and the synchronization subunit is used to synchronize the voltage equalization process with the control cycle of FCS-MPC.

[0224] It should be noted that those skilled in the art can clearly understand that the specific implementation process of the above-mentioned modular multilevel converter submodule fault-tolerant operation system 300 and each unit can be referred to the corresponding description in the foregoing method embodiments. For the sake of convenience and brevity, it will not be repeated here.

[0225] The aforementioned modular multilevel converter submodule fault-tolerant operation system 300 can be implemented as a computer program, which can be used in, for example... Figure 18 It runs on the computer device shown.

[0226] Please see Figure 18 , Figure 18 This is a schematic block diagram of a computer device provided in an embodiment of this application. The computer device 500 can be a server, wherein the server can be a standalone server or a server cluster composed of multiple servers.

[0227] See Figure 18 The computer device 500 includes a processor 502, a memory, and a network interface 505 connected via a system bus 501. The memory may include a non-volatile storage medium 503 and internal memory 504.

[0228] The non-volatile storage medium 503 may store an operating system 5031 and a computer program 5032. The computer program 5032 includes program instructions that, when executed, cause the processor 502 to perform a fault-tolerant operation method for a modular multilevel converter submodule.

[0229] The processor 502 provides computing and control capabilities to support the operation of the entire computer device 500.

[0230] The internal memory 504 provides an environment for the operation of the computer program 5032 in the non-volatile storage medium 503. When the computer program 5032 is executed by the processor 502, the processor 502 can execute a fault-tolerant operation method for a modular multilevel converter submodule.

[0231] This network interface 505 is used for network communication with other devices. Those skilled in the art will understand that... Figure 18The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the computer device 500 to which the present application is applied. The specific computer device 500 may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0232] The processor 502 is used to run the computer program 5032 stored in the memory to implement all the steps of the modular multilevel converter submodule fault-tolerant operation method.

[0233] It should be understood that in the embodiments of this application, the processor 502 may be a central processing unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor may be a microprocessor or any conventional processor.

[0234] It will be understood by those skilled in the art that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program includes program instructions and can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the embodiments of the above methods.

[0235] Therefore, the present invention also provides a storage medium. This storage medium can be a computer-readable storage medium. The storage medium stores a computer program, wherein when executed by a processor, the computer program causes the processor to perform all steps of the modular multilevel converter submodule fault-tolerant operation method.

[0236] The storage medium can be any computer-readable storage medium capable of storing program code, such as a USB flash drive, portable hard drive, read-only memory (ROM), magnetic disk, or optical disk.

[0237] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of this invention.

[0238] In the embodiments provided by this invention, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative. For example, the division of each unit is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.

[0239] The steps in the method of this invention can be adjusted, merged, or reduced in order according to actual needs. The units in the system of this invention can be merged, divided, or reduced according to actual needs. Furthermore, the functional units in the various embodiments of this invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0240] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a storage medium. Based on this understanding, the technical solution of the present invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, a terminal, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention.

[0241] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A fault-tolerant operation method for a modular multilevel converter submodule, characterized in that, include: Identify and handle submodule faults in the MMC system, and adjust the capacitor voltages of the remaining submodules to ensure the stability of the DC side voltage when a submodule fault occurs; With the DC side voltage stable, AC current tracking is set as the highest priority. By establishing a mathematical model and designing a value function, the optimal switching sequence is found within a finite control set. After completing current tracking, phase-to-phase circulating current suppression is selected as a secondary objective. Discretization and voltage compensation techniques are used to minimize the impact of circulating current without interfering with current performance. After optimizing the secondary objectives, a sorting and equalizing voltage algorithm is implemented to monitor and dynamically adjust the input or bypass status of each submodule in real time to ensure the voltage balance of the capacitors in the bridge arm. Under the condition of stable DC-side voltage, AC current tracking is set as the highest priority. The optimal switching sequence is found within a finite control set by establishing a mathematical model and designing a value function, including: When the DC side voltage is stable, set AC current tracking to the highest priority; A mathematical model of the output AC current is established using the backward Euler method, and a value objective function is constructed based on this model. The reference value of the AC current is determined by the reference values ​​of active power and reactive power. Based on the mathematical model and the value objective function, hierarchical optimization FCS-MPC is implemented to obtain the optimal switching sequence; The step of implementing hierarchical optimization FCS-MPC based on the mathematical model and the value objective function to obtain the optimal switching sequence includes: Set the weight coefficient of the most important control objective to 1, and the weight coefficient of the rest to 0; Based on the mathematical model and the value objective function, optimize the most important objective until the optimal switch sequence is found; After completing current tracking, interphase circulating current suppression is selected as a secondary objective. Discretization and voltage compensation techniques are used to minimize the impact of circulating current without interfering with current performance. This includes: After determining the optimal switching sequence, the next most important targets are selected in order of priority and further optimized in the neighborhood of the optimal switching sequence until all targets have been optimized. The hierarchical optimization FCS-MPC control isolates each value objective function. First, the most important control objective is selected and its weight coefficient is set to 1, while the weight coefficients of the others are set to 0. Then, after the most important objective is controlled to the optimal, the optimal switching sequence is obtained. Subsequent control objectives are selected according to priority order. The optimal switching sequence of the second priority objective is found in the neighborhood of the optimal switching sequence, and so on, until all objective value functions are optimized.

2. The fault-tolerant operation method for a modular multilevel converter submodule according to claim 1, characterized in that, The process of identifying and handling submodule faults in the MMC system, and adjusting the capacitor voltages of the remaining submodules to ensure the stability of the DC-side voltage when a submodule fault occurs, includes: Identify and handle submodule faults in the MMC system, according to Adjust the rated capacitor voltage of the remaining sub-modules, and adjust the total number of sub-modules to be put into the upper and lower bridge arms of the sub-modules according to the rated capacitor voltage, so that they are no longer equal to the original set value. Among them, U cref_pj The voltage of the upper arm submodule is N; the number of upper arm fault submodules is N. fault_pj U cref_nj The voltage of the lower bridge arm submodule is N; the number of faulty lower bridge arm submodules is N. fault_nj U dc Represents the DC power supply voltage, and N represents the number of submodules in each bridge arm; the number of operable submodules in the upper bridge arm becomes NN. fault_pj The number of operable submodules in the lower bridge arm becomes N. fault_nj When N fault_pj =N fault_nj At that time, the maximum number of output levels on the AC side is 2 (NN). fault_pj +1; when N fault_pj ≠N fault_nj At that time, the maximum number of output levels on the AC side is (NN) fault_pj +1) (NN fault_nj +1)-1.

3. The fault-tolerant operation method for a modular multilevel converter submodule according to claim 1, characterized in that, The mathematical model is as follows: The value objective function is ; in, i j_phase [ k +1] indicates the first j Xiangzai k Predicted current at time +1 i j_phase [ k ] is the first j Xiangzai k The actual current at any given moment; T s To control the periodic sampling time; L arm This refers to the inductance value of the bridge arm; u arm_pj [ k +1] indicates the first j The upper bridge arm is k The sum of the voltages of all sub-modules at time +1; u arm_nj [ k +1] indicates the first j The lower bridge arm is k The sum of the voltages of all sub-modules at time +1; u j_phase [ k +1] is the first j Xiangzai k The output phase voltage at time +1; its corresponding objective function Indicates the first j Xiangzai k The reference value of the current at time +1. For the first j Xiangzai k The predicted current value obtained from the prediction model at time +1.

4. The fault-tolerant operation method for a modular multilevel converter submodule according to claim 1, characterized in that, The optimization of the most important objective based on the mathematical model and the value objective function until the optimal switch sequence is found includes: When in a stable fault-tolerant operating state, assuming that the circulating current is completely suppressed, the voltage of the submodule capacitors is equal to the rated value; the reference values ​​of the upper and lower bridge arm voltages are calculated using the reference and predicted values ​​of the AC current. Divide the reference voltage values ​​of the upper and lower bridge arms by the rated voltage values ​​of the capacitors of the sub-modules within each bridge arm and round down to obtain the number of sub-modules that should be put into operation. Based on the number of sub-modules to be deployed, the relationship between the voltage difference between the upper and lower bridge arms and the capacitor voltage of the sub-modules under different conditions is analyzed to determine the value of the corresponding objective function, and the optimal switching sequence is determined based on the value.

5. The fault-tolerant operation method for a modular multilevel converter submodule according to claim 1, characterized in that, After determining the optimal switching sequence, the next most important targets are selected sequentially according to a set priority order for further optimization within the neighborhood of the optimal switching sequence, until all targets have been optimized. This includes: The interphase circulation is discretized by backward Euler and its objective value function is constructed to obtain the mathematical model of the interphase circulation and the objective value function. Using the interphase circulating current reference value, the interphase circulating current mathematical model is used to calculate the predicted value of the circulating current at a specified time, and the deviation between the bridge arm voltage and the DC side voltage is calculated. Circulating current is suppressed by applying the same voltage compensation to the upper and lower bridge arms, without affecting the AC current value. The number of sub-modules to be deployed in the upper and lower bridge arms is determined based on the voltage deviation range in order to optimize system performance.

6. The fault-tolerant operation method for a modular multilevel converter submodule according to claim 5, characterized in that, After optimizing the secondary objective, a sorting and voltage equalization algorithm is implemented to monitor and dynamically adjust the input or bypass status of each submodule in real time, ensuring voltage balance within the bridge arm capacitors. This includes: After optimizing the secondary objective, the voltage difference between each submodule is monitored and analyzed in real time using a sorting and equalizing voltage algorithm. Prioritize selecting switching operation sequences that help optimize voltage distribution for adjustment; Dynamic voltage balance of capacitors is achieved by bypassing high voltage and connecting low voltage submodules. The voltage equalization process is synchronized with the control cycle of FCS-MPC.

7. A modular multilevel converter submodule fault-tolerant operation system, characterized in that, The system uses the modular multilevel converter submodule fault-tolerant operation method as described in any one of claims 1 to 6, including: The adjustment unit is used to identify and handle submodule faults in the MMC system, and adjust the capacitor voltage of the remaining submodules to ensure the stability of the DC side voltage when a submodule fault occurs. The main objective optimization unit is used to set AC current tracking as the highest priority when the DC side voltage is stable. It finds the optimal switching sequence within a finite control set by establishing a mathematical model and designing a value function. The secondary optimization unit is used to select interphase circulating current suppression as a secondary objective after current tracking is completed, and to minimize the impact of circulating current without interfering with current performance by using discretization and voltage compensation techniques. The voltage balancing unit is used to implement a sorting and equalizing voltage algorithm after secondary target optimization, monitor and dynamically adjust the input or bypass status of each submodule in real time, and ensure the voltage balance of the capacitors in the bridge arm.

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