Epitaxial structure of GaN HEMT (High Electron Mobility Transistor) with low specific conduction resistivity and preparation method thereof

Abstract

The invention relates to an epitaxial structure of a low-specific on-resistivity GaN HEMT and a preparation method thereof, and the preparation method comprises the steps: S1, sequentially growing an initial layer, a buffer layer, a channel layer, a first insertion layer, a first barrier layer, a second insertion layer and a second barrier layer on a substrate from bottom to top, and obtaining a thick barrier epitaxial wafer; s2, preparing a hard mask layer, patterning and etching the hard mask layer, then transferring the hard mask layer to the upper surface of the thick barrier epitaxial wafer, and etching the thick barrier epitaxial wafer to the upper surface of the second insertion layer; s3, secondarily growing a p-GaN layer on the upper surface of the second insertion layer in the gate region; and S4, removing the polycrystalline GaN in a non-gate region, depositing metal on the p-GaN layer to manufacture a gate, and depositing metal on two sides of the structure to manufacture a source and a drain respectively. By selectively growing the p-GaN layer in the grid region, two-dimensional electron gas in a channel is effectively exhausted, and the carrier concentration of the region below the grid is remarkably reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor process, in particular to a low specific on-resistance GaN HEMT epitaxial structure and a preparation method thereof. BACKGROUND

[0002] Gallium nitride (GaN) is very suitable for manufacturing high-efficiency power switching devices due to its high critical breakdown field and relatively large carrier mobility compared with Si materials. This stimulates the development of advanced GaN components.

[0003] A conventional GaN high electron mobility transistor (GaN HEMT) still has a high concentration of two-dimensional electron gas (2DEG) in the channel without any bias, and the conventional AlGaN / GaN HEMT device is a depletion-mode device. The HEMT is in an on state without voltage between the gate and the source, and is in an off state if a negative voltage is applied to the gate. If the device is misdirected in the case of loss of gate signal, a short circuit of the circuit will be caused, so it is rarely used directly in the circuit. Because of the requirements for circuit reliability and safety, the HEMT is turned off without voltage between the gate and the source, and is turned on with positive voltage, so the normally-off GaN HEMT, also called enhancement-mode GaN HEMT, is a more conventional and mainstream GaN power device.

[0004] At present, the enhancement-mode HEMT has p-GaN gate and recessed gate schemes. However, the p-GaN HEMT on the market has the defects of large specific on-resistance and dynamic resistance degradation at high frequency; the recessed gate enhancement-mode GaN HEMT also has the problem of gate dielectric reliability. SUMMARY

[0005] Based on the above description, the present application provides a low specific on-resistance GaN HEMT epitaxial structure and a preparation method thereof, aiming to reduce the process difficulty of etching process steps, improve the within-chip uniformity and inter-chip reliability, and finally realize the complementary scheme of recessed gate enhancement-mode and p-GaN enhancement-mode.

[0006] The technical solution of the present application to solve the above technical problems is as follows: The present application provides a preparation method of a low specific on-resistance GaN HEMT epitaxial structure, comprising: S1. growing a starting layer, a buffer layer, a channel layer, a first insertion layer, a first barrier layer, a second insertion layer and a second barrier layer on a substrate from bottom to top to obtain a thick barrier epitaxial wafer; S2. preparing a hard mask layer, defining a gate region on the hard mask layer, and after patterning and etching the gate region of the hard mask layer, transferring the hard mask layer to the upper surface of the thick barrier epitaxial wafer, and etching the thick barrier epitaxial wafer to the upper surface of the second insertion layer; S3. growing a p-GaN layer on the upper surface of the second insertion layer in the gate region by a low-temperature molecular beam epitaxy process; S4. removing the polycrystalline GaN in the non-gate region, depositing a metal on the p-GaN layer to form a gate after the horizontal GaN HEMT process, and depositing a metal on both sides of the structure to form a source and a drain, respectively.

[0007] Further, in step S1, the first insertion layer is an AlN layer or an AlGaN layer, the first barrier layer is an AlGaN layer, the second insertion layer is an AlN layer or an AlGaN layer, and the second barrier layer is an AlGaN layer.

[0008] Further, in the first insertion layer, the Al content is not less than 40%, and in the second insertion layer, the Al content is not less than 40%.

[0009] Further, in step S1, the thickness of the first insertion layer is 0-2 nm, the thickness of the first barrier layer is 1 nm-20 nm, the thickness of the second insertion layer is 1 nm-4 nm, and the thickness of the second barrier layer is 1 nm-20 nm.

[0010] Further, in step S1, the substrate is a p-type conductive silicon wafer or a top silicon conductive SOI wafer.

[0011] Further, the channel layer is an i-GaN layer.

[0012] Further, in step S1, a cap layer is also grown on the second barrier layer, and the cap layer is a GaN layer or a SiN layer.

[0013] Further, in step S4, when the polycrystalline GaN in the non-gate region is removed, the hard mask layer is also removed.

[0014] Further, the thickness of the cap layer is 1 nm-3 nm.

[0015] The application further provides a low specific on-resistance GaN HEMT epitaxial structure prepared by the preparation method of the low specific on-resistance GaN HEMT epitaxial structure.

[0016] Compared with the prior art, the technical scheme of the application has the following beneficial technical effects: (1) In the technical scheme of the present application, by selectively growing a p-GaN layer in the gate region, a p-GaN / AlGaN heterojunction structure is formed, effectively depleting the two-dimensional electron gas (2DEG) in the channel, significantly reducing the carrier concentration in the region below the gate; by optimizing the interface characteristics through the double insertion layer (AlN) and the double barrier layer structure, the dislocation and interface state density are reduced; at the same time, the p-GaN layer grown by low-temperature molecular beam epitaxy (LT-MBE) has higher crystal quality and better interface integrity, effectively suppressing the charge trapping effect, thereby alleviating the dynamic resistance degradation problem under high frequency, and improving the stability and efficiency of the device in high-frequency, high-power density application scenarios.

[0017] (2) Compared with the recessed gate enhancement mode HEMT, which needs to be etched to the vicinity of the channel layer and deposit the gate dielectric, there are problems such as many interface defects of the gate dielectric / semiconductor, high risk of breakdown, poor process repeatability, etc. The present application does not need deep trench etching, and the p-GaN regrowth is located on the second insertion layer, the interface is controllable, the thermal stability is good, and the main channel layer is not damaged, which fundamentally avoids the reliability problems such as gate leakage and threshold voltage drift caused by recessed gate, and improves the stability of the device during long-term operation.

[0018] (3) The scheme of using MBE secondary epitaxy p-GaN process to realize enhancement mode GaN HEMT power device adopts a thick barrier layer structure, the channel electrons are farther away from the surface of the barrier layer, and there is no etching damage on the surface of the barrier layer above the channel layer, so the device has better high-frequency dynamic characteristics; using GaN low-damage etching process, the structure described is easier to prepare a recess in the gate region, and the secondary epitaxy p-GaN realizes enhancement mode, and the low-damage etching interface can be repaired before secondary epitaxy, and in this scheme, the gate does not need gate dielectric, the threshold voltage stability and consistency of the gate are improved, so that the good HEMT two-dimensional electron gas is less degraded, the risk of crack of the epitaxial wafer is low, and the p-GaN grown by MBE does not need subsequent activation treatment. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 It is a process schematic diagram of the p-GaN gate scheme in the prior art; Figure 2 It is a process schematic diagram of the recessed gate scheme in the prior art; Figure 3 It is a process schematic diagram of an embodiment of the preparation method of the epitaxial structure of the low specific on-resistance GaN HEMT in the present application; Figure 4 It is a TEM detection result graph of the epitaxial structure of the low specific on-resistance GaN HEMT provided by embodiment 1 in the present application. DETAILED DESCRIPTION

[0020] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0022] Gallium nitride (GaN) is well-suited for manufacturing high-efficiency power switching devices compared to silicon due to its high critical breakdown electric field and relatively large carrier mobility. This has spurred the development of advanced GaN devices.

[0023] Conventional gallium nitride high electron mobility transistors (GaN HEMTs) still exhibit a high concentration of two-dimensional electron gas (2DEG) in the channel even without any bias voltage, making them depletion-mode devices. When no voltage is applied between the gate and source, the HEMT is in the on state; when a negative voltage is applied to the gate, it is off. If the device is mistakenly turned on due to gate signal loss, it can cause a short circuit, thus limiting its direct use in circuits. Due to requirements for circuit reliability and safety, normally-off HEMTs, which are off when no voltage is applied between the gate and source and turn on when a positive voltage is applied, are called enhancement-mode GaN HEMTs and are the more conventional and mainstream GaN power devices.

[0024] Currently, enhancement-mode HEMTs include p-GaN gate and grooved gate schemes. p-GaN gate schemes include... Figure 1 As shown, adding a p-GaN layer between the gate metal and the AlGaN layer raises the conduction band of the gate region above the Fermi level and puts the device into enhancement mode, increasing the threshold voltage (V0). t Typically in the range of 1.0 V-2.0 V, dynamic resistance degradation is prone to occur at high frequencies; the 2DEG charge density in E-mode devices usually needs to be reduced to achieve a certain Vth, resulting in a larger 2DEG sheet resistance; reducing the 2DEG charge density by thinning the AlGaN barrier layer brings the 2DEG closer to the interface, making the dynamic characteristics more susceptible to interface defects and resulting in poor dynamic performance; during the processing, the p-GaN needs to be etched away, which inevitably causes etching loss to the AlGaN barrier layer, and the defect states lead to even worse dynamic performance.

[0025] Groove gate scheme, such as Figure 2As shown, the recessed gate enhancement scheme is realized by using a two-step method, i.e., the method of regrowing the barrier layer, which is essentially a MISFET scheme. To achieve good gate regulation, the gate dielectric layer needs to be relatively thin, which poses a great problem for the reliability of the gate dielectric. In addition, due to the existence of a large number of interface defects between GaN and the dielectric layer, the recessed E-mode device has not yet been mass-produced.

[0026] To solve the above problems, the previous patents CN120264802A and CN120239293A disclose a method for reducing the specific on-resistance of an enhancement-mode GaN HEMT. Based on the previous p-GaN scheme, the method proposes to form a gate recess by using an AlGaN barrier layer low-damage etching process, and then to realize an enhancement-mode GaN HEMT by using an MBE regrowth p-GaN process, which is expected to significantly reduce the specific on-resistance and improve the dynamic performance of the device. However, after in-depth research, there is still room for improvement in this scheme. One of the key technical difficulties in the previous scheme is to achieve low-damage controllable depth etching of the barrier layer recessed gate region, and to improve the within-wafer uniformity and wafer-to-wafer reliability.

[0027] In view of this, in the prior art Figure 3 The present application provides a method for preparing an epitaxial structure of a low-specific on-resistance GaN HEMT, comprising: S1. Growing, from bottom to top, a starting layer, a buffer layer, a channel layer, a first insertion layer, a first barrier layer, a second insertion layer and a second barrier layer on a substrate to obtain a thick-barrier epitaxial wafer; S2. Preparing a hard mask layer, defining a gate region on the hard mask layer, and then transferring the hard mask layer to the upper surface of the thick-barrier epitaxial wafer after patterning and etching the gate region of the hard mask layer to the upper surface of the second insertion layer; S3. Using a low-temperature molecular beam epitaxy process to regrow a p-GaN layer on the upper surface of the second insertion layer in the gate region; S4. Removing the polycrystalline GaN in the non-gate region, and then depositing metal on the p-GaN layer to make a gate electrode, and depositing metal on both sides of the structure to make a source electrode and a drain electrode, respectively, to obtain the low-specific on-resistance GaN HEMT.

[0028] In the technical solution of the application, the p-GaN layer is selectively grown in the gate region to form a p-GaN / AlGaN heterojunction structure, effectively depleting the two-dimensional electron gas (2DEG) in the channel, and significantly reducing the carrier concentration in the region below the gate; the interface characteristics are optimized by the double insertion layer (AlN) and the double barrier layer structure to reduce the dislocation and interface state density; at the same time, the p-GaN layer grown by low-temperature molecular beam epitaxy (LT-MBE) has higher crystal quality and better interface integrity, effectively suppressing the charge trapping effect, thereby alleviating the dynamic resistance degradation problem under high frequency, and improving the stability and efficiency of the device in high-frequency and high-power density application scenarios. Compared with the recessed gate enhanced HEMT which needs to be etched to the vicinity of the channel layer and deposit the gate dielectric, there are many problems such as high risk of breakdown, poor process repeatability, and many interface defects of gate dielectric / semiconductor, the present application does not need deep trench etching, the p-GaN regrowth is located on the second insertion layer, the interface is controllable, the thermal stability is good, and the main channel layer is not damaged, which fundamentally avoids the reliability problems such as gate leakage and threshold voltage drift caused by recessed gate, and improves the stability of the device during long-term operation.

[0029] The scheme for realizing the enhanced GaN HEMT power device by MBE secondary epitaxy p-GaN process adopts a thick barrier layer structure, the channel electrons are farther away from the surface of the barrier layer, and there is no etching damage on the surface of the barrier layer above the channel layer, so that the device has better high-frequency dynamic characteristics; the GaN low-damage etching process is used to prepare the gate region recess more easily by using the described structure, and the secondary epitaxy p-GaN realizes enhancement, the low-damage etching interface can be repaired before secondary epitaxy, and the gate does not need gate dielectric in the scheme, so that the threshold voltage stability and consistency of the gate are improved, the degradation of the grown HEMT two-dimensional electron gas is small, the risk of crack of the epitaxial wafer is low, and the MBE grown p-GaN does not need subsequent activation treatment.

[0030] The dielectric etching is used to realize the opening of the hard mask in the gate region, and the secondary epitaxy p-GaN realizes enhancement on this basis, the etching surface can be repaired before secondary epitaxy, and the gate does not need gate dielectric in the scheme, so that the reliability of the gate is improved, and the stability of the device is further improved.

[0031] Further, in step S1, the first insertion layer is an AlN layer or an AlGaN layer, the first barrier layer is an AlGaN layer, the second insertion layer is an AlN layer or an AlGaN layer, and the second barrier layer is an AlGaN layer.

[0032] In the technical solution of the present application, the first barrier layer and the second barrier layer both adopt AlGaN material, and the AlN or AlGaN layer of the first insertion layer and the second insertion layer is combined to form a double polarization induction structure; the AlN insertion layer has strong spontaneous polarization and piezoelectric polarization effect, and can significantly enhance the polarization charge density at the AlGaN / AlN / GaN interface, thereby greatly improving the concentration of 2DEG in the channel and improving the on-current capability of the device; by introducing the AlN or AlGaN insertion layer (especially AlN) between the channel layer and the barrier layer, the interface band offset can be effectively adjusted, a steeper band gradient is formed, which is beneficial to the transfer of electrons from the barrier layer to the channel and reduces the scattering effect.

[0033] Further, in the first insertion layer, the Al content is not less than 40%; in the second insertion layer, the Al content is not less than 40%.

[0034] In the technical solution of the present application, the first insertion layer and the second insertion layer both adopt AlGaN or AlN material with high Al content, which can greatly enhance the spontaneous polarization and piezoelectric polarization intensity in the AlGaN / insertion layer / GaN heterostructure; the high Al component leads to greater band discontinuity and stronger polarization charge accumulation, thereby inducing a higher density of two-dimensional electron gas in the channel region, effectively improving the on-current capability of the device, reducing the on-resistance per unit area, and realizing lower specific on-resistance.

[0035] Preferably, when the first insertion layer is Al x Ga 1-x N, x≥0.4; when the second insertion layer is Al x Ga 1-x N, x≥0.4.

[0036] Further, in step S1, the thickness of the first insertion layer is 0-2 nm, the thickness of the first barrier layer is 1 nm-20 nm, the thickness of the second insertion layer is 1 nm-4 nm, and the thickness of the second barrier layer is 1 nm-20 nm.

[0037] In the technical solution of the application, the thickness of the first insertion layer is controlled within 2 nm to avoid cracks or three-dimensional island growth of the AlN layer itself, ensure the continuity of epitaxy and the flatness of the interface, and prevent stress accumulation and dislocation proliferation caused by the over-thick insertion layer; the thickness of the first barrier layer is controlled within 20 nm to ensure the formation of a complete and continuous heterojunction interface, avoid island growth leading to uneven 2DEG, and enhance the electrostatic shielding capability of the channel, the breakdown voltage and the gate control stability of the device without significantly increasing the parasitic resistance; the thickness of the second insertion layer is controlled within 4 nm to effectively limit the contribution of the layer to the overall structure stress, avoid cracks or warping caused by the over-thick high-Al component layer, and prevent the over-modulation of the channel energy band and the influence on the 2DEG mobility of the source and drain ends; and the thickness of the second barrier layer is controlled within 20 nm to form a "double-barrier" structure with the first barrier layer, further enhance the polarization charge density, and optimize the energy band by thickness matching to reduce electron scattering and improve transport efficiency.

[0038] It should be noted that in a specific structure, the thickness of the first insertion layer is 0, so that the first insertion layer is omitted, and the structure is simplified.

[0039] Further, in step S1, the substrate is a p-type conductive silicon wafer or a top-silicon conductive SOI wafer.

[0040] In the technical solution of the application, the p-type silicon substrate has a certain hole concentration, and in the GaN epitaxial growth process, the buffer layer structure can be designed appropriately to effectively block the leakage of electrons from the active region to the substrate and reduce the reverse leakage current; when the top-silicon conductive SOI substrate is used, the core advantage lies in that a buried oxygen layer (SiO2) is embedded in the middle to achieve complete electrical isolation between the device and the substrate.

[0041] Further, the channel layer is an i-GaN layer.

[0042] In the technical solution of the application, the intrinsic GaN channel has a pure surface and a low defect density, which is beneficial to the epitaxial growth of high-quality AlN insertion layers or AlGaN barrier layers thereon to form an atomically flat heterojunction interface.

[0043] Further, in step S1, a cap layer is also grown on the second barrier layer, and the cap layer is a GaN layer or a SiN layer.

[0044] In the technical solution of the application, the GaN cap layer or the SiN cap layer is introduced as the last epitaxial layer, which can effectively isolate the AlGaN barrier layer from the external environment and prevent oxidation and carbon contamination of the AlGaN barrier layer during the cooling process after high-temperature growth and the interval period of subsequent processes.

[0045] Further, in step S4, the polycrystalline GaN in the non-gate region is removed, and the hard mask layer is also removed at the same time.

[0046] In the technical solution of the present application, the hard mask layer is removed so as to directly deposit a passivation layer on the surface of GaN and AlGaN, form a tighter chemical bond, and significantly enhance the adhesion and interface stability.

[0047] It should be noted that if the hard mask medium has been considered as a passivation layer, the above steps can not be performed.

[0048] Further, the thickness of the cap layer is 1 nm-3 nm.

[0049] In the technical solution of the present application, by controlling the thickness to be within 3 nm, the stress can be in a releasable range, and structural failure can be avoided; if the cap layer is too thick, stress accumulation will cause the wafer to warp, crack or dislocation proliferation, which will seriously affect the device yield and reliability.

[0050] The present application also provides a low specific on-resistance GaN HEMT epitaxial structure prepared according to the preparation method of the low specific on-resistance GaN HEMT epitaxial structure as described above.

[0051] Since the low specific on-resistance GaN HEMT epitaxial structure of the present application adopts all the technical solutions of the above embodiments, it at least has all the beneficial effects brought by the technical solutions of the above embodiments, which will not be repeated here.

[0052] The technical solution of the present application will be further described in detail below in combination with specific embodiments, and it should be understood that the following embodiments are only used to explain the present application and do not limit the present application.

[0053] The materials and reagents used in the following embodiments can be obtained from commercial channels unless otherwise specified.

[0054] Example 1 The present embodiment provides a low specific on-resistance GaN HEMT epitaxial structure, which is prepared according to the preparation method of the low specific on-resistance GaN HEMT epitaxial structure as described above. Figure 3 The preparation method is as follows: S1. Growing a starting layer, a buffer layer, a channel layer, a first AlN insertion layer (space 1), a first AlGaN barrier layer (barrier 1), a second AlN insertion layer (space 2) and a second AlGaN barrier layer (barrier 2) on the substrate in sequence from bottom to top to obtain a thick barrier epitaxial wafer; The thickness of the first AlN insertion layer is 0-2 nm, the thickness of the first AlGaN barrier layer is 1 nm-20 nm, the thickness of the second AlN insertion layer is 1 nm-4 nm, and the thickness of the second AlGaN barrier layer is 1 nm-20 nm.

[0055] S2. A hard mask layer is prepared, a gate region is defined on the hard mask layer, and after the gate region of the hard mask is patterned and etched, the hard mask layer is transferred to the upper surface of the thick barrier epitaxial wafer, and the thick barrier epitaxial wafer is etched to the upper surface of the second AlN insertion layer; S3. A p-GaN layer is grown on the upper surface of the second AlN insertion layer in the gate region by using a low-temperature molecular beam epitaxy process; S4. The polycrystalline GaN in the non-gate region is removed, and after the horizontal GaN HEMT process is completed, a metal is deposited on the p-GaN layer to form a gate, and a metal is deposited on both sides of the structure to form a source and a drain, respectively.

[0056] TEM detection is performed on the epitaxial structure of the low specific on-resistance GaN HEMT provided in Embodiment 1, and the results are shown in FIG. 2. Figure 4 Obviously, the etching depth stops on the second AlN insertion layer, indicating that the second AlN insertion layer proposed in Embodiment 1 can effectively block etching.

[0057] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

[0058] In summary, the technical solution of the present application has the following beneficial technical effects: (1) In the technical solution of the present application, the p-GaN layer is selectively grown in the gate region to form a p-GaN / AlGaN heterojunction structure, which effectively depletes the two-dimensional electron gas (2DEG) in the channel and significantly reduces the carrier concentration in the region below the gate. The interface characteristics are optimized by the double insertion layer (AlN) and the double barrier layer structure to reduce the dislocation and interface state density. At the same time, the p-GaN layer grown by low-temperature molecular beam epitaxy (LT-MBE) has higher crystal quality and better interface integrity, effectively suppressing the charge trapping effect, thereby alleviating the dynamic resistance degradation problem under high frequency, and improving the stability and efficiency of the device in high-frequency and high-power density application scenarios.

[0059] (2) Compared with the recessed gate enhanced HEMT, the problems of high risk of breakdown, poor process repeatability and many interface defects of gate dielectric / semiconductor exist due to etching to the vicinity of the channel layer and depositing the gate dielectric, the p-GaN regrowth is located on the second insertion layer in the present application, the interface is controllable, the thermal stability is good, and the main channel layer is not damaged, which fundamentally avoids the reliability problems of gate leakage, threshold voltage drift and the like caused by the recessed gate, and improves the stability of long-term operation of the device.

[0060] (3) The scheme of the enhanced GaN HEMT power device is realized by using the MBE secondary epitaxy p-GaN process, a thick barrier layer structure is adopted, the channel electrons are farther away from the surface of the barrier layer, and there is no etching damage on the surface of the barrier layer above the channel layer, the device has better high-frequency dynamic characteristics; the GaN low-damage etching process is used to prepare the recessed gate of the gate region more easily by using the structure described above, the secondary epitaxy p-GaN realizes the enhancement, the low-damage etching interface can be repaired before the secondary epitaxy, and the gate does not need the gate dielectric in the scheme, the stability and consistency of the gate threshold voltage are improved, so that the good HEMT two-dimensional electron gas is less degraded, the risk of crack of the epitaxial wafer is low, and the p-GaN grown by MBE does not need subsequent activation treatment.

Claims

1. A method for fabricating an epitaxial structure of GaN HEMT with low specific on-resistivity, characterized in that, include: S1. A starting layer, a buffer layer, a channel layer, a first insertion layer, a first barrier layer, a second insertion layer, and a second barrier layer are grown sequentially from bottom to top on the substrate to obtain a thick barrier epitaxial wafer. S2. Prepare a hard mask layer, define a gate region on the hard mask layer, pattern and etch the gate region of the hard mask layer, transfer the hard mask layer to the upper surface of the thick barrier epitaxial wafer, and etch the thick barrier epitaxial wafer to the upper surface of the second insertion layer. S3. A p-GaN layer is grown a second time on the upper surface of the second insertion layer in the gate region using a low-temperature molecular beam epitaxy process; S4. After removing the non-gate region of polycrystalline GaN and fabricating the horizontal GaN HEMT process, deposit metal on the p-GaN layer to form the gate, and deposit metal on both sides of the structure to form the source and drain, respectively, to obtain the desired structure.

2. The method for fabricating the epitaxial structure of a low specific on-resistivity GaN HEMT according to claim 1, characterized in that, In step S1, the first insertion layer is an AlN layer or an AlGaN layer, the first barrier layer is an AlGaN layer, the second insertion layer is an AlN layer or an AlGaN layer, and the second barrier layer is an AlGaN layer.

3. The method for fabricating the epitaxial structure of a low specific resistivity GaN HEMT according to claim 2, characterized in that, In the first insertion layer, the Al content is not less than 40%; in the second insertion layer, the Al content is not less than 40%.

4. The method for fabricating the epitaxial structure of a low specific on-resistivity GaN HEMT according to claim 2, characterized in that, In step S1, the thickness of the first insertion layer is 0-2 nm, the thickness of the first barrier layer is 1 nm-20 nm, the thickness of the second insertion layer is 1 nm-4 nm, and the thickness of the second barrier layer is 1 nm-20 nm.

5. The method for fabricating the epitaxial structure of a low specific on-resistivity GaN HEMT according to claim 1, characterized in that, In step S1, the substrate is a p-type conductive silicon wafer or a top-silicon conductive SOI wafer.

6. The method for fabricating the epitaxial structure of a low specific on-resistivity GaN HEMT according to claim 1, characterized in that, The channel layer is an i-GaN layer.

7. The method for fabricating the epitaxial structure of a low specific on-resistivity GaN HEMT according to claim 1, characterized in that, In step S1, a cap layer is also grown on the second barrier layer, which is a GaN layer or a SiN layer.

8. The method for fabricating the epitaxial structure of a low specific on-resistivity GaN HEMT according to claim 7, characterized in that, The thickness of the cap layer is 1 nm to 3 nm.

9. The method for fabricating the epitaxial structure of a low specific on-resistivity GaN HEMT according to claim 1, characterized in that, In step S4, when removing the polycrystalline GaN in the non-gate region, the hard mask layer is also removed.

10. An epitaxial structure of a GaN HEMT with low specific on-resistivity, characterized in that, The epitaxial structure of low specific on-resistivity GaN HEMT was prepared according to any one of claims 1 to 9.

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