Method for preparing metal silicide, semiconductor device and method for preparing the same

Abstract

This disclosure discloses a method for preparing metal silicides, a semiconductor device, and the same method. The method includes: preparing a substrate, a gate structure, and a substrate protective layer, wherein the substrate protective layer is located in the active region of the substrate; the gate structure includes, from bottom to top, a metal work function layer for regulating the gate threshold voltage and a gate protective layer for protecting the gate structure; using a contact hole process, etching the substrate protective layer with an etching gas to form a first contact hole with its bottom located in the active region; and forming metal silicides in the active region using the first contact hole as a reaction window. The scheme of this disclosure simplifies the steps in the gate sidewall thickening process and the wet gate sidewall thinning process, thereby solving the problem of voids in the interlayer insulating dielectric layer and reducing the risk of device bridging. Simultaneously, it avoids damage to the metal silicides and gate structure caused by the chemical solutions used in the wet gate sidewall thinning process, thereby reducing the risk of poor device contact and device failure.

Description

Technical Field

[0001] This disclosure generally relates to the field of semiconductor device fabrication technology. More specifically, this disclosure relates to a method for preparing metal silicides, a semiconductor device fabrication method, and a semiconductor device. Background Technology

[0002] With the continuous development of integrated circuit manufacturing technology, in order to improve the integration density of integrated circuits, increase device operating speed, and reduce power consumption, the feature size of semiconductor processes is constantly shrinking. This has led to a corresponding reduction in the size of the gate, source, and drain structures in semiconductor devices, while their equivalent series resistance increases accordingly, thus affecting the operating speed of integrated circuits. To improve the equivalent series resistance, metal silicide technology has emerged.

[0003] To improve the equivalent series resistance of the drain structure region (active region) and the contact resistance of the contact holes, metal silicide processes are used to form metal silicides in the active region of semiconductor devices. In existing semiconductor device fabrication processes, the metal silicide process precedes the metal gate process and is achieved through a metal silicide barrier layer process. To prevent excessive diffusion of metal silicides from causing leakage risks, existing metal silicide barrier layer processes reduce the reaction window of the metal silicides through gate sidewall thickening. Furthermore, to prevent voids during interlayer dielectric filling, an additional wet gate sidewall thinning process is required after metal silicide formation and before interlayer dielectric filling to expand the filling window of the interlayer dielectric layer.

[0004] However, thickening the gate sidewall leads to insufficient cleaning window for the metal silicide, resulting in unreacted metal silicide residues on the device surface, which can cause short circuits or open circuits in the contact holes. While expanding the cleaning window through wet gate sidewall thinning can solve the problem of residual defects on the device surface, the cleaning chemicals can easily erode the high-dielectric material in the gate structure along the weak side of the gate sidewall, causing device failure. At the same time, the chemicals in the wet gate sidewall thinning process can also erode the oxide layer on the surface of the metal silicide, causing metal silicide loss and increasing the risk of poor device contact.

[0005] In view of this, there is an urgent need to provide a metal silicide preparation scheme to simplify the gate sidewall thickening process and the wet gate sidewall thinning process, so as to eliminate the defects and risks caused by the above processes and improve the yield of semiconductor devices. Summary of the Invention

[0006] In order to at least address one or more of the technical problems mentioned above, this disclosure proposes metal silicide preparation schemes in several aspects.

[0007] In a first aspect, this disclosure provides a method for preparing a metal silicide, comprising: preparing a substrate, a gate structure, and a substrate protective layer, wherein the substrate protective layer is located in the active region of the substrate, and the gate structure comprises: a metal work function layer for regulating the gate threshold voltage and a gate protective layer for protecting the gate structure, which are disposed sequentially from bottom to top; using a contact hole process, etching the substrate protective layer by an etching gas to form a first contact hole with its bottom located in the active region; and forming a metal silicide in the active region using the first contact hole as a reaction window.

[0008] In some embodiments, the substrate protective layer includes: a first protective layer and a second protective layer disposed sequentially from bottom to top, wherein the first protective layer and the second protective layer are made of different compounds; the gate protective layer includes: a third protective layer and a fourth protective layer disposed sequentially from bottom to top, wherein the third protective layer and the fourth protective layer are made of different compounds, and the fourth protective layer and the first protective layer are made of the same compound; the etching gas includes: a first etching gas and a second etching gas; and etching the substrate protective layer with the etching gas using a contact hole process to form a first contact hole with its bottom located in the active region includes: etching the second protective layer with the first etching gas using a contact hole process; and etching the first protective layer with the second etching gas using a contact hole process to form a first contact hole with its bottom located in the active region.

[0009] In some embodiments, the first etching gas is an etching gas with a high selectivity to the compound used in the second protective layer, and the second etching gas is an etching gas with a high selectivity to the compound used in the first protective layer.

[0010] In some embodiments, the first protective layer is a first silicon nitride layer, the second protective layer is a first silicon oxide layer, the third protective layer is a second silicon oxide layer, and the fourth protective layer is a second silicon nitride layer. The first silicon nitride layer and the first silicon oxide layer are disposed sequentially from bottom to top in the active region of the substrate, and the metal work function layer, the second silicon oxide layer, and the second silicon nitride layer are disposed sequentially from bottom to top to form a gate structure.

[0011] In some embodiments, etching the second protective layer with a first etching gas includes: etching a first silicon oxide layer with an etching gas having a high selectivity to silicon oxide; etching the first protective layer with a second etching gas to form a first contact hole in the active region of the substrate includes: etching a first silicon nitride layer with an etching gas having a high selectivity to silicon nitride to form a first contact hole in the active region of the substrate.

[0012] In some embodiments, fabricating a substrate, a gate structure, and a substrate protective layer includes: fabricating a semiconductor substrate structure, the semiconductor substrate structure including: a substrate, a dummy gate structure located above the substrate, a first protective layer, and a second protective layer; and sequentially filling the dummy gate structure with a metal work function layer, a third protective layer, and a fourth protective layer to form a gate structure.

[0013] In some embodiments, sequentially filling a dummy gate structure with a metal work function layer, a third protective layer, and a fourth protective layer to form a gate structure includes: sequentially depositing and growing a metal work function layer, a third protective layer, and a fourth protective layer over a semiconductor substrate structure; and using a chemical mechanical polishing process to remove the metal work function layer, the third protective layer, and the fourth protective layer over a second protective layer, so that the top surfaces of the gate structure and the second protective layer are flush.

[0014] In some embodiments, after removing the metal work function layer, the third protective layer, and the fourth protective layer above the second protective layer using a chemical mechanical polishing process, the method further includes depositing and growing an interlayer insulating dielectric layer on the top surface of the gate structure and the second protective layer, wherein the interlayer insulating dielectric layer and the second protective layer are made of the same compound.

[0015] In some embodiments, etching the second protective layer with a first etching gas includes etching an interlayer insulating dielectric layer and a second protective layer with a first etching gas to form a first contact hole with its bottom located in the first protective layer.

[0016] In some embodiments, fabricating a semiconductor substrate structure includes: fabricating a substrate; fabricating a polysilicon gate over the substrate; sequentially depositing and growing a first protective layer and a second protective layer in the active region of the substrate; and removing the polysilicon from the polysilicon gate to form a pseudo-gate structure.

[0017] In a second aspect, this disclosure provides a method for fabricating a semiconductor device, comprising: fabricating a substrate, a gate structure, and a substrate protective layer, wherein the substrate protective layer is located in the active region of the substrate, and the gate structure comprises: a metal work function layer for regulating the gate threshold voltage and a gate protective layer for protecting the gate structure, which are sequentially disposed from bottom to top; using a contact hole process, etching the substrate protective layer with an etching gas to form a first contact hole with its bottom located in the active region; using the first contact hole as a reaction window, forming a metal silicide in the active region; etching away the gate protective layer to form a second contact hole with its bottom located in the metal work function layer; and filling the first and second contact holes with metal to form a semiconductor device having metal vias.

[0018] In some embodiments, the substrate protection layer includes: a first protection layer and a second protection layer disposed sequentially from bottom to top, wherein the first protection layer and the second protection layer are made of different compounds; the gate protection layer includes: a third protection layer and a fourth protection layer disposed sequentially from bottom to top, wherein the third protection layer and the fourth protection layer are made of different compounds, and the fourth protection layer and the first protection layer are made of the same compound; the etching gas includes: a first etching gas and a second etching gas; etching the substrate protection layer with the etching gas using a contact hole process to form a first contact hole with its bottom located in the active region includes: etching the second protection layer with the first etching gas using a contact hole process; and etching the first protection layer and the fourth protection layer with the second etching gas using a contact hole process to form a first contact hole with its bottom located in the active region and a second contact hole with its bottom located in the third protection layer; etching away the gate protection layer to form a second contact hole with its bottom located in the metal work function layer includes: etching away the third protection layer to form a second contact hole with its bottom located in the metal work function layer.

[0019] In some embodiments, fabricating a substrate, a gate structure, and a substrate protective layer includes: fabricating a semiconductor substrate structure, the semiconductor substrate structure including: a substrate, a dummy gate structure located above the substrate, a first protective layer, and a second protective layer; sequentially filling the dummy gate structure with a metal work function layer, a third protective layer, and a fourth protective layer to form a gate structure; depositing and growing an interlayer insulating dielectric layer on the top surface of the gate structure and the second protective layer, the interlayer insulating dielectric layer and the second protective layer using the same compound; etching the second protective layer with a first etching gas includes: etching the interlayer insulating dielectric layer and the second protective layer with a first etching gas to form a first contact hole with its bottom located in the first protective layer and a second contact hole with its bottom located in the fourth protective layer.

[0020] In a third aspect, this disclosure provides a semiconductor device prepared by performing the semiconductor device preparation method as described in the second aspect.

[0021] The unexpected technical effect of this invention is that, through the method for preparing metal silicides provided above, the gate structure is prepared before the metal silicide is formed, including the preparation of the substrate protective layer located in the active region of the substrate. Since it is not necessary to thicken the gate sidewalls before preparing the metal silicide, the interlayer insulating dielectric layer can have sufficient filling windows, effectively avoiding the generation of voids and reducing the risk of device bridging. Simultaneously, since the gate sidewalls are not thickened, a wet gate sidewall thinning process is not required during the above preparation process, and the metal silicide will not be lost due to the chemical solutions used in the wet gate sidewall thinning process, effectively reducing the risk of poor device contact. After the interlayer insulating dielectric layer is filled, the present invention forms a first contact hole using a contact hole process as a reaction window for the active region metal silicide. During the preparation of the first contact hole, the gate structure can be effectively protected by the gate protective layer, thereby ensuring the integrity of the interlayer insulating dielectric layer and the gate structure, and enabling the metal silicide to be precisely formed in the active region of the substrate. The first contact hole can also provide a sufficient cleaning process window for residual metal silicides, and the hole wall of the first contact hole can also effectively prevent excessive diffusion of metal silicides in the active region and protect the sidewalls of the gate structure, thereby eliminating the defects and device failure risks of unreacted metal silicide residues, and thus improving the yield of semiconductor devices. Attached Figure Description

[0022] The above and other objects, features, and advantages of exemplary embodiments of this disclosure will become readily apparent upon reading the following detailed description with reference to the accompanying drawings. In the drawings, several embodiments of this disclosure are illustrated by way of example and not limitation, and like or corresponding reference numerals denote like or corresponding parts, wherein:

[0023] Figure 1 A schematic diagram of the existing metal silicide process flow is shown;

[0024] Figure 2 An exemplary flowchart of a method for preparing metal silicides according to some embodiments of this disclosure is shown;

[0025] Figure 3 An exemplary flowchart of a method for preparing metal silicides according to other embodiments of this disclosure is shown;

[0026] Figure 4 A schematic diagram illustrating the metal silicide preparation process of some embodiments of this disclosure is shown;

[0027] Figure 5 An exemplary flowchart of a method for preparing metal silicides according to further embodiments of this disclosure is shown;

[0028] Figure 6An exemplary flowchart of a method for preparing metal silicides according to some embodiments of the present disclosure is shown;

[0029] Figure 7 A schematic diagram illustrating the metal silicide preparation process of some other embodiments of this disclosure is shown;

[0030] Figure 8 An exemplary flowchart of a semiconductor device fabrication method according to some embodiments of this disclosure is shown;

[0031] Figure 9 An exemplary flowchart of a semiconductor device fabrication method according to some embodiments of this disclosure is shown;

[0032] Figure 10 An exemplary flowchart of a semiconductor device fabrication method according to other embodiments of this disclosure is shown;

[0033] Figure 11 A schematic diagram of the semiconductor device fabrication process according to some embodiments of this disclosure is shown. Detailed Implementation

[0034] The technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this disclosure, not all of them. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0035] It should be understood that the terms “comprising” and “including” used in this disclosure and claims indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.

[0036] It should also be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this disclosure. As used in this disclosure and claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used in this disclosure and claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes such combinations.

[0037] As used in this specification and claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if [described condition or event] is detected" may be interpreted, depending on the context, as "once determined," "in response to determination," "once [described condition or event] is detected," or "in response to detection of [described condition or event]."

[0038] The specific embodiments disclosed herein will now be described in detail with reference to the accompanying drawings.

[0039] Exemplary application scenarios

[0040] In existing metal silicide processes, in order to prevent excessive diffusion of metal silicides during the thermal process, which could lead to device leakage, the gate sidewalls need to be thickened to reduce the reaction window of the metal silicides. After the metal silicides are formed, a wet gate sidewall thinning process is also required to facilitate the subsequent filling of the interlayer insulating dielectric layer.

[0041] Figure 1 A schematic diagram of a conventional metal silicide process flow is shown. In step A, the gate sidewall 101 is thickened to reduce the reaction window of the metal silicide, and metal silicide 102 is formed on substrate 105 under the reduced reaction window. However, thickening the gate sidewall reduces the filling space of the interlayer insulating dielectric layer, resulting in voids in the interlayer insulating dielectric layer. This causes metal to fill into the voids during subsequent processes, creating a risk of device bridging. To reduce the risk of device bridging, in step B, the conventional process adds an additional wet gate sidewall thinning process before filling the interlayer insulating dielectric layer, thereby expanding the filling window of the interlayer insulating dielectric layer. Then, step C is performed, where the etch stop layer 104 and the interlayer insulating dielectric layer 103 are deposited and grown sequentially, thereby reducing the risk of void formation.

[0042] However, the chemicals used in wet gate sidewall thinning processes can erode metal silicides, causing silicide loss and posing a risk of poor contact in subsequent contact hole processes. Furthermore, gate sidewall thickening processes result in insufficient cleaning windows for metal silicides, leaving unreacted metal silicide residues on the device surface. If cleaning is performed after wet gate sidewall thinning, the cleaning chemicals can easily erode the high-dielectric material in the gate structure along the weak sidewall path, causing device failure.

[0043] In other words, while the combination of gate sidewall thickening and wet gate sidewall thinning processes can ensure the precise formation of metal silicides in the active region of the substrate and prevent void defects in the interlayer insulating dielectric layer, it may affect the integrity of the gate structure, leading to the risk of bridging, poor contact and device failure.

[0044] Exemplary application scheme

[0045] In view of this, the present disclosure provides a metal silicide preparation scheme, which realizes the preparation of metal silicide through contact hole process, reduces the risk of device leakage caused by excessive diffusion of metal silicide, simplifies the gate sidewall thickening process and wet gate sidewall thinning process, thereby preventing chemical solutions from damaging the gate structure and metal silicide and affecting device performance.

[0046] Figure 2 An exemplary flowchart of a method 200 for preparing metal silicides according to some embodiments of this disclosure is shown, such as Figure 2 As shown, in step S201, a substrate, a gate structure, and a substrate protective layer are prepared;

[0047] In step S202, the substrate protective layer is etched by etching gas using a contact hole process to form a first contact hole with its bottom located in the active region.

[0048] In step S203, metal silicide is formed in the active region using the first contact hole as the reaction window.

[0049] In this embodiment, the active region of the substrate refers to the area on the substrate used to form active devices, such as transistors or diodes. The active region is the part of the device that actually operates, such as the source, drain, and channel. The non-active region of the substrate refers to the part of the substrate outside the active region, and it is mainly used to achieve electrical isolation between devices and prevent leakage current. In this embodiment, both the gate structure and the substrate protection layer are located above the substrate; specifically, both the gate structure and the substrate protection layer are located in the active region of the substrate. Further, the gate structure includes a metal work function layer and a gate protection layer arranged sequentially from bottom to top. The metal work function layer is a structure used in semiconductor manufacturing to adjust the threshold voltage of transistors. The metal work function layer is typically deposited on a high-dielectric layer using techniques such as atomic layer deposition or magnetron sputtering.

[0050] Metal silicides are structures used in semiconductor devices to reduce the contact resistance between the metal and silicon, thereby improving the device's electrical performance. In semiconductor devices, metal silicides are typically located in the active region of the substrate. Metal silicides can significantly reduce the contact resistance between the active region and the gate structure, thus improving device performance. In current metal silicide processes, the metal gate process is usually performed after the metal silicide is prepared to form the gate structure. This necessitates combining gate sidewall thickening and wet gate sidewall thinning processes, increasing the risk of poor device contact and failure.

[0051] Compared to existing metal silicide processes, in this embodiment, step S202 uses a contact hole process to form a first contact hole in the active region of the substrate, and in step S203, the first contact hole serves as a reaction window to form metal silicide in the active region of the substrate. Since steps S202 to S203 are performed after the gate structure and substrate protective layer are fabricated, the gate structure sidewalls do not need to be thickened using a gate sidewall thickening process. Sufficient spacing can be maintained between the gate structures, preventing void defects during substrate protective layer deposition and effectively reducing the risk of device bridging. Because the gate structure sidewalls are not thickened, and this embodiment utilizes a contact hole process to form the reaction window for metal silicide, this embodiment can also eliminate the wet gate sidewall thinning process, thereby eliminating the risk of metal silicide damage and gate structure damage caused by the wet gate sidewall thinning process and reducing the probability of poor device contact and failure.

[0052] Furthermore, during step S202, the etching gas used can have a high selectivity for the substrate protective layer material. In the etching process, the selectivity (SR) refers to the ratio of the etching rate of the material to be etched to the etching rate of the masking layer (e.g., photoresist). A high selectivity means that the etching rate of the material to be etched is significantly higher than that of the masking layer material. By using an etching gas with a high selectivity, the target material can be etched without damaging other materials. In this embodiment, the substrate protective layer can be removed by etching with a high-selectivity etching gas. At the same time, the gate structure is protected by the gate protective layer to prevent the metal work function layer from being etched, thereby forming a first contact hole in the active region of the substrate. This exposes the active region of the substrate at the bottom of the first contact hole, facilitating the subsequent formation of metal silicide in the active region of the substrate.

[0053] During step S203, the first contact hole provides a reaction window for the preparation of metal silicides, and the hole wall of the first contact hole can effectively prevent excessive diffusion of metal silicides in the active region. Furthermore, for unreacted metal silicide residues, this embodiment can still use a cleaning process to remove them. In this case, the hole wall of the first contact hole can effectively protect the gate structure sidewalls from the chemical solutions used in the cleaning process, thereby simultaneously solving the problems of unreacted metal silicide residue defects and device failure, thus improving the yield of semiconductor devices.

[0054] As an example, in practical applications, a self-aligned metal silicide process can be used to form metal silicides in the active region. Furthermore, after the metal silicides are formed, a cleaning process can be used to remove any unreacted metal silicide residues.

[0055] In some embodiments, the substrate protection layer and the gate protection layer may be composite layers with different structures, thereby preventing the substrate protection layer and the gate protection layer from being simultaneously etched away by the etching gas.

[0056] As an example, the substrate protection layer includes a first protection layer and a second protection layer disposed sequentially from bottom to top, and the gate protection layer includes a third protection layer and a fourth protection layer disposed sequentially from bottom to top. It should be noted that, in this embodiment, the direction from the gate structure to the substrate is defined as downward, and the direction from the substrate to the gate structure is defined as upward. It can be understood that, in this embodiment, the first and second protection layers are sequentially disposed above the substrate, and the metal work function layer, the third protection layer, and the fourth protection layer are sequentially disposed above the substrate.

[0057] For the multiple protective layers shown above, the first and second protective layers use different compounds, the third and fourth protective layers use different compounds, and the fourth and first protective layers use the same compound. Through proper configuration of the protective layer materials and selection of the etching gas, the second protective layer can be etched in a separate etching process, while the fourth and first protective layers can be etched simultaneously in another etching process.

[0058] As an example, the etching gas may include a first etching gas and a second etching gas. In this embodiment, the first and second etching gases are used to perform targeted etching on different structural layers.

[0059] Figure 3 An exemplary flowchart of a method 300 for preparing metal silicides according to other embodiments of this disclosure is shown, such as Figure 3 As shown, in step S301, a substrate, a gate structure, and a substrate protective layer are prepared;

[0060] In step S302, the second protective layer is etched using a first etching gas through a contact hole process.

[0061] In step S303, the first protective layer is etched using a second etching gas through a contact hole process to form a first contact hole with its bottom located in the active region;

[0062] In step S304, metal silicide is formed in the active region using the first contact hole as the reaction window.

[0063] To facilitate understanding of steps S301 to S304 above by those skilled in the art Figure 4 A schematic diagram illustrating the metal silicide preparation process of some embodiments of this disclosure is shown, such as... Figure 4As shown, in process a, by performing step S301, a substrate 105, a gate structure 106 located above the substrate, and a substrate protection layer 107 located between the gate structures 106 can be prepared. The gate structure 106 includes a metal work function layer 1061, a third protection layer 1062, and a fourth protection layer 1063 arranged sequentially from bottom to top. The substrate protection layer 107 includes a first protection layer 1071 and a second protection layer 1072 arranged sequentially from bottom to top.

[0064] In process b, by performing step S302, a first contact hole 108 can be formed in the active region of the substrate 105. At this time, the bottom of the first contact hole 108 is located in the first protective layer 1071. In some embodiments, the first etching gas can be an etching gas with a high selectivity for the compound used in the second protective layer 1072, so as to selectively etch the second protective layer.

[0065] In step c, by performing step S303, the first contact hole 108 can be further deepened. At this time, the bottom of the first contact hole 108 is located in the active region of the substrate 105. In some embodiments, the second etching gas can be an etching gas with a high selectivity to the compound used in the first protective layer 1071, thereby selectively etching the first protective layer 1071. It should be further noted that since the first protective layer 1071 and the fourth protective layer 1063 use the same compound, in step c, the fourth protective layer 1063 is simultaneously etched to form the second contact hole 109. Since the third protective layer 1062 and the fourth protective layer 1063 use different compounds, the bottom of the second contact hole 109 remains at the third protective layer 1062.

[0066] In process d, by performing step S304, metal silicide 102 can be formed at the bottom of the first contact hole 108, i.e., the exposed active region of the substrate.

[0067] Silicon nitride and silicon oxide are commonly used compounds for etch stop / protective layers in semiconductor devices. As an example, the first to fourth protective layers can be selected from the following compounds in sequence: silicon nitride, silicon oxide, silicon oxide, and silicon nitride. In this case, the first protective layer is a first silicon nitride layer, the second protective layer is a first silicon oxide layer, the third protective layer is a second silicon oxide layer, and the fourth protective layer is a second silicon nitride layer.

[0068] Taking semiconductor devices using the above-mentioned compounds as protective layer materials as an example, some embodiments disclosed herein provide the following methods for preparing metal silicides. Figure 5 An exemplary flowchart of a method 500 for preparing metal silicides according to further embodiments of this disclosure is shown, such as Figure 5 As shown, the method includes:

[0069] In step S501, a substrate, a gate structure, and a substrate protective layer are prepared;

[0070] In step S502, the first silicon oxide layer is etched using a contact hole process with an etching gas that has a high selectivity for silicon oxide.

[0071] In step S503, the first contact hole is formed in the active region of the substrate by etching the first silicon nitride layer with an etching gas having a high selectivity to silicon nitride using a contact hole process.

[0072] In step S504, metal silicide is formed in the active region using the first contact hole as the reaction window.

[0073] In this embodiment, the gate structure prepared in step S501 includes a metal work function layer, a second silicon oxide layer, and a second silicon nitride layer arranged sequentially from bottom to top. The substrate protection layer prepared includes a first silicon nitride layer and a first silicon oxide layer arranged sequentially from bottom to top. In other words, the first silicon nitride layer and the first silicon oxide layer are arranged sequentially from bottom to top in the active region of the substrate, and the metal work function layer, the second silicon oxide layer, and the second silicon nitride layer are arranged sequentially from bottom to top to form the gate structure.

[0074] In this embodiment, during step S502, because an etching gas with a high selectivity to silicon oxide is used, the second silicon nitride layer in the gate structure is not affected by the etching gas during the etching process of removing the first silicon oxide layer to form the first contact hole. Then, in step S503, because an etching gas with a high selectivity to silicon nitride is used, the first contact hole, which was originally etched to the first silicon nitride layer, is further etched deeper, eventually stopping at the active region of the substrate. Further, during the deepening of the first contact hole, the second silicon nitride layer is also etched away by the etching gas with a high selectivity to silicon nitride, thereby forming the second contact hole on the gate structure. The etching of the second contact hole stops at the second silicon oxide layer. The remaining second silicon oxide layer protects the metal work function layer in the gate structure in step S504, for example, as a metal silicide barrier layer at the top of the gate structure.

[0075] In any of the metal silicide preparation methods shown in the preceding embodiments, the metal silicide process is performed after the substrate, gate structure, and substrate protective layer are prepared. The preparation method of metal silicide is described below in conjunction with the preparation process of the substrate, gate structure, and substrate protective layer.

[0076] Figure 6 An exemplary flowchart of a method 600 for preparing metal silicides according to some embodiments of this disclosure is shown, such as Figure 6As shown, in step S601, a semiconductor substrate structure is prepared. The semiconductor substrate structure includes: a substrate, a dummy gate structure located above the substrate, a first protective layer, and a second protective layer.

[0077] In step S602, a metal work function layer, a third protective layer, and a fourth protective layer are sequentially filled into the pseudo-gate structure to form a gate structure;

[0078] In step S603, an interlayer insulating dielectric layer is deposited and grown on the top surface of the gate structure and the second protective layer;

[0079] In step S604, a first contact hole is formed by etching the interlayer insulating dielectric layer and the second protective layer with a first etching gas using a contact hole process, with the bottom located in the first protective layer.

[0080] In step S605, the first protective layer is etched using a second etching gas through a contact hole process to form a first contact hole with its bottom located in the active region.

[0081] In step S606, metal silicide is formed in the active region using the first contact hole as the reaction window.

[0082] In this embodiment, the dummy gate structure is a temporary structure in semiconductor manufacturing, designed to provide temporary gate functionality during the manufacturing process so that it can be replaced with the final gate structure in subsequent processes. In some embodiments, the fabrication process of the dummy gate structure is as follows:

[0083] 1. Preparation of gate oxide layer (SiO2 / SiON)

[0084] On a substrate where active region doping and isolation structure (STI) fabrication have been completed, an initial SiO2 layer is grown via thermal oxidation. If SiON (silicon oxynitride) is used, nitrogen is introduced through NH3 plasma treatment. The core function of the gate oxide layer is to ensure interface quality. The gate oxide layer is an "atomic-level buffer layer" between the silicon substrate and the high-dielectric-constant dielectric layer (HfO2), and its function is to solve the "compatibility problem between the high-dielectric-constant material and the silicon substrate".

[0085] 2. Deposition of high dielectric constant dielectric layer

[0086] Atomic layer deposition (ALD) technology is used to deposit a hafnium dioxide (HfO2) layer on top of the gate oxide layer (SiO2 / SiON). HfO2 is a "functional core layer" that replaces the traditional SiO2 gate dielectric. Its core function is to "ensure gate capacitance" while "solving tunneling leakage problems".

[0087] 3. Preparation of TiN barrier layer

[0088] A TiN layer is deposited on the HfO2 layer using physical vapor deposition (PVD) or ALD technology. Its core function is to serve as a high dielectric constant dielectric layer and a barrier layer for the subsequent polysilicon gate, preventing Si in the polysilicon from diffusing into HfO2, and also serving as a stop layer for subsequent etching.

[0089] 4. Preparation of polycrystalline silicon pseudo-gate

[0090] Polysilicon is deposited on the TiN layer by LPCVD, the gate pattern is defined by deep ultraviolet (DUV) lithography, and inductively coupled plasma (ICP) etching is used to sequentially etch the polysilicon, TiN layer, and HfO2 layer until the gate oxide layer is exposed, forming a stacked structure: polysilicon / TiN / HfO2 / SiO2.

[0091] 5. Pseudo-gate structure forming (polysilicon removal)

[0092] The active area and other regions are covered with photoresist, exposing only the polysilicon at the top of the dummy gate. Wet etching is then performed, using the TiN layer as an etch stop layer, to ultimately form a "dummy gate framework" composed of TiN / HfO2 / SiO2, with the trench depth consistent with the original polysilicon thickness.

[0093] In some embodiments, based on the above-described fabrication process of the pseudo-gate structure, step S601 can be performed as follows: First, a substrate is prepared; then, a gate oxide layer, a high dielectric constant dielectric layer, a TiN barrier layer, and a polysilicon gate are prepared on the substrate; then, a first protective layer and a second protective layer are sequentially deposited and grown in the active region of the substrate; finally, the polysilicon in the polysilicon gate is removed to form a pseudo-gate structure.

[0094] In some other embodiments, when performing step S602, a metal work function layer, a third protective layer, and a fourth protective layer may be deposited and grown sequentially above the semiconductor substrate structure. At this time, the metal work function layer, the third protective layer, and the fourth protective layer also cover the second protective layer. Then, the metal work function layer, the third protective layer, and the fourth protective layer above the second protective layer are removed using a chemical mechanical polishing process so that the top surface of the gate structure and the second protective layer are flush.

[0095] Furthermore, in some embodiments, the interlayer insulating dielectric layer can also be prepared before the metal silicide process. As an example, after step S602 is completed, step S603 can be performed to deposit and grow the interlayer insulating dielectric layer on the top surface of the gate structure and the second protective layer. In this embodiment, the interlayer insulating dielectric layer and the second protective layer use the same compound; as an example, when the second protective layer is a first silicon oxide layer, the interlayer insulating dielectric layer also uses silicon oxide. After the interlayer insulating dielectric layer is prepared, steps S604 to S606 are performed to prepare the metal silicide using the contact hole process.

[0096] According to the preparation method of metal silicides shown in the previous embodiments, Figure 7 Schematic diagrams illustrating the metal silicide preparation process of other embodiments of this disclosure are shown, such as... Figure 7 As shown, in step e, a semiconductor substrate structure is fabricated, comprising: a substrate 105, a dummy gate structure 106w located above the substrate, a first protective layer 1071, and a second protective layer 1072. In step f, a metal work function layer 1061, a third protective layer 1062, and a fourth protective layer 1063 are sequentially deposited and grown on the fabricated semiconductor substrate structure. In step g, a chemical mechanical polishing process is used to remove excess thin film structures from the device surface. Here, excess thin film structures on the device surface refer to the metal work function layer 1061, the third protective layer 1062, and the fourth protective layer 1063 above the second protective layer 1072, thereby achieving device surface planarization. In step h, an interlayer insulating dielectric layer 103 is deposited and grown on the top surface of the gate structure 106 and the second protective layer 1072 using a deposition process such as chemical vapor deposition. The interlayer insulating dielectric layer 103 and the second protective layer 1072 are then etched using a first etching gas to form a first contact hole 108 with its bottom located in the first protective layer 1071 and a second contact hole 109 with its bottom located in the fourth protective layer 1063. In step i, the first protective layer 1071 and the fourth protective layer 1063 are etched using a second etching gas to deepen the first contact hole 108 and the second contact hole 109. The bottom of the deepened first contact hole 108 is located in the active region, and the bottom of the deepened second contact hole 109 is located in the third protective layer 1062. In step j, using the first contact hole 108 as a reaction window, a metal silicide 102 is formed at the bottom of the first contact hole 108, i.e., in the active region of the substrate.

[0097] The preceding embodiments illustrate a method for preparing metal silicides, which addresses the problems of poor device contact and device failure risks present in existing metal silicide processes.

[0098] Based on the metal silicide preparation method shown in any of the preceding embodiments, some embodiments of this disclosure provide a semiconductor device preparation method.

[0099] Figure 8 An exemplary flowchart of a semiconductor device fabrication method 800 according to some embodiments of this disclosure is shown, such as... Figure 8 As shown, in step S801, a substrate, a gate structure, and a substrate protective layer are prepared;

[0100] In step S802, the substrate protective layer is etched by etching gas using a contact hole process to form a first contact hole with its bottom located in the active region.

[0101] In step S803, metal silicide is formed in the active region using the first contact hole as the reaction window;

[0102] In step S804, the gate protection layer is etched away to form a second contact hole with its bottom located in the metal work function layer;

[0103] In step S805, metal is filled into the first contact hole and the second contact hole to form a semiconductor device with metal vias.

[0104] In this embodiment, the substrate protection layer is located in the active region of the substrate. The gate structure is also located in the active region of the substrate, and the gate structure includes a metal work function layer and a gate protection layer disposed sequentially from bottom to top. It should be noted that the execution method of the above steps S801 to S803 is the same as that of steps S201 to S203 in the previous embodiment, and will not be described in detail here.

[0105] In this embodiment, during the formation of the metal silicide, the gate protection layer in the gate structure protects the metal work function layer in the gate structure. After the metal silicide is formed, metal vias are formed to connect the semiconductor device and the first metal layer. The first metal layer is the bottom metal layer used in chip manufacturing to realize local signal interconnections. It is typically used to connect the source, drain, and gate of the semiconductor device and to achieve short-distance signal transmission. Multiple metal layers further form a metal interconnect structure to realize electrical connections between different levels within the chip.

[0106] In this embodiment, in order to enable the gate structure to achieve electrical connection, the gate protective layer needs to be removed to expose the metal work function layer before forming the metal via. At this time, a second contact hole with its bottom located on the metal work function layer will be formed on the gate structure. Then, the metal via is formed by filling the contact hole with metal, such as tungsten.

[0107] According to the metal silicide preparation method shown in the previous embodiments, in some embodiments, the substrate protective layer and the gate protective layer can be composite layers with different structures, thereby preventing the substrate protective layer and the gate protective layer from being simultaneously etched away by the etching gas.

[0108] As an example, the substrate protection layer includes a first protection layer and a second protection layer disposed sequentially from bottom to top, and the gate protection layer includes a third protection layer and a fourth protection layer disposed sequentially from bottom to top, wherein the first protection layer and the second protection layer use different compounds, the third protection layer and the fourth protection layer use different compounds, and the fourth protection layer and the first protection layer use the same compound.

[0109] Figure 9 An exemplary flowchart of a semiconductor device fabrication method 900 according to some embodiments of this disclosure is shown, such as... Figure 9 As shown, in step S901, a substrate, a gate structure, and a substrate protective layer are prepared;

[0110] In step S902, the second protective layer is etched using a first etching gas through a contact hole process.

[0111] In step S903, the first protective layer and the fourth protective layer are etched by the second etching gas using a contact hole process to form a first contact hole with its bottom located in the active region and a second contact hole with its bottom located in the third protective layer.

[0112] In step S904, metal silicide is formed in the active region using the first contact hole as the reaction window;

[0113] In step S905, the third protective layer is etched away to form a second contact hole with its bottom located in the metal work function layer;

[0114] In step S906, metal is filled into the first contact hole and the second contact hole to form a semiconductor device with metal vias.

[0115] In this embodiment, step S901 is the same as step S801 in the previous embodiment, and will not be described again here.

[0116] In semiconductor manufacturing technology, silicon nitride and silicon oxide are commonly used compounds for etch stop layers / protective layers in semiconductor devices. As an example, the first to fourth protective layers can be selected from the following compounds in sequence: silicon nitride, silicon oxide, silicon oxide, and silicon nitride. In this case, the first protective layer is a first silicon nitride layer, the second protective layer is a first silicon oxide layer, the third protective layer is a second silicon oxide layer, and the fourth protective layer is a second silicon nitride layer.

[0117] Based on the above materials, step S902 can be performed as follows: using a contact hole process, the first silicon oxide layer is etched with an etching gas having a high selectivity to silicon oxide to form a first contact hole with its bottom located on the first silicon nitride layer. Step S903 can be performed as follows: using an etching gas having a high selectivity to silicon nitride, the first silicon nitride layer and the second silicon nitride layer are etched to form a first contact hole with its bottom located in the active region and a second contact hole with its bottom located on the second silicon oxide layer. Step S905 can be performed as follows: etching away the second silicon oxide layer to deepen the second contact hole, forming a second contact hole with its bottom located on the metal work function layer.

[0118] As an example, when etching away the second silicon oxide layer, a SiCoNi chemical in-situ pre-cleaning process can be used. The SiCoNi chemical in-situ pre-cleaning process is a highly selective semiconductor surface pre-cleaning technology. This process has high selectivity for removing silicon oxide, and therefore can effectively remove the second silicon oxide layer.

[0119] In this embodiment, step S906 is the same as step S805 in the previous embodiment, and will not be described in detail here.

[0120] In some implementations, in the aforementioned semiconductor device fabrication method, the gate structure is formed based on a pseudo-gate structure. In conjunction with the gate structure fabrication process, Figure 10 Exemplary flowcharts of semiconductor device fabrication methods according to other embodiments of this disclosure are shown, such as... Figure 10 As shown, in step S1001, a semiconductor substrate structure is prepared. The semiconductor substrate structure includes: a substrate, a dummy gate structure located above the substrate, a first protective layer, and a second protective layer.

[0121] In step S1002, a metal work function layer, a third protective layer, and a fourth protective layer are sequentially filled into the pseudo-gate structure to form a gate structure;

[0122] In step S1003, an interlayer insulating dielectric layer is deposited and grown on the top surface of the gate structure and the second protective layer;

[0123] In step S1004, the interlayer insulating dielectric layer and the second protective layer are etched by the first etching gas to form a first contact hole with the bottom located in the first protective layer and a second contact hole with the bottom located in the fourth protective layer.

[0124] In step S1005, the first protective layer and the fourth protective layer are etched by the second etching gas to form a first contact hole with its bottom located in the active region and a second contact hole with its bottom located in the third protective layer;

[0125] In step S1006, the third protective layer is etched away to form a second contact hole with its bottom located in the metal work function layer;

[0126] In step S1007, metal is filled into the first contact hole and the second contact hole to form a semiconductor device with metal vias.

[0127] In this embodiment, steps S1001 to S1005 can be referred to in conjunction with the foregoing text. Figure 6 The described embodiment, specifically, can be found in steps S601 to S605. It should be noted that in step S1004, the first etching gas, through etching the interlayer insulating dielectric layer, also forms a second contact hole with its bottom located in the fourth protective layer. Then, in step S1005, the second etching gas, through etching the fourth protective layer, further deepens the second contact hole, so that its bottom is located in the third protective layer.

[0128] In this embodiment, steps S1006 to S1007 can be referred to in conjunction with the foregoing text. Figure 9The described embodiments, specifically steps S905 to S906, will not be repeated here.

[0129] Based on the semiconductor device fabrication method shown in the preceding embodiments, Figure 11 Schematic diagrams of semiconductor fabrication processes according to some embodiments of this disclosure are shown, such as... Figure 11 As shown, in step k, a substrate 105, a dummy gate structure 106w located above the substrate 105, a first protective layer 1071, and a second protective layer 1072 are fabricated to form a semiconductor substrate structure. In step l, a metal work function layer 1061, a third protective layer 1062, and a fourth protective layer 1063 are sequentially deposited and grown on the semiconductor substrate structure. In step m, the metal work function layer 1061, the third protective layer 1062, and the fourth protective layer 1063 above the second protective layer 1072 are removed by chemical mechanical polishing, so that the top of the gate structure 106w is flush with the top of the second protective layer 1072. In step n, an interlayer insulating dielectric layer 103 is deposited and grown on the top surface of the gate structure 106 and the second protective layer 1072. The interlayer insulating dielectric layer 103 and the second protective layer 1072 are then etched using a first etching gas to form a first contact hole 108 and a second contact hole 109. The bottom of the first contact hole 108 is located within the first protective layer 1071, and the bottom of the second contact hole 109 is located within the fourth protective layer 1063. In step o, the first protective layer 1071 and the fourth protective layer 1063 are etched using a second etching gas to deepen the first contact hole 108 and the second contact hole 109. The bottom of the deepened first contact hole 108 is located in the active region, and the bottom of the deepened second contact hole 109 is located within the third protective layer 1062. In step p, using the first contact hole 108 as a reaction window, a metal silicide 102 is formed at the bottom of the first contact hole 108, i.e., in the active region of the substrate. Furthermore, in step p, unreacted metal silicides can be removed by a cleaning process. In step q, the third protective layer 1062 is etched away, further deepening the second contact hole 109. At this point, the metal work function layer 1061 is exposed at the bottom of the second contact hole 109. In step r, metal is filled into the first contact hole 108 and the second contact hole 109 to form a metal via 110, thus obtaining a semiconductor device.

[0130] Based on the semiconductor device fabrication methods illustrated in any of the foregoing embodiments, some embodiments of this disclosure also provide a semiconductor device. Further, the metal silicide in this semiconductor device can be fabricated by performing the foregoing combined... Figures 2-7 The described method forms the metal silicide in the semiconductor device using a contact hole process. Compared to semiconductor devices obtained using existing metal silicide processes, the semiconductor device in this embodiment has a lower probability of device bridging, poor contact, and device failure, resulting in a higher device yield.

[0131] In summary, the embodiments disclosed herein provide a method for preparing metal silicides. The unexpected technical effect of this invention is that the metal silicide is prepared through a contact hole process, which simplifies the steps involved in the wet gate sidewall thinning process. This not only reduces the preparation cost but also eliminates the problems of excessive diffusion of metal silicides and damage to the gate structure caused by the wet gate sidewall thinning process, thereby reducing the risk of device leakage and device failure.

[0132] Furthermore, in the method for preparing metal silicides shown in some embodiments of this disclosure, the interlayer insulating dielectric layer is formed before the metal silicide. Since there is no need to thicken the gate sidewall, voids will not occur during the preparation of the interlayer insulating dielectric layer, thereby reducing the risk of device bridging, short circuits in contact hole connections, and poor contact.

[0133] Furthermore, some embodiments disclosed herein also provide a semiconductor device fabrication method in which the gate structure is fabricated before the metal silicide is formed. This simplifies the gate sidewall thickening process, reduces the risk of voids in the interlayer insulating dielectric layer, and thus avoids device bridging problems. The metal silicide in the active region is fabricated using a contact hole process, simplifying the wet gate sidewall thinning process. This avoids loss of the metal silicide due to the chemical solutions used in the wet gate sidewall thinning process, and also prevents the chemical solutions from the cleaning process from eroding the high-dielectric material in the gate structure along the weak side of the gate sidewall. This effectively reduces the risk of poor device contact and device failure.

[0134] While numerous embodiments of this disclosure have been shown and described herein, it will be apparent to those skilled in the art that such embodiments are provided by way of example only. Many modifications, alterations, and alternatives will occur to those skilled in the art without departing from the spirit and intent of this disclosure. It should be understood that various alternatives to the embodiments of this disclosure described herein may be employed in the practice of this disclosure. The appended claims are intended to define the scope of this disclosure and therefore cover equivalents or alternatives within the scope of these claims.

[0135] The collection and acquisition of various data disclosed herein comply with relevant laws and regulations and are authorized by the data providers. Any organization or individual that needs to obtain external data shall obtain authorization in accordance with the law and ensure data security. It is prohibited to illegally collect, use, process, or transmit unauthorized or unprotected data, or to illegally buy, sell, provide, or disclose unauthorized or unprotected data.

Claims

1. A method for preparing a metal silicide, characterized by, The method comprises the following steps: preparing a substrate, a gate structure and a substrate protection layer, the substrate protection layer is located in an active area of the substrate, and the gate structure comprises a metal work function layer for regulating a gate threshold voltage and a gate protection layer for protecting the gate structure which are sequentially arranged from bottom to top; forming a first contact hole with a bottom located in the active area by etching the substrate protection layer through a contact hole process and an etching gas; forming a metal silicide in the active area by taking the first contact hole as a reaction window, wherein the substrate protection layer comprises a first protection layer and a second protection layer which are sequentially arranged from bottom to top, and the first protection layer and the second protection layer are made of different compounds; the gate protection layer comprises a third protection layer and a fourth protection layer which are sequentially arranged from bottom to top, and the third protection layer and the fourth protection layer are made of different compounds, and the fourth protection layer and the first protection layer are made of the same compound; and the etching gas comprises a first etching gas and a second etching gas; the step of forming the first contact hole with a bottom located in the active area by etching the substrate protection layer through a contact hole process and an etching gas comprises the following steps: etching the second protection layer through the first etching gas by using a contact hole process; and etching the first protection layer through the second etching gas by using a contact hole process to form the first contact hole with a bottom located in the active area.

2. The method of claim 1, wherein, The first protection layer is a first silicon nitride layer, the second protection layer is a first silicon oxide layer, the third protection layer is a second silicon oxide layer, and the fourth protection layer is a second silicon nitride layer, the first silicon nitride layer and the first silicon oxide layer are sequentially arranged from bottom to top in the active area of the substrate, and the metal work function layer, the second silicon oxide layer and the second silicon nitride layer are sequentially arranged from bottom to top to form the gate structure.

3. The method of claim 1, wherein, The method comprises the following steps: preparing a semiconductor substrate structure, the semiconductor substrate structure comprises the substrate, a pseudo gate structure located above the substrate, the first protection layer and the second protection layer; and sequentially filling the metal work function layer, the third protection layer and the fourth protection layer into the pseudo gate structure to form the gate structure.

4. The method of claim 3, wherein, The step of sequentially filling the metal work function layer, the third protection layer and the fourth protection layer into the pseudo gate structure to form the gate structure comprises the following steps: sequentially depositing and growing the metal work function layer, the third protection layer and the fourth protection layer above the semiconductor substrate structure; and removing the metal work function layer, the third protection layer and the fourth protection layer above the second protection layer by using a chemical mechanical polishing process, so that the top surfaces of the gate structure and the second protection layer are flush.

5. The method of claim 3, wherein, The method comprises the following steps: preparing the substrate; preparing a polysilicon gate above the substrate; sequentially depositing and growing the first protection layer and the second protection layer in the active area of the substrate; removing the polysilicon in the polysilicon gate to form the pseudo gate structure.

6. A method of fabricating a semiconductor device, characterized by, The method comprises the following steps: A substrate, a gate structure and a substrate protection layer are prepared, the substrate protection layer is located in an active region of the substrate, and the gate structure comprises, from bottom to top, a metal work function layer for regulating a gate threshold voltage and a gate protection layer for protecting the gate structure; A contact hole process is used to etch the substrate protection layer by using an etching gas to form a first contact hole with a bottom located in the active region; A metal silicide is formed in the active region by taking the first contact hole as a reaction window; The gate protection layer is etched to form a second contact hole with a bottom located in the metal work function layer; Metal is filled into the first contact hole and the second contact hole to form a semiconductor device with a metal via, wherein The substrate protection layer comprises, from bottom to top, a first protection layer and a second protection layer, and the first protection layer and the second protection layer are made of different compounds; the gate protection layer comprises, from bottom to top, a third protection layer and a fourth protection layer, and the third protection layer and the fourth protection layer are made of different compounds, and the fourth protection layer and the first protection layer are made of the same compound; and the etching gas comprises a first etching gas and a second etching gas; The etching of the substrate protection layer by using the contact hole process to form the first contact hole with the bottom located in the active region comprises: The second protection layer is etched by using the first etching gas through the contact hole process; and The first protection layer and the fourth protection layer are etched by using the second etching gas through the contact hole process to form the first contact hole with the bottom located in the active region and the second contact hole with the bottom located in the third protection layer; The etching of the gate protection layer to form the second contact hole with the bottom located in the metal work function layer comprises: The third protection layer is etched to form the second contact hole with the bottom located in the metal work function layer.

7. The semiconductor device preparation method according to claim 6, wherein The preparation of the substrate, the gate structure and the substrate protection layer comprises: A semiconductor substrate structure is prepared, and the semiconductor substrate structure comprises the substrate, a dummy gate structure located above the substrate, the first protection layer and the second protection layer; The metal work function layer, the third protection layer and the fourth protection layer are sequentially filled into the dummy gate structure to form the gate structure; An interlayer dielectric layer is deposited and grown on the top surface of the gate structure and the second protection layer, and the interlayer dielectric layer and the second protection layer are made of the same compound; The etching of the second protection layer by using the first etching gas comprises: The interlayer dielectric layer and the second protection layer are etched by using the first etching gas to form the first contact hole with the bottom located in the first protection layer and the second contact hole with the bottom located in the fourth protection layer.

8. A semiconductor device, characterized by comprising: The semiconductor device is prepared by performing the semiconductor device preparation method according to any one of claims 6-7.

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