Test platform of power management chip

Abstract

The invention provides a test platform for a power management chip. The test platform comprises an upper computer, a control panel, a load daughter board and an instrument, the control board is configured to receive a test instruction sent by the upper computer, configure the instrument based on the test instruction, send a test signal to the load daughter board, receive a response signal sent by the load daughter board, obtain a test result based on the response signal and send the test result to the upper computer; the load daughter board is configured to bear the tested power management chip, receive the test signal sent by the control board, match the test signal to the tested power management chip, obtain a response signal output by the tested power management chip and send the response signal to the control board; wherein the load daughter board is provided with a load circuit and is configured to provide a peripheral circuit for the tested power management chip, and the control board is further configured to switch the type of the load circuit. Wherein different types of power management chips can be verified by switching the types of the load circuits on the load daughter board.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of automation testing, and in particular, to a test platform for a power management chip. BACKGROUND

[0002] This section is intended to provide background or context to the embodiments of the disclosure recited in the claims. The description herein does not constitute admission that the prior art is prior art nor, that anything in this section is "prior art" with respect to the disclosure.

[0003] Power management integrated circuits (PMICs) are chips that take on the responsibility of power conversion, distribution, detection, and other power management in electronic device systems, and are mainly responsible for identifying the CPU power supply amplitude, generating a corresponding short square wave, and driving the power output of the subsequent circuit.

[0004] The scope of power management is relatively wide, including power conversion (DC-DC, AC-DC, and DC-AC), power distribution and detection, and systems that combine power conversion and power management. Accordingly, the classification of power management chips also includes these aspects, such as linear power chips, voltage reference chips, switching power chips, LCD drive chips, LED drive chips, voltage detection chips, battery charging management chips, gate drivers, load switches, wide-bandgap switches, etc.

[0005] Therefore, in the related art, when verifying the power management chip, a dedicated verification scheme is usually needed for different types of power management chips, and there is a lack of a scheme that can comprehensively verify different types of power management chips. SUMMARY

[0006] Therefore, the purpose of the present disclosure is to provide a test platform for a power management chip, which at least partially solves one of the technical problems in the related art.

[0007] To achieve the above purpose, the exemplary embodiments of the present disclosure provide a test platform for a power management chip, which comprises a host computer, a control board, a load sub-board, and an instrument.

[0008] The host computer, the load sub-board, and the instrument are connected to the control board.

[0009] The host computer is configured to send a test instruction to the control board and receive a test result sent by the control board.

[0010] The control board is configured to receive the test command sent by the host computer, configure the instrument based on the test command, send a test signal to the load sub-board, receive a response signal sent by the load sub-board, obtain the test result based on the response signal, and send the test result to the host computer.

[0011] The load subboard is configured to carry the power management chip under test, receive the test signal sent by the control board, match the test signal to the power management chip under test, obtain the response signal output by the power management chip under test, and send the response signal to the control board.

[0012] The load subboard is provided with a load circuit, which is configured to provide peripheral circuits to the power management chip under test. The control board is also configured to switch the type of the load circuit.

[0013] In some exemplary embodiments, the instrument has a SENSE readback function.

[0014] In some exemplary embodiments, the instrument includes a first power supply, a signal generator, a multimeter, an oscilloscope, and a source measurement unit.

[0015] In some exemplary embodiments, the oscilloscope and the load subboard are connected via an SMA coaxial cable;

[0016] The oscilloscope is configured to send an input signal to the power management chip under test on the load subboard via the SMA coaxial cable, and to acquire the output signal output by the power management chip under test.

[0017] In some exemplary embodiments, the load subboard is provided with an amplification circuit, which is configured to amplify the response signal after acquiring the response signal output by the power management chip under test, and send the amplified response signal to the control board.

[0018] In some exemplary embodiments, the control board includes a control core module, a second power supply module, a communication interface module, a relay switch matrix, an adjustable power supply module, and a digital channel module.

[0019] In some exemplary embodiments, the relay switch matrix is ​​configured to configure the excitation signal and test signal of the instrument according to the test command.

[0020] In some exemplary embodiments, the adjustable power supply module includes a voltage converter and a programmable power management chip under test.

[0021] The voltage converter is configured to convert the power supply voltage into a target voltage;

[0022] The programmable power management chip under test is configured to output the target voltage.

[0023] In some exemplary embodiments, the digital channel module includes an FPGA control unit, a vector storage module, a program storage module, a power supply module, a driver module, a communication board communication interface, and a channel output interface.

[0024] In some exemplary embodiments, the driving module is configured as a dual single-ended driving / receiving channel or a single differential driving / receiving channel;

[0025] Each of the channels is configured to provide a high-speed window comparator for functional testing, as well as a single-pin PMU with programmable voltage / current output and high-precision voltage / current measurement capabilities.

[0026] As can be seen from the above description, the power management chip test platform provided in this embodiment includes a host computer, a control board, a load sub-board, and instruments; the host computer, the load sub-board, and the instruments are all connected to the control board; the host computer is configured to send test commands to the control board and receive test results sent by the control board; the control board is configured to receive the test commands sent by the host computer, configure the instruments based on the test commands, send test signals to the load sub-board, receive response signals sent by the load sub-board, obtain the test results based on the response signals, and send the test results to the host computer; the load sub-board is configured to carry the power management chip under test, receive the test signals sent by the control board, match the test signals to the power management chip under test, obtain the response signals output by the power management chip under test, and send the response signals to the control board; wherein, the load sub-board is provided with a load circuit, and the load circuit is configured to provide peripheral circuits to the power management chip under test, and the control board is also configured to switch the type of the load circuit. By switching the type of load circuit on the load subboard, the verification requirements for different types of power management chips can be met. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in this disclosure or related technologies, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram of a test platform for a power management chip provided as an exemplary embodiment of this disclosure;

[0029] Figure 2 A schematic diagram of the structure of a control panel provided for an exemplary embodiment of this disclosure;

[0030] Figure 3 A schematic diagram of a Sparton6 power module circuit provided for an exemplary embodiment of this disclosure;

[0031] Figure 4 A schematic diagram of a Bank memory circuit provided for an exemplary embodiment of this disclosure;

[0032] Figure 5 A schematic diagram of a download mode selection circuit provided for an exemplary embodiment of this disclosure;

[0033] Figure 6 A schematic diagram of a Flash memory circuit provided for an exemplary embodiment of the present disclosure;

[0034] Figure 7 A schematic diagram of a crystal oscillator circuit provided as an exemplary embodiment of this disclosure;

[0035] Figure 8 A schematic diagram of a communication interface module circuit provided for an exemplary embodiment of this disclosure;

[0036] Figure 9 A schematic diagram of a relay switch matrix circuit provided for an exemplary embodiment of this disclosure;

[0037] Figure 10 A schematic diagram of the software framework of a host computer provided for an exemplary embodiment of this disclosure. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this disclosure clearer, the principles and spirit of this disclosure will be described below with reference to several exemplary embodiments. It should be understood that these embodiments are provided merely to enable those skilled in the art to better understand and implement this disclosure, and are not intended to limit the scope of this disclosure in any way. Rather, these embodiments are provided to make this disclosure more thorough and complete, and to fully convey the scope of this disclosure to those skilled in the art.

[0039] In this article, it is important to understand that any number of elements in the accompanying figures is for illustrative purposes and not for limitation, and any naming is for distinction only and has no limiting meaning.

[0040] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this disclosure should have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms "first," "second," and similar words used in the embodiments of this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly. The article "a" or "an" preceding an element does not exclude the existence of multiple such elements.

[0041] The principles and spirit of this disclosure will be explained in detail below with reference to several representative embodiments.

[0042] As described in the background section, power management integrated circuits are chips in electronic device systems that are responsible for the transformation, distribution, detection, and other power management of electrical energy. They are mainly responsible for identifying the CPU power supply amplitude, generating corresponding short-wave pulses, and driving subsequent circuits to output power.

[0043] Power management encompasses a relatively broad range, including power conversion (DC-DC, AC-DC, and DC-AC), power distribution and detection, as well as systems that combine power conversion and power management. Correspondingly, power management chips are categorized in these areas, such as linear power supply chips, voltage reference chips, switching power supply chips, LCD driver chips, LED driver chips, voltage detection chips, battery charging management chips, gate drivers, load switches, and wide-bandgap switches.

[0044] The inventors of this disclosure have discovered that when verifying power management chips in related technologies, it is usually necessary to design a dedicated verification scheme for different types of power management chips, and there is a lack of a scheme that can comprehensively verify different types of power management chips.

[0045] To address the aforementioned issues, this disclosure provides a test platform for a power management chip, comprising a host computer, a control board, a load sub-board, and instruments. The host computer, the load sub-board, and the instruments are all connected to the control board. The host computer is configured to send test commands to the control board and receive test results from the control board. The control board is configured to receive the test commands from the host computer, configure the instruments based on the test commands, send test signals to the load sub-board, receive response signals from the load sub-board, obtain the test results based on the response signals, and send the test results to the host computer. The load sub-board is configured to carry the power management chip under test, receive the test signals from the control board, match the test signals to the power management chip under test, obtain the response signals output by the power management chip under test, and send the response signals to the control board. The load sub-board is provided with a load circuit configured to provide peripheral circuitry to the power management chip under test. The control board is also configured to switch the type of the load circuit.

[0046] By switching the type of load circuit on the load subboard, the verification requirements for different types of power management chips can be met.

[0047] After introducing the basic principles of this disclosure, various non-limiting embodiments of this disclosure will be described in detail below.

[0048] The power management chip test platform includes a host computer, a control board, a load sub-board, and instruments;

[0049] The host computer, the load sub-board, and the instrument are all connected to the control board;

[0050] The host computer is configured to send test commands to the control board and receive test results sent by the control board.

[0051] The control board is configured to receive the test command sent by the host computer, configure the instrument based on the test command, send a test signal to the load sub-board, receive a response signal sent by the load sub-board, obtain the test result based on the response signal, and send the test result to the host computer.

[0052] The load subboard is configured to carry the power management chip under test, receive the test signal sent by the control board, match the test signal to the power management chip under test, obtain the response signal output by the power management chip under test, and send the response signal to the control board.

[0053] The load subboard is provided with a load circuit, which is configured to provide peripheral circuits to the power management chip under test. The control board is also configured to switch the type of the load circuit.

[0054] In some exemplary embodiments, the instrument includes a first power supply, a signal generator, a multimeter, an oscilloscope, and a source measurement unit.

[0055] In some exemplary embodiments, the instrument has a SENSE readback function.

[0056] refer to Figure 1 This is a schematic diagram of a test platform for a power management chip provided in an exemplary embodiment of this disclosure.

[0057] The test platform for power management chips includes a host computer, a control board, a load sub-board, and instruments.

[0058] The load subboard is equipped with a chip socket for mounting the device under test.

[0059] The control board is connected to a power supply and a digital channel.

[0060] The instrument includes a power supply, a signal generator, a multimeter, an oscilloscope, and a source measurement unit.

[0061] In practical implementation, this disclosure adopts an approach that integrates third-party standard instruments and self-developed control circuits. The power management chip under test is connected to the test platform via a load sub-board. To meet various environmental testing requirements, a high-speed flexible flat cable connector is used between the load sub-board and the test platform. The instruments and control circuits are installed in a vertical cabinet, and the test control board is implemented as an external platform within the cabinet. The test platform needs to integrate instruments such as a power supply, signal generator, multimeter, oscilloscope, and source measurement unit (SMU), as well as a control board. The control board functions include instrument signal input and switching, power channels, and digital channels.

[0062] The test platform integrates two power supplies, a signal generator, a multimeter, an oscilloscope, a source measurement unit, a load subboard, and a control board. The control board functions include instrument signal input and switching, power channels, and digital channels.

[0063] As an example, the power supply used is a DC power supply RMX-4104-36-24, which provides input signals to the power management chip under test.

[0064] A signal generator is used to generate noise signals to measure the power rejection ratio of the power management chip under test.

[0065] A multimeter is used to accurately measure output voltage.

[0066] An oscilloscope is used to measure various timing parameters of the power management chip under test.

[0067] The source measurement unit (SMU) is used to provide an adjustable load current to the power management chip under test and measure the output voltage of the power management chip under test.

[0068] The control board is used to provide the resources of various instruments to the load subboard via connectors.

[0069] As an example, the control board features 8 adjustable power supplies and 16 digital channels. These can be used to power the peripheral circuitry and auxiliary power rails of the power management chip under test (PDT), and to measure the DC parameters on the control pins of the DDT.

[0070] The entire test platform is controlled by a host computer, including the on / off switching of relays on the control board, the output settings and switches of various devices, and the measurement of relevant data. The platform integrates two 3-channel power supplies to provide operating power to the power management chip under test (PDT) and its peripheral circuits, and also features power consumption testing capabilities. An integrated signal generator provides test signals to the DDT during verification testing. An oscilloscope is used to measure the DDT's operating status and various time parameters. The control board is responsible for configuring external instrument resources, signal amplification, switching test circuits, and data transmission. The load sub-board is customized according to the DDT and connects to the control board via a high-speed connector to form a complete test circuit. For the DDT, the platform primarily provides the following resources: power resources, analog test signal resources, test control signal resources, and DDT output signal acquisition. The test signals for the DDT are divided into analog input signals and digital control signals. The analog input signal is provided by an external signal generator, which is amplified on the control board to increase the amplitude range. Then, controlled by relays on the control board, it is divided into 32 independent signals and transmitted to the chip under test (DUT) on the daughterboard. The digital control signal is provided by the FPGA via a level conversion chip. The test platform provides 16 configurable, independent control signals. The output signal test of the DUT chip is completed on the daughterboard, and the output is connected to an oscilloscope via an SMA coaxial cable to read the output waveform. The daughterboard contains the load circuit for the power management chip under test, and its load type can be switched via relays. The relay control signals are provided by the control board. The entire test process is controlled by the host computer, including the on / off state of the control board relays, the output settings and switches of various peripheral instruments, and the measurement of relevant data.

[0071] In some exemplary embodiments, the load subboard is provided with a chip socket configured to carry the power management chip under test.

[0072] In some exemplary embodiments, the oscilloscope and the load subboard are connected via an SMA coaxial cable;

[0073] The oscilloscope is configured to send an input signal to the power management chip under test on the load subboard via the SMA coaxial cable, and to acquire the output signal output by the power management chip under test.

[0074] Daughterboard Circuit Design: The load daughterboard is customized based on the power supply under test (DPUT) and its power management chip (PDC). It mainly includes the DPUT chip and necessary peripheral circuitry. The DPUT chip's input signals are introduced to the daughterboard from the control board, while the output signals are returned to the control board via connectors to complete the test. In time parameter and Power Supply Rejection Ratio (PSRR) tests, the DPUT chip's input and output signals are directly acquired and measured on the daughterboard via an oscilloscope connected to an SMA coaxial cable to ensure test accuracy. In the test platform, most external instruments have a SENSE feedback line. The connection point of the feedback line in the circuit determines the test accuracy. Considering that this test platform is for DPUT chip application verification, the SENSE line is connected to the input and output capacitors of the DPUT chip, where feasible.

[0075] In some exemplary embodiments, the load subboard is provided with an amplification circuit, which is configured to amplify the response signal after acquiring the response signal output by the power management chip under test, and send the amplified response signal to the control board.

[0076] In some exemplary embodiments, the control board includes a control core module, a second power supply module, a communication interface module, a relay switch matrix, an adjustable power supply module, and a digital channel module.

[0077] refer to Figure 2 This is a schematic diagram of a control panel provided in an exemplary embodiment of the present disclosure.

[0078] The control board is the core of the test platform, and its main functions include host computer communication, relay control, peripheral power supply modules, and digital channel functions. Its structure includes: a control core module, a relay switch matrix, a power supply module and communication interface module, an adjustable power supply module, and a digital channel module.

[0079] refer to Figure 3 This is a schematic diagram of a Sparton6 power module circuit provided in an exemplary embodiment of the present disclosure.

[0080] refer to Figure 4 This is a schematic diagram of a Bank memory circuit provided in an exemplary embodiment of the present disclosure.

[0081] refer toFigure 5 This is a schematic diagram of a download mode selection circuit provided in an exemplary embodiment of the present disclosure.

[0082] The control core module can utilize Xilinx's Sparton 6 series FPGAs. This series of FPGAs is a high-capacity FPGA that employs 45nm low-power copper plating technology, achieving a good balance between power consumption, performance, and cost. Internally, it features dual registers, a 6-input LUT, and a series of built-in test platform modules. These test platform modules include 18kb Block RAM, a second-generation DSP48A21 Slice, an SDRAM memory interface (DDR interface), a robust hybrid clock management module, Select IO technology, an optimized high-speed serial transceiver GTP Transceiver, a PCIe interface, advanced test platform-level power management modes, automatic configuration detection, and enhanced IP with AES and Device DNA protection.

[0083] refer to Figure 6 For FPGA program loading, flash connections are as follows: Figure 6 As shown: MOSI is connected to the SPI flash data input pin. After sending commands and addresses to the SPI flash device, the MOSI pin becomes high impedance. DIN is the serial data input pin, used to receive serial data from the FPGA data source. DIN needs to be connected to the serial data output pin source. The FCS flash chip selector supports SPI flash device configuration.

[0084] refer to Figure 7 The global clock line can be driven by a global clock buffer, which can also perform fault-free clock multiplexing and clock enable functions. Configure the clock inputs, outputs, and grounding terminals, and provide capacitors and resistors of specific sizes according to the instruction manual to ensure that the clock circuit's inputs and outputs meet expectations.

[0085] Power Module: The control board's power module is responsible for configuring the 5V input of the external DC regulated power supply to 3.3V and 1.2V to power the FPGA and other control chips. To ensure the accuracy of the FPGA power supply, this platform selects Texas Instruments' "TLV62130" power management chip. This chip has a high input voltage range of 3-17V, and the output voltage can be guaranteed to fluctuate within a range of 0.9-5.5V with 5% accuracy. Its maximum output current can reach 3A. Furthermore, the chip has a "SENSE+" telemetry voltage function, which can be connected to the chip under test (DUT) to adjust the output voltage in real time and ensure the accuracy of the supply voltage. Its compact 3mm*3mm VQFN package reduces the complexity of board layout. This power management chip also features output soft-start functionality to control the power rise time, and has a "PowerGood" function that allows multiple power rails to be connected in series.

[0086] refer to Figure 8 The communication interface module is designed to facilitate communication between the test platform and the host computer. To improve the versatility of the test platform, a replaceable universal communication module is used in this design. First, on the control board, the connection relationship with the communication module is designed according to fixed interfaces. Its signals must include: receiver, transmitter, power supply, and ground. Simultaneously, the communication module sub-boards also follow the same interface definition to design communication module sub-boards with different standards. The serial port module uses the "MAX13236" chip as its main chip. This chip has a wide input voltage range, an output voltage range of 3-5.5V, a speed of 3Mbps, and strong anti-interference capabilities.

[0087] In some exemplary embodiments, the relay switch matrix is ​​configured to configure the excitation signal and test signal of the instrument according to the test command.

[0088] refer to Figure 9The relay switch matrix on the control board is used to connect the excitation signals and test signals from external source meters to the test circuit according to the test items. The relay matrix includes two types of relays: Panasonic's ALZN1B05W and OMRON's G6K-2F. The Panasonic ALZN1B05W can withstand 16A DC current and is mainly used to connect the input / output test circuits of the power supply under test (DPUT) and the DPUT chip, meeting the electrical parameter ranges of the DPUT chip and external instruments. Its maximum on-resistance is 100mΩ; connecting the terminals in parallel in the circuit can further reduce the on-resistance. The OMRON G6K-2F is used to connect the functional pin test circuits of the DPUT and the DPUT chip. When the DPUT and the DPUT chip have positive and negative outputs, the test platform tests the positive and negative output terminals respectively. The test circuit uses a relay to switch the circuit path to ensure the correct connection of the test instruments to the circuit.

[0089] In some exemplary embodiments, the adjustable power supply module includes a voltage converter and a programmable power management chip under test.

[0090] The voltage converter is configured to convert the power supply voltage into a target voltage;

[0091] The programmable power management chip under test is configured to output the target voltage.

[0092] Adjustable Power Supply Module: The adjustable power supply module employs a two-stage power control. The first stage uses a DC-DC converter to provide the appropriate voltage for subsequent voltage conversions. The advantage of DC-DC converters is their high conversion efficiency. The disadvantage is their high output noise. The second stage uses the AD5560 as the adjustable output. This power management chip under test has high output accuracy and low noise. However, its disadvantage is that the additional voltage drop is consumed by itself, resulting in significant heat generation. The two stages work together; the first stage converts the power supply to the voltage required by the second stage, and then the second stage outputs the accurate desired voltage.

[0093] In some exemplary embodiments, the digital channel module includes an FPGA control unit, a vector storage module, a program storage module, a power supply module, a driver module, a communication board communication interface, and a channel output interface.

[0094] Digital Channel Module: The digital channel module is mainly responsible for vector expansion, arbitrary signal generation, signal capture, and correct / incorrect signal determination. This module includes an FPGA control unit, vector storage module, program storage module, power supply module, driver module, and communication board interfaces and channel output interfaces. The FPGA control unit is responsible for algorithm generation, vector expansion, generation of various trigger edges, and generation of arbitrary cycles. In this design, a Xilinx K7 series FPGA is used for implementation. The vector storage module is used to store vectors. It mainly includes DDR chips, DDR reference voltage, and a 200MHz clock reference module. Due to the large depth of the actual vectors, a dedicated large-capacity storage is required for vector placement. Furthermore, due to the actual speed requirements, DDR3 is used for vector storage. DDR3 has strict requirements in both the actual physical structure design and logic function design, so special processing is necessary. This design uses Micron's MT41J128M16, which has a size of 2Gbit, can hold a maximum of 32M rows of test vectors, and has a maximum storage speed of 1866MT / s, fully meeting the requirements of this design. The reference voltage chip used is the TI TPS51206. The TPS51206 power management chip under test (DUT) is a double data rate (DDR) terminating regulator with a VTTREF buffered reference output. This DUT is specifically designed for space-constrained test platforms with low input voltage, low cost, and low external component count. It maintains a fast transient response and requires only one 10μF ceramic output capacitor. The DUT supports remote sensing and meets all power requirements for DDR2, DDR3, and low-power DDR3 (DDR3L) and DDR4 VTT buses. VTT has a ±2A peak current capability. The DUT supports all DDR power states, placing VTT in a high-impedance state (suspended to RAM) in S3 state and discharging VTT and VTTREF (suspended to disk) in S4 / S5 states. The driver module used is the Analog Devices ADATE305 driver chip. The ADATE305 is a complete single-chip solution for performing driver, comparator, and active load (DCL) functions, a per-pin PMU, and DC-level pin electronics in ATE applications. It also integrates an HVOUT driver and a VHH buffer, capable of generating voltages up to 13.5V. The driver provides three active states: data high, data low, and timeout, as well as a suppressor state. The suppressor state, when used with integrated dynamic clamping, facilitates high-speed active termination. By adjusting the positive and negative supply voltages, the ADATE305 supports two output voltage ranges: -2.0V to +6.0V and -1.5V to +6.0V.

[0095] In some exemplary embodiments, the driving module is configured as a dual single-ended driving / receiving channel or a single differential driving / receiving channel;

[0096] Each of the channels is configured to provide a high-speed window comparator for functional testing, as well as a single-pin PMU with programmable voltage / current output and high-precision voltage / current measurement capabilities.

[0097] The ADATE305 can be used as either a dual single-ended drive / receive channel or a single differential drive / receive channel. Each channel provides a high-speed window comparator for functional testing, as well as a single-pin PMU with FV / FI and MV / MI functions. All DC levels required for the DCL function are generated by an on-chip 14-bit DAC. The single-pin PMU features an on-chip 16-bit DAC for high-precision operation and integrates range setting resistors to minimize the number of external power management devices (PDDs) required. This design enables output of excitation waveforms, comparison of PDD return waveforms, and measurement of various parameters such as VOL and VOH.

[0098] refer to Figure 10 This is a schematic diagram of the software framework of the host computer provided in an exemplary embodiment of this disclosure.

[0099] The software is primarily used for functional verification of typical power management chips under test (PDT). During operation, it manages the DDT, controls peripheral testing equipment and control boards, controls the test process, displays test results in real-time, and saves test data. Different modules are developed for different functions, working together to form a complete software testing platform to achieve the following: DDT chip management: Divided into two lists (large and small models), allowing for adding, deleting, and modifying DDT chips. Device control: Provides control functions for power supply equipment, oscilloscopes, and other peripheral devices during the test process. User interface module: Provides parameter configuration and real-time display of test results. Database management: Provides adding, deleting, and modifying operations for various tables. Test process control: Calls various modules to implement the DDT chip testing functionality. To achieve these functions, the software is divided into a user interface module, an information management module, a hardware communication module, a test process control module, and sub-modules implementing specific functions (data conversion, file management, text output, etc.). The user interface module mainly includes: a window management module, a configuration information management module, and a display management module. The chip information management module is responsible for adding, deleting, and modifying chip information, and loads and saves data by manipulating the chip information data model and file management module. The hardware communication module is responsible for communication with the lower-level machine, including a data conversion module, a communication protocol module, and a port module. The test process control module implements all chip testing methods by calling various sub-modules, and then organizes these into a complete test process.

[0100] This exemplary embodiment discloses a test platform designed for the performance verification and experimentation of power management chips such as LDO (Low Dropout Linear Regulator), voltage reference chips, and microcircuit modules. From an application perspective, it enables comprehensive testing and verification of parameters such as the output load capacity, output accuracy, input voltage threshold, rise time, fall time, and DC parameters of control pins for power management chips.

[0101] This disclosure adopts a sub-board and control board design. All input signals for the power management chip under test (PDT) are provided by the control board. For different types of PDTs, only a customized sub-board is needed to complete the testing, saving testing time and costs. Since PDTs come in various forms, including multi-input, multi-output, and multi-control types, the test platform provides a sufficient number of test signals to meet the testing needs of different types of PDTs. Regarding the isolation between different channels of the power supply, the input signals of each channel need to be configured independently. The test signals provided by the test platform can be flexibly switched on and off without affecting each other.

[0102] This disclosure provides verification functions for various power management chips. For power management chips under test in different applications, there are situations where the load current is high. In this invention, due to the structural limitations of the test platform, the input and output signals of the power management chip under test must pass through a certain length of traces, connectors, or switches before being transmitted to the chip. During this process, line loss caused by the excessive input and output current of the power management chip under test is unavoidable, which directly leads to inaccurate measurement of the input and output voltages of the power management chip under test. To address this, this disclosure first uses an instrument with a SENSE readback function as the input source and load of the power management chip under test; secondly, in the circuit design, the circuit connection point of the SENSE line is placed as close as possible to the pins of the power management chip under test without affecting the circuit control function, to ensure measurement accuracy. When performing power ripple rejection ratio testing on the test platform, an oscilloscope is used to read the input and output signal ripple of the power management chip under test. However, due to the bandwidth limitations of the oscilloscope itself, the measurement accuracy is limited. In the design of the daughterboard, on the one hand, this disclosure adopts an approximate "in-proximity" method, that is, the probe directly measures to provide the shortest grounding loop, which can eliminate some high-frequency noise interference; on the other hand, for cases where the output ripple value is too small, the daughterboard can provide a low offset voltage, high gain, and low noise amplifier circuit for the output ripple of the power management chip under test, and then the amplifier output can be measured with an oscilloscope, which greatly improves the accuracy of the test.

[0103] In related technologies, ATE (Automatic Test Equipment) is commonly used to test power management chips (PDS). However, these are generally immovable after installation, making it impossible to perform multi-stress condition assessments on the DPS. This disclosure presents a dedicated test platform for power management chips, which is portable and can be used with environmental testing equipment such as temperature chambers, low-pressure chambers, and vibration tables, offering flexibility. Furthermore, it features a general-purpose control board and customized sub-board structure specifically designed for the characteristics of power management chips. Compared to the general structure and performance characteristics of commonly used ATE, this platform is more targeted and focused. Based on the verification requirements of power management chips, a specialized control board and sub-board are designed, shortening the development cycle and reducing technical investment.

[0104] For ease of description, the above apparatus is described in terms of its functions, divided into various modules. Of course, in implementing this disclosure, the functions of each module can be implemented in one or more software and / or hardware.

[0105] It should be noted that although several modules or units for the device used to perform actions have been mentioned in the detailed description above, this division is not mandatory. In fact, according to embodiments of this disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided and embodied by multiple modules or units.

[0106] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this disclosure (including the claims) is limited to these examples; within the framework of this disclosure, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this disclosure as described above, which are not provided in detail for the sake of brevity.

[0107] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this disclosure, the provided drawings may or may not show well-known power / ground connections to integrated circuit (IC) chips and other components. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this disclosure, and this also takes into account the fact that the details of implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this disclosure will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuitry) have been set forth to describe exemplary embodiments of this disclosure, it will be apparent to those skilled in the art that the embodiments of this disclosure may be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0108] Although this disclosure has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.

[0109] This disclosure is intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

[0110] While the spirit and principles of this disclosure have been described with reference to several specific embodiments, it should be understood that this disclosure is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined for benefit; such division is merely for convenience of expression. This disclosure is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. The scope of the appended claims is to be interpreted in the broadest sense, thereby encompassing all such modifications and equivalent structures and functions.

Claims

1. A test platform for a power management chip, the test platform comprising: The system comprises a host computer, a control board, a load daughter board and an instrument; The host computer, the load daughter board and the instrument are connected with the control board; The host computer is configured to send a test instruction to the control board and receive a test result sent by the control board; The control board is configured to receive the test instruction sent by the host computer, configure the instrument based on the test instruction, send a test signal to the load daughter board, receive a response signal sent by the load daughter board, obtain the test result based on the response signal, and send the test result to the host computer; The load daughter board is configured to carry a power management chip under test, receive the test signal sent by the control board, match the test signal to the power management chip under test, obtain the response signal output by the power management chip under test, and send the response signal to the control board; The load daughter board is provided with a load circuit configured to provide a peripheral circuit for the power management chip under test, and the control board is further configured to switch the type of the load circuit.

2. The platform of claim 1, wherein, The instrument has a SENSE readback function.

3. The platform of claim 1, wherein, The instrument comprises a first power supply, a signal generator, a multimeter, an oscilloscope and a source measurement unit.

4. The platform of claim 3, wherein, The oscilloscope and the load daughter board are connected through an SMA coaxial cable; The oscilloscope is configured to send an input signal to the power management chip under test on the load daughter board through the SMA coaxial cable and obtain an output signal output by the power management chip under test.

5. The platform of claim 1, wherein, The load daughter board is provided with an amplification circuit configured to amplify the response signal output by the power management chip under test and send the amplified response signal to the control board.

6. The platform of claim 1, wherein, The control board comprises a control core module, a second power supply module, a communication interface module, a relay switch matrix, an adjustable power supply module and a digital channel module.

7. The platform of claim 6, wherein, The relay switch matrix is configured to configure the excitation signal and the test signal of the instrument according to the test instruction.

8. The platform of claim 6, wherein, The adjustable power supply module comprises a voltage converter and a programmable power supply for the power management chip under test; The voltage converter is configured to convert a power supply voltage into a target voltage; The programmable power supply for the power management chip under test is configured to output the target voltage.

9. The platform of claim 6, wherein, The digital channel module comprises an FPGA control unit, a vector storage module, a program storage module, a power supply module, a drive module, a communication board communication interface and a channel output interface.

10. The platform of claim 9, wherein, The drive module is configured as a double single-ended drive / receive channel or a single differential drive / receive channel; Each channel is configured to provide a high-speed window comparator for functional testing, and a single-pin PMU with programmable voltage / current output function and high-precision voltage / current measurement function.

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