Code compilation methods, devices, electronic devices, and readable storage media

Abstract

This application provides a code compilation method, apparatus, electronic device, and readable storage medium, relating to the field of processor technology. The method includes: obtaining assignment statements in the code to be compiled, and registers corresponding to each variable in the assignment statements; if there are conflict registers with multiple corresponding variables in the registers, setting a shadow register and a semaphore for each variable corresponding to the conflict registers; compiling the code to be compiled into first hardware description language code including shadow registers and semaphores; the shadow registers are used to write the variable values ​​of the variables corresponding to the shadow registers; the semaphores are used to sequentially write the variable values ​​in the shadow registers to the conflict registers according to the priority of the variables after the variable values ​​are written to the shadow registers. The method of this application can solve the multi-source drive error problem when multiple assignment statements assign values ​​to the same variable during code compilation.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to a code compilation method, apparatus, electronic device, and readable storage medium. Background Technology

[0002] Hardware Description Language (HDL) can be used to describe the structure and behavior of hardware. HDL languages ​​have wide applications in scenarios such as simple logic circuit development and complex chip development.

[0003] Assignment statements can be used to assign values ​​to variables and write the results to the corresponding registers. However, due to limitations of hardware description languages, if multiple assignment statements assign values ​​to the same variable, multiple variable values ​​will be written to the same register simultaneously, causing a multi-drive error. Currently, there is a lack of methods in related technologies to solve this problem. Summary of the Invention

[0004] This application provides a code compilation method, apparatus, device, and medium to solve the problem of multiple drive errors that occur when multiple assignment statements assign values ​​to the same variable in the prior art.

[0005] In a first aspect, embodiments of this application provide a code compilation method, including:

[0006] Obtain the code to be compiled, the assignment statements in the code to be compiled, and the register corresponding to each variable in the assignment statements; the assignment statements are used to assign values ​​to the variables.

[0007] If there is a conflicting register with multiple corresponding variables in the register, then a shadow register and a semaphore are set for each variable corresponding to the conflicting register; the shadow registers of each variable corresponding to the conflicting register are different from each other;

[0008] The code to be compiled is compiled into a first hardware description language code that includes the shadow register and semaphore;

[0009] The shadow register is used to write the variable value of the variable corresponding to the shadow register; the semaphore is used to write the variable value in the shadow register sequentially into the conflict register according to the priority of the variable after the variable value is written into the shadow register.

[0010] Secondly, embodiments of this application provide a code compilation apparatus, the apparatus comprising:

[0011] The first acquisition module is used to acquire the code to be compiled, the assignment statements in the code to be compiled, and the registers corresponding to each variable in the assignment statements; the assignment statements are used to assign values ​​to the variables.

[0012] The setting module is used to set a shadow register and a semaphore for each variable corresponding to the conflicting register if there is a conflicting register with multiple corresponding variables in the register; the shadow registers of each variable corresponding to the conflicting register are different from each other;

[0013] A compilation module is used to compile the code to be compiled into first hardware description language code including the shadow register and semaphore;

[0014] The shadow register is used to write the variable value of the variable corresponding to the shadow register; the semaphore is used to write the variable value in the shadow register sequentially into the conflict register according to the priority of the variable after the variable value is written into the shadow register.

[0015] Thirdly, embodiments of this application also provide an electronic device, including a processor;

[0016] Memory used to store the processor's executable instructions;

[0017] The processor is configured to execute the instructions to implement the method of the first aspect.

[0018] Fourthly, embodiments of this application also provide a computer-readable storage medium that, when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, enables the electronic device to perform the method of the first aspect.

[0019] In this embodiment, the code to be compiled, the assignment statements in the code to be compiled, and the registers corresponding to the variables in the assignment statements are obtained. The variables in the assignment statements are those that need to be assigned values ​​through the assignment statements; the registers corresponding to the variables in the assignment statements are registers used to write the variable values ​​assigned to the variables by the assignment statements. If there are conflict registers with multiple corresponding variables, a shadow register is set for each variable corresponding to the conflict register. The shadow register is used to write the variable value of the variable corresponding to the shadow register. Therefore, even if there are conflict registers with multiple corresponding variables, the variable values ​​of the multiple variables corresponding to the conflict register will not be written to the conflict register simultaneously, but will be written to their respective shadow registers. After writing to the shadow registers, based on semaphores and according to the priority of each variable, the variable values ​​are sequentially written to the conflict registers. This solves the problem of multi-drive errors that occur when multiple variable values ​​are written to conflict registers simultaneously in related technologies.

[0020] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram illustrating an application scenario of a code compilation method provided in an embodiment of this application;

[0023] Figure 2 This is a flowchart of a code compilation method provided in an embodiment of this application;

[0024] Figure 3 This is a flowchart of another code compilation method provided in an embodiment of this application;

[0025] Figure 4 This is a flowchart of another code compilation method provided in the embodiments of this application;

[0026] Figure 5 This is a block diagram of a code compilation device provided in an embodiment of the present invention;

[0027] Figure 6 This is a block diagram of an electronic device provided in an embodiment of the present invention;

[0028] Figure 7 This is a block diagram of another electronic device according to another embodiment of the present invention. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] The terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and not to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class and are not limited in number; for example, a first object can be one or more. Furthermore, the term "and / or" in the specification and claims is used to describe the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, and B alone. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. In the embodiments of this application, the term "multiple" refers to two or more, and other quantifiers are similar.

[0031] Figure 1 This is a schematic diagram illustrating an application scenario of a code compilation method provided in an embodiment of this application. (Refer to...) Figure 1 Application scenarios include at least compilers.

[0032] During code compilation, the source code to be compiled is input into the compiler, and the compiler compiles it to obtain hardware description language (Verilog) code.

[0033] When compiling code from languages ​​other than Verilog (such as C) into Verilog, each function generates an `always` block. Unlike the sequential execution of code in other languages, the code within each `always` block executes in parallel. If an assignment statement exists within an `always` block, the value of the variable assigned to it is written to the corresponding register. If assignment statements in different `always` blocks assign values ​​to the same variable, the values ​​assigned to that variable by each statement might be written to the register corresponding to that variable simultaneously, leading to a multi-drive error. Currently, there is a lack of methods to address this problem in related technologies.

[0034] In this embodiment, the code to be compiled, the assignment statements in the code to be compiled, and the registers corresponding to the variables in the assignment statements are obtained. The assignment statements are used to assign values ​​to the variables. If there are conflict registers with multiple corresponding variables in the registers, a shadow register and a semaphore are set for each variable corresponding to the conflict register. The code to be compiled is compiled into first hardware description language code including shadow registers and semaphores. The shadow register is used to write the variable values ​​of the variables corresponding to the shadow registers. The semaphores are used to write the variable values ​​in the shadow registers into the conflict registers in order according to the priority of the variables corresponding to the semaphores.

[0035] It should be noted that the above application scenarios are merely illustrative descriptions of the embodiments of this application. In this application, the code that needs to be compiled into Verilog is not limited to C language code, but can also be Python code, natural language description, or code of other language types, which is not limited here.

[0036] The code compilation method provided in this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0037] Figure 2 This is a flowchart of the steps of a code compilation method provided in an embodiment of this application, such as... Figure 2 As shown, the method may include:

[0038] Step 101: Obtain the code to be compiled, the assignment statements in the code to be compiled, and the registers corresponding to each variable in the assignment statements.

[0039] The assignment statement is used to assign a value to a variable; the same variable corresponds to the same register.

[0040] For example, the language type of the code to be compiled can be C, Python, natural language description, or other languages ​​other than Verilog.

[0041] The assignment statement is used to assign a value to a variable. For example, the assignment statement "c_value=0" means to assign a value to the variable "c_value" and assign it the value 0.

[0042] The register corresponding to the variable in the assignment statement is used to write the value of the variable in the assignment statement. The same variable corresponds to the same register. For example, if the variable in the assignment statements "c_value=0" and "c_value=1" is "c_value", then the register corresponding to the variable "c_value" in these two assignment statements is the same register.

[0043] Step 102: If there is a conflict register with multiple corresponding variables in the register, then set a shadow register and a semaphore for each variable corresponding to the conflict register.

[0044] In this context, the shadow registers of each variable corresponding to the conflict register are different from each other.

[0045] For example, if the code to be compiled includes the assignment statements "c_value=0" and "c_value=1", and the register corresponding to the variable "c_value" in these two assignment statements is the same register; in other words, if the register corresponds to two identical variables "c_value", then the register corresponding to the variable "c_value" is the conflict register.

[0046] Step 103: Compile the code to be compiled into first hardware description language code that includes shadow registers and semaphores.

[0047] The shadow register is used to write the variable value corresponding to the shadow register; the semaphore is used to write the variable value in the shadow register sequentially to the conflict register according to the priority of the variable after the variable value is written to the shadow register.

[0048] After the code to be compiled into the first hardware description language (HTALY) code, different assignment statements can generate different always blocks during the execution of the HTALY code. In Verilog code, the code in different always blocks can execute simultaneously. When executing assignment statements in different always blocks, the values ​​of the variables in the assignment statements are not written to the conflict register, but to the shadow register. Because the shadow registers corresponding to different variables are different, even if multiple values ​​of the same variable are written simultaneously, the problem of multiple identical variable values ​​being written to the same register, thus avoiding the multi-drive error, will not occur.

[0049] After writing the variable values ​​to the shadow register, the variable values ​​in the shadow register are then written sequentially to the conflict register according to the semaphore and the variable priority. Because the variable values ​​obtained from the shadow register are written to the conflict register sequentially, multi-drive errors caused by multiple variable values ​​being written to the conflict register simultaneously will not occur.

[0050] Variables with the same identifier (e.g., variable name) have the same register, and the registers corresponding to the same variables are called conflict registers. The identifiers of the same variables can be changed to different identifiers, thereby changing their corresponding registers; specifically, the conflict register is changed to a shadow register.

[0051] After setting a shadow register for the variable corresponding to the conflict register, multiple source writes of the same variable can be avoided. For the write to take effect, the variable value in the shadow register also needs to be written into the conflict register. For example, an always block can be generated to write the variable value in the shadow register into the conflict register. Specifically, a semaphore mechanism can be used to sequentially write the variable value in the shadow register into the conflict register.

[0052] In this embodiment, the code to be compiled, the assignment statements in the code to be compiled, and the registers corresponding to the variables in the assignment statements are obtained. The variables in the assignment statements are those that need to be assigned values ​​through the assignment statements; the registers corresponding to the variables in the assignment statements are registers used to write the variable values ​​assigned to the variables by the assignment statements. If there are conflict registers with multiple corresponding variables, a shadow register is set for each variable corresponding to the conflict register. The shadow register is used to write the variable value of the variable corresponding to the shadow register. Therefore, even if there are conflict registers with multiple corresponding variables, the variable values ​​of the multiple variables corresponding to the conflict register will not be written to the conflict register simultaneously, but will be written to their respective shadow registers. After writing to the shadow registers, based on semaphores and according to the priority of each variable, the variable values ​​are sequentially written to the conflict registers. This solves the multi-drive error problem that occurs when multiple variable values ​​are written to conflict registers simultaneously in related technologies.

[0053] Reference Figure 3 The method in this embodiment may include the following steps:

[0054] Step 201: Obtain the mixed source code.

[0055] The hybrid source code includes a second hardware description language code and code to be compiled; the code to be compiled includes a first code belonging to a high-level language and / or a second code belonging to a natural language description.

[0056] For example, the high-level language can be C, Python, or other high-level languages.

[0057] For example, step 201 may include the following sub-steps:

[0058] Sub-step A1: Configure environment parameters for the code to be compiled.

[0059] The environmental parameters include a preset clock signal and / or a preset reset signal; the name of the preset clock signal is the same as the name of the clock signal in the second hardware description language, and the name of the preset reset signal is the same as the name of the reset signal in the second hardware description language.

[0060] Sub-step A2 involves inserting the code to be compiled, configured with environment parameters, into a source file containing a second hardware description language to obtain hybrid source code.

[0061] For example, the code for inserting minimal environment parameters into C language code is shown below:

[0062] #pragma c_start

[0063] #pragma “clk_n,rst_n”

[0064] void main()

[0065] {

[0066] / / C code

[0067] }

[0068] #pragma c_end

[0069] Here, the string "#pragma c_start" represents the name of the clock signal, and the string "#pragma "clk_n,rst_n"" represents the name of the reset signal. These two signals will be used for code generation during the subsequent HLS compilation stage.

[0070] In this embodiment, environment parameters are configured for the code to be compiled. The code to be compiled with the environment parameters configured is then inserted into a source file containing a second hardware description language to obtain hybrid source code. The environment parameters include a preset clock signal and / or a preset reset signal. The name of the preset clock signal is the same as the name of the clock signal in the second hardware description language, and the name of the preset reset signal is the same as the name of the reset signal in the second hardware description language. Inserting the code to be compiled with the environment parameters configured into a source file containing a second hardware description language results in highly usable hybrid source code. After compiling the hybrid source code to obtain a Verilog compilation result, the execution of the compilation result will not result in errors due to the existence of multiple clock signal names and multiple reset signal names.

[0071] For example, step 202 may also include the following sub-steps:

[0072] Sub-step B1: Obtain the circuit type of the circuit to be described.

[0073] Circuit types can include the functional type of the circuit, the circuit structure type, etc.

[0074] Sub-step B2: Obtain the language type that matches the circuit type and generate the code to be compiled belonging to the language type.

[0075] The code to be compiled corresponds to the circuit to be described.

[0076] For example, the language type of the code to be compiled should match the type of hardware structure and / or hardware behavior described by the code. For instance, if the described hardware belongs to at least one of the following categories, the corresponding code to be compiled can be high-level language code (e.g., C language code): circuit parts with low timing requirements, algorithmic circuit parts, and circuit parts that need to be completed quickly. Here, circuit parts that need to be completed quickly refer to circuits that can be quickly prototyped after the circuit design requirements are given; in other words, for circuit parts with a relatively short design cycle, a high-level language can be used to complete them in seconds.

[0077] For example, if the hardware being described is simple in structure or has low requirements, the corresponding code to be compiled can be a natural language description. Low-requirement hardware refers to hardware components with relatively low requirements for area, performance, power consumption, execution efficiency, and execution speed, or those with relatively low requirements for compilation speed.

[0078] Furthermore, for circuit components that can be described using high-level language code and natural language as mentioned above, they can be directly described using Verilog code.

[0079] In this embodiment, based on the circuit type of the circuit to be described, a language type compatible with the circuit type is obtained, and code to be compiled belonging to that language type is generated, improving the flexibility of obtaining the code to be compiled. The code to be compiled is the code compatible with the circuit type of the circuit to be described. The code to be compiled is inserted into the second hardware description language code to obtain hybrid source code. The hybrid source code can combine the advantages of the code to be compiled and the second hardware description language code.

[0080] The environmental parameters include a preset clock signal and / or a preset reset signal; the name of the preset clock signal is the same as the name of the clock signal in the first hardware description language, and the name of the preset reset signal is the same as the name of the reset signal in the first hardware description language.

[0081] Step 202: Extract the code to be compiled from the mixed source code.

[0082] In this embodiment, hybrid source code is obtained. The hybrid source code includes second hardware description language code and code to be compiled. The code to be compiled includes first code belonging to a high-level language and / or second code belonging to a natural language description. Obtaining the code to be compiled includes extracting the code to be compiled from the hybrid source code. Compared to related technologies that obtain code of a single language type and convert it to Verilog code, this embodiment can obtain hybrid source code containing second hardware description language code, first code belonging to a high-level language, and / or second code belonging to a natural language description, improving the flexibility of obtaining the hybrid source code to be compiled and reducing the difficulty of obtaining it. For example, if the developer is more familiar with high-level language code, they can generate first code in a high-level language for the circuit to be described and insert it into an existing second hardware description language to obtain the hybrid source code. During the compilation of the hybrid source code, only the code to be compiled that does not belong to Verilog needs to be extracted and compiled, improving the flexibility of the method.

[0083] For example, step 201 may include the following sub-steps:

[0084] Sub-step B1: Insert the code to be compiled into the second hardware description language.

[0085] Specifically, obtain the Verilog source file containing the second hardware description language, and insert the code to be compiled into the source file.

[0086] Sub-step B2 inserts a start position marker and an end position marker at the start and end positions of the code to be compiled, respectively.

[0087] The start and end position identifiers can be set according to user needs, such as letters or a combination of letters and numbers.

[0088] Correspondingly, step 202 may include the following sub-steps:

[0089] Sub-step C1: Identify the start position identifier and the end position identifier.

[0090] The start and end position identifiers can be pre-stored. During processing, the characters in the mixed code are compared with the pre-stored start and end position identifiers to achieve the recognition of the start and end position identifiers.

[0091] Sub-step C2 extracts the code to be compiled between the start position identifier and the end position identifier.

[0092] In one embodiment, the code segment that inserts the start position identifier and the end position identifier can be as follows:

[0093] #pragma c_start

[0094] / / C code

[0095] #pragma c_end

[0096] Here, `pragma c_start` and `pragma c_end` are the start and end position identifiers, respectively. Further, the start position identifier `#pragma c_start` and the end position identifier `c_end` in the mixed source code are identified, and the C language code between the start and end position identifiers `#pragma c_start` and `c_end` is extracted from the source code to be compiled.

[0097] In this embodiment, code to be compiled is inserted into a second hardware description language. A start position identifier and an end position identifier are inserted at the start and end positions of the code to be compiled, respectively. During the extraction of the code to be compiled from the mixed source code, only the start and end position identifiers need to be identified to accurately extract the code between them. Based on this embodiment, the inserted start and end position identifiers enable automatic and accurate separation of code from different language types.

[0098] If the code to be compiled includes second code belonging to a natural language description, the following steps are included after step 201:

[0099] Step 203: Convert the second code into conversion code belonging to a high-level language.

[0100] For example, High-Level Synthesis (HLS) tools can be used to convert the second code into conversion code belonging to a high-level language.

[0101] Step 204: Based on the conversion code, obtain the assignment statement and the register corresponding to each variable in the assignment statement.

[0102] Step 205: If there is a conflict register with multiple corresponding variables in the register, then set a shadow register and a semaphore for each variable corresponding to the conflict register.

[0103] In this context, the shadow registers of each variable corresponding to the conflict register are different from each other.

[0104] The shadow register is used to write the variable value corresponding to the shadow register; the semaphore is used to write the variable value in the shadow register sequentially to the conflict register according to the priority of the variable corresponding to the semaphore.

[0105] If the identifier (e.g., name) of the variable to be assigned is the same in different assignment statements, it means that the variables in different assignment statements are the same, and these variables correspond to the same register, which is a conflict register.

[0106] Set a shadow register for each variable corresponding to the conflict register, including: modifying the variable name of the variable corresponding to the conflict register so that the names of each variable are different.

[0107] Registers corresponding to the same variable name are the same. After the variable names are modified to be different from each other, the registers corresponding to each variable are different. These registers are used to temporarily store the variable values ​​of the variables corresponding to the registers. These registers are the shadow registers in this embodiment.

[0108] Step 206: The conversion code is compiled into first hardware description language code that includes shadow registers and semaphores.

[0109] In related technologies, artificial intelligence or machine learning methods can be used to directly convert natural language descriptions into Verilog code using large-scale training sets and corpora. However, this approach requires labeling a large number of matching pairs between natural language descriptions and Verilog code to obtain training data. The training process requires large-scale, high-quality training data, which is time-consuming and labor-intensive. Furthermore, the scope of manually constructed matching pairs is limited and cannot cover all application scenarios. Because it is difficult to construct a sufficiently large and high-quality training set (e.g., accurate matching between natural language descriptions and Verilog), the conversion performance of directly converting natural language descriptions to Verilog is poor, and this method, which requires manual construction of training data, suffers from inefficiency.

[0110] In this embodiment, the second code is converted into conversion code belonging to a high-level language. Based on the conversion code, assignment statements and the registers corresponding to each variable in the assignment statements are obtained. If there are conflicting registers with multiple corresponding variables, a shadow register and a semaphore are set for each variable corresponding to the conflicting register. The shadow registers of each variable corresponding to the conflicting register are different from each other. The conversion code is compiled into first hardware description language code including shadow registers and semaphores. By converting the second code belonging to natural language description into conversion code belonging to a high-level language, and then compiling the conversion code into first hardware description language code, compared with the related technology of directly converting natural language description into Verilog code, the conversion result of the second code belonging to natural language description into first hardware description language code in this embodiment has high accuracy.

[0111] Obtaining a large number of matching pairs between natural language descriptions and Verilog code is quite challenging, while in practical applications, there is a wealth of mapping data between natural language descriptions and high-level language code. Therefore, in this embodiment, the mapping data between natural language descriptions and high-level language code used in the process of converting the second code of the natural language description into the conversion code of the high-level language is easier to obtain, reducing the difficulty of obtaining training data in related technologies and improving processing efficiency.

[0112] Compared to mapping from natural language descriptions to Verilog code, mapping between natural language descriptions and high-level language code is more universal and can cover a wider range of application scenarios. Therefore, compared to related technologies, this embodiment has a broader range of application scenarios.

[0113] Compared to Verilog code, high-level language code has a wider range of applications. Therefore, in this embodiment, the second code describing the natural language is first converted into high-level language conversion code, and then the high-level language conversion code is converted into Verilog compilation results by the compiler, which reduces the development difficulty for developers.

[0114] The high-level language (C code) generated in this embodiment has good readability and structure. Designers can directly review, modify or optimize intermediate results, realize the "human-in-the-loop" design process, enhance controllability, and improve the interpretability and controllability of the processing.

[0115] For example, after the second code describing the natural language is converted into the conversion code of the high-level language, the conversion code can be compiled into the first hardware description language belonging to Verilog using the HLS tool.

[0116] In related technologies, methods that directly generate Verilog code using a training set do not require the use of HLS tools and cannot be optimized using HLS tools, such as for pipeline optimization, parallelism extraction, and resource scheduling. In this embodiment, however, HLS tools are used to convert the second code into a first hardware description language, resulting in a more accurate first description language.

[0117] Existing technologies convert natural language descriptions into Verilog code based on machine learning models and training datasets. However, if errors occur during the conversion process, it is difficult to trace the cause of the error, leading to debugging difficulties in the final converted Verilog code. In this embodiment, the code is compiled using the HLS tool. If the compiled first description language code encounters errors, the cause of the error can be traced and debugged.

[0118] Step 207: Merge the first hardware description language and the second hardware description language to obtain the compilation result for the mixed source code.

[0119] In this embodiment, after setting shadow registers and semaphores for each variable corresponding to the conflict register to obtain the code compilation result for the code to be compiled, the first hardware description language and the second hardware description language are merged to obtain the compilation result for the mixed source code. Therefore, the compilation result of the mixed source code can be accurately obtained.

[0120] The following example, using the embedding of C code and natural language descriptions in a single Verilog source file for auxiliary circuit design, further illustrates this embodiment. (Refer to...) Figure 4 The method may include the following steps:

[0121] Step S1: Obtain the mixed source code.

[0122] The mixed source code in the source file to be processed includes second hardware description language code belonging to Verilog code, and code to be compiled, which includes at least one of C language code and natural language description.

[0123] For example, the code to be compiled is inserted into a Verilog file containing a second hardware description language, and a start position marker (e.g., #pragma c_start) and an end position marker (e.g., #pragma c_end) are inserted at the start and end positions of the code to be compiled.

[0124] During the preprocessing stage, the preprocessing module identifies `#pragma c_start` and `#pragma c_end`, and extracts C code from the source code to be compiled based on the keywords used to identify the start and end positions. After the C code is extracted, it is used as the C code for later use; what remains is standard Verilog code.

[0125] For example, a clock signal and a reset signal are set for the code to be compiled. The clock signal has the same name as the clock signal in the second hardware description language, and the reset signal has the same name as the reset signal in the second hardware description language. This ensures that the resulting mixed source code will not have errors during subsequent compilation and execution.

[0126] Step S2: The preprocessor performs code segmentation and extraction on the mixed source code. If the second code belonging to natural language description is extracted, proceed to step S3; if the first code belonging to C language is extracted, proceed to step S4; if the second Verilog code is extracted, proceed to step S5.

[0127] Step S3: Using a large language model and prompt word system, the second code belonging to the natural language description is converted into the conversion code belonging to the C language, and then proceed to step S4.

[0128] Specifically, the process involves obtaining natural language descriptions and their corresponding C language code. A training dataset is then constructed based on these descriptions and the C language code. This training dataset is used to train a large language model and a prompting word system. A more complete prompting word system within the large language model is more conducive to generating accurate C language code.

[0129] After extracting the second code for natural language description from the mixed source code, the second code is input into the trained large language model and prompt word system to obtain the converted code output by the large language model and prompt word system.

[0130] Step S4: Compile the C language code using the HLS compiler to obtain the first Verilog code.

[0131] For C code, minimum environment parameters need to be specified to ensure compatibility with the Verilog code embedded within the C code. For example, minimum environment parameters might include a preset clock signal and a preset reset signal, with the preset clock signal having the same name as the clock signal in the Verilog code, and the preset reset signal having the same name as the reset signal in the Verilog code.

[0132] For example, the code for inserting minimal environment parameters into C language code is shown below:

[0133] #pragma c_start

[0134] #pragma “clk_n,rst_n”

[0135] void main()

[0136] {

[0137] / / C code

[0138] }

[0139] #pragma c_end

[0140] Here, the string "#pragma c_start" represents the name of the clock signal, and the string "#pragma "clk_n,rst_n"" represents the name of the reset signal. These two signals will be used for code generation during the subsequent HLS compilation stage.

[0141] For each C function, an independent always block is generated.

[0142] In software development, accessing and writing the same variable across multiple functions is a common practice. However, due to limitations of the Verilog language, assigning values ​​to the same register within two or more always blocks can cause a multi-drive error during synthesis. This embodiment addresses this multi-drive error by setting a shadow register.

[0143] Furthermore, when a variable has multiple assignment sources, regardless of whether the assignment sources are in the same block (always block) or different always blocks, the variable can be considered to have multiple driving sources. If multiple driving sources assign values ​​to the variable simultaneously, assignment races may occur, which can lead to driving errors.

[0144] In this embodiment, the C language code is automatically analyzed using compilation technology. Specifically, the statements in each function are analyzed, and the register information of all registers written to is recorded and entered into list L.

[0145] After analyzing all functions, list L can be used to obtain the conflict registers with multiple source access conflicts. A conflict register with multiple source access conflicts refers to a register containing the values ​​of multiple variables to be written.

[0146] After obtaining the conflict registers with multi-source access conflicts, the variable names corresponding to these registers are replaced. After the variable names are changed, the corresponding registers are also changed; these changed registers are called shadow registers. Based on this embodiment, shadow registers can be set for conflict registers with multi-source access conflicts; wherein multiple shadow registers are used to temporarily write the variable values ​​of the corresponding variables into the registers.

[0147] After setting the shadow register, in the final generated Verilog code, when writing to the register in each always block, the actual result of the write operation is to write the variable's value to the shadow register, rather than to the conflict register where there is a multi-source access conflict.

[0148] For example, if both functions func1 and func2 corresponding to register A contain assignment statements, the values ​​assigned to variables in these statements will be written to register A. In this case, register A becomes a conflict register with multiple source conflicts, and the values ​​of multiple variables corresponding to the conflict register may be written to the conflict register simultaneously, which can lead to a multi-drive error.

[0149] This embodiment resolves the multi-drive error problem caused by conflicting registers by setting shadow registers. For example, if register A has assignment statements in two functions, func1 and func2, two shadow registers, A1 and A2, are automatically created. Each function generates always1 and always2, and always1 actually writes to A1, while always2 writes to A2.

[0150] Setting a shadow register only prevents multiple source writes to the same variable. To make the write effective, a new always register needs to be automatically generated, which is responsible for completing the actual write to register A. That is, the write process needs to be completed in conjunction with the semaphore mechanism.

[0151] Specifically, while automatically generating shadow registers A1 and A2, semaphores W1 and W2 are also generated simultaneously. That is, through compiler processing, when writing variable values ​​to shadow registers, semaphores are also set at the same time, and the semaphores indicate that a write request exists.

[0152] In the automatically generated always block, the semaphore is responsible for handling all write requests and writing to register A according to a preset priority strategy. Specifically, the semaphore, according to the priority corresponding to each variable, sequentially writes the variable values ​​written to shadow registers A1 and A2 into register A.

[0153] In related technologies, artificial intelligence or machine learning methods can be used to directly generate hardware description languages ​​from natural language descriptions based on large-scale training sets and corpora. However, this method relies on a large number of well-annotated natural language description-hardware description pairs as training data, and the time and labor costs of acquiring such data are high. Furthermore, the training data from Huqiu has limited coverage of application scenarios and is difficult to encompass all application scenarios.

[0154] Furthermore, the methods used in these technologies directly convert natural language descriptions into Verilog using artificial intelligence or machine learning. This process does not require processing by HLS tools and therefore cannot leverage the optimization capabilities provided by the HLS toolchain (such as pipelining, parallelism extraction, and resource scheduling) to optimize the code, resulting in low hardware efficiency and poor performance. In other words, these technologies lack high-level comprehensive optimization support.

[0155] Furthermore, the Verilog code generated by related techniques lacks traceability to the original natural language description, making it difficult to verify its functional correctness and increasing the complexity of design verification and debugging. In other words, this method suffers from difficulties in verification and debugging.

[0156] In this embodiment, the natural language description is first converted into a high-level language (e.g., C or Python), and then the high-level language is converted into a hardware description language. This progressive generation method, by introducing a high-level language as an intermediate representation and combining it with high-level synthesis (HLS) technology to generate Verilog code, can overcome the shortcomings of directly converting natural language descriptions into Verilog in related technologies.

[0157] Furthermore, this embodiment does not require acquiring a large amount of natural language descriptions and their corresponding Verilog code; it only needs to obtain the mapping data from the natural language descriptions to the C language to achieve code compilation. The mapping data from natural language descriptions to the C language is richer and easier to obtain. Based on this embodiment, data preparation costs can be significantly reduced.

[0158] In addition, the mapping from natural language description to C language has greater versatility and can cover a wider range of algorithms and application scenarios; at the same time, C language, as a language widely mastered by software engineers, lowers the barrier to entry and reduces the dependence on training data.

[0159] In this embodiment, after converting the natural language description into a high-level language, the code can be compiled using HLS tools to fully utilize HLS optimization capabilities, thereby automatically implementing advanced optimizations such as pipelined processing, parallelization, and resource sharing, generating high-performance, low-power hardware circuits, and improving the final Verilog quality.

[0160] Step S5: Merge the code.

[0161] Step S6: Use a standard Verilog compiler to process the merged code in a unified manner to obtain the compilation result of the mixed source code.

[0162] In this embodiment, the merged code includes: the Verilog code obtained after inputting the C language code into the HLS compiler, and the original Verilog code. After the C language code is converted to Verilog code, both it and the original Verilog code are Verilog code, so they can be merged into the same file.

[0163] After merging them into a single file, you can input all the values ​​into the Verilog compiler to get the final compilation result.

[0164] The method of this embodiment will be further illustrated below with reference to specific examples. In this embodiment, the hybrid source code is shown below:

[0165] reg a;

[0166] always @ (posedge clk_1) begin

[0167] if(rst) begin

[0168] a=1'b0

[0169] end

[0170] else begin

[0171] a<=a+1'b1

[0172] end

[0173] end

[0174] #pragma c_start / / #pragma c_start is the starting position identifier for the code to be compiled.

[0175] #pragma “clk_1,rst” / / clk_1 represents the clock signal, rst represents the reset signal

[0176] int c_value;

[0177] Void main1()

[0178] {

[0179] c_value = 0; / / c_value is the variable in the assignment statement.

[0180] }

[0181] Void main2()

[0182] {

[0183] c_value = 1; / / c_value is the variable in the assignment statement.

[0184] }

[0185] #pragma c_end / / #pragma c_end is the end marker for the code to be compiled.

[0186] The above-mentioned hybrid source code is compiled according to the method of this embodiment, and the compilation result is as follows:

[0187] reg a;

[0188] always @ (posedge clk_1) begin

[0189] If(rst) begin

[0190] a=1'b0;

[0191] end

[0192] else begin

[0193] a<=a+1'b1;

[0194] end

[0195] end

[0196] reg c_value_1;

[0197] reg c_value_2;

[0198] reg c_value_w1;

[0199] reg c_value_w2;

[0200] The main1 function is automatically generated.

[0201] always @ (posedge clk_1) begin

[0202] c_value_1<=1'b0; / / Change the variable name of c_value to c_value_1 so that its value is written to shadow register 1.

[0203] c_value_w1 <= 1; / / c_value_w1 is a semaphore, enabling the write flag.

[0204] end

[0205] The main1 function is automatically generated.

[0206] always @ (posedge clk_1) begin

[0207] c_value_2<=1'b1; / / Change the name of variable c_value to c_value_2 so that its value is written to shadow register 2.

[0208] c_value_w2<=1; / / c_value_w2 is a semaphore, enabling the write flag.

[0209] end

[0210] / / Always block used for actual writing

[0211] always @ (posedge clk_1) begin

[0212] if(c_value_w1==1) begin

[0213] c_value <= c_value_1;

[0214] c_value_w1<=0;

[0215] end

[0216] end

[0217] The above embodiments illustrate the case of embedding C language. In practical applications, natural language descriptions can also be embedded. When embedding natural language descriptions, only one step needs to be added to extract the paragraphs of the natural language description, convert them to C based on the large language model, and then perform the above C to Verilog translation process.

[0218] User-written Verilog code containing C programs is processed by this solution's compiler to generate standard Verilog code. It supports seamless integration between C and Verilog code, allowing mutual access to each other's elements. It can also embed natural language descriptions, converting them into C code using a large language model and a specially constructed prompting word system, and then transpiling them into Verilog using HLS.

[0219] This invention combines natural language description and high-level language circuit description, which can significantly improve the efficiency of circuit design, reduce the development cycle, and has certain economic benefits.

[0220] This invention proposes an architecture that embeds high-level languages ​​(such as C) and natural language descriptions of requirements into RTL, and implements the construction of a complete processing flow. Specifically, it employs a two-stage translation mechanism: natural language description is converted to a high-level language, and then to Verilog, addressing the problems of existing mainstream solutions.

[0221] The register-based language (R) can be used.

[0222] Register-transfer level (RTL) language is used for hardware design and development. RTL is a language used to directly describe hardware circuit structures. RTL demands high skill from developers and has a long development and verification cycle. In related technologies, RTL can be directly generated from natural language descriptions; however, this process relies on a training dataset for a hardware description language (such as Verilog). In practical applications, it is difficult to obtain a sufficiently large Verilog training dataset, resulting in poor performance when directly converting natural language descriptions into RTL.

[0223] In this embodiment, a code generation technique based on a large language model is introduced to convert the requirements of natural language description into a high-level language, and then the high-level language is translated into RTL code. In other words, this embodiment achieves the hybrid use of RTL code and High-level Synthesis (HLS) technology through a two-step conversion scheme. HLS technology can use a high-level language, combined with the software development process, to generate a hardware description language. Based on this embodiment, high-level language and natural language descriptions can be embedded in a single RTL code to assist in describing the hardware.

[0224] This hybrid development approach has at least the following advantages: it combines the strengths of various languages; for example, normal functions can be developed using Verilog. For circuit sections with low timing requirements and needing rapid completion, or in algorithmic circuit units, high-level languages ​​(such as C) can be directly used. For hardware components with even lower requirements, natural language descriptions can be used to describe hardware behavior and generate a hardware description language. In this embodiment, the appropriate language type can be selected based on the hardware characteristics, and then the language in a specific format can be embedded into the Verilog source file to obtain the final Verilog code.

[0225] refer to Figure 5 This illustrates a code compilation apparatus provided in an embodiment of this application. The code compilation apparatus 30 includes:

[0226] The first acquisition module 301 is used to acquire the code to be compiled, the assignment statements in the code to be compiled, and the registers corresponding to each variable in the assignment statements; the assignment statements are used to assign values ​​to the variables.

[0227] The setting module 302 is used to set a shadow register and a semaphore for each variable corresponding to a conflict register if there is a conflict register with multiple corresponding variables in the register; the shadow registers of each variable corresponding to the conflict register are different from each other;

[0228] Compiler module 303 is used to compile the code to be compiled into first hardware description language code including shadow registers and semaphores;

[0229] The shadow register is used to write the variable value corresponding to the shadow register; the semaphore is used to write the variable value in the shadow register sequentially to the conflict register according to the priority of the variable after the variable value is written to the shadow register.

[0230] Optionally, device 30 also includes:

[0231] The second acquisition module is used to acquire hybrid source code before acquiring the code to be compiled; the hybrid source code includes second hardware description language code and code to be compiled; the code to be compiled includes first code belonging to a high-level language and / or second code belonging to a natural language description.

[0232] The first acquisition module 301 includes:

[0233] The first submodule is used to extract the code to be compiled from the mixed source code.

[0234] Optionally, device 30 also includes:

[0235] The merging module is used to merge the first hardware description language and the second hardware description language after compiling the code to be compiled into first hardware description language code including shadow registers and semaphores, to obtain the compilation result for the mixed source code.

[0236] Optionally, the second acquisition module includes:

[0237] The configuration submodule is used to configure environment parameters for the code to be compiled;

[0238] The first code insertion submodule is used to insert the code to be compiled, configured with environment parameters, into the source file containing the second hardware description language to obtain hybrid source code;

[0239] The environmental parameters include a preset clock signal and / or a preset reset signal; the name of the preset clock signal is the same as the name of the clock signal in the second hardware description language, and the name of the preset reset signal is the same as the name of the reset signal in the second hardware description language.

[0240] Optionally, the first acquisition module 301 may include:

[0241] The second acquisition submodule is used to acquire the circuit type of the circuit to be described.

[0242] The third acquisition submodule is used to acquire the target language type that matches the circuit type and generate the code to be compiled belonging to the target language type.

[0243] Optionally, the second acquisition module includes:

[0244] The second insertion submodule is used to insert code to be compiled into the second hardware description language;

[0245] The third insertion submodule is used to insert start position markers and end position markers at the start and end positions of the code to be compiled, respectively.

[0246] The first acquisition submodule includes:

[0247] The identification submodule is used to identify the start and end position identifiers;

[0248] The extraction submodule is used to extract the code to be compiled between the start and end position identifiers.

[0249] Optionally, if the code to be compiled includes second code belonging to a natural language description, the first acquisition module 301 includes:

[0250] The conversion submodule is used to convert the second code into conversion code belonging to a high-level language;

[0251] Based on the conversion code, obtain the assignment statement and the register corresponding to each variable in the assignment statement;

[0252] Compiler module 303 includes:

[0253] The compilation submodule is used to compile the translation code into first hardware description language code, including shadow registers and semaphores.

[0254] In this embodiment, the code to be compiled, the assignment statements in the code to be compiled, and the registers corresponding to the variables in the assignment statements are obtained. The variables in the assignment statements are those that need to be assigned values ​​through the assignment statements; the registers corresponding to the variables in the assignment statements are registers used to write the variable values ​​assigned to the variables by the assignment statements. If there are conflict registers with multiple corresponding variables, a shadow register is set for each variable corresponding to the conflict register. The shadow register is used to write the variable value of the variable corresponding to the shadow register. Therefore, even if there are conflict registers with multiple corresponding variables, the variable values ​​of the multiple variables corresponding to the conflict register will not be written to the conflict register simultaneously, but will be written to their respective shadow registers. After writing to the shadow registers, based on semaphores and according to the priority of each variable, the variable values ​​are sequentially written to the conflict registers. This solves the multi-drive error problem that occurs when multiple variable values ​​are written to conflict registers simultaneously in related technologies.

[0255] Figure 6 This is a block diagram illustrating an electronic device 700 according to an exemplary embodiment. For example, the electronic device 700 may be a mobile phone, computer, digital broadcasting terminal, messaging device, game console, tablet device, medical device, fitness equipment, personal digital assistant, etc.

[0256] Reference Figure 6 The electronic device 700 may include one or more of the following components: a processing component 702, a memory 704, a power supply component 706, a multimedia component 708, an audio component 710, an input / output (I / O) interface 712, a sensor component 714, and a communication component 716.

[0257] Processing component 702 typically controls the overall operation of electronic device 700, such as operations associated with display, telephone calls, data communication, camera operation, and recording operations. Processing component 702 may include one or more processors 720 to execute instructions to complete all or part of the steps of the methods described above. Furthermore, processing component 702 may include one or more modules to facilitate interaction between processing component 702 and other components. For example, processing component 702 may include a multimedia module to facilitate interaction between multimedia component 708 and processing component 702.

[0258] Memory 704 is used to store various types of data to support the operation of electronic device 700. Examples of this data include instructions for any application or method operating on electronic device 700, contact data, phonebook data, messages, pictures, multimedia, etc. Memory 704 can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0259] Power supply component 706 provides power to various components of electronic device 700. Power supply component 706 may include a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to electronic device 700.

[0260] Multimedia component 708 includes a screen that provides an output interface between electronic device 700 and user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touchscreen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, swipes, and gestures on the touch panel. The touch sensors may not only sense the boundaries of touch or swipe actions but also detect the duration and pressure associated with the touch or swipe operation. In some embodiments, multimedia component 708 includes a front-facing camera and / or a rear-facing camera. When electronic device 700 is in an operating mode, such as shooting mode or multimedia mode, the front-facing camera and / or rear-facing camera may receive external multimedia data. Each front-facing camera and rear-facing camera may be a fixed optical lens system or have focal length and optical zoom capabilities.

[0261] Audio component 710 is used to output and / or input audio signals. For example, audio component 710 includes a microphone (MIC) used to receive external audio signals when electronic device 700 is in an operating mode, such as call mode, recording mode, and voice recognition mode. The received audio signals may be further stored in memory 704 or transmitted via communication component 716. In some embodiments, audio component 710 also includes a speaker for outputting audio signals.

[0262] I / O interface 712 provides an interface between processing component 702 and peripheral interface modules, such as keyboards, click wheels, buttons, etc. These buttons may include, but are not limited to, home buttons, volume buttons, power buttons, and lock buttons.

[0263] Sensor assembly 714 includes one or more sensors for providing state assessments of various aspects of electronic device 700. For example, sensor assembly 714 may detect the on / off state of electronic device 700, the relative positioning of components such as the display and keypad of electronic device 700, changes in position of electronic device 700 or a component of electronic device 700, the presence or absence of user contact with electronic device 700, orientation or acceleration / deceleration of electronic device 700, and temperature changes of electronic device 700. Sensor assembly 714 may include a proximity sensor configured to detect the presence of nearby objects without any physical contact. Sensor assembly 714 may also include a light sensor, such as a CMOS or CCD image sensor, for use in imaging applications. In some embodiments, sensor assembly 714 may also include an accelerometer, gyroscope, magnetometer, pressure sensor, or temperature sensor.

[0264] Communication component 716 facilitates wired or wireless communication between electronic device 700 and other devices. Electronic device 700 can access wireless networks based on communication standards, such as WiFi, carrier networks (such as 2G, 3G, 7G, or 5G), or combinations thereof. In one exemplary embodiment, communication component 716 receives broadcast signals or broadcast-related information from an external broadcast management system via a broadcast channel. In one exemplary embodiment, communication component 716 also includes a near-field communication (NFC) module to facilitate short-range communication. For example, the NFC module may be implemented based on radio frequency identification (RFID) technology, Infrared Data Association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology, and other technologies.

[0265] In an exemplary embodiment, the electronic device 700 may be implemented by one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components to implement a code compilation method provided in the embodiments of this application.

[0266] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is also provided, such as a memory 704 including instructions, which can be executed by a processor 720 of an electronic device 700 to perform the above-described method. For example, the non-transitory storage medium may be a ROM, random access memory (RAM), CD-ROM, magnetic tape, floppy disk, and optical data storage device, etc.

[0267] Figure 7 This is a block diagram illustrating an electronic device 800 according to an exemplary embodiment. For example, the electronic device 800 may be provided as a server. (Refer to...) Figure 7 The electronic device 800 includes a processing component 822, which further includes one or more processors, and memory resources represented by memory 832 for storing instructions, such as application programs, that can be executed by the processing component 822. The application programs stored in memory 832 may include one or more modules, each corresponding to a set of instructions. Furthermore, the processing component 822 is configured to execute instructions to perform a code compilation method provided in embodiments of this application.

[0268] Electronic device 800 may also include a power supply component 826 configured to perform power management of electronic device 800, a wired or wireless network interface 850 configured to connect electronic device 800 to a network, and an input / output (I / O) interface 858. Electronic device 800 may operate on an operating system stored in memory 832, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, or similar.

[0269] This application also provides a computer program product, including a computer program and a code compilation method implemented when the computer program is executed by a processor.

[0270] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the application disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0271] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

[0272] The above are merely preferred embodiments of this application and are not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

[0273] The foregoing has provided a detailed description of a code compilation method, apparatus, electronic device, and computer-readable storage medium provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A code compiling method characterized by, The method comprises the following steps: acquiring a to-be-compiled code, assignment statements in the to-be-compiled code, and registers corresponding to each variable in the assignment statements respectively; the assignment statements are used to assign variable values to the variables; if there are conflict registers with multiple corresponding variables in the registers, a shadow register and a semaphore are respectively set for each variable corresponding to the conflict registers; the shadow registers of the variables corresponding to the conflict registers are different from each other; the to-be-compiled code is compiled into a first hardware description language code comprising the shadow registers and the semaphore; wherein the shadow registers are used to write variable values of the variables corresponding to the shadow registers; and the semaphore is used to sequentially write the variable values in the shadow registers into the conflict registers according to the priorities of the variables after the variable values are written into the shadow registers.

2. The method of claim 1, wherein, Before acquiring the to-be-compiled code, the method further comprises the following steps: acquiring a mixed source code; the mixed source code comprises a second hardware description language code and the to-be-compiled code; the to-be-compiled code comprises a first code belonging to a high-level language and / or a second code belonging to a natural language description; the step of acquiring the to-be-compiled code comprises the following steps: extracting the to-be-compiled code from the mixed source code.

3. The method of claim 2, wherein, After the to-be-compiled code is compiled into the first hardware description language code comprising the shadow registers and the semaphore, the method further comprises the following steps: merging the first hardware description language and the second hardware description language to obtain a compilation result for the mixed source code.

4. The method of claim 2, wherein, the step of acquiring the mixed source code comprises the following steps: configuring an environment parameter for the to-be-compiled code; inserting the to-be-compiled code configured with the environment parameter into a source file comprising the second hardware description language to obtain the mixed source code; wherein the environment parameter comprises a preset clock signal and / or a preset reset signal; the name of the preset clock signal is the same as that of a clock signal in the second hardware description language, and the name of the preset reset signal is the same as that of a reset signal in the second hardware description language.

5. The method of claim 2, wherein, The method further comprises the following steps: acquiring a circuit type of a to-be-described circuit, acquiring a target language type adapted to the circuit type and generating the to-be-compiled code belonging to the target language type; the to-be-compiled code corresponds to the to-be-described circuit.

6. The method of claim 2, wherein, the step of acquiring the mixed source code comprises the following steps: inserting the to-be-compiled code into the second hardware description language; inserting a start position identifier and an end position identifier into a start position and an end position of the to-be-compiled code respectively; the step of extracting the to-be-compiled code from the mixed source code comprises the following steps: identifying the start position identifier and the end position identifier; extracting the to-be-compiled code between the start position identifier and the end position identifier.

7. The method of claim 1, wherein, In the case that the to-be-compiled code comprises the second code belonging to the natural language description, the step of acquiring the assignment statements in the to-be-compiled code and the registers corresponding to each variable in the assignment statements respectively comprises the following steps: converting the second code into converted code belonging to a high-level language; According to the conversion code, an assignment statement is acquired, and each variable in the assignment statement corresponds to a register respectively; The compiling the to-be-compiled code into the first hardware description language code comprising the shadow register and the semaphore comprises: The converting code is compiled into the first hardware description language code comprising the shadow register and the semaphore.

8. A code compiling apparatus characterized by comprising: The apparatus comprises: A first acquisition module is configured to acquire to-be-compiled code, an assignment statement in the to-be-compiled code, and a register corresponding to each variable in the assignment statement; the assignment statement is used to assign a variable value to the variable; A setting module is configured to, if there is a conflict register having a plurality of corresponding variables in the register, set a shadow register and a semaphore for each of the variables corresponding to the conflict register respectively; the shadow register of each variable corresponding to the conflict register is different from each other; A compiling module is configured to compile the to-be-compiled code into a first hardware description language code comprising the shadow register and the semaphore; The shadow register is used to write a variable value of a variable corresponding to the shadow register; and the semaphore is used to, after the variable value is written into the shadow register, sequentially write the variable value in the shadow register into the conflict register according to a priority of the variable.

9. An electronic device, comprising: Comprise: A processor; A memory for storing instructions executable by the processor; The processor is configured to execute the instructions to implement the method of any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device can perform the method of any one of claims 1 to 7.

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