A clock tree synthesis method and system

Abstract

The present application relates to the technical field of integrated circuits, and particularly relates to a clock tree synthesis method and system. The present application generates multiple optimization groups by dynamically grouping clock trees, and then iteratively optimizes each optimization group to balance clock skew. Specifically, in the iteration process, a skew compensation device is inserted into the optimization group with the minimum delay, and in each iteration, the skew of the optimization group after the skew compensation device is inserted is balanced, and then it is determined whether the skew is balanced. If so, the iteration is ended. If not, the next iteration is continued until all optimization groups reach the clock skew balance, and the iteration optimization is ended. By using the above scheme, the clock network convergence efficiency and layout adaptability are significantly improved while ensuring the optimization accuracy through the cooperative optimization of the grouping strategy and the clock skew balance mechanism.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a clock tree synthesis method and system. Background Technology

[0002] In integrated circuit design, the core objective of Clock Tree Synthesis (CTS) is to precisely control the clock skew (Skew) of the clock signal arriving at the timing cell. Common mainstream methods include geometric topology, dynamic programming, and machine learning-assisted methods.

[0003] However, as integrated circuit designs become increasingly complex and hierarchical, current clock tree synthesis methods face significant challenges in practical applications. Traditional geometric topology methods (such as H-tree / DME) are limited by physical dependencies in the layout and scalability, making it difficult to solve the timing convergence problem in hierarchical designs. Dynamic programming methods require repeated decomposition of the clock structure and triggering of global timing updates, resulting in an excessively large solution space and a dramatic increase in processing time. While machine learning-assisted methods show potential, their strong data dependence, weak generalization ability, and high computational overhead still hinder industrial-scale deployment. Therefore, a new method is needed to address these issues. Summary of the Invention

[0004] The present invention provides a clock tree synthesis method and system that effectively solves the problem of timing convergence difficulties in existing clock tree synthesis schemes, which leads to the difficulty of clock tree balancing.

[0005] According to the first aspect, one embodiment provides a clock tree synthesis method, comprising:

[0006] Obtain the clock tree of the target integrated circuit;

[0007] All nodes in the clock tree, except the root node, are grouped to generate multiple groups to be optimized; each group to be optimized includes at least one child node.

[0008] Iterative optimization is performed on each group to be optimized until all groups to be optimized achieve clock skew balance, including:

[0009] Determine whether each of the groups to be optimized in the current iteration is the first iteration. If so, insert a deviation compensation device into each of the groups to be optimized. Otherwise, insert a deviation compensation device into only the group to be optimized with the smallest delay in the current iteration.

[0010] Clock skew balancing is performed on the group to be optimized after the current insertion deviation compensation device;

[0011] Determine whether all the groups to be optimized in the current iteration have reached clock skew balance. If so, end the iteration optimization. Otherwise, perform the next iteration optimization for each group to be optimized until all the groups to be optimized reach clock skew balance and end the iteration optimization.

[0012] In one feasible implementation, grouping all nodes in the clock tree except the root node includes:

[0013] Obtain all nodes in the clock tree except the root node;

[0014] Based on the spatial distribution and temporal characteristics of all nodes except the root node, a physical-driven grouping strategy and / or a time-driven grouping strategy are dynamically selected to achieve dynamic grouping of all nodes except the root node.

[0015] In one feasible implementation, the clock skew balancing of the group to be optimized after the current round of insertion bias compensation device includes:

[0016] Obtain the optimization groups with at least two child nodes in the current iteration, and perform intra-group clock skew balancing for each optimization group with at least two child nodes, so that the clock skew in each optimization group with at least two child nodes is less than or equal to a preset target value.

[0017] Obtain the optimization group with only one child node in the current iteration, and balance the clock skew between the optimization groups with only one child node so that the clock skew between the optimization groups with only one child node reaches the preset target value.

[0018] In one feasible implementation, the step of performing intra-group clock skew balancing on each of the optimization groups having at least two child nodes, so that the clock skew within each optimization group having at least two child nodes is less than or equal to a preset target value, includes:

[0019] The position of the deviation compensation device inserted in the current optimization group with at least two child nodes is fine-tuned.

[0020] If the clock skew in the optimization group after the position of the deviation compensation device is fine-tuned is less than or equal to the preset target value, then return to the previous step and continue to fine-tune the position of the deviation compensation device inserted in the next optimization group with at least two child nodes; otherwise, take the node in the current optimization group where the deviation compensation device is inserted as the root node, and regroup all nodes in the current optimization group except the root node, turning the current optimization group into multiple optimization subgroups. Iterate and optimize each optimization subgroup until all optimization subgroups corresponding to the current optimization group reach clock skew balance. This includes: inserting the deviation compensation device into the optimization subgroup with the smallest delay in the current iteration; balancing the clock skew of the optimization subgroups after the insertion of the deviation compensation device in the current iteration; and determining whether all optimization subgroups in the current iteration have reached clock skew balance. If so, end the iterative optimization; otherwise, perform the next round of iterative optimization for each optimization subgroup until all optimization subgroups reach clock skew balance and end the iterative optimization.

[0021] In one feasible implementation, fine-tuning the position of the deviation compensation device inserted within the current optimization group having at least two child nodes includes:

[0022] Obtain the delay data of all receivers in the current optimization group, and calculate the current clock skew based on the delay data of all receivers; the current clock skew is the difference between the maximum and minimum values ​​of the delay data of all receivers; the receiver is the node in the current optimization group that is directly connected to the deviation compensation device.

[0023] Determine whether the current clock skew is less than or equal to the preset target value. If so, there is no need to fine-tune the position of the deviation compensation device inserted in the current optimization group; otherwise, save the current state as "best state record" and continue to obtain the current clock skew.

[0024] If the current clock skew obtained is decreasing compared to the previous one, but is still greater than the preset target value, then the average delay data is calculated based on the delay data of all receivers in the current optimization group.

[0025] Generate a direction vector pointing from each of the receiving ends to the deviation compensation device;

[0026] Scale each of the aforementioned direction vectors to a unit vector;

[0027] The difference between the delay data of each receiver and the average delay data is calculated, and the thrust of each receiver is calculated based on the unit vector of each receiver and its corresponding difference.

[0028] Add the thrust of all the receiving ends together to obtain the resultant force vector;

[0029] The position of the deviation compensation device inserted in the current optimization group is adjusted according to the resultant force vector;

[0030] Return to the step of "obtain the delay data of all receivers in the current optimization group and calculate the current clock skew based on the delay data of all receivers" to calculate the clock skew of the current optimization group after the position of the deviation compensation device is adjusted.

[0031] In one feasible implementation, before performing inter-group clock skew balancing on the optimization group having only one child node, the method further includes:

[0032] If a violation is found in the transition time of the deviation compensation device inserted into the current optimization group with only one child node, a buffer chain is used to eliminate the violation. Otherwise, the process continues to determine whether a violation is found in the transition time of the next deviation compensation device inserted into the optimization group with only one child node, until all violations in the transition time of the deviation compensation devices inserted into the optimization group with only one child node are eliminated.

[0033] In one feasible implementation, the step of balancing the inter-group clock skew of the optimization group with only one child node, so that the clock skew between the optimization groups with only one child node reaches a preset target value, includes:

[0034] The position of the deviation compensation device inserted in the optimization group with only one child node with the minimum delay is finely adjusted so that the clock skew between the optimization groups with only one child node reaches the preset target value.

[0035] According to a second aspect, one embodiment provides a clock tree synthesis system, comprising:

[0036] The acquisition module is used to acquire the clock tree of the target integrated circuit;

[0037] The grouping module is used to group all nodes in the clock tree except the root node to generate multiple groups to be optimized; each group to be optimized includes at least one child node;

[0038] The balancing module is used to iteratively optimize each group of devices until all groups achieve clock skew balance, including:

[0039] Determine whether each of the groups to be optimized in the current iteration is the first iteration. If so, insert a deviation compensation device into each of the groups to be optimized. Otherwise, insert a deviation compensation device into only the group to be optimized with the smallest delay in the current iteration.

[0040] Clock skew balancing is performed on the group to be optimized after the current insertion deviation compensation device;

[0041] Determine whether all the groups to be optimized in the current iteration have reached clock skew balance. If so, end the iteration optimization. Otherwise, perform the next iteration optimization for each group to be optimized until all the groups to be optimized reach clock skew balance and end the iteration optimization.

[0042] According to a third aspect, one embodiment provides a computer-readable storage medium storing a computer program that can be executed by a processor to implement the method described above.

[0043] According to a fourth aspect, one embodiment provides a computer program product including a computer program and / or instructions that, when executed by a processor, implement the method as described above.

[0044] According to the clock tree synthesis method / system of the above embodiments, the clock tree is dynamically grouped to generate multiple groups to be optimized, and then each group to be optimized is iteratively optimized to achieve clock skew balance for all groups. Specifically, in the first iteration, a skew compensation device is inserted into each of the groups to be optimized. In subsequent iterations, a skew compensation device is inserted into the group with the smallest delay. In each iteration, the clock skew balance is performed on the groups to be optimized after the insertion of the skew compensation device in the current round, and then it is determined whether skew balance has been achieved. If it has, the iteration ends; if not, the next iteration continues until all groups to be optimized achieve clock skew balance, thus ending the iterative optimization. By adopting the above scheme of this application, through the synergistic optimization of the grouping strategy and the clock skew balance mechanism, the convergence efficiency and layout adaptability of the clock network are significantly improved while ensuring optimization accuracy. Moreover, the optimization scheme of this application is activated only in hotspot areas, thus improving the optimization efficiency of the optimization algorithm. Attached Figure Description

[0045] Figure 1 A flowchart of a clock tree synthesis method provided in this embodiment;

[0046] Figure 2 This is a flowchart of grouping the clock tree provided in this embodiment;

[0047] Figure 3This is a flowchart of clock skew balancing for the group to be optimized after the insertion deviation compensation device, provided in this embodiment.

[0048] Figure 4 This embodiment provides a flowchart for clock skew balancing of a group to be optimized with at least two child nodes.

[0049] Figure 5 This is a structural block diagram of a clock tree integrated system provided in this embodiment.

[0050] Reference numerals: 100, acquisition module; 200, grouping module; 300, balancing module. Detailed Implementation

[0051] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0052] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0053] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. The terms "connection" and "linkage" used in this application, unless otherwise specified, include both direct and indirect connections (linkages).

[0054] refer to Figure 1 The clock tree synthesis method provided in this embodiment specifically includes the following steps:

[0055] Step 100: Obtain the clock tree of the target integrated circuit through the acquisition module;

[0056] Step 200: The grouping module groups all nodes in the clock tree except the root node, generating multiple groups to be optimized; each group to be optimized includes at least one child node.

[0057] In practical applications, after the clock tree of the target integrated circuit is first obtained by the acquisition module, the clock tree is dynamically grouped by the grouping module. Specifically, the following dynamic grouping strategy can be adopted:

[0058] Step 210: Obtain all nodes in the clock tree except the root node;

[0059] Step 220: Dynamically select a physical-driven grouping strategy and / or a time-driven grouping strategy based on the spatial distribution and temporal characteristics of all nodes except the root node to achieve dynamic grouping of all nodes except the root node.

[0060] Specifically, all nodes in the clock tree except the root node are retrieved. During grouping, different grouping strategies are selected based on the size of the child sinkpins, dividing the pins driven by the current level into multiple optimization groups. This step generates a group set G = {g1, g2, ..., g...}. n}, where g n This indicates the number of sink pins driven within a group. For example, based on the spatial distribution of sink pins, a physically driven grouping strategy is adopted to ensure that the sink pins within each group are physically clustered together. This reduces wiring length and signal transmission delay within the group, while also reducing signal crosstalk between groups. Its core logic is "spatial proximity priority." When the number of sink pins (fan-out count) exceeds a set threshold, this grouping strategy is activated. In this embodiment, a K-Means++-based method is used as the physically driven grouping strategy to cluster the sink pins. Of course, other clustering methods can also be used, such as K-Means, K-Modoids, and DBSCAN.

[0061] Alternatively, based on the clock signal transmission requirements of the pins, a timing-driven grouping strategy can be adopted to ensure that the pins within each group have similar timing constraints (such as clock arrival time and delay margin), facilitating centralized adjustments to common constraints within the group during subsequent iterative optimization. The core logic is "prioritizing consistency of timing characteristics." In this embodiment, a grouping strategy based on the clock arrival time (CAT) is used to group sink pins with smaller current CAT deviations into the same group. Of course, sink pins with similar timing margins (slack) within a certain range can also be grouped together.

[0062] Alternatively, timing-driven grouping may lead to physical dispersion of sink pins within a group, necessitating correction of the grouping results. If the spatial dispersion of sink pins in each group exceeds a set threshold, the group is split into 2-3 subgroups using a physical-driven grouping strategy, while ensuring that the timing characteristics within each subgroup still meet the constraints. During grouping, it's also advisable to consider making the load capacitance of logic cells in each group as similar as possible to ensure uniform specifications can be used when inserting buffers, simplifying timing optimization.

[0063] The clock tree synthesis method in this implementation adopts a hierarchical recursive optimization architecture. Its core process is driven by the SkewRecur() function (i.e., a recursive function), which takes the clock tree driving point StartPin (which can be understood as the root node) as input parameter and performs synthesis optimization on the clock subtree below the StartPin node through recursive calls; where the sink pin driven by StartPin is the timing endpoint. The specific implementation process is as follows.

[0064] Step 300: The balancing module iteratively optimizes each group to be optimized until all groups to be optimized achieve clock skew balance, including:

[0065] Step 400: Determine whether each group to be optimized in the current iteration is the first iteration. If so, proceed to step 500: Insert a deviation compensation device into each group to be optimized. Otherwise, proceed to step 600: Insert a deviation compensation device into only the group to be optimized with the smallest delay in the current iteration.

[0066] Step 700: Perform clock skew balancing on the group to be optimized after the current round of insertion deviation compensation device;

[0067] Step 800: Determine whether all groups to be optimized in the current iteration have reached clock skew balance. If so, proceed to step 900 to end the iteration optimization. Otherwise, return to step 300 and perform the next iteration optimization for each group to be optimized until all groups to be optimized reach clock skew balance and the iteration optimization ends.

[0068] In this embodiment, a recursive function is used for iterative optimization. The recursive function is called to iteratively optimize each group until all groups reach clock skew balance. Specifically, during the iterative optimization, in the first iteration, all groups (g1-g...) are optimized... nInsert a buffer at the group drive point. In subsequent iterations, insert the buffer only into the group with the smallest current delay. In practice, the buffer can be inserted at the center of the sink pin's bonding box. Alternatively, as another iteration method, the buffer can be inserted into the group with the largest skew in the first iteration. That is, in the first iteration, the skew compensation device is inserted into the group with the smallest delay. In the above-mentioned alternative iteration method, since the clock tree is also grouped before the first iteration, the delay data of each group to be optimized needs to be obtained separately. Then, the group with the smallest delay data is selected, and the skew compensation device is inserted into this group. The other groups to be optimized remain scattered. Then, the clock skew balancing within and / or between groups is performed on the groups to be optimized with the inserted skew compensation device. The clock skew balancing method is as follows.

[0069] For obtaining the delay data of each optimization group, the delay data of optimization groups with only one child node can be obtained directly. For optimization groups with at least two child nodes, the delay data is obtained as follows: the minimum delay of all child nodes in the optimization group is taken as the minimum delay data of the group, and the maximum delay among all child nodes is taken as the maximum delay data of the group. In addition, the clock skew of the group is the difference between the maximum delay data and the minimum delay data in the group.

[0070] In practical applications, the deviation compensation device can be a buffer, or it can be replaced by other components, such as a clock gating unit instead of a regular buffer, or an inverter.

[0071] In the current iteration, after clock skew balancing for all groups to be optimized after inserting buffers, it is necessary to determine whether all groups to be optimized have achieved clock skew balancing in this iteration. If so, the iteration optimization ends; otherwise, it means that some groups to be optimized after inserting buffers have not achieved clock skew balancing, so the process returns to step 300 and restarts the next iteration optimization, performing the next iteration optimization for each group to be optimized again. This cycle continues until clock skew balancing is achieved for all groups to be optimized, and then the iteration optimization ends. Using the above-mentioned scheme of this application, through the synergistic optimization of the grouping strategy and the clock skew balancing mechanism, the clock network convergence efficiency and layout adaptability are significantly improved while ensuring optimization accuracy. Furthermore, the optimization scheme of this application is activated only in hotspot regions, thus improving the optimization efficiency of the algorithm.

[0072] In one feasible implementation, such as Figure 3 As shown, clock skew balancing is performed on the group to be optimized after the current insertion bias compensation device, specifically including:

[0073] Step 710: Obtain the optimization groups with at least two child nodes in the current iteration, and perform intra-group clock skew balancing for each optimization group with at least two child nodes, so that the clock skew in each optimization group with at least two child nodes is less than or equal to the preset target value.

[0074] When performing clock skew balancing on the optimization groups after the current insertion of the bias compensation device, the number of child nodes in each optimization group varies. Some optimization groups may have only one child node, while others may have at least two. Therefore, clock skew balancing needs to be performed separately for optimization groups with different numbers of child nodes. First, intra-group clock skew balancing is performed on optimization groups with at least two child nodes. Then, these groups can be used as reference groups. Finally, inter-group clock skew balancing is performed on optimization groups with only one child node.

[0075] For optimization groups with at least two child nodes, clock skew balancing is performed within each optimization group to ensure that the clock skew within each optimization group is less than or equal to a preset target value. For details, refer to... Figure 4 The specific steps involved in its implementation include:

[0076] Step 711: Fine-tune the position of the deviation compensation device inserted in the current optimization group with at least two child nodes.

[0077] First, the position of the bias compensation device inserted in one of the optimization groups with at least two child nodes in the current iteration is fine-tuned. The core is to fine-tune the position and type of the buffer so that the Skew (skew) within the group is less than or equal to the preset target value (e.g., 10 ps). If successful, True is returned; otherwise, the SkewRecur() function is recursively called with the newly added buffer driver point (addedBufDriver) as the parameter to achieve in-depth optimization of local hot spots.

[0078] In this implementation scheme, the algorithm for fine-tuning the position of the buffer within the group adopts an iterative mechanical simulation framework, and the specific implementation steps are as follows:

[0079] Obtain the delay data of all receivers in the current optimization group, and calculate the current clock skew based on the delay data of all receivers; the current clock skew is the difference between the maximum and minimum values ​​of the delay data of all receivers; the receiver is the node in the current optimization group that is directly connected to the deviation compensation device.

[0080] Determine whether the current clock skew is less than or equal to the preset target value. If so, there is no need to fine-tune the position of the deviation compensation device inserted in the current optimization group; otherwise, save the current state as "best state record" and continue to obtain the current clock skew.

[0081] If the current clock skew obtained is decreasing compared to the previous one, but is still greater than the preset target value, then the average delay data is calculated based on the delay data of all receivers in the current optimization group.

[0082] Generate a direction vector pointing from each receiver to the deviation compensation device;

[0083] Scale each direction vector to a unit vector;

[0084] Calculate the difference between the delay data and the average delay data of each receiver, and calculate the thrust of each receiver based on the unit vector of each receiver and its corresponding difference.

[0085] Add up the thrust from all the receivers to get the resultant force vector;

[0086] The position of the deviation compensation device inserted in the current optimization group is adjusted according to the resultant force vector;

[0087] Return to the step of "obtain the delay data of all receivers in the current optimization group and calculate the current clock skew based on the delay data of all receivers" to calculate the clock skew of the current optimization group after the position of the deviation compensation device is adjusted.

[0088] Specifically, after starting optimization, the delay data of all child nodes directly connected to the inserted buffer in the current optimization group with at least two child nodes in the current iteration is read. The maximum and minimum delay data are selected from these delay data, and the difference between them is calculated. This difference is the clock skew of the current optimization group with at least two child nodes. After obtaining the clock skew, it is checked whether the clock skew meets the target. Specifically, it is determined whether the clock skew value is less than or equal to a preset target value. If the clock skew value is less than or equal to the preset target value, it means that no fine-tuning of the position and type of the inserted buffer in the current optimization group is needed. If the clock skew value is greater than the preset target value, it means that fine-tuning of the position and type of the inserted buffer in the current optimization group is needed. Specifically, the current clock skew value is first saved as the "best record" for possible rollback. Then, the clock skew of the current optimization group with at least two child nodes in the current iteration is reread. The clock skew value read this time is compared with the previous clock skew value. If the current clock skew value is found to be larger or unchanged compared to the previous value, it indicates that the latency has deteriorated or stalled. In this case, the process rolls back to the previous "best record" and returns, indicating that the optimization has failed. If the current clock skew value is found to be smaller than the previous value, but still greater than the preset target value, it indicates that clock skew optimization is still in progress. In this case, the next step is executed: calculating the buffer movement direction. Specifically, the average delay data of all receivers in the current optimization group with at least two child nodes is calculated. Using this average delay data as a benchmark, the following operations are performed on each receiver: a direction vector pointing to the buffer is generated (i.e., the direction vector from the receiver to the buffer position). For ease of calculation, each of these direction vectors is scaled to a unit length (i.e., only the direction is retained). Then, the thrust of each receiver is calculated using the formula: unit vector × (current delay data - average delay data). Points with delays higher than the average will "push" the buffer away, while points with delays lower than the average will "pull" the buffer closer. After obtaining the thrust of each receiver, the thrusts of all receivers are added together to obtain the resultant force vector. The buffer is moved according to the resultant force vector. As a specific movement method, the resultant force vector is adjusted to a standard step size (i.e., normalized). Then, the new target position of the buffer is calculated according to its direction. Finally, the buffer is moved to the new target position, realizing the movement of the inserted buffer position within the current optimization group. Then, the delay data of all receivers in the current optimization group are reacquired in the current iteration, and the clock skew of the current optimization group is recalculated.

[0089] After fine-tuning the buffers inserted within the current optimization group with at least two child nodes in the current iteration, the following steps are performed:

[0090] Step 712: Determine whether the clock skew in the optimization group after the position fine-tuning of the deviation compensation device is less than or equal to the preset target value. If yes, return to the previous step, i.e., step 711, but continue to fine-tune the position of the deviation compensation device inserted in the next optimization group with at least two child nodes in the current iteration; otherwise, execute step 713: Take the node with the deviation compensation device inserted in the current optimization group as the root node, and regroup all the next-level nodes in the current optimization group except the root node, turning the current optimization group into multiple optimization subgroups; Step 714: Iterate through each optimization subgroup. The optimization continues until all subgroups corresponding to the current optimization group achieve clock skew balance, including: Step 715: In the current iteration, insert a deviation compensation device into the optimization group with the smallest delay; Step 716: Perform clock skew balance on the optimization groups after inserting the deviation compensation device in the current iteration; Step 717: Determine whether all optimization groups have achieved clock skew balance in the current iteration. If yes, proceed to Step 718: End the iterative optimization; otherwise, return to Step 714 and perform the next round of iterative optimization on each optimization group until all optimization groups achieve clock skew balance, thereby ending the iterative optimization.

[0091] Specifically, after fine-tuning the buffer inserted into the current optimization group with at least two child nodes in the current iteration, it is necessary to determine whether the fine-tuned clock skew is less than or equal to the preset target value. If the fine-tuned clock skew is less than or equal to the preset target value, the above steps are repeated to continue fine-tuning the position of the buffer inserted into the next optimization group with at least two child nodes in the current iteration, using the same fine-tuning method.

[0092] If the delay is not less than the target value, the newly added buffer driver point (i.e., the node where the buffer is inserted) in the current optimization group in the current iteration is taken as the new root node, and the recursive function is called to perform iterative optimization on the current optimization group again. Specifically, the current optimization group is dynamically grouped according to the dynamic grouping strategy above, generating multiple optimization groups, and the operation of step 300 is repeated to perform iterative optimization on each optimization group. In each round of iteration, the buffer is inserted only in the optimization group with the smallest delay among all optimization groups. Specifically, clock skew balancing is performed on the optimization groups after the buffer is inserted in the current round. First, the optimization groups with at least two child nodes in the current iteration are obtained, and the clock skew balancing is performed on each optimization group with at least two child nodes to make the clock skew in each optimization group with at least one child node less than or equal to the preset target value; then,

[0093] The process begins by identifying the optimization groups with only one child node in the current iteration. Clock skew balancing is then performed on these groups to achieve a preset target value. The specific implementation principle is the same as the clock skew balancing principle described above, and will not be elaborated upon here. Next, it is determined whether all optimization groups in the current iteration have achieved clock skew balance. If so, the current optimization group has achieved clock skew balance, and the current iteration (second iteration) ends. Then, the positions of the buffers inserted in the next optimization group with at least two child nodes in the current iteration (first iteration) are fine-tuned. Otherwise, based on the above principle, the steps are repeated for each optimization group in the next iteration until all optimization groups in the current optimization group achieve clock skew balance. At this point, the current optimization group has also achieved clock skew balance. Then, return to the previous iteration and fine-tune the position of the buffer inserted in the next optimization group with at least two child nodes in the current iteration. Continue until the clock skew is balanced in all optimization groups with at least two child nodes in the current iteration (i.e., the first iteration).

[0094] It should be noted that the iterative optimization algorithm used in this embodiment is based on the scenario where all Sink Pins driven by StartPin are timing endpoints (without lower-level loads). It can also be generalized to a hierarchical structure where Sink Pins contain intermediate driving nodes: by traversing the clock tree from bottom to top, calling the SkewRecur() function on the driving point layer by layer, and skipping the grouping (GroupSinkPin) and buffer insertion (AddBufGroupPin) steps in the first iteration, hierarchical recursive optimization is achieved.

[0095] Step 720: Obtain the optimization group with only one child node in the current iteration, and balance the clock skew between the optimization groups with only one child node so that the clock skew between the optimization groups with only one child node reaches the preset target value.

[0096] For a group to be optimized that has only one child node, clock skew balancing is achieved through the following steps:

[0097] The position of the deviation compensation device inserted in the optimization group with only one child node with the smallest delay is fine-tuned so that the clock skew between the optimization groups with only one child node reaches the preset target value.

[0098] Specifically, as an ideal implementation, the optimization group with at least two child nodes after clock skew balancing within the aforementioned group can be used as the reference group. The clock skew of the reference group is used as the clock skew of the optimization group with only one child node. Therefore, for all optimization groups with only one child node, the optimization group with the smallest delay is selected to adjust the position of its buffer, so that the clock skew between optimization groups with only one child node is equal to the clock skew of the reference group. The specific position adjustment method can use a wire loop algorithm for fine-tuning the buffer position. Specifically, if there is no transition violation, the buffer inserted in the optimization group with the smallest delay is directly moved to its source end. If there is still no transition violation, the buffer is moved to the center between the source and sink ends, and a wire loop algorithm is performed to increase the delay, aligning it with the delays of other groups. The wire loop algorithm includes, but is not limited to, snaking and jogging methods. However, in practical applications, it is difficult to make the clock skew between groups with only one child node exactly equal to the clock skew of the reference group. Therefore, as another implementation method, the group with the smallest delay among all groups with only one child node is selected, and the position of the deviation compensation device inserted in the group with the smallest delay is fine-tuned. The specific position adjustment method is the same as above, and will not be repeated here. The goal is to make the clock skew between all groups with only one child node reach the range of the preset target value (that is, to make the clock skew between groups with only one child node less than or equal to the preset target value).

[0099] Furthermore, in this embodiment, before performing inter-group clock skew balancing on the optimization group with only one child node, the method further includes: determining whether there is a violation in the transition time of the deviation compensation device inserted in the current optimization group with only one child node; if so, using a buffer chain to eliminate the violation in the transition time of the deviation compensation device inserted in the current optimization group with only one child node; otherwise, continuing to determine whether there is a violation in the transition time of the deviation compensation device inserted in the next optimization group with only one child node, until all violations in the transition time of the deviation compensation devices inserted in all optimization groups with only one child node are eliminated.

[0100] Specifically, before clock skew balancing for groups of devices with only one child node, it is necessary to check and address transition time violations. Transition time violations typically refer to situations where the rise or fall time of a signal exceeds the maximum allowable value during its propagation in the circuit. This can affect the timing performance of the circuit, especially in high-speed digital circuits. Excessive transition time may cause the signal to fail to stabilize before the clock edge arrives, resulting in a setup time violation. Furthermore, excessively long transition times may also cause the signal to fail to hold for a sufficient time after the clock edge arrives, resulting in a hold time violation. In clock skew balancing, transition time violations mean that the signal's transition time exceeds the tolerance range of the circuit design, which may exacerbate timing problems caused by clock skew. Therefore, to balance clock skew, the transition time of each group of devices with only one child node needs to be checked. If violations are found, a buffer chain algorithm is used to eliminate them, thereby eliminating problems such as excessively long signal rise / fall times or insufficient drive.

[0101] It should be noted that in the above embodiments, the termination condition of the iterative loop of the recursive function is that the clock skew within all groups and the clock skew between all groups in the clock tree to be optimized meet the standard, or the maximum number of iterations is reached, then the iteration is terminated.

[0102] In addition, this embodiment also provides a clock tree synthesis system, see reference. Figure 5 The system includes: an acquisition module 100, a grouping module 200, and a balancing module 300. The acquisition module 100 acquires the clock tree of the target integrated circuit; the grouping module 200 groups all nodes in the clock tree except the root node, generating multiple groups to be optimized; each group to be optimized includes at least one child node; the balancing module 300 iteratively optimizes each group to be optimized until all groups to be optimized achieve clock skew balance, including:

[0103] Determine whether each group to be optimized in the current iteration is the first iteration. If so, insert a deviation compensation device into each group to be optimized. Otherwise, insert a deviation compensation device into the group to be optimized with the smallest delay in the current iteration.

[0104] Clock skew balancing is performed on the group to be optimized after the current insertion deviation compensation device;

[0105] Determine whether all groups to be optimized in the current iteration have reached clock skew balance. If so, end the iteration optimization. Otherwise, perform the next iteration optimization for each group to be optimized until all groups to be optimized reach clock skew balance and end the iteration optimization.

[0106] This embodiment of a clock tree synthesis system involves acquiring the clock tree of the target integrated circuit through an acquisition module 100, dynamically grouping the clock tree through a grouping module 200 to generate multiple groups to be optimized, and then iteratively optimizing each group through a balancing module 300 to achieve clock skew balance for all groups. Specifically, in the first iteration, a skew compensation device is inserted into each of the groups to be optimized. In subsequent iterations, a skew compensation device is inserted into the group with the smallest delay. In each iteration, clock skew balance is performed on the groups to be optimized after the insertion of the skew compensation device. It is then determined whether skew balance has been achieved. If it has, the iteration ends; otherwise, the iteration continues until all groups to be optimized achieve clock skew balance, thus ending the iteration optimization. The clock tree synthesis system of this application, through the synergistic optimization of the grouping strategy and the clock skew balance mechanism, significantly improves the clock network convergence efficiency and layout adaptability while ensuring optimization accuracy. Furthermore, the optimization scheme of this application is activated only in hotspot areas, thus improving the optimization efficiency of the optimization algorithm. Furthermore, since the above embodiments of the clock tree synthesis method have already described each module in detail, this embodiment will not elaborate further here.

[0107] This embodiment provides a computer-readable storage medium storing a computer program that can be executed by a processor to implement the method described above. Since a clock tree synthesis method has been described in detail in the above embodiments, this embodiment will not repeat that description further.

[0108] This embodiment provides a computer program product, including a computer program and / or instructions, which, when executed by a processor, implement the method described above. Since a clock tree synthesis method has been described in detail in the above embodiments, this embodiment will not repeat that description further.

[0109] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0110] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A clock tree synthesis method, characterized by, The method comprises the following steps: acquiring a clock tree of a target integrated circuit; grouping all nodes in the clock tree except a root node to generate a plurality of groups to be optimized; each of the groups to be optimized comprises at least one sub-node; iterative optimization is performed on each of the groups to be optimized until all the groups to be optimized reach clock skew balance, which comprises the following steps: determining whether each of the groups to be optimized in the current iteration is the first iteration, if yes, inserting a skew compensation device into each of the groups to be optimized, otherwise, inserting the skew compensation device into only one group to be optimized with the minimum delay in the current iteration; acquiring groups to be optimized with at least two sub-nodes in the current iteration, performing intra-group clock skew balance on each of the groups to be optimized with at least two sub-nodes to make the clock skew in each of the groups to be optimized with at least two sub-nodes less than or equal to a preset target value; acquiring groups to be optimized with only one sub-node in the current iteration, performing inter-group clock skew balance on the groups to be optimized with only one sub-node to make the clock skew between the groups to be optimized with only one sub-node reach a preset target value; determining whether all the groups to be optimized in the current iteration reach clock skew balance, if yes, ending the iterative optimization, otherwise, performing the next round of iterative optimization on each of the groups to be optimized until all the groups to be optimized reach clock skew balance to end the iterative optimization.

2. The clock tree synthesis method of claim 1, wherein, The grouping of all the nodes in the clock tree except the root node comprises the following steps: acquiring all the nodes in the clock tree except the root node; dynamically selecting a physical-driven grouping strategy and / or a timing-driven grouping strategy according to the spatial position distribution and timing characteristics of all the nodes except the root node to realize dynamic grouping of all the nodes except the root node.

3. The clock tree synthesis method of claim 1, wherein, The intra-group clock skew balance performed on each of the groups to be optimized with at least two sub-nodes to make the clock skew in each of the groups to be optimized with at least two sub-nodes less than or equal to a preset target value comprises the following steps: fine-tuning the position of the skew compensation device inserted in the current one of the groups to be optimized with at least two sub-nodes. judging whether the clock skew of the to-be-optimized group after the position of the bias compensation device is fine-tuned is less than or equal to a preset target value, if yes, returning to the previous step to continue fine-tuning the position of the bias compensation device inserted in the to-be-optimized group having at least two child nodes; otherwise, taking the node of the bias compensation device inserted in the current to-be-optimized group as a root node, re-grouping all nodes in the current to-be-optimized group except the root node, changing the current to-be-optimized group into a plurality of to-be-optimized groups, and iteratively optimizing each to-be-optimized group until each to-be-optimized group corresponding to the current to-be-optimized group reaches clock skew balance, including: in the current iteration, inserting a bias compensation device in a to-be-optimized group having the minimum delay; performing clock skew balance on the to-be-optimized group after the bias compensation device is inserted in the current iteration; judging whether all to-be-optimized groups in the current iteration reach clock skew balance, if yes, ending the iterative optimization, otherwise, performing the next round of iterative optimization on each to-be-optimized group until all to-be-optimized groups reach clock skew balance and the iterative optimization ends.

4. The clock tree synthesis method of claim 3, wherein, The fine-tuning of the position of the bias compensation device inserted in the current to-be-optimized group having at least two child nodes includes: obtaining delay data of all receiving ends in the current to-be-optimized group, and calculating a current clock skew based on the delay data of all receiving ends; the current clock skew is a difference between a maximum value and a minimum value in the delay data of all receiving ends; the receiving end is a node directly connected to the bias compensation device in the current to-be-optimized group; judging whether the current clock skew is less than or equal to the preset target value, if yes, not fine-tuning the position of the bias compensation device inserted in the current to-be-optimized group; otherwise, saving the current state as a "best state record" and continuing to obtain the current clock skew; if the current clock skew obtained by continuing to obtain is smaller than the last time but still greater than the preset target value, calculating average delay data based on the delay data of all receiving ends in the current to-be-optimized group; generating a direction vector from each receiving end to the bias compensation device respectively; scaling each direction vector into a unit vector; calculating a difference between the delay data of each receiving end and the average delay data respectively, and calculating a thrust of each receiving end based on the unit vector of each receiving end and the corresponding difference; adding the thrusts of all receiving ends to obtain a resultant vector; adjusting the position of the bias compensation device inserted in the current to-be-optimized group based on the resultant vector; returning to the step of "obtaining delay data of all receiving ends in the current to-be-optimized group, and calculating a current clock skew based on the delay data of all receiving ends", to calculate the clock skew of the to-be-optimized group after the position of the bias compensation device is adjusted.

5. The clock tree synthesis method of claim 1, wherein, Before the inter-group clock skew balance on the to-be-optimized group having only one child node, further including: determine whether the transition time of the deviation compensation device inserted in the current said group of only one child node exists violation, if yes, use the buffer chain to eliminate the violation of the transition time of the deviation compensation device inserted in the current said group of only one child node; otherwise, continue to determine whether the transition time of the deviation compensation device inserted in the next said group of only one child node exists violation, until all the violations of the transition time of the deviation compensation device inserted in the said group of only one child node are eliminated.

6. The clock tree synthesis method of claim 5, wherein, The inter-group clock skew balancing of the said group of only one child node makes the clock skew between the said group of only one child node reach a preset target value, comprising: Fine-tuning the position of the deviation compensation device inserted in the said group of only one child node with the minimum delay, so that the clock skew between the said group of only one child node reaches a preset target value.

7. A clock tree synthesis system, comprising: Comprise: An acquisition module is used to acquire the clock tree of a target integrated circuit; A grouping module is used to group all nodes in the clock tree except the root node to generate a plurality of optimization groups; each said optimization group includes at least one child node; A balancing processing module is used to iteratively optimize each optimization group until all optimization groups reach clock skew balance, comprising: If it is the first iteration in the current iteration, a deviation compensation device is inserted in each said optimization group, otherwise, only a deviation compensation device is inserted in the optimization group with the minimum delay in the current iteration; Obtain the optimization group with at least two child nodes in the current iteration, and balance the clock skew in each said optimization group with at least two child nodes to make the clock skew in each said optimization group with at least two child nodes less than or equal to a preset target value; obtain the optimization group with only one child node in the current iteration, and balance the clock skew between the said optimization group with only one child node to make the clock skew between the said optimization group with only one child node reach a preset target value; If all said optimization groups in the current iteration reach clock skew balance, the iteration optimization is ended, otherwise, the next round of iteration optimization is performed on each optimization group until all said optimization groups reach clock skew balance to end the iteration optimization.

8. A computer-readable storage medium, characterized in that, The medium stores a computer program, which can be executed by a processor to implement the method of any one of claims 1-6.

9. A computer program product comprising computer programs and / or instructions, characterized in that, The computer program and / or instructions are executed by the processor to implement the method of any one of claims 1-6. The computer program and / or instructions are executed by the processor to implement the method of any one of claims 1-6.

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