A clock tree synthesis optimization method, device and product based on machine learning

Abstract

A clock tree synthesis optimization method, device and product based on machine learning, the clock tree synthesis optimization method comprising: obtaining a trained replacement cell prediction model, wherein the trained replacement cell prediction model is used to predict the optimal replacement cell corresponding to the to-be-optimized cell in the clock tree synthesis; integrating the trained replacement cell prediction model into an EDA tool, so as to call the trained replacement cell prediction model through the EDA tool integrated with the trained replacement cell prediction model to predict the optimal replacement cell corresponding to the to-be-optimized cell in the clock tree synthesis. The above clock tree synthesis optimization method aims to reduce the running time of replacing the selected cell with a weaker driving capability cell of the same type in the clock tree synthesis stage without significantly deteriorating the clock timing and meeting the design rule violation requirement.

Description

Technical Field

[0001] This invention relates to the field of machine learning technology, and specifically to a method, device, and product for comprehensive optimization of clock trees based on machine learning. Background Technology

[0002] Clock tree synthesis is a core component of digital integrated circuit back-end design. Its goal is to construct a low-bias, low-latency, and highly stable clock distribution network while meeting design rules. As process technology evolves to below 5nm, the power consumption of the clock distribution network increases to 35% to 45%, and high-frequency designs (>5GHz) require picosecond-level accuracy for timing convergence. Process upgrades have doubled runtime, highlighting the challenges.

[0003] During the clock tree synthesis stage, the power consumption of a single unit is reduced by replacing its cells with weaker driving capabilities, i.e., smaller size and lower power consumption. This replacement process accounts for a significant portion of the runtime and requires multiple iterations for verification, resulting in redundant time overhead. Summary of the Invention

[0004] The present invention aims to reduce the runtime of replacing selected cells with weaker cells of the same type during the clock tree synthesis stage without significantly deteriorating clock timing and while meeting design rule violation requirements.

[0005] According to the first aspect, one embodiment provides a clock tree synthesis optimization method based on machine learning, comprising:

[0006] Obtain a trained replacement unit prediction model, wherein the trained replacement unit prediction model is used to predict the optimal replacement unit corresponding to the unit to be optimized in clock tree synthesis;

[0007] The trained replacement unit prediction model is integrated into an EDA tool so that the EDA tool with the trained replacement unit prediction model can call the trained replacement unit prediction model to predict the optimal replacement unit corresponding to the unit to be optimized in clock tree synthesis.

[0008] In some embodiments, the training method of the replacement unit prediction model includes:

[0009] For the training unit in clock tree synthesis, a training dataset for the training unit is constructed. The training unit is the unit in clock tree synthesis that needs to reduce power consumption. The training dataset includes multiple training data, which have different data features and data labels. The data features include circuit features, library cell features, and process features. The data labels include the replacement state of the training unit and the power consumption of the equivalent replacement unit. The equivalent replacement unit is a unit of the same type used to replace the training unit.

[0010] Based on the training dataset, a trained replacement unit prediction model is obtained through machine learning algorithms.

[0011] In some embodiments, constructing the training dataset for the unit to be trained includes:

[0012] Obtain multiple equivalent replacement units and sort them according to the power consumption of the equivalent replacement units from smallest to largest.

[0013] Among the sorted equivalent replacement units, equivalent replacement units are selected sequentially to replace the unit to be trained, and the first equivalent replacement unit that meets the preset time sequence verification requirements is taken as the target replacement unit.

[0014] The data label of the training unit is generated according to the target replacement unit, and the data features of the training unit and the data features and data labels of the associated units corresponding to the training unit are obtained.

[0015] The training dataset of the unit to be trained is obtained by concatenating the data label of the unit to be trained, the data features of the unit to be trained, and the data features and data labels of the associated units corresponding to the unit to be trained.

[0016] In some embodiments, when the unit to be trained is equivalent to a node, the associated unit corresponding to the unit to be trained is the parent node of the node.

[0017] In some embodiments, the step of training a pre-trained replacement unit prediction model based on the training dataset using a machine learning algorithm includes:

[0018] A baseline model is determined based on the machine learning algorithm, and the model parameters of the baseline model are initialized and configured.

[0019] The baseline model is trained iteratively for multiple rounds based on the training dataset until the training rounds reach a preset number of rounds or the baseline model meets the preset convergence requirements. Then, the baseline model that reaches the preset number of rounds or meets the preset convergence requirements is used as the trained replacement unit prediction model.

[0020] In some embodiments, the training method for each round of iterative training includes:

[0021] The training dataset is input into the baseline model to obtain power consumption prediction values ​​and replacement prediction probability values;

[0022] The multi-task composite loss value is calculated based on the preset multi-task composite loss function, the power consumption prediction value, and the replacement prediction probability value. The multi-task composite loss function includes a power consumption regression loss function, a replacement decision loss function, and a dynamic weight coefficient, which is calculated based on the training round of the current iteration.

[0023] The gradient value is calculated based on the multi-task composite loss value, and the parameters of the baseline model are updated using the gradient value and a preset optimization algorithm.

[0024] In some embodiments, the multi-task composite loss function is expressed as follows:

[0025] ;

[0026] ;

[0027] in, Let N represent the multi-task composite loss function, and let N represent the number of samples for the power prediction regression task in the training dataset. This represents the actual power consumption value of the i-th unit to be trained. This represents the predicted power consumption value of the i-th unit to be trained. Represents the normalization constant. This represents the dynamic weight coefficients, and M represents the number of samples in the training dataset that replace the decision classification task. The weights of positive samples are represented. This represents the true label of the j-th sample. This represents the Sigmoid function. This represents the value output by the j-th sample after processing by the baseline model. This indicates that the predicted probability value will be replaced. represents the weight of the negative sample, t represents the current training iteration round, and T represents the total number of training iteration rounds.

[0028] In some embodiments, integrating the trained replacement unit prediction model into the EDA tool includes:

[0029] The trained replacement unit prediction model is converted into a replacement unit prediction model in a preset format;

[0030] A pre-defined front-end library is integrated into the development environment of the EDA tool, wherein the front-end library is used to load and run the pre-defined format of the replacement unit prediction model;

[0031] In the EDA tool, a preset loading function is used to load the preset format replacement unit prediction model, so as to integrate the trained replacement unit prediction model into the EDA tool.

[0032] According to a second aspect, one embodiment provides a clock tree synthesis and optimization device based on machine learning, comprising:

[0033] Memory, used to store programs;

[0034] A processor for implementing the clock tree synthesis optimization method by executing a program stored in the memory.

[0035] According to a third aspect, one embodiment provides a computer program product, including a computer program and / or instructions, which, when executed by a processor, implement the clock tree synthesis optimization method.

[0036] According to the above embodiments, the machine learning-based clock tree synthesis optimization method, the machine learning-based clock tree synthesis optimization device, and the computer program product, since the trained replacement unit prediction model is integrated into the EDA tool, and the trained replacement unit prediction model can predict the optimal replacement unit corresponding to the unit to be optimized in the clock tree synthesis, the EDA tool with the integrated trained replacement unit prediction model can call the trained replacement unit prediction model to predict the optimal replacement unit corresponding to the unit to be optimized in the clock tree synthesis, thereby realizing fast inference of unit replacement, achieving the goal of reducing runtime overhead, and improving optimization efficiency. Attached Figure Description

[0037] Figure 1 This is a flowchart of the clock tree synthesis optimization method based on machine learning in the embodiments of this application;

[0038] Figure 2 This is a flowchart of a training method for a replacement unit prediction model in one embodiment;

[0039] Figure 3 This is a flowchart illustrating the construction of a training dataset for a unit to be trained in one embodiment.

[0040] Figure 4 This is a node topology diagram in one embodiment when the unit to be trained is equivalent to a node;

[0041] Figure 5 This is a flowchart illustrating how a trained replacement unit prediction model is obtained by training a training dataset using a machine learning algorithm in one embodiment.

[0042] Figure 6 This is a flowchart of a training method for each round of iterative training in one embodiment;

[0043] Figure 7 This is a flowchart illustrating the integration of a trained replacement unit prediction model into an EDA tool in one embodiment;

[0044] Figure 8 This is a comparison chart of different metrics used in one embodiment to verify whether the number of checks in time series analysis is reduced, employing the iterative method, the bisection method, and the method of this application respectively.

[0045] Figure 9 This is a comparison chart of different indicators used in one embodiment to verify whether a strategy significantly leads to a deterioration in PPA, employing the iterative method, the bisection method, and the method of this application. Detailed Implementation

[0046] The present invention will now be described in further detail with reference to specific embodiments and accompanying drawings. Similar elements in different embodiments are referred to by associated similar element reference numerals. In the following embodiments, many details are described to facilitate a better understanding of this application. However, those skilled in the art will readily recognize that some features may be omitted in different situations, or may be replaced by other elements, materials, or methods. In some cases, certain operations related to this application are not shown or described in the specification. This is to avoid obscuring the core parts of this application with excessive description. For those skilled in the art, detailed description of these related operations is not necessary; they can fully understand the related operations based on the description in the specification and general technical knowledge in the art.

[0047] Furthermore, the features, operations, or characteristics described in the specification can be combined in any suitable manner to form various embodiments. At the same time, the steps or actions in the method description can be rearranged or adjusted in a manner obvious to those skilled in the art. Therefore, the various orders in the specification and drawings are only for the clear description of a particular embodiment and do not imply a necessary order, unless otherwise stated that a particular order must be followed.

[0048] The serial numbers assigned to components in this document, such as "first" and "second," are used only to distinguish the described objects and have no sequential or technical meaning. Unless otherwise specified, the terms "connection" and "linkage" used in this application include both direct and indirect connections (linkages).

[0049] In the design of digital integrated circuits, Clock Tree Synthesis (CTS) has spawned various design strategies to reduce power consumption, which can be mainly divided into two categories: 1. Traditional solutions, and 2. Intelligent solutions. Traditional solutions involve the following specific approaches: 1.1 Iterative verification method: After obtaining all available equivalent cells and sorting them by power consumption, the current cell is replaced sequentially until the first low-power cell that meets the timing and design rule violation (DRV) requirements is found. Each replacement requires a complete timing analysis and DRV check; 1.2 Binary search method: After obtaining all available equivalent cells and sorting them by power consumption, a binary search method is used to find the first low-power cell that meets the timing and DRV requirements. Each replacement requires a complete timing analysis and DRV check; 1.3 Table-based replacement method, but with limited accuracy and poor PPA (Performance, Power, Area). The common problem with traditional solutions is that a complete timing analysis and DRV check must be performed for each cell replacement. With a 7-nanometer process, the time taken for a single timing analysis and design rule violation check is approximately 0.05s-0.07s. When 100,000 replacement verifications are required, the cumulative time taken for timing analysis and design rule violation checks can reach 1 hour and 30 minutes.

[0050] In the field of traditional integrated circuit design, traditional cell-level power optimization strategies have demonstrated mature engineering value in optimizing power performance per achievable (PPA) metrics. However, their inherently high time overhead has become a core bottleneck restricting the efficiency of advanced process design. From a technical mechanism perspective, such methods require an average of 3-4 iterative verification processes to optimize the power consumption of a single standard cell. Each iteration involves two computationally intensive tasks: full-chip timing analysis and design rule violation checking. At 7nm and below advanced process nodes, a single timing analysis requires calculating the path delay and verifying the timing margin of hundreds of millions of transistors, while design rule violation checking requires a full verification of the physical rule compliance of nanometer-level interconnect structures. The combined operation can take hundreds of milliseconds per iteration. When chip design scale exceeds tens of millions of gates, the cell-level optimization time often accounts for more than 30% of the entire physical implementation stage, severely restricting design iteration efficiency. In recent years, artificial intelligence technologies, represented by deep learning, have provided a way to break through this bottleneck. Intelligent solutions are mainly implemented through deep learning algorithms. Deep learning algorithms, through multi-layer nonlinear neural network architecture, can automatically mine the implicit mapping relationship between unit features (such as input conversion time and load capacitance) and the optimal replacement scheme from massive historical design data. Its end-to-end prediction capability can compress the iterative verification process of traditional methods into a single inference calculation.

[0051] To achieve global optimization of PPA (Power Performance Area) metrics, existing low-power cell optimization techniques require multiple rounds of iterative replacement of the target cell, leading to a significant increase in the time overhead of timing analysis and design rule violation checks. Current clock tree synthesis strategies have two major limitations: firstly, they heavily rely on engineers' experience-based decisions; and secondly, the synthesis process is excessively time-consuming. Given that low-power optimization of a single cell requires multiple iterations of timing analysis and design rule violation checks, the resulting significant runtime overhead has become a key bottleneck restricting design efficiency. To address these issues, this application proposes a machine learning-based clock tree synthesis optimization method. In this method, a trained replacement cell prediction model is obtained, which is used to predict the optimal replacement cell for the cell to be optimized in clock tree synthesis. The trained replacement cell prediction model is integrated into an EDA tool, allowing the tool to call the model to predict the optimal replacement cell for the cell to be optimized in clock tree synthesis.

[0052] The clock tree synthesis optimization method based on machine learning provided in the embodiments of this application is described below with reference to the accompanying drawings.

[0053] Figure 1 A flowchart of a clock tree synthesis optimization method based on machine learning provided in an embodiment of this application is shown, which will be described in detail below.

[0054] Step S10: Obtain a trained replacement unit prediction model.

[0055] Specifically, in the clock tree synthesis stage, a trained replacement unit prediction model is acquired to predict the optimal replacement unit corresponding to the unit to be optimized in the clock tree synthesis, and the optimal replacement unit is used to replace the unit to be optimized. The training process of the replacement unit prediction model mainly includes two stages: a data preparation stage and a model training stage. In the data preparation stage, the training dataset required for supervised learning is constructed. This training dataset covers multi-dimensional information such as circuit characteristics, library cell attributes, and process parameters. In the model training stage, the model is trained and validated using the training dataset, forming a replacement unit prediction model that can be directly used for inference.

[0056] For example, in clock tree synthesis, the unit to be optimized is a buffer, an inverter, or an integrated clock gating unit. A buffer is selected as the unit to be optimized, and a trained replacement unit prediction model is used to predict the optimal replacement unit corresponding to the selected buffer. The optimal replacement unit is a buffer with weaker driving capability, and the selected buffer is replaced by a buffer with weaker driving capability.

[0057] Step S20: Integrate the trained replacement unit prediction model into the EDA tool so that the EDA tool with the integrated trained replacement unit prediction model can call the trained replacement unit prediction model to predict the optimal replacement unit corresponding to the unit to be optimized in the clock tree synthesis.

[0058] Specifically, the trained replacement unit prediction model is loaded, and then a dedicated encapsulation architecture inheriting from the standard neural network base class is constructed. This dedicated encapsulation architecture includes a key transformation module that converts the trained replacement unit prediction model into a target framework executable unit, enabling the target framework executable unit to be integrated into EDA tools and realize the application of the trained replacement unit prediction model in real-world scenarios. When calling the trained replacement unit prediction model to predict the optimal replacement unit corresponding to the unit to be optimized in clock tree synthesis, a dual-path parallel computing mechanism is implemented during forward propagation. The first path directly outputs a continuous prediction result, while the second path outputs a probabilistic classification judgment through a nonlinear activation function, forming a standardized two-element output structure.

[0059] In this embodiment, a trained replacement unit prediction model is used to predict the optimal replacement unit corresponding to the unit to be optimized in clock tree synthesis. Verification can be completed with only a single timing analysis and design rule violation check, thus avoiding the redundant time overhead caused by multiple iterative verifications in traditional strategies. The trained replacement unit prediction model is deployed and integrated into EDA tools to achieve rapid inference of unit replacement schemes, thereby reducing runtime overhead. At the same time, an adaptation bridge is established between the machine learning model and the industrial-grade deployment framework, providing a standardized interface for subsequent serialization operations while maintaining the prediction accuracy and task independence characteristics of the original model.

[0060] Please refer to Figure 2 In some embodiments, the training method of the replacement unit prediction model includes steps S11 to S12, which are described in detail below.

[0061] Step S11: For the unit to be trained in the clock tree synthesis, construct the training dataset for the unit to be trained.

[0062] Specifically, the unit to be trained is the unit whose power consumption needs to be reduced in clock tree synthesis. The training dataset includes multiple training data, which have different data features and data labels. The data features include circuit features, library cell features and process features. The data labels include the replacement state of the unit to be trained and the power consumption of the equivalent replacement unit. The equivalent replacement unit is a unit of the same type used to replace the unit to be trained.

[0063] For example, circuit characteristics include input transition time, output transition time, minimum delay, maximum delay, and capacitive load; library cell characteristics include area and power consumption; and process characteristics include process, voltage, and temperature.

[0064] Step S12: Based on the training dataset, a trained replacement unit prediction model is obtained by training a machine learning algorithm.

[0065] Specifically, a well-trained replacement unit prediction model is obtained by using common machine learning algorithms, including Gradient Boosting Machine (GBM), extreme gradient boosting (XGBoost), back propagation (BP), residual network (ResNet), K-Nearest Neighbors (KNN), and Long Short-Term Memory (LSTM). XGBoost, which boasts excellent feature selection capabilities and training efficiency, can be selected as the benchmark model for training to obtain a well-trained replacement unit prediction model.

[0066] In this embodiment, by explicitly defining the data characteristics of the training data for the unit to be trained, supervised learning can learn data patterns and features through this training dataset, thereby improving classification accuracy. Simultaneously, based on the training dataset and machine learning algorithms, a replacement unit prediction model is trained, facilitating subsequent integration into EDA tools.

[0067] Please refer to Figure 3 In some embodiments, step S11: constructing the training dataset of the unit to be trained, including steps S111 to S114, which are described in detail below.

[0068] Step S111: Obtain multiple equivalent replacement units and sort them according to the power consumption of the equivalent replacement units from smallest to largest.

[0069] Specifically, if the unit to be trained is a buffer, then multiple equivalent replacement units are buffers with different power consumptions. The multiple buffers with different power consumptions are sorted according to the order of power consumption from smallest to largest.

[0070] For example, the unit to be trained is buffer E, and multiple equivalent replacement units include buffer A, buffer B and buffer C, wherein the power consumption of buffer A < the power consumption of buffer B < the power consumption of buffer C, and the multiple equivalent replacement units are arranged in ascending order of power consumption as buffer A, buffer B and buffer C.

[0071] Step S112: Select equivalent replacement units sequentially from the sorted equivalent replacement units to replace the unit to be trained, and take the first equivalent replacement unit that meets the preset timing verification requirements as the target replacement unit.

[0072] For example, buffer A is selected to replace the unit to be trained. Timing analysis and design rule violation checks are performed on the clock tree synthesis after replacing the unit with buffer A. If the preset timing requirements are met, buffer A is selected as the target replacement unit, and no other equivalent replacement units are used to replace the unit to be trained. If the preset timing requirements are not met, buffer B is selected to replace the unit to be trained. Timing analysis and design rule violation checks are performed on the clock tree synthesis after replacing the unit with buffer B to determine if the preset timing requirements are met. If they are met, buffer B is selected as the target replacement unit; otherwise, buffer C is used to replace the unit to be trained, and so on. It is worth noting that if multiple equivalent replacement units are selected and replace the unit to be trained, and none of them meet the preset timing requirements (i.e., buffer A, buffer B, and buffer C all fail to meet the preset timing requirements), then the corresponding data label is generated based on the unit to be trained.

[0073] Step S113: Generate data labels for the units to be trained based on the target replacement units, and obtain the data features of the units to be trained, as well as the data features and data labels of the associated units corresponding to the units to be trained.

[0074] Specifically, the data label of the unit to be trained is set to replaceable, and the power consumption of the target replacement unit is set. If multiple equivalent replacement units are selected and used to replace the unit to be trained, and none of them meet the preset timing verification requirements, then the corresponding data label is generated based on the unit to be trained. In this case, the data label of the unit to be trained is set to non-replaceable, and the power consumption of the unit to be trained is set.

[0075] For example, the unit to be trained is a buffer E, and its power consumption is P. E The target replacement unit is buffer A, and its power consumption is P. A Then the data labels of the units to be trained are replaceable, P A If, after replacing buffers A, B, and C, none of them meet the preset timing verification requirements, then the data label for the unit to be trained will be buffer E, P. E .

[0076] Step S114: Concatenate the data label of the unit to be trained, the data features of the unit to be trained, and the data features and data labels of the associated units corresponding to the unit to be trained to obtain the training dataset of the unit to be trained.

[0077] Specifically, for the data features and data labels of the unit to be trained, or the data features and data labels of the associated units corresponding to the unit to be trained, separators such as commas or spaces can be used to separate them, ensuring that the data is stored in the log in a standardized and orderly manner, which facilitates subsequent reading and processing.

[0078] For example, the data characteristics and data tags of the unit to be trained can be represented as "input transition time, output transition time, minimum delay, maximum delay, capacitive load, area, power consumption, unit code, process, voltage, temperature; tag". Here, the unit code is the sequence number of the unit to be trained among the multiple units in the clock tree synthesis.

[0079] In some embodiments, the concatenated data can be preprocessed to obtain the training dataset for the units to be trained. First, the concatenated data undergoes data cleaning, including removing blank lines, formatting errors, and other invalid data; handling missing values ​​using methods such as mean imputation and median imputation; and identifying and processing outliers through statistical analysis and visualization to ensure the accuracy and reliability of the concatenated data. Second, data analysis techniques such as Principal Component Analysis (PCA) or Self-Organizing Map (SOM) are used to reduce the dimensionality of the data. After dimensionality reduction, data transformation is performed, such as using one-hot encoding or label encoding to convert categorical data into numerical data, and standardizing or normalizing continuous data to facilitate model training and learning. Finally, the label data in the concatenated data is preprocessed. Specifically, the power consumption label for the units to be trained (a regression task label) is normalized to its maximum or minimum value, while the replacement state label for the units to be trained (a classification task label) is kept as a 0 / 1 binary code. The preprocessed data is divided into training and testing datasets in an 8:2 ratio to form the input feature matrix and output label vector required for model training, creating a dataset that can be directly used for training. The dataset is then saved in a suitable format such as CSV, JSON, or Pickle.

[0080] In this embodiment of the application, in order to address the problems of insufficient datasets and lack of data to assist model training, the above data mining method is designed to create datasets to assist model training.

[0081] In some embodiments, when the unit to be trained is equivalent to a node, the associated unit corresponding to the unit to be trained is the parent node of the node. Specifically, the unit to be trained is considered as a node (Node), and each node has its corresponding parent node (Parent Node).

[0082] In this embodiment of the application, considering that the parent node usually has a direct influence on the attributes or behavior of the node, the parent node of the node is determined as the associated unit corresponding to the node's training unit. In this way, when the data features and data labels of the training unit and the data features and data labels of the associated unit corresponding to the training unit are concatenated, the model can directly learn this dependency when using the training dataset to train the model, avoiding the loss of local information caused by relying only on the current node.

[0083] Please refer to Figure 4 In some embodiments, Figure 4 As a node topology graph, when the unit to be trained is equivalent to a node, the associated unit corresponding to the unit to be trained can also be the node's sibling node or child node. By concatenating the data features and data labels of the sibling node with the data features and data labels of the node, or concatenating the data features and data labels of the child node with the data features and data labels of the node, the training dataset of the unit to be trained is obtained.

[0084] Please refer to Figure 5 In some embodiments, step S12: Based on the training dataset, a trained replacement unit prediction model is obtained by training through a machine learning algorithm, including steps S121 to S122, which are described in detail below.

[0085] Step S121: Determine the baseline model based on the machine learning algorithm and initialize the model parameters of the baseline model.

[0086] Specifically, XGBoost, a machine learning algorithm with excellent feature selection capability and training efficiency, is selected as the benchmark model for model training. After determining the benchmark model, the model parameters of the benchmark model will be initialized and configured. The initialization configuration includes setting the basic learner parameters, configuring the dynamic weight coefficients, and defining the weights of the loss function.

[0087] Step S122: Perform multiple rounds of iterative training on the benchmark model based on the training dataset until the training rounds reach the preset number of rounds or the benchmark model meets the preset convergence requirements. Then, the benchmark model that has reached the preset number of rounds or meets the convergence requirements is used as the trained replacement unit prediction model.

[0088] In this embodiment, using the baseline model that has reached the required number of training rounds as the trained replacement unit prediction model can prevent the model from stopping prematurely during training and failing to reach a relatively stable state. Using the baseline model that meets the convergence requirements as the trained replacement unit prediction model can avoid unnecessary waste of computational resources, improve training efficiency, and prevent overfitting.

[0089] Please refer to Figure 6 In some embodiments, the training method for each round of iterative training includes steps S122a to S122c, which are described in detail below.

[0090] Step S122a: Input the training dataset into the baseline model to obtain the power consumption prediction value and the replacement prediction probability value.

[0091] Specifically, forward propagation calculations are performed based on the training dataset and the benchmark model. The training dataset is input into the benchmark model, and the model performs calculations based on its own structure and parameters. On the one hand, it calculates the power consumption prediction value, which is the output of the regression task. On the other hand, it calculates the replacement prediction probability value, which is the output of the classification task. Through these two output values, the model completes the preliminary processing of the training dataset on two different tasks.

[0092] Step S122b: Calculate the multi-task composite loss value based on the preset multi-task composite loss function, power consumption prediction value, and replacement prediction probability value.

[0093] Specifically, the multi-task composite loss function includes a power regression loss function, a replacement decision loss function, and dynamic weight coefficients, where the dynamic weight coefficients are calculated based on the training epoch of the current iteration. For the regression task, an appropriate power regression loss function is used to calculate the difference between the predicted power consumption value and the actual power consumption value, thus obtaining the loss value for the regression task. For the classification task, an appropriate replacement decision loss function is used to calculate the difference between the predicted replacement probability and the actual replacement label, thus obtaining the loss value for the classification task.

[0094] For example, if the current training iteration is at epoch t, ​​the Sigmoid function is used to adjust the weights of the regression and classification tasks based on the training epoch t. The Sigmoid function maps the training epoch t to the (0, 1) interval, thereby dynamically changing the relative importance of the two tasks in subsequent calculations as the training epochs change.

[0095] Step S122c: Calculate the gradient value based on the multi-task composite loss value, and update the parameters of the baseline model using the gradient value and the preset optimization algorithm.

[0096] Specifically, the gradient of the multi-task composite loss value with respect to the baseline model is calculated, and the gradient value is obtained. A second-derivative optimization method is then used to update the parameters of the baseline model based on the gradient value. Specifically, information related to the second derivative, such as the Hessian matrix, is calculated to determine the direction and step size of the parameter updates, ensuring that the model parameters are adjusted in a way that reduces the loss function.

[0097] In some embodiments, due to multi-task requirements, while retaining the original XGBoost boosting framework, the loss function system of the weak learner, i.e., the loss function system of the decision tree, is reconstructed. Specifically, a multi-task composite loss function is used instead of the default squared loss function. For the regression task of power consumption prediction, a normalized mean squared error loss is used, while for the classification task of replacement decision, a weighted cross-entropy loss is used. Multi-task gradient fusion is achieved through dynamic weight coefficients. The formula for the multi-task composite loss function is as follows:

[0098] ;

[0099] ;

[0100] in, Let N represent the multi-task composite loss function, and let N represent the number of samples for the power prediction regression task in the training dataset. This represents the actual power consumption value of the i-th unit to be trained. This represents the predicted power consumption value of the i-th unit to be trained. Represents the normalization constant. This represents the dynamic weight coefficients, and M represents the number of samples in the training dataset that replace the decision classification task. The weights of positive samples are represented. This represents the true label of the j-th sample. This represents the Sigmoid function. This represents the value output by the j-th sample after processing by the baseline model. This indicates that the predicted probability value will be replaced. represents the weight of the negative sample, t represents the current training iteration round, and T represents the total number of training iteration rounds.

[0101] The above parameters are further explained as follows: normalization constant Typically, this represents the maximum power consumption of the units to be trained in the training dataset. Its purpose is to normalize the error, making the loss value more stable and unaffected by specific power consumption units. A positive sample refers to the true label y of the j-th sample. j A sample with a value of 1 is a replaceable sample, and a negative sample is the true label y of the j-th sample. j A sample with a value of 0 cannot be replaced. Indicates the numerical value Mapping to the range (0, 1) represents the probability that the model predicts a temporal violation in that sample. This represents the logits value output by the last layer of the baseline model after the j-th sample has been processed.

[0102] Please refer to Figure 7 In some embodiments, step S20: integrating the trained replacement unit prediction model into the EDA tool includes steps S21 to S23, which are described in detail below.

[0103] Step S21: Convert the trained replacement unit prediction model into a replacement unit prediction model in a preset format.

[0104] Specifically, based on the characteristics of the trained replacement unit prediction model, an appropriate transformation method is selected for model transformation. If the model structure is relatively simple and the control flow is fixed, `torch.jit.trace` is used, which can generate Torch Script code by tracing the model's execution path and is suitable for most conventional neural networks. If the model contains dynamic control flow, such as conditional statements and loops, `torch.jit.script` is used, which can perform static analysis on the model code and generate Torch Script. The trained replacement unit prediction model is a PyTorch model.

[0105] Step S22: Integrate the pre-defined front-end library into the development environment of the EDA tool.

[0106] Specifically, the front-end library is used to load and run replacement unit prediction models in a pre-defined format.

[0107] For example, the development environment of an EDA tool can be a C++ environment, and the front-end library can be the LibTorch library. The LibTorch library can be integrated into the C++ environment of the EDA tool.

[0108] Step S23: In the EDA tool, use the preset loading function to load the preset format replacement unit prediction model, so as to integrate the trained replacement unit prediction model into the EDA tool.

[0109] For example, the default loading function can be `torch::jit::load`. `torch::jit::load` loads the Torch Script model to integrate the trained replacement unit prediction model into the EDA tool. Specifically, `torch::jit::load` transforms the data in the EDA tool, then calls `forward()` to perform inference, and finally parses the output into a format that the EDA tool can process.

[0110] In this embodiment of the application, the trained model is integrated into the EDA tool via Torch Script. This requires converting the model into a Python-independent deployment format and calling it in a C++ environment.

[0111] In some embodiments, the trained model is not limited to a single type of model architecture, but includes, but is not limited to, traditional machine learning models, neural network models, and reinforcement learning models.

[0112] In this embodiment, a complete solution for power consumption optimization of a single unit to be optimized is constructed by integrating the trained replacement unit prediction model into an EDA tool. Each process sequentially completes its corresponding key steps, ensuring the overall efficiency and systematic nature of the process. Among these steps, constructing the training dataset for the unit to be trained is a fundamental step, undertaking the crucial task of dataset creation. An offline training and online inference approach is adopted, using the training dataset to train the model and obtain an offline model. The trained offline model is then embedded into the EDA tool to enable its application in real-world scenarios. Through the orderly connection and collaborative work of these steps, a complete process from data preparation to model application and optimization is successfully constructed, providing a practical solution for reducing the power consumption of a single unit to be optimized and improving program operating efficiency.

[0113] In this application embodiment, the main key technical points include the following three points: (1) Using a network model strategy to accelerate the optimization cycle of reducing the power consumption of a single unit to be optimized: By applying the network model, it directly affects the optimization cycle and significantly improves efficiency; (2) Data feature definition method: It covers the combination of node feature types and the splicing method of different node features, providing accurate and effective input data support for the model, which is an important foundation for achieving optimization acceleration; (3) Model embedding tool scheme: It is specifically used to reduce the power consumption of a single unit to be optimized and ensure that the model can run effectively in the actual tool.

[0114] This application deploys the offline-trained model into an actual program. Through comparative experiments with iterative verification and binary search methods, the system verifies the practical application performance of the proposed scheme in the clock tree synthesis stage. The core objective of this application is to achieve accurate prediction of the optimal low-power unit based on existing data characteristics without significantly reducing performance metrics such as PPA, thereby reducing the number of timing analysis and design rule checks, ultimately achieving an effective reduction in program runtime. The verification scheme includes two key dimensions: first, verifying the reduction effect of timing analysis and design rule checks; second, verifying the degree of system runtime optimization while maintaining a relatively stable PPA.

[0115] In some embodiments, verification is performed to determine whether the number of timing analysis checks is reduced. Trail represents the number of method calls, STA represents the number of timing analysis executions, Commit represents the number of units that pass timing analysis, S-Time represents the total time spent on timing analysis, Q-time represents the total time spent on other stages, and T-Time represents the reduction in the total system time for a single unit stage. These six metrics are used as evaluation indicators for verification. Please refer to [reference needed]. Figure 8 , Figure 8 The comparison of six metrics between the iterative method, the bisection method, and the method of this application is shown. In the experimental data, the best result is marked in red, and the second best result is marked in blue. (See reference.) Figure 8 As can be seen, the solution of this application significantly reduces the total system runtime by reducing the trigger frequency of timing analysis. In the power consumption optimization scenario of a single unit, the runtime of the solution of this application is only 1 / 5 of that of the iterative method, which verifies the significant advantage of the solution of this application in terms of efficiency improvement.

[0116] In some embodiments, the main evaluation metrics used during verification to determine whether the strategy significantly worsens the PPA are: Maximum Latency, Misalignment (MMSkew), Maximum Transition (Max Transition), Area, and Line Length (clklen). Please refer to [link / reference]. Figure 9 The best results for key performance indicators are marked in red, and the second best results are marked in blue. Experimental results show that the proposed strategy suffers from insufficient accuracy in identifying the number of units passing time-series analysis, leading to a 1.2% increase in Area. However, key performance indicators such as maximum latency, clock skew, maximum transition time, and interconnect length do not show significant degradation and remain within acceptable ranges. This result indicates that the strategy achieves effective control of core performance parameters while sacrificing a small area, meeting the preset goal of "not significantly reducing PPA". In summary, Figure 8 and Figure 9 The data results meet the requirement of significantly reducing runtime without significantly reducing PPA and Max Latency.

[0117] This application provides a clock tree synthesis and optimization device based on machine learning, including:

[0118] Memory, used to store programs;

[0119] A processor is used to implement clock tree synthesis optimization methods by executing programs stored in memory.

[0120] This application provides a computer program product, including a computer program and / or instructions, which implement a clock tree synthesis optimization method when executed by a processor.

[0121] Those skilled in the art will understand that all or part of the functions of the various methods in the above embodiments can be implemented by hardware or by computer programs. When all or part of the functions in the above embodiments are implemented by computer programs, the program can be stored in a computer-readable storage medium, which may include: read-only memory, random access memory, disk, optical disk, hard disk, etc., and the program is executed by a computer to achieve the above functions. For example, the program can be stored in the memory of a device, and when the program in the memory is executed by the processor, all or part of the above functions can be achieved. In addition, when all or part of the functions in the above embodiments are implemented by computer programs, the program can also be stored in a server, another computer, disk, optical disk, flash drive, or external hard drive, etc., and can be downloaded or copied to the memory of a local device, or the system of the local device can be updated. When the program in the memory is executed by the processor, all or part of the functions in the above embodiments can be achieved.

[0122] The above examples illustrate the present invention only to aid in understanding it and are not intended to limit the scope of the invention. Those skilled in the art can make various simple deductions, modifications, or substitutions based on the principles of this invention.

Claims

1. A clock tree synthesis optimization method based on machine learning, characterized in that, The method comprises the following steps: obtaining a trained replacement unit prediction model, wherein the trained replacement unit prediction model is used to predict an optimal replacement unit corresponding to a unit to be optimized in clock tree synthesis, and a training method of the replacement unit prediction model comprises the following steps: constructing a training data set of a unit to be trained in clock tree synthesis; determining a benchmark model according to a machine learning algorithm, and initializing and configuring model parameters of the benchmark model; performing multiple rounds of iterative training on the benchmark model based on the training data set until a preset round is reached or the benchmark model meets a preset convergence requirement, then taking the benchmark model reaching the round or the benchmark model meeting the convergence requirement as the trained replacement unit prediction model; and the training method of each round of iterative training comprises the following steps: inputting the training data set into the benchmark model to obtain a power consumption prediction value and a replacement prediction probability value, calculating a multi-task composite loss value based on a preset multi-task composite loss function, the power consumption prediction value and the replacement prediction probability value; calculating a gradient value according to the multi-task composite loss value, and updating the parameters of the benchmark model by using the gradient value and a preset optimization algorithm; and the multi-task composite loss function is expressed as: ； ； wherein, denotes a multi-task compound loss function, N denotes the number of samples of the power consumption prediction regression task in the training data set, denotes the real power consumption value of the i-th to-be-trained unit, denotes the power consumption prediction value of the i-th to-be-trained unit, denotes a normalization constant, denotes a dynamic weight coefficient, M denotes the number of samples of the replacement decision classification task in the training data set, denotes the weight of a positive sample, denotes the real label of the j-th sample, denotes a Sigmoid function, denotes the output value of the j-th sample after being processed by the benchmark model, denotes a replacement prediction probability value, denotes the weight of a negative sample, t denotes the round of the current iteration training, and T denotes the total number of iteration training rounds; integrating the trained replacement unit prediction model into an EDA tool, so as to call the trained replacement unit prediction model by the EDA tool integrated with the trained replacement unit prediction model to predict an optimal replacement unit corresponding to a unit to be optimized in clock tree synthesis.

2. The clock tree synthesis optimization method of claim 1, wherein, The unit to be trained is a unit in clock tree synthesis that needs to reduce power consumption, the training data set comprises multiple training data, the training data has different data features and data labels, the data features comprise circuit features, library unit features and process features, and the data labels comprise a replacement state of the unit to be trained and power consumption of an equivalent replacement unit, the equivalent replacement unit is a same-type unit used to replace the unit to be trained.

3. The clock tree synthesis optimization method of claim 1, wherein, The method for constructing the training data set of the unit to be trained comprises the following steps: obtaining multiple equivalent replacement units, and sorting the multiple equivalent replacement units according to an ascending order of power consumption of the equivalent replacement units; selecting the equivalent replacement units in the sorted multiple equivalent replacement units in sequence to replace the unit to be trained, and taking a first equivalent replacement unit meeting a preset timing verification requirement as a target replacement unit; generating a data label of the unit to be trained according to the target replacement unit, and obtaining data features of the unit to be trained and data features and data labels of associated units corresponding to the unit to be trained; splicing the data label of the unit to be trained, the data features of the unit to be trained and the data features and data labels of the associated units corresponding to the unit to be trained to obtain the training data set of the unit to be trained.

4. The clock tree synthesis optimization method of claim 3, wherein, When the unit to be trained is equivalent to a node, the associated units corresponding to the unit to be trained are parent nodes of the node.

5. The clock tree synthesis optimization method of claim 1, wherein The multi-task composite loss function comprises a power consumption regression loss function, a replacement decision loss function and a dynamic weight coefficient, and the dynamic weight coefficient is calculated according to a training round of current iterative training.

6. The clock tree synthesis optimization method of claim 1, wherein, The integrating the trained replacement unit prediction model into the EDA tool comprises: Converting the trained replacement unit prediction model into a replacement unit prediction model in a preset format; Integrating a preset front-end library into a development environment of the EDA tool, wherein the front-end library is used to load and run the replacement unit prediction model in the preset format; In the EDA tool, the replacement unit prediction model in the preset format is loaded by using a preset loading function, so as to integrate the trained replacement unit prediction model into the EDA tool.

7. A machine learning based clock tree synthesis optimization apparatus, comprising: Comprise: A memory for storing a program; A processor for executing the program stored in the memory to implement the clock tree synthesis optimization method according to any one of claims 1-6.

8. A computer program product comprising computer programs and / or instructions, characterized in that, The computer program and / or instructions are executed by the processor to implement the clock tree synthesis optimization method according to any one of claims 1-6.

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