Multi-working-mode-oriented integrated circuit segmented clock tree synthesis method and multi-working-mode-oriented integrated circuit segmented clock tree synthesis system

Abstract

The invention relates to the field of rear-end design of digital integrated circuits, in particular to an integrated circuit segmented clock tree synthesis method and system oriented to multiple working modes, and the method comprises the steps: employing a segmented optimization strategy, firstly dividing the working modes into a high-frequency function mode group and a low-frequency test mode group based on a clock frequency, the high-frequency group is preferentially subjected to clock tree synthesis and the network is fixed, and then the low-frequency group is optimized on the fixed basis. According to the method, global balance conflicts are reduced through priority isolation, high-frequency path time sequence quality is improved, and meanwhile low-frequency path power consumption overhead is controlled. And finally, time sequence convergence and power consumption are verified, and collaborative optimization of the time sequence and the power consumption in a multi-mode scene is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of digital integrated circuit back-end design, in particular to a segmented clock tree synthesis method and system for multi-working mode integrated circuits. BACKGROUND

[0002] The existing segmented clock tree synthesis method for multi-working mode integrated circuits is a clock distribution strategy for chip design with multiple working states such as high performance or low power mode. The core idea is to divide the clock tree structure into multiple logical segments, and each segment can be independently configured and optimized according to the current activated working mode of the chip.

[0003] The existing segmented clock tree synthesis method for multi-working mode integrated circuits has the following technical pain points, specifically: in chip design including functional mode and multiple test modes, the clock frequencies required by different working modes differ by orders of magnitude. The core clock in the functional mode needs to reach gigahertz level to achieve high performance, while the clock in the scan test mode only needs to be megahertz level to complete basic operations. The existing unified clock tree synthesis method cannot meet the global clock balancing target of all modes, and has to build the clock network with the most stringent high-frequency timing standard. The optimization tool will insert excessive buffer units on the low-frequency clock path to force its delay to match the high-speed path. This over-optimization strategy leads to unnecessary increase in power consumption and area of non-critical paths. More importantly, the critical high-speed clock path is artificially lengthened due to the global balancing constraint, and the delay and clock skew are difficult to optimize, which becomes the bottleneck of timing convergence. For example, in a chip using a unified synthesis strategy, to balance the low-speed clock in the test mode, the tool may add redundant buffers or routing on the critical clock path in the functional mode, making it difficult to meet the setup time and hold time of the high-frequency path, and increasing the dynamic power consumption of the clock network. SUMMARY

[0004] In view of the deficiencies of the prior art, the present application provides a segmented clock tree synthesis method and system for multi-working mode integrated circuits, which solves the technical problems of difficult timing convergence of critical high-speed clock paths and excessive power consumption of clock trees caused by using a unified clock tree synthesis method due to significant differences in clock frequencies under multi-working mode.

[0005] To solve the above technical problems, the specific content of the present application is as follows:

[0006] In a first aspect, the present application provides a segmented clock tree synthesis method for multi-working mode integrated circuits, comprising:

[0007] Step 1, obtaining layout data of integrated circuit design, the layout data including netlist of timing convergence;

[0008] Step 2: Based on the layout data, analyze multiple operating modes of the integrated circuit design, and divide the multiple operating modes into a first priority group and a second priority group according to the clock frequency. The first priority group includes functional modes with high clock frequency, and the second priority group includes test modes with low clock frequency.

[0009] Step 3: Perform a first segment clock tree synthesis on the first priority group to obtain a first clock tree network. The first segment clock tree synthesis includes creating a first clock synthesis specification file and setting first clock co-optimization parameters. After completing the first segment clock tree synthesis, fix the first clock tree network.

[0010] Step 4: Perform a second clock tree synthesis on the second priority group to obtain a second clock tree network. The second clock tree synthesis includes creating a second clock synthesis specification file and setting second clock co-optimization parameters. The second clock tree synthesis is performed on the basis of the fixed first clock tree network.

[0011] Step 5: After completing the synthesis of the second segment of the clock tree, verify the timing convergence and clock tree power consumption, so that the timing convergence is achieved and the clock tree power consumption is reduced.

[0012] Furthermore, the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes described in this invention, wherein dividing the multiple operating modes into a first priority group and a second priority group according to the clock frequency, includes:

[0013] Extract the clock domain and its corresponding clock frequency value under the multiple working modes;

[0014] The working mode of the clock domain whose clock frequency value exceeds the preset high frequency threshold is dynamically assigned to the first priority group;

[0015] The operating modes of clock domains whose clock frequency values ​​are lower than or equal to a preset low-frequency threshold are dynamically assigned to the second priority group.

[0016] The preset high-frequency threshold and the preset low-frequency threshold are set according to the process node and performance target of the integrated circuit design.

[0017] Furthermore, in the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes described in this invention, the setting of the first clock co-optimization parameters includes:

[0018] Identify the clock structure types included in the first priority group;

[0019] In response to the identification of the clock structure of the high-frequency master clock, a first target skew range and a first winding rule are configured for the corresponding clock tree. The first target skew range is 30ps to 100ps, and the first winding rule uses high-layer metal with a width twice the standard width and a spacing three times the standard spacing.

[0020] In response to the identification of a low-frequency communication clock structure, a second target skew range and a second winding rule are configured for the corresponding clock tree. The second target skew range is 100ps to 200ps, and the second winding rule uses high-layer metal with a width twice the standard width and a spacing twice the standard spacing.

[0021] Furthermore, in the multi-mode integrated circuit segmented clock tree synthesis method of the present invention, the fixing of the first clock tree network includes:

[0022] Position the mode switching multiplexer that connects the first priority group and the second priority group;

[0023] Set the clock input port attribute corresponding to the second priority group in the mode switching multiplexer to the stop propagation attribute;

[0024] When the stop propagation attribute is set, the clock signal of the second priority group is blocked at the clock input port of the mode switching multiplexer during the second segment clock tree synthesis.

[0025] Furthermore, in the multi-mode integrated circuit segmented clock tree synthesis method of the present invention, the setting of the second clock co-optimization parameters includes:

[0026] Based on the fixed first clock tree network, the average insertion delay of the clock signal of the first priority group propagating from the first input port of the mode switching multiplexer to the clock pin of the timing unit is calculated.

[0027] The average insertion delay is configured as a port delay attribute and assigned to the clock input port in the mode switching multiplexer corresponding to the second priority group.

[0028] Configure a third target skew range and a third winding rule globally for the clock tree of the second priority group. The third target skew range is 100ps to 250ps. The third winding rule uses high-layer metal and has a width twice the standard width and a spacing twice the standard spacing.

[0029] Furthermore, in the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes described in this invention, the creation of the first clock synthesis specification file includes:

[0030] Detect whether the clock structure of the integrated circuit design contains a target clock structure including a frequency divider register and a multi-stage multiplexer;

[0031] In response to the detection of the target clock structure, a comment operation is performed on the clock ignore attribute of the test clock input port in the multi-level multiplexer in the first clock synthesis specification file;

[0032] The annotation operation is used to activate the balance optimization of the test clock input port in subsequent clock tree synthesis.

[0033] Furthermore, in the multi-mode integrated circuit segmented clock tree synthesis method of the present invention, step 5 further includes:

[0034] When the timing fails to converge or the clock tree power consumption does not reach the expected target, an adjustment instruction is generated;

[0035] Based on the adjustment instructions, at least one of the constraints in the first clock synthesis specification file or the first clock co-optimization parameters is iteratively modified.

[0036] Using the modified constraints or the first clock co-optimization parameters, re-execute the first clock tree synthesis and the second clock tree synthesis until timing convergence and clock tree power consumption reaches the expected target.

[0037] Furthermore, in the multi-mode integrated circuit segmented clock tree synthesis method of the present invention, the first segment clock tree synthesis of the first priority group and the second segment clock tree synthesis of the second priority group are executed by the segmented synthesis instruction set in the clock tree synthesis tool;

[0038] The segmented synthesis instruction set includes: a first instruction for creating a clock synthesis specification file, a second instruction for setting clock co-optimization parameters, and a third instruction for triggering segmented clock tree synthesis operations.

[0039] Furthermore, the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes described in this invention also includes:

[0040] The embedded digital integrated circuit back-end design flow includes the layout data source being the node where the layout is completed and the timing is initially converged, the node where the timing convergence and clock tree power consumption are verified, and the output to the winding stage for subsequent physical implementation.

[0041] Secondly, this invention provides a segmented clock tree synthesis system for integrated circuits oriented towards multiple operating modes, applied to the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes as described above, including:

[0042] The data acquisition module is configured to acquire layout data of integrated circuit design, wherein the layout data includes a time-converged netlist;

[0043] The analysis and division module is configured to analyze multiple operating modes of the integrated circuit design based on the layout data, and divide the multiple operating modes into a first priority group and a second priority group according to the clock frequency, wherein the first priority group includes functional modes with high clock frequency, and the second priority group includes test modes with low clock frequency.

[0044] The first synthesis processing module is configured to perform a first segment clock tree synthesis on the first priority group to obtain a first clock tree network. The first segment clock tree synthesis includes creating a first clock synthesis specification file and setting first clock co-optimization parameters. After completing the first segment clock tree synthesis, the first clock tree network is fixed.

[0045] The second synthesis processing module is configured to perform a second segment clock tree synthesis on the second priority group to obtain a second clock tree network. The second segment clock tree synthesis includes creating a second clock synthesis specification file and setting second clock co-optimization parameters. The second segment clock tree synthesis is performed on the basis of the fixed first clock tree network.

[0046] The verification output module is configured to verify timing convergence and clock tree power consumption after completing the synthesis of the second segment of the clock tree, so as to achieve timing convergence and reduce clock tree power consumption.

[0047] Beneficial effects of this invention;

[0048] This invention employs a segmented clock tree synthesis method for multiple operating modes. Based on clock frequency, priority groups are dynamically divided. First, the first priority group for high-frequency functional modes undergoes clock tree synthesis and network fixation. Then, the second priority group for low-frequency test modes is optimized in an isolated environment. This overcomes the problems of high-frequency path timing convergence difficulties and excessive power consumption in low-frequency paths caused by global balance constraints in traditional unified optimization methods. The priority grouping mechanism, combined with differentiated collaborative optimization parameter configuration, enables strict skew control and high-layer metal winding for high-frequency paths, shortening critical path delays. Simultaneously, relaxed constraints are used for low-frequency paths to reduce buffer insertion and lower dynamic power consumption. Dynamic adjustment of port attributes for special clock structures such as multiplexers and annotation operations activate balance optimization, enhancing timing consistency under multi-mode switching. Segmented processing reduces global conflicts, and iterative correction improves timing convergence efficiency and controls power consumption, reducing the number of design iterations. This method is suitable for high-performance integrated circuit back-end design. Attached Figure Description

[0049] To more clearly illustrate the technical solution of the present invention, the drawings used in the embodiments will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on the drawings without creative effort.

[0050] Figure 1 This is a flowchart illustrating a segmented clock tree synthesis method for integrated circuits with multiple operating modes, according to the present invention.

[0051] Figure 2 This is a schematic diagram of the special clock structure described in this invention.

[0052] Figure 3 This is a schematic diagram of the connection of the multiplexer responsible for mode switching in an embodiment of the present invention. Detailed Implementation

[0053] To make the technical solution of the present invention clearer, the present invention will be clearly and completely described below with reference to specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. The present invention provided by various embodiments will be described in detail below with reference to the accompanying drawings. To better understand the purpose of the present invention, the present invention will be described in further detail below.

[0054] Firstly, please refer to Figure 1 This invention provides a segmented clock tree synthesis method for integrated circuits with multiple operating modes, comprising:

[0055] Step 1: Obtain the layout data of the integrated circuit design, which includes a timing-converged netlist;

[0056] Step 2: Based on the layout data, analyze multiple operating modes of the integrated circuit design, and divide the multiple operating modes into a first priority group and a second priority group according to the clock frequency. The first priority group includes functional modes with high clock frequency, and the second priority group includes test modes with low clock frequency.

[0057] Step 3: Perform a first segment clock tree synthesis on the first priority group to obtain a first clock tree network. The first segment clock tree synthesis includes creating a first clock synthesis specification file and setting first clock co-optimization parameters. After completing the first segment clock tree synthesis, fix the first clock tree network.

[0058] Step 4: Perform a second clock tree synthesis on the second priority group to obtain a second clock tree network. The second clock tree synthesis includes creating a second clock synthesis specification file and setting second clock co-optimization parameters. The second clock tree synthesis is performed on the basis of the fixed first clock tree network.

[0059] Step 5: After completing the synthesis of the second segment of the clock tree, verify the timing convergence and clock tree power consumption, so that the timing convergence is achieved and the clock tree power consumption is reduced.

[0060] In the field of digital integrated circuit back-end design, clock tree synthesis is a critical step affecting timing convergence and power consumption optimization. This invention proposes a segmented clock tree synthesis method, which addresses scenarios with significant clock frequency differences across multiple operating modes. Through priority partitioning and step-by-step optimization, it aims to improve the timing quality of high-frequency paths and control overall power consumption. This invention starts from the nodes after placement and operates based on the timing-converged netlist data.

[0061] Obtaining layout data for integrated circuit design is the starting point of this methodology. This data originates from the stage in the chip physical implementation process where cell placement is complete and timing has initially converged. Layout data includes netlist information and cell positional relationships, providing a foundation for subsequent clock tree analysis. In practical applications, layout quality directly impacts the initial conditions for clock tree synthesis; therefore, it is necessary to ensure that the netlist timing has been initially optimized to avoid repeated iterations in subsequent steps due to improper layout.

[0062] Based on layout data, multiple operating modes of the integrated circuit are analyzed and grouped according to clock frequency. This step extracts the clock domain and its frequency value for each mode, assigning high-frequency functional modes to the first priority group and low-frequency test modes to the second priority group. The dynamic nature of the grouping is reflected in the threshold settings; high-frequency and low-frequency thresholds are dynamically adjusted according to process nodes and performance targets. For example, at advanced process nodes, the high-frequency threshold may be set higher to focus on the critical path. This grouping mechanism avoids resource waste during unified optimization, making subsequent synthesis more targeted.

[0063] When performing the first clock tree synthesis on the first priority group, a dedicated clock synthesis specification file needs to be created and clock co-optimization parameters configured. The specification file defines the structural constraints of the clock tree, while the optimization parameters include the target skew range and winding rules; for example, for high-frequency master clocks, the skew range is set more strictly, and high-layer metal is used for winding to reduce delay. After synthesis, the first clock tree network is fixed, and the multiplexer is switched via positioning mode to set the clock input port attribute of its second priority group to stop propagation, thereby blocking interference from the test clock signal. This fixing operation ensures the stability of the high-frequency path and provides an isolated environment for subsequent synthesis.

[0064] In scenarios with special clock structures, such as those involving divider registers and multi-stage multiplexers, the ignore attribute of the test clock port needs to be commented out when creating the specification file to activate balance optimization. This adaptive handling avoids excessive skew in test mode and improves the robustness of the method.

[0065] The second stage of clock tree synthesis is performed on a fixed network. A separate specification file is created for the second priority group, and co-optimization parameters are set. Key operations include calculating the average insertion delay of the first priority group clock from the multiplexer port to the timing unit, and configuring this delay as an attribute at the input of the second priority group to maintain timing consistency. In the parameter configuration, the skew range is relatively lenient, and the routing rules emphasize resource balancing, thereby reducing power consumption while meeting low-frequency requirements.

[0066] After completing the two-stage synthesis, timing convergence and clock tree power consumption are verified. If the expected goals are not achieved, adjustment instructions are generated and constraints or optimization parameters are iteratively corrected, for example, by re-executing the synthesis steps until convergence. The verification process is integrated into the standard back-end flow, and after passing, the output is sent to the routing stage to ensure the continuity of physical implementation. This invention reduces global balance constraint conflicts through segmented processing, which can reduce the number of iterations in practical applications. However, the effect is affected by layout quality and threshold settings, and needs to be dynamically adjusted according to the specific design.

[0067] Specifically, the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes described in this invention, wherein dividing the multiple operating modes into a first priority group and a second priority group according to the clock frequency includes:

[0068] Extract the clock domain and its corresponding clock frequency value under the multiple working modes;

[0069] The working mode of the clock domain whose clock frequency value exceeds the preset high frequency threshold is dynamically assigned to the first priority group;

[0070] The operating modes of clock domains whose clock frequency values ​​are lower than or equal to a preset low-frequency threshold are dynamically assigned to the second priority group.

[0071] The preset high-frequency threshold and the preset low-frequency threshold are set according to the process node and performance target of the integrated circuit design.

[0072] In the segmented clock tree synthesis method for multi-operating-mode integrated circuits, the process of prioritizing groups begins with a comprehensive analysis of the design's operating modes. Using back-end design tools, the clock domains involved in each operating mode and their corresponding clock frequency values ​​are extracted. This operation is based on the netlist data after timing convergence following placement. Clock domain identification relies on the analysis of clock sources and timing paths, while frequency values ​​are obtained from design constraint files, such as by outputting clock cycle information for each mode using static timing analysis tools. This extraction method provides the data foundation for subsequent grouping, enabling the partitioning process to be tailored to the actual clock characteristics.

[0073] The setting of preset high-frequency and low-frequency thresholds is a dynamic process, adjusted according to the process node and performance goals of the integrated circuit design. For example, at advanced process nodes, the high-frequency threshold may be set higher to focus on gigahertz-level functional modes, while the low-frequency threshold is set for megahertz-level test modes. Threshold settings must consider the delay characteristics of the process library and the speed requirements of the design to avoid resource waste caused by uniform standards. Through a dynamic allocation mechanism, clock domains with clock frequencies exceeding the high-frequency threshold are automatically assigned to the first priority group, while those with frequencies below or equal to the low-frequency threshold are assigned to the second priority group. This grouping logic ensures that high-frequency paths are prioritized for optimization.

[0074] The priority grouping process logically connects the layout data analysis and clock tree synthesis stages. Extracting the clock domain and frequency values ​​is a prerequisite, providing input for threshold comparison; dynamic grouping classifies operating modes based on the comparison results, and the classification results directly guide the priority order of subsequent segmented synthesis. In practical applications, threshold setting may require multiple iterations. For example, if timing convergence is unsatisfactory after initial grouping, the threshold may be readjusted to balance the grouping granularity. This flexibility adapts to the complexity of multi-mode designs and avoids the optimization deficiencies or over-optimization problems caused by rigid partitioning.

[0075] The partitioning process is embedded in the back-end flow of digital integrated circuits, starting from post-placement nodes. The grouping results are used to create differentiated clock synthesis specification files. For example, high-frequency functional modes are grouped into the first group, and subsequent synthesis will employ strict skew constraints, while low-frequency test modes in the second group will use more lenient rules. The causal chain between steps reflects a frequency-oriented optimization strategy, reducing global balance conflicts through priority isolation, and laying the foundation for timing convergence and power consumption control.

[0076] Specifically, the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes described in this invention, wherein setting the first clock co-optimization parameter includes:

[0077] Identify the clock structure types included in the first priority group;

[0078] In response to the identification of the clock structure of the high-frequency master clock, a first target skew range and a first winding rule are configured for the corresponding clock tree. The first target skew range is 30ps to 100ps, and the first winding rule uses high-layer metal with a width twice the standard width and a spacing three times the standard spacing.

[0079] In response to the identification of a low-frequency communication clock structure, a second target skew range and a second winding rule are configured for the corresponding clock tree. The second target skew range is 100ps to 200ps, and the second winding rule uses high-layer metal with a width twice the standard width and a spacing twice the standard spacing.

[0080] In the segmented clock tree synthesis method for integrated circuits with multiple operating modes, setting the first clock co-optimization parameters is a crucial step in optimizing the clock network of the first priority group. This step aims to configure parameters differently based on the timing sensitivity of the clock structure, thereby prioritizing the performance of high-frequency paths during segmented synthesis. In practice, the clock tree synthesis tool analyzes the netlist data after placement to identify the various clock structure types included in the first priority group, such as distinguishing between high-frequency master clocks and low-frequency communication clocks by parsing clock domains and timing paths.

[0081] When identifying clock structure types, the tool extracts attribute information from the clock source, including clock frequency and drive strength, and dynamically classifies it in conjunction with design constraint documents. For example, in the back-end process of digital integrated circuits, static timing analysis results can be used to help determine the criticality of the clock. For the clock structure of a high-frequency master clock, the configuration process involves setting a narrower target skew range and employing high-layer metal routing rules to reduce interconnect delay; the routing rules specify the multiple relationship between metal width and spacing to enhance signal integrity. This configuration method helps shorten the propagation delay of the critical path, but it requires a trade-off in routing resource usage to avoid overcrowding.

[0082] For the clock structure of low-frequency communication clocks, parameter configuration focuses on reducing optimization overhead. The target skew range is set relatively loosely, and the routing rules adopt more resource-efficient solutions. For example, adjusting the width and spacing multiple of the upper metal layer can reduce the number of buffer insertions while meeting basic timing requirements. During configuration, the tool automatically applies parameters based on the clock tree topology, but designers may need to manually fine-tune them according to the characteristics of the process library to cope with the variability under different nodes.

[0083] The logical relationship between the steps is a progressive optimization: first, the optimization target is clarified by identifying the clock type; then, customized parameters are applied to different types to achieve a balance between timing and power consumption during the synthesis stage. This differentiated approach avoids the resource waste caused by uniform optimization, but it relies on accurate clock classification; if the identification is inaccurate, it may cause local timing conflicts. In practical applications, parameter configuration needs to be iteratively verified to ensure seamless integration with subsequent segmented synthesis.

[0084] Specifically, the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes described in this invention, wherein fixing the first clock tree network includes:

[0085] Position the mode switching multiplexer that connects the first priority group and the second priority group;

[0086] Set the clock input port attribute corresponding to the second priority group in the mode switching multiplexer to the stop propagation attribute;

[0087] When the stop propagation attribute is set, the clock signal of the second priority group is blocked at the clock input port of the mode switching multiplexer during the second segment clock tree synthesis.

[0088] In segmented clock tree synthesis, fixing the first clock tree network is a crucial operation for isolating high-frequency and low-frequency clock domains. Its purpose is to maintain the stability of the first priority group's clock paths and prevent interference from being introduced in subsequent synthesis stages. This step begins with a deep analysis of the netlist data. Using integrated circuit back-end design tools, the clock domain connectivity is analyzed to identify the multiplexer instances responsible for mode switching. Each multiplexer is typically located at the intersection of the clock distribution network, with its input ports corresponding to the clock signals for functional and test modes, respectively. The tool traverses the cell connectivity in the netlist, dynamically locating all multiplexer nodes involved in mode switching based on clock source attributes and timing path mappings, laying the foundation for attribute configuration.

[0089] After locating the multiplexer, the clock propagation attributes of its input ports need to be dynamically configured. Specifically, designers use the command interface of the clock tree synthesis tool, such as the `set_ccopt_property` command, to modify the clock input port attribute corresponding to the second priority group in the multiplexer to a stopped propagation state. This attribute setting blocks the propagation of the clock signal from the test mode path to the functional mode path, causing the tool to treat only the multiplexer output as the clock endpoint during subsequent synthesis. In practice, changes to port attributes must be verified based on timing constraint files to avoid misjudging clock domain boundaries; simultaneously, the tool automatically checks attribute consistency to prevent clock conflicts in multi-mode scenarios.

[0090] After setting the stop propagation attribute, the second stage of clock tree synthesis can be performed in an isolated environment. The clock signal of the second priority group is blocked at the multiplexer input port, meaning the synthesis tool will not rebalance or insert buffers into the fixed first clock tree network. This blocking mechanism reduces the coupling between clock trees, allowing the optimization of low-frequency clock paths to no longer be constrained by the strict limitations of high-frequency paths. Logically, this step forms a causal chain with the previous step: attribute configuration is the means of achieving isolation, while the blocking effect is the direct manifestation of isolation, together ensuring the timing consistency of segmented synthesis. In multi-mode chip design, this method helps reduce the number of iterations, but its effectiveness depends on the accuracy of the multiplexer positioning and the completeness of the attribute settings, requiring dynamic adjustment based on the placement data.

[0091] Specifically, the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes described in this invention, wherein setting the second clock co-optimization parameter includes:

[0092] Based on the fixed first clock tree network, the average insertion delay of the clock signal of the first priority group propagating from the first input port of the mode switching multiplexer to the clock pin of the timing unit is calculated.

[0093] The average insertion delay is configured as a port delay attribute and assigned to the clock input port in the mode switching multiplexer corresponding to the second priority group.

[0094] Configure a third target skew range and a third winding rule globally for the clock tree of the second priority group. The third target skew range is 100ps to 250ps. The third winding rule uses high-layer metal and has a width twice the standard width and a spacing twice the standard spacing.

[0095] During the setup of the second clock co-optimization parameters, based on the fixed first clock tree network, the average insertion delay of the first priority group clock signal from the specified input port of the mode switching multiplexer to the clock pin of the timing cell needs to be calculated first. This operation is typically achieved using delay extraction commands in clock tree synthesis tools, such as dynamically obtaining statistical values ​​of path delays within the skew group using the `get_ccopt_skew_group_delay` command. The purpose of calculating the average insertion delay is to provide baseline data for subsequent port attribute configuration, thereby maintaining timing consistency under multi-mode switching during the second stage of synthesis. In practical applications, the tool will traverse all relevant paths in the first priority group clock domain and perform delay estimation based on the physical information of the netlist after placement. However, the results may be affected by cell library variations or routing congestion and need to be verified in conjunction with design constraints.

[0096] Next, the calculated average insertion delay is dynamically configured as a port delay attribute to the clock input port in the mode-switching multiplexer corresponding to the second priority group. The configuration process is accomplished using a clock co-optimization instruction set, such as using the `set_ccopt_property` command to assign the delay value to the port's `insertion_delay` attribute. This setting ensures that during the second-stage clock tree synthesis, the tool treats the multiplexer input port as a virtual clock endpoint, avoiding interference with the fixed network. In complex clock structures, port attribute configuration needs to be coordinated with clock ignore attribute adjustment. For example, when the multiplexer is connected to a divider register, the balance optimization status of the test clock port needs to be checked to prevent abnormal skew.

[0097] After configuring the port delay, the target skew range and routing rules are globally defined for the clock tree of the second priority group. The skew range is set to a relatively lenient interval to accommodate the timing requirements of low-frequency test modes; the routing rules use higher metal layers and increase the multiple relationship between conductor width and spacing to balance signal integrity and resource utilization. Parameter configuration is achieved through the specification file of the clock tree synthesis tool, for example, specifying skew group constraints in the create_ccopt_clock_tree_spec view. In practice, the selection of the skew range needs to consider the characteristics of the process node, and the routing rules need to be coordinated with the metal layer strategy of the first synthesis segment to avoid inter-layer conflicts. This differentiated configuration reduces power consumption while providing sufficient optimization margin for the low-frequency path, but it needs to be iteratively adjusted through timing verification.

[0098] The parameter setting process embodies the progressive logic of segmented synthesis: delay calculation is the basic step, providing data support for port attributes; attribute configuration connects the preceding and following steps, isolating high and low priority clock domains; and global parameter definition ultimately achieves independent optimization of the second segment of the clock tree. Each step is seamlessly connected through a tool instruction chain. For example, in the back-end process of digital integrated circuits, parameter updates trigger clock tree reconstruction, but this may increase runtime due to design scale. Application scenarios are commonly seen in multi-mode chip designs, such as systems that simultaneously include gigahertz functional modes and megahertz test modes, where the correct handling of mode switching multiplexers is crucial. Through segmented optimization, the timing quality of high-frequency paths is improved, while the power consumption of low-frequency paths is controlled; however, the effectiveness depends on the quality of the placement phase and the rationality of threshold settings.

[0099] Specifically, the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes described in this invention, wherein creating a first clock synthesis specification file includes:

[0100] Detect whether the clock structure of the integrated circuit design contains a target clock structure including a frequency divider register and a multi-stage multiplexer;

[0101] In response to the detection of the target clock structure, a comment operation is performed on the clock ignore attribute of the test clock input port in the multi-level multiplexer in the first clock synthesis specification file;

[0102] The annotation operation is used to activate the balance optimization of the test clock input port in subsequent clock tree synthesis.

[0103] In the process of segmented clock tree synthesis of integrated circuits, creating the first clock synthesis specification file involves a detailed analysis of the clock structure. The tool scans the netlist data after placement, dynamically identifying the presence of target clock structures including divider registers and multi-stage multiplexers. This detection is based on clock domain resolution algorithms, matching predefined component connection patterns, such as divider register outputs connected to multiplexer data inputs, thereby locating critical nodes that may affect timing. By automatically traversing the clock path, designers can identify complex topologies early, providing input for subsequent optimizations.

[0104] After detecting the target clock structure, the system performs a commenting operation in the first clock synthesis specification file, modifying the clock ignore attribute of the test clock input ports for the multi-stage multiplexer. Specifically, the commenting operation is implemented through the command interface of the clock tree synthesis tool. For example, the `set_ccopt_property` command can be used to remove the ignore status, allowing the previously ignored test clock ports to be considered in the balance calculation. This step depends on the accuracy of the detection results; if the structure is not fully identified, the commenting may be invalid. Therefore, it is necessary to repeatedly verify the data in conjunction with the layout data.

[0105] The purpose of the annotation operation is to activate the balance optimization for the test clock input port, avoiding excessive accumulation of clock skew in multi-mode scenarios. For example, in Figure 2 In the special clock structure shown, if the test port of the multiplexer is ignored, the low-frequency clock path may not be able to coordinate with the high-frequency path, causing timing conflicts. By annotating the attributes, the tool will force the delay of the port to be balanced during the synthesis stage, thereby improving the consistency of the clock tree.

[0106] Ultimately, this adaptive approach enhances the robustness of clock tree synthesis, particularly for integrated circuit designs involving mixed-mode switching. The synergy between detection and annotation ensures that optimization resources are focused on critical regions; however, in deeper multi-level multiplexer hierarchies, the annotation scope may need to be extended to the clock network to maintain global balance.

[0107] Specifically, in the multi-mode integrated circuit segmented clock tree synthesis method of the present invention, step 5 further includes:

[0108] When the timing fails to converge or the clock tree power consumption does not reach the expected target, an adjustment instruction is generated;

[0109] Based on the adjustment instructions, at least one of the constraints in the first clock synthesis specification file or the first clock co-optimization parameters is iteratively modified.

[0110] Using the modified constraints or the first clock co-optimization parameters, re-execute the first clock tree synthesis and the second clock tree synthesis until timing convergence and clock tree power consumption reaches the expected target.

[0111] When timing verification results indicate that the clock tree network has not reached convergence or that power consumption exceeds expected targets, the system triggers an adjustment instruction generation mechanism. This process is typically implemented through the report parsing function in a clock tree synthesis tool. The tool extracts information on non-compliant paths in the setup and hold times from the timing report and dynamically identifies under-optimized areas based on power consumption analysis results. The generation of adjustment instructions relies on predefined threshold comparison logic. For example, when the number of non-compliant paths exceeds a set proportion or the dynamic power consumption value is higher than the target threshold, the tool automatically outputs targeted correction suggestions. In practical applications, designers may need to intervene and review the instruction content, especially in scenarios with severe multi-mode cross-coupling, manually fine-tuning instruction priorities to focus on key conflict points.

[0112] Based on the generated adjustment instructions, the correction operation focuses on iteratively updating at least one of the constraints in the first clock synthesis specification file or the first clock co-optimization parameters. Constraint correction may involve adjusting the numerical range of the clock skew target or modifying the hierarchical strategy of the winding rules, while the iteration of co-optimization parameters targets the insertion delay compensation value or buffer drive strength configuration. The correction process implements batch attribute updates through tool scripts, such as using the `set_ccopt_property` command to reset the skew group target, or using the `edit_clock_spec` command to adjust the metal layer allocation rules in the specification file. The logic of iterative correction is to gradually approach the optimal solution, re-evaluating the timing and power consumption tradeoffs after each correction to avoid over-optimization leading to resource waste. In complex designs, corrections may need to be performed in rounds, with the first round prioritizing high-frequency path constraints, and subsequent iterations extending to global parameter coordination.

[0113] Using revised constraints or co-optimization parameters, the system re-executes the complete process of the first and second clock tree synthesis stages. During resynthesis, the tool reconstructs the clock topology based on the updated specification file and applies new co-optimization parameters for buffer insertion and routing optimization. This stage must maintain the isolation characteristics of segmented synthesis, ensuring that the first priority group clock network remains fixed in the second synthesis, allowing only the second priority group to be adjusted based on the revised parameters. The exit condition for the iterative loop depends on the successful completion of both timing verification and power consumption assessment. If convergence is not achieved after multiple iterations, it may be necessary to backtrack to the placement stage to reassess the data preparation quality. In practice, the number of iterations is limited by design size and tool efficiency; a maximum iteration threshold is typically set to avoid infinite loops.

[0114] The iterative correction process is embedded in the back-end design environment of digital integrated circuits, and its effectiveness depends on the quality of the initial layout data and the rationality of the operating mode division. At advanced process nodes, the correction process may require additional verification such as noise analysis and signal level to address timing fluctuations caused by physical effects. Through this closed-loop optimization mechanism, the segmented clock tree synthesis method improves timing convergence efficiency in multi-mode scenarios while keeping power consumption within an acceptable range.

[0115] Specifically, the segmented clock tree synthesis method for integrated circuits oriented to multiple operating modes described in this invention, wherein the first segment clock tree synthesis of the first priority group and the second segment clock tree synthesis of the second priority group are performed by the segmented synthesis instruction set in the clock tree synthesis tool;

[0116] The segmented synthesis instruction set includes: a first instruction for creating a clock synthesis specification file, a second instruction for setting clock co-optimization parameters, and a third instruction for triggering segmented clock tree synthesis operations.

[0117] In the segmented clock tree synthesis method for integrated circuits with multiple operating modes, the segmented synthesis instruction set serves as a core component of the clock tree synthesis tool, used for the step-by-step construction and optimization of the clock network. This instruction set is integrated into the digital integrated circuit back-end design environment, processing clock domains of different priority groups through serialization operations to adapt to scenarios with significant clock frequency differences across multiple operating modes. The instruction set is designed based on a priority grouping mechanism, first synthesizing the first priority group for high-frequency functional modes, and then processing the second priority group for low-frequency test modes on a fixed network basis, thereby reducing conflicts caused by global balance constraints.

[0118] The first instruction for creating a clock synthesis specification file generates constraint definitions for a specific priority group by parsing the netlist data after placement. In practice, the instruction dynamically constructs the specification file based on the analysis view of the priority group, such as identifying complex topologies like frequency dividers or multi-stage multiplexers in the clock structure. When a special clock structure is detected, the tool automatically adjusts attribute settings, such as commenting out the ignored states of test clock ports to activate balanced optimization. The creation of the specification file depends on the quality of the netlist with timing convergence during the placement phase; if the initial data is biased, it may increase the number of subsequent synthesis iterations.

[0119] The second instruction for setting clock co-optimization parameters configures differentiated parameters based on the timing sensitivity of priority groups. For high-frequency clocks in the first priority group, the instruction configures a strict skew target range and high-layer metal routing rules to reduce interconnect delay; while for low-frequency clocks in the second priority group, a more lenient skew target and a more resource-efficient routing strategy are adopted. The parameter setting process incorporates clock domain analysis results, such as dynamically adjusting the optimization target by identifying the structural types of the master clock and communication clock. When executing the instruction, process node characteristics must be considered; if routing resources are limited, manual fine-tuning of parameters may be necessary to balance timing and area overhead.

[0120] The third instruction triggering the segmented clock tree synthesis operation is responsible for initiating the physical implementation phase of the clock tree. Based on the specification file and optimization parameters generated in the preceding steps, the instruction performs operations such as buffer insertion and routing optimization to construct the clock network. In the segmented process, the instruction first performs synthesis on the first priority group and fixes the network, then performs independent optimization on the second priority group to avoid cross-interference. The effectiveness of the synthesis operation is limited by the tool's algorithm; for example, in complex clock topologies, skew control may require multiple iterations to achieve convergence.

[0121] The logical relationship of the segmented synthesis instruction set is manifested as a progressive workflow: creating a specification file provides the structural foundation for parameter settings, parameter configuration guides the specific optimization direction of the synthesis operation, and synthesis triggering completes network construction. This serialization process ensures that high-frequency paths are optimized first, while low-frequency paths are adapted in an isolated environment, thereby improving timing convergence efficiency. In practical applications, the execution of the instruction set is embedded in the standard backend process, starting from the post-layout node and outputting to the routing stage, but the overall effect depends on the rationality of the initial layout data and the accuracy of the threshold settings. If the design scale is large or the mode switching is frequent, the instruction sequence may need to be dynamically adjusted in conjunction with static timing analysis to cope with timing fluctuations.

[0122] Specifically, the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes described in this invention further includes:

[0123] The embedded digital integrated circuit back-end design flow includes the layout data source being the node where the layout is completed and the timing is initially converged, the node where the timing convergence and clock tree power consumption are verified, and the output to the winding stage for subsequent physical implementation.

[0124] In the back-end design flow of digital integrated circuits, the segmented clock tree synthesis method embeds a standard physical implementation sequence, starting from the node where placement is complete and timing has initially converged. Placement data is typically exported from cell placement tools, including preliminarily optimized netlist information. The timing path has reached basic convergence through static timing analysis, providing a stable foundation for clock tree synthesis. In practice, designers need to confirm that the netlist timing report has no major violations, such as setup and hold times meeting the technology library requirements, to avoid repeated iterations in subsequent steps due to unreasonable placement. The data quality at this stage directly affects the clock tree construction efficiency; if there are deviations in the initial timing, the placement strategy or constraints may need to be readjusted.

[0125] After clock tree synthesis, node integration for timing convergence verification and clock tree power consumption is performed using static timing analysis tools to check clock path skew and delay in all operating modes. Power consumption assessment extracts dynamic power consumption data using power analysis tools, focusing on clock network buffer insertion and routing resource usage. When timing reports show that the number of non-compliant paths exceeds a preset threshold or power consumption values ​​fail to meet targets, the system generates adjustment instructions to guide designers in revising clock synthesis specifications or optimizing parameters. For example, in multi-mode scenarios, clock paths in high-frequency functional modes may exhibit abnormal skew due to test mode interference, requiring local resynthesis to balance timing and power consumption. The verification process is not a one-time pass; it often relies on multiple iterations to approximate the optimal solution. The number of iterations is constrained by the design scale and tool convergence speed.

[0126] After verification, the optimized netlist data is output to the routing stage for subsequent physical implementation. The routing tool receives the netlist synthesized from the clock tree and performs metal layer allocation and interconnect optimization to ensure clock signal integrity while reducing crosstalk. Data consistency must be maintained during the output process, for example, by transmitting cell locations and clock constraints using standard exchange formats to avoid information loss. After the routing stage is completed, the chip enters the approval process, including final timing verification and physical rule checks, but the quality of clock tree synthesis is essentially determined at this point. The embedding process reflects the phased collaboration of the backend design, with clock tree synthesis acting as a crucial link, its output directly affecting routing resource allocation and final performance metrics.

[0127] Secondly, this invention provides a segmented clock tree synthesis system for integrated circuits oriented towards multiple operating modes, applied to the segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes as described above, including:

[0128] The data acquisition module is configured to acquire layout data of integrated circuit design, wherein the layout data includes a time-converged netlist;

[0129] The analysis and division module is configured to analyze multiple operating modes of the integrated circuit design based on the layout data, and divide the multiple operating modes into a first priority group and a second priority group according to the clock frequency, wherein the first priority group includes functional modes with high clock frequency, and the second priority group includes test modes with low clock frequency.

[0130] The first synthesis processing module is configured to perform a first segment clock tree synthesis on the first priority group to obtain a first clock tree network. The first segment clock tree synthesis includes creating a first clock synthesis specification file and setting first clock co-optimization parameters. After completing the first segment clock tree synthesis, the first clock tree network is fixed.

[0131] The second synthesis processing module is configured to perform a second segment clock tree synthesis on the second priority group to obtain a second clock tree network. The second segment clock tree synthesis includes creating a second clock synthesis specification file and setting second clock co-optimization parameters. The second segment clock tree synthesis is performed on the basis of the fixed first clock tree network.

[0132] The verification output module is configured to verify timing convergence and clock tree power consumption after completing the synthesis of the second segment of the clock tree, so as to achieve timing convergence and reduce clock tree power consumption.

[0133] In the field of digital integrated circuit back-end design, clock tree synthesis under multiple operating modes faces significant challenges. Due to the order-of-magnitude difference in clock frequencies between functional and test modes, traditional unified optimization methods often construct the global clock network using the most stringent high-frequency timing standards. This results in low-frequency paths being excessively inserted into buffer cells, increasing unnecessary power consumption and area. Simultaneously, critical high-speed paths are lengthened due to global balance constraints, becoming timing convergence bottlenecks. This invention addresses this technical problem by proposing a segmented clock tree synthesis method. Through priority partitioning and step-by-step optimization, it achieves a synergistic improvement in timing and power consumption.

[0134] The specific implementation begins at the node where layout is complete and timing has initially converged. Designers acquire the layout data of the integrated circuit design, including the timing-converged netlist. Based on the netlist data, all operating modes are analyzed, and the clock domain and its clock frequency value for each mode are extracted. Priority groups are dynamically divided according to preset high-frequency and low-frequency thresholds. The high-frequency and low-frequency thresholds are set based on the process node and performance targets. For example, in advanced processes, the high-frequency threshold may be adjusted to the gigahertz level to classify high-frequency functional modes into the first priority group and low-frequency test modes into the second priority group. This division mechanism avoids rigid classification and allows for dynamic adjustment of the grouping granularity according to design requirements.

[0135] When performing the first segment of clock tree synthesis on the first priority group, a first clock synthesis specification file is created, and clock co-optimization parameters are set. The specification file defines clock tree structure constraints, while the optimization parameters are configured differently for different clock structure types. The clock structure types included in the first priority group are identified, such as high-frequency master clocks or low-frequency communication clocks. For high-frequency master clocks, a strict target skew range is configured, high-layer metal winding rules are adopted, and conductor width and spacing are set to multiples of standard values ​​to reduce interconnect delay. For low-frequency communication clocks, the target skew range is relatively relaxed, and winding rules focus on resource efficiency, reducing the number of buffer insertions. The synthesis operation is executed through the segmented synthesis instruction set in the clock tree synthesis tool, such as using the create specification file instruction and the set parameter instruction to trigger clock tree construction. After synthesis, the first clock tree network is fixed, and the mode switching multiplexer for the priority group is located. The clock input port attribute corresponding to the second priority group in the multiplexer is set to the stop propagation attribute to block test clock signal interference and maintain high-frequency path stability.

[0136] Based on the fixed network, a second-stage clock tree synthesis is performed. A second clock synthesis specification file is created for the second priority group, and second clock co-optimization parameters are set. The average insertion delay of the first priority group clock signal propagating from the first input port of the mode switching multiplexer to the clock pin of the timing unit is calculated. This delay is configured as a port delay attribute to the clock input port of the second priority group in the multiplexer to maintain timing consistency under multi-mode switching. A more lenient target skew range and routing rules are configured globally for the second priority group. The skew range allows for greater tolerance, and the routing rules use high-layer metal, with width and spacing set as multiples of standard values ​​to balance signal integrity and resource consumption. During synthesis, if a special clock structure is detected, such as a target clock structure including a frequency divider register and multiple-stage multiplexers, refer to... Figure 2 The diagram shows that the clock ignore attribute of the test clock input port of the multi-stage multiplexer is commented out in the specification file, and the balance optimization is activated to avoid excessive skew in the test mode.

[0137] After completing the two-stage synthesis, timing convergence and clock tree power consumption are verified. Static timing analysis tools are used to check clock path skew and delay, and power analysis tools are used to evaluate dynamic power consumption. If timing convergence is not achieved or power consumption does not meet expectations, adjustment instructions are generated to iteratively correct the constraints or co-optimization parameters in the first clock synthesis specification file. For example, the skew target or routing rules are reset, and the segmented synthesis is re-executed using the corrected parameters until timing convergence and power consumption optimization are achieved. After successful verification, data is output to the routing stage for subsequent physical implementation, embedding into the standard back-end design flow. In the mode switching multiplexer processing, refer to... Figure 3 The connection diagram shown requires dynamic verification of port attribute configurations in conjunction with layout data to prevent clock domain conflicts.

[0138] This method reduces global balance constraint conflicts through segmented optimization. However, in practical applications, its effectiveness is affected by the placement quality threshold setting and may require multiple iterations. Designers need to fine-tune parameters according to the characteristics of the process library and the design scale. For example, in complex clock topologies, skew control needs to be combined with noise analysis. Overall, segmented clock tree synthesis improves the timing quality of high-frequency paths in multi-operating-mode scenarios while controlling the power consumption of low-frequency paths, making it suitable for high-performance integrated circuit design.

[0139] This invention addresses the issue of significant clock frequency differences across multiple operating modes by introducing a segmented clock tree synthesis method. It abandons the traditional unified optimization strategy and instead employs a clock frequency-based priority grouping mechanism. The solution first acquires the layout data of the integrated circuit design, including the timing-converged netlist. Then, it analyzes the clock domain and its frequency values ​​for all operating modes, dynamically assigning high-frequency functional modes to the first priority group and low-frequency test modes to the second priority group. This division sets thresholds based on process nodes and performance targets, avoiding rigid classification and ensuring that optimization resources are focused on timing-sensitive paths.

[0140] The segmented synthesis process begins with synthesizing the first segment of the clock tree for the first priority group, creating a dedicated clock synthesis specification file, and setting clock co-optimization parameters. For the high-frequency master clock structure, a strict target skew range is configured, and a winding rule using high-layer metal is adopted to reduce interconnect delay; for low-frequency communication clocks, the skew constraint is relaxed to optimize resource efficiency. After synthesis, the first clock tree network is fixed, and the multiplexer is switched via positioning mode to set the clock input port attribute corresponding to the second priority group to the stop propagation attribute, blocking test clock signal interference and maintaining high-frequency path stability.

[0141] Based on the fixed network, a second segment of clock tree synthesis is performed. An independent specification file is created for the second priority group, and co-optimization parameters are set. The average insertion delay of the first priority group clock propagation from the multiplexer input port to the timing unit is calculated, and this delay is configured as a port attribute for the clock input ports of the second priority group to maintain timing consistency under multi-mode switching. A relatively lenient target skew range and routing rules are configured globally for the second priority group to reduce the number of buffer insertions and control power consumption. When a special clock structure containing a divider register and multiple-stage multiplexers is detected, the scheme activates balance optimization by annotating the clock ignore attribute of the test clock input port to avoid skew anomalies.

[0142] After completing the two synthesis stages, timing convergence and clock tree power consumption are verified. If the expected results are not achieved, adjustment instructions are generated to iteratively correct constraints or optimize parameters, and synthesis is re-executed until convergence is achieved. The solution reduces global balance constraint conflicts through priority isolation and step-by-step optimization, ensuring that high-frequency paths receive strict timing processing first, while low-frequency paths avoid over-optimization. This effectively alleviates the timing convergence pressure on critical high-speed clock paths and reduces unnecessary power consumption. This invention's flow is embedded in the back-end design of digital integrated circuits, achieving continuity in physical implementation from post-placement node output to the routing stage.

Claims

1. A segmented clock tree synthesis method for integrated circuits with multiple operating modes, characterized in that, include: Step 1: Obtain the layout data of the integrated circuit design, which includes a timing-converged netlist; Step 2: Based on the layout data, analyze multiple operating modes of the integrated circuit design, and divide the multiple operating modes into a first priority group and a second priority group according to the clock frequency. The first priority group includes functional modes with high clock frequency, and the second priority group includes test modes with low clock frequency. Step 3: Perform a first segment clock tree synthesis on the first priority group to obtain a first clock tree network. The first segment clock tree synthesis includes creating a first clock synthesis specification file and setting first clock co-optimization parameters. After completing the synthesis of the first clock tree segment, fix the first clock tree network; Step 4: Perform a second clock tree synthesis on the second priority group to obtain a second clock tree network. The second clock tree synthesis includes creating a second clock synthesis specification file and setting second clock co-optimization parameters. The second clock tree synthesis is performed on the basis of the fixed first clock tree network. Step 5: After completing the synthesis of the second segment of the clock tree, verify the timing convergence and clock tree power consumption, so that the timing convergence is achieved and the clock tree power consumption is reduced.

2. The segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes according to claim 1, characterized in that, The step of dividing the multiple operating modes into a first priority group and a second priority group based on clock frequency includes: Extract the clock domain and its corresponding clock frequency value under the multiple working modes; The working mode of the clock domain whose clock frequency value exceeds the preset high frequency threshold is dynamically assigned to the first priority group; The operating modes of clock domains whose clock frequency values ​​are lower than or equal to a preset low-frequency threshold are dynamically assigned to the second priority group. The preset high-frequency threshold and the preset low-frequency threshold are set according to the process node and performance target of the integrated circuit design.

3. The segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes according to claim 2, characterized in that, The setting of the first clock coordination optimization parameters includes: Identify the clock structure types included in the first priority group; In response to the identification of the clock structure of the high-frequency master clock, a first target skew range and a first winding rule are configured for the corresponding clock tree. The first target skew range is 30ps to 100ps, and the first winding rule uses high-layer metal with a width twice the standard width and a spacing three times the standard spacing. In response to the identification of a low-frequency communication clock structure, a second target skew range and a second winding rule are configured for the corresponding clock tree. The second target skew range is 100ps to 200ps, and the second winding rule uses high-layer metal with a width twice the standard width and a spacing twice the standard spacing.

4. The segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes according to claim 3, characterized in that, The fixed first clock tree network includes: Position the mode switching multiplexer that connects the first priority group and the second priority group; Set the clock input port attribute corresponding to the second priority group in the mode switching multiplexer to the stop propagation attribute; When the stop propagation attribute is set, the clock signal of the second priority group is blocked at the clock input port of the mode switching multiplexer during the second segment clock tree synthesis.

5. The segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes according to claim 4, characterized in that, The setting of the second clock coordination optimization parameters includes: Based on the fixed first clock tree network, the average insertion delay of the clock signal of the first priority group propagating from the first input port of the mode switching multiplexer to the clock pin of the timing unit is calculated. The average insertion delay is configured as a port delay attribute and assigned to the clock input port in the mode switching multiplexer corresponding to the second priority group. Configure a third target skew range and a third winding rule globally for the clock tree of the second priority group. The third target skew range is 100ps to 250ps. The third winding rule uses high-layer metal and has a width twice the standard width and a spacing twice the standard spacing.

6. The segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes according to claim 1, characterized in that, The creation of the first clock synthesis specification file includes: Detect whether the clock structure of the integrated circuit design contains a target clock structure including a frequency divider register and a multi-stage multiplexer; In response to the detection of the target clock structure, a comment operation is performed on the clock ignore attribute of the test clock input port in the multi-level multiplexer in the first clock synthesis specification file; The annotation operation is used to activate the balance optimization of the test clock input port in subsequent clock tree synthesis.

7. The segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes according to claim 1, characterized in that, Step 5 further includes: When the timing fails to converge or the clock tree power consumption does not reach the expected target, an adjustment instruction is generated; Based on the adjustment instructions, at least one of the constraints in the first clock synthesis specification file or the first clock co-optimization parameters is iteratively modified. Using the modified constraints or the first clock co-optimization parameters, re-execute the first clock tree synthesis and the second clock tree synthesis until timing convergence and clock tree power consumption reaches the expected target.

8. The segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes according to claim 1, characterized in that, The first segment clock tree synthesis of the first priority group and the second segment clock tree synthesis of the second priority group are performed by the segmented synthesis instruction set in the clock tree synthesis tool; The segmented synthesis instruction set includes: a first instruction for creating a clock synthesis specification file, a second instruction for setting clock co-optimization parameters, and a third instruction for triggering segmented clock tree synthesis operations.

9. The segmented clock tree synthesis method for integrated circuits oriented towards multiple operating modes according to claim 1, characterized in that, Also includes: The embedded digital integrated circuit back-end design flow includes the layout data source being the node where the layout is completed and the timing is initially converged, the node where the timing convergence and clock tree power consumption are verified, and the output to the winding stage for subsequent physical implementation.

10. A segmented clock tree synthesis system for integrated circuits oriented to multiple operating modes, applied to the segmented clock tree synthesis method for integrated circuits oriented to multiple operating modes as described in any one of claims 1 to 9, characterized in that, include: The data acquisition module is configured to acquire layout data of integrated circuit design, wherein the layout data includes a time-converged netlist; The analysis and division module is configured to analyze multiple operating modes of the integrated circuit design based on the layout data, and divide the multiple operating modes into a first priority group and a second priority group according to the clock frequency, wherein the first priority group includes functional modes with high clock frequency, and the second priority group includes test modes with low clock frequency. The first synthesis processing module is configured to perform a first segment clock tree synthesis on the first priority group to obtain a first clock tree network. The first segment clock tree synthesis includes creating a first clock synthesis specification file and setting first clock co-optimization parameters. After completing the first segment clock tree synthesis, the first clock tree network is fixed. The second synthesis processing module is configured to perform a second segment clock tree synthesis on the second priority group to obtain a second clock tree network. The second segment clock tree synthesis includes creating a second clock synthesis specification file and setting second clock co-optimization parameters. The second segment clock tree synthesis is performed on the basis of the fixed first clock tree network. The verification output module is configured to verify timing convergence and clock tree power consumption after completing the synthesis of the second segment of the clock tree, so as to achieve timing convergence and reduce clock tree power consumption.

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