Clock switching circuit
By introducing a crystal oscillator failure detection module and a clock synchronization module into the clock switching circuit, the problem of clock glitches caused by crystal oscillator failure is solved, and the system is able to switch stably to the RC clock, ensuring the normal operation of the system.
Patent Information
- Application Number
- CN202311716995.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-12-09
- Publication Date
- 2026-01-06
AI Technical Summary
Existing clock switching circuits are prone to generating glitches when the crystal oscillator fails, leading to system instability and inability to function properly.
A clock switching circuit was designed, including a crystal oscillator failure detection module, a clock gating module, and a clock synchronization module. By using low-pass type clock gating and clock synchronization, it is ensured that no glitches are generated when switching to the internal RC clock in the event of crystal failure.
This effectively avoids clock glitches when the crystal oscillator fails, ensuring normal system operation and improving system stability and reliability.
Smart Images
Figure CN121283377A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to chip digital circuit design technology, and in particular to a clock switching circuit. Background Technology
[0002] If a crystal oscillator is stored for too long, or if its internal space is not clean enough, small water droplets or impurities can easily adhere to its surface. Interference can also cause the crystal oscillator to become unstable or stop working; this is called crystal oscillator failure. The procedure for detecting crystal oscillator failure in a chip is as follows:
[0003] 1) The hardware switches to an internal safety clock, allowing the system to continue functioning normally.
[0004] 2) Turn off the crystal oscillator analog circuit.
[0005] 3) Generate an interrupt notification to the CPU for processing.
[0006] Because a crystal oscillator failure can cause the clock to stop high or low, or become unstable, many current practices use a multiplexer (MUX) to switch the clock direction. When the crystal oscillator fails, the MUX selects the chip's internal RC clock, such as... Figure 1 As shown. However, when the crystal oscillator fails and the output is an unstable clock, switching to an RC clock will produce glitches in the switched clock, such as... Figure 2 As shown. Summary of the Invention
[0007] The technical problem to be solved by the present invention is to provide a clock switching circuit that can ensure that no glitches occur when the crystal oscillator fails and switches to the internal RC clock, so that the system can work normally.
[0008] To solve the above-mentioned technical problems, the present invention provides a clock switching circuit, which includes a crystal oscillator, a clock gating system, a multiplexer, a clock synchronization module, and a crystal oscillator failure detection module.
[0009] The crystal oscillator failure detection module is used to output a crystal oscillator failure signal. When the crystal oscillator fails, the crystal oscillator failure signal is high level; otherwise, the crystal oscillator failure signal is low level.
[0010] The clock gate has one input connected to the crystal clock output from the crystal oscillator, and the other input connected to the output of the first inverter U1. Its output is connected to the 0th input of the multiplexer.
[0011] When the output of the first inverter U1 is low, the clock gate output remains low.
[0012] When the output of the first inverter U1 is high, the output of the clock gate changes with the crystal oscillator clock.
[0013] The clock synchronization module has one input terminal connected to the internal RC clock of the chip, another input terminal connected to the crystal oscillator failure signal, and its output terminal connected to the selection terminal of the multiplexer.
[0014] The clock synchronization module outputs a low level when the crystal oscillator failure signal is low; and outputs a high level when the first falling edge of the internal RC clock occurs after the crystal oscillator failure signal changes from low to high.
[0015] The multiplexer has its first input terminal connected to the internal RC clock of the chip, and its output terminal outputs the switched clock.
[0016] When the clock synchronization module outputs a low level, the output of the multiplexer is the same as its 0th input.
[0017] When the clock synchronization module outputs a high level, the output of the multiplexer is the same as its first input.
[0018] Preferably, the clock synchronization module synchronizes the crystal oscillator failure signal with the internal RC clock of the chip for 1.5 beats and then outputs it to the selection terminal of the multiplexer.
[0019] Ideally, the crystal oscillator should fail when the clock stops oscillating or becomes unstable.
[0020] Preferably, the crystal oscillator clock stop includes two states: the crystal oscillator clock remains at a low level and the crystal oscillator clock remains at a high level.
[0021] Preferably, the clock synchronization module includes a first edge-triggered D flip-flop, a second edge-triggered D flip-flop, and a second inverter U2;
[0022] The first edge-triggered D flip-flop has its CP terminal connected to one input terminal of the clock synchronization module, its D terminal connected to the other input terminal of the clock synchronization module, and its Q terminal connected to the D terminal of the second edge-triggered D flip-flop.
[0023] The second inverter U2 has its input terminal connected to one input terminal of the clock synchronization module, and its output terminal connected to the CP terminal of the second edge-triggered D flip-flop.
[0024] The second edge-triggered D flip-flop has its Q terminal serving as the output of the clock synchronization module.
[0025] Preferably, the D flip-flop is an integrated flip-flop or a flip-flop composed of gate circuits.
[0026] Preferably, the first inverter U1 and the second inverter U2 are TTL NOT gates or CMOS inverters.
[0027] In the clock switching circuit of this invention, after the crystal oscillator failure detection module detects a crystal oscillator failure, it performs low-pass clock gating on the crystal oscillator clock using an inverted crystal oscillator failure signal. This ensures that the clock gating signal stops low, preventing the crystal oscillator clock from flipping after a failure. When the crystal oscillator failure signal is low, the clock synchronization module outputs a low level; when the crystal oscillator failure signal changes from low to high, the clock synchronization module outputs a high level when the first falling edge of the internal RC clock appears. The falling edge of the clock synchronization module's output signal is later than the falling edge of the internal RC clock but earlier than the next rising edge. In static timing analysis (STA), a timing check is performed on the multiplexer (MUX) selection terminal (the clock synchronization module's output signal) and the first input terminal (the internal RC clock), thus ensuring that there are no glitches (e.g., when switching from a crystal oscillator failure to the internal RC clock). Figure 4 , Figure 5 , Figure 6 and Figure 7 (As shown), this enables the system to function properly. Attached Figure Description
[0028] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 It is a common clock switching circuit structure;
[0030] Figure 2 This is a timing diagram of a common clock switching circuit;
[0031] Figure 3 This is a schematic diagram of an embodiment of the clock switching circuit of the present invention;
[0032] Figure 4 This is a timing diagram of a clock switching circuit embodiment of the present invention where crystal oscillator clock frequency instability causes crystal oscillator failure at a low level of the crystal oscillator clock.
[0033] Figure 5 This is a timing diagram of a clock switching circuit embodiment of the present invention where crystal oscillator failure occurs at the high level of the crystal oscillator clock due to unstable crystal oscillator clock frequency.
[0034] Figure 6This is a timing diagram of a clock switching circuit embodiment of the present invention where crystal oscillator failure occurs at the high level of the crystal clock due to crystal oscillator oscillation stoppage.
[0035] Figure 7 This is a timing diagram of a clock switching circuit embodiment of the present invention, showing the crystal oscillator failure caused by crystal oscillator oscillation stopping at a low level of the crystal oscillator clock. Detailed Implementation
[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0037] The terms "first," "second," and similar words used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Words such as "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are used only to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0038] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0039] Example 1
[0040] like Figure 3 As shown, a clock switching circuit includes a crystal oscillator, a clock gating, a multiplexer (MUX), a clock synchronization module, and a crystal oscillator failure detection module;
[0041] The crystal oscillator failure detection module is used to output a crystal oscillator failure signal. When the crystal oscillator fails, the crystal oscillator failure signal is high level; otherwise, the crystal oscillator failure signal is low level.
[0042] The clock gating has one input connected to the crystal clock output from the crystal oscillator, and the other input connected to the output of the first inverter U1. Its output is connected to the 0th input of the multiplexer (MUX).
[0043] When the output of the first inverter U1 is low, the output of the clock gating remains low.
[0044] When the output of the first inverter U1 is high, the output of the clock gating changes with the crystal oscillator clock.
[0045] The clock synchronization module has one input terminal connected to the internal RC clock of the chip, another input terminal connected to the crystal oscillator failure signal, and its output terminal connected to the selection terminal of the multiplexer (MUX).
[0046] The clock synchronization module outputs a low level when the crystal oscillator failure signal is low; and outputs a high level when the first falling edge of the internal RC clock occurs after the crystal oscillator failure signal changes from low to high.
[0047] The multiplexer (MUX) has its first input connected to the internal RC clock of the chip, and its output outputs the switched clock.
[0048] When the clock synchronization module outputs a low level, the output of the multiplexer (MUX) is the same as its 0th input.
[0049] When the clock synchronization module outputs a high level, the output of the multiplexer (MUX) is the same as its first input.
[0050] In the clock switching circuit of Example 1, after the crystal oscillator failure detection module detects a crystal oscillator failure, it performs low-pass clock gating on the crystal oscillator clock using an inverted crystal oscillator failure signal. This prevents the gated crystal oscillator clock from flipping. When the crystal oscillator failure signal is low, the clock synchronization module outputs a low level; when the crystal oscillator failure signal changes from low to high, the clock synchronization module outputs a high level when the first falling edge of the internal RC clock appears. The falling edge of the clock synchronization module's output signal is later than the falling edge of the internal RC clock but earlier than the next rising edge. In STA (static timing analysis), timing checks are performed on the multiplexer (MUX) selection terminal (the output signal of the clock synchronization module) and the first input terminal (the internal RC clock), thus ensuring that there are no glitches (such as...) when switching from the crystal oscillator failure to the internal RC clock. Figure 4 , Figure 5 , Figure 6 and Figure 7 (As shown), this enables the system to function properly.
[0051] Example 2
[0052] Based on the clock switching circuit of Embodiment 1, the clock synchronization module outputs the crystal oscillator failure signal to the selection terminal of the multiplexer (MUX) after synchronizing it with the internal RC clock of the chip for 1.5 beats.
[0053] Ideally, the crystal oscillator should fail when the crystal clock stops oscillating or becomes unstable (the rate of change of the crystal signal frequency exceeds a set value, such as 0.01).
[0054] Preferably, the crystal oscillator clock stop includes two states: stop low (the crystal oscillator clock remains at a low level) and stop high (the crystal oscillator clock remains at a high level).
[0055] In the clock switching circuit of Embodiment 2, the clock synchronization module synchronizes the crystal oscillator failure signal with the internal RC clock for 1.5 beats and then outputs it to the selection terminal of the multiplexer (MUX). The rising edge of the output signal of the clock synchronization module is later than the falling edge of the internal RC clock and earlier than the next rising edge. In STA (static timing analysis), a timing check is performed on the selection terminal of the multiplexer (MUX) (the crystal oscillator failure signal synchronized with the internal RC clock for 1.5 beats) and the first input terminal (the internal RC clock), thereby ensuring that there are no glitches when the crystal oscillator fails and switches to the internal RC clock (e.g., Figure 4 , Figure 5 , Figure 6 and Figure 7 (As shown).
[0056] Example 3
[0057] Based on the clock switching circuit of Embodiment 2, the clock synchronization module includes a first edge-triggered D flip-flop, a second edge-triggered D flip-flop, and a second inverter U2;
[0058] The first edge-triggered D flip-flop has its CP terminal connected to one input terminal of the clock synchronization module, its D terminal connected to the other input terminal of the clock synchronization module, and its Q terminal connected to the D terminal of the second edge-triggered D flip-flop.
[0059] The second inverter U2 has its input terminal connected to one input terminal of the clock synchronization module, and its output terminal connected to the CP terminal of the second edge-triggered D flip-flop.
[0060] The second edge-triggered D flip-flop has its Q terminal serving as the output of the clock synchronization module.
[0061] Preferably, the D flip-flop is an integrated flip-flop or a flip-flop composed of gate circuits.
[0062] Preferably, the first inverter U1 and the second inverter U2 are TTL NOT gates or CMOS inverters.
[0063] In the clock switching circuit of Embodiment 3, the first edge D flip-flop uses the rising edge and the second edge D flip-flop uses the falling edge. The crystal oscillator failure signal is synchronized with the internal RC clock for 1.5 beats and then output to the selection terminal of the multiplexer (MUX).
[0064] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A clock switching circuit, characterized by, It includes a crystal oscillator, a clock gating, a multiplexer, a clock synchronization module and a crystal oscillator failure detection module. The crystal oscillator failure detection module is configured to output a crystal oscillator failure signal, the crystal oscillator failure signal being high when the crystal oscillator fails, and the crystal oscillator failure signal being low otherwise. The clock gating has one input end connected to a crystal oscillator clock output by the crystal oscillator, another input end connected to an output end of a first inverter (U1), and an output end connected to a 0th input end of the multiplexer. When the output end of the first inverter (U1) is low, the output of the clock gating is maintained as low. When the output end of the first inverter (U1) is high, the output of the clock gating changes with the crystal oscillator clock. The clock synchronization module has one input end connected to an internal RC clock of a chip, another input end connected to the crystal oscillator failure signal, and an output end connected to a selection end of the multiplexer. When the crystal oscillator failure signal is low, the clock synchronization module outputs low; when the crystal oscillator failure signal changes from low to high, the clock synchronization module outputs high at a first falling edge of the internal RC clock of the chip. The multiplexer has a 1st input end connected to the internal RC clock of the chip, and an output end outputting a switched clock. When the output of the clock synchronization module is low, the output of the multiplexer is consistent with the 0th input end of the multiplexer. When the output of the clock synchronization module is high, the output of the multiplexer is consistent with the 1st input end of the multiplexer.
2. The clock switching circuit according to claim 1, wherein the clock synchronization module synchronizes the crystal oscillator failure signal with the internal RC clock for 1.5 beats and then outputs the crystal oscillator failure signal to the selection end of the multiplexer.
3. The clock switching circuit according to claim 1, wherein the crystal oscillator fails when the crystal oscillator clock stops or is unstable.
4. The clock switching circuit according to claim 1, wherein the crystal oscillator clock stopping includes two states of the crystal oscillator clock being maintained as low and the crystal oscillator clock being maintained as high.
5. The clock switching circuit according to claim 1, wherein the clock synchronization module includes a first edge D flip-flop, a second edge D flip-flop and a second inverter (U2). The first edge D flip-flop has a CP end connected to one input end of the clock synchronization module, a D end connected to another input end of the clock synchronization module, and a Q end connected to a D end of the second edge D flip-flop. The second inverter (U2) has an input end connected to one input end of the clock synchronization module, and an output end connected to a CP end of the second edge D flip-flop. The Q end of the second edge D flip-flop is used as an output end of the clock synchronization module.
6. The clock switching circuit according to claim 1, wherein the D flip-flop is an integrated flip-flop or a flip-flop composed of gate circuits.
7. The clock switching circuit according to claim 1, wherein the first inverter (U1) and the second inverter (U2) are TTL NOT gates or CMOS inverters.