Semiconductor element with vertical channel transistor and preparation method thereof

Abstract

The invention provides a semiconductor element and a preparation method thereof. The semiconductor device includes a bit line extending along a first direction; the first word line extends along a second direction and is arranged above the bit line; and a second word line extending along the second direction and disposed over the bit line. The semiconductor device also includes a first pillar structure overlapping the first word line and the second word line.

Description

[0001] Cross-referencing

[0002] This application claims priority to U.S. Patent Application No. 18 / 760,207 (i.e., priority date "July 1, 2024"), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device and a method for fabricating a semiconductor device. In particular, it relates to a semiconductor device having a vertical channel transistor. Background Technology

[0004] Dynamic Random Access Memory (DRAM) is a key component in modern computing, comprising multiple memory cells. Each memory cell includes a transistor and a capacitor, which work together to store and retrieve data. DRAM operates by manipulating word lines and bit lines to control the transistors, thereby facilitating the reading and writing of data to the memory cell.

[0005] To enhance DRAM efficiency and capacity, the size of a single memory cell has been significantly reduced. This size reduction, from a hexagonal feature size (6F)... 2 ) to square feature size (4F) 2 This reduced the footprint of DRAM cells and subsequently increased the integration density of multiple DRAM cells within a DRAM cell.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this disclosure. Summary of the Invention

[0007] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a bit line extending along a first direction; a first word line extending along a second direction and disposed above the bit line; and a second word line extending along the second direction and disposed above the bit line. The semiconductor device also includes a first pillar structure overlapping the first word line and the second word line.

[0008] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a bit line; and a first pillar structure disposed on the bit line and having a first surface and a second surface. The semiconductor device further includes a first word line connected to the first surface of the first pillar structure; and a second word line connected to the second surface of the first pillar structure.

[0009] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a bit line extending along a first direction; forming a first word line extending along a second direction and disposed above the bit line; and forming a second word line extending along the second direction and disposed above the bit line. The method further includes forming a pillar structure overlapping the first word line and the second word line.

[0010] By overlapping the vertical channel transistor with two word lines, the spacing between word lines can be reduced without affecting their width. This innovative design also allows for the selection of a memory cell using the two word lines, effectively preventing interference between word lines in different memory cells. Therefore, data retention time is extended, and the overall operational reliability of the semiconductor device is significantly enhanced.

[0011] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0012] A more complete understanding of this disclosure can be obtained by referring to the detailed description and claims. This disclosure should also be understood to be associated with the element numbers in the drawings, which represent similar elements throughout the description.

[0013] Figure 1A This is a top-view schematic diagram illustrating a portion of a semiconductor element according to some embodiments of this disclosure.

[0014] Figure 1B This is a top-view schematic diagram illustrating a portion of a semiconductor element according to some embodiments of this disclosure.

[0015] Figure 2A This is a top-view schematic diagram illustrating a portion of a semiconductor element according to some embodiments of this disclosure.

[0016] Figure 2B This is a cross-sectional schematic diagram illustrating semiconductor elements according to some embodiments of the present disclosure.

[0017] Figure 3A This is a top-view schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0018] Figure 3BThis is a top-view schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0019] Figure 3C This is a top-view schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0020] Figure 3D This is a top-view schematic diagram illustrating one or more stages of a method for fabricating a semiconductor element according to some embodiments of the present disclosure.

[0021] Figure 4 This is a flowchart illustrating a method for fabricating semiconductor elements according to some embodiments of this disclosure.

[0022] Explanation of reference numerals in the attached figures:

[0023] 1a: Semiconductor element

[0024] 1b: Semiconductor components

[0025] 2a: Semiconductor components

[0026] 10: Bit line

[0027] 11: Bitline

[0028] 12: Bit line

[0029] 20: Character Line

[0030] 20d: Dielectric layer

[0031] 20i: Gate dielectric

[0032] 21: Character Line

[0033] 21d: Dielectric layer

[0034] 21i: Gate dielectric

[0035] 22: Character Line

[0036] 23: Character Line

[0037] 23d: Dielectric layer

[0038] 30: Column structure

[0039] 31: Column Structure

[0040] 32: Column Structure

[0041] 33: Column Structure

[0042] 34: Column Structure

[0043] 35: Column Structure

[0044] 36: Column Structure

[0045] 37: Column Structure

[0046] 38: Column Structure

[0047] 40: Contact Area

[0048] 101: Surface

[0049] 102: Surface

[0050] 201: Surface

[0051] 202: Surface

[0052] 311: Surface

[0053] 312: Surface

[0054] 400: Preparation method

[0055] AA: Active Zone

[0056] A-A': section line

[0057] BL: Bitline

[0058] CA: Contact Area

[0059] S41~S45: Steps

[0060] WL: Character Line

[0061] X: First direction

[0062] Y: Second direction

[0063] Z: Third-party direction Detailed Implementation

[0064] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0065] It should be understood that although the terms first, second, third, etc., may be used herein to describe various elements, components, regions, layers, or sections, these elements, components, regions, layers, or sections are not limited by these terms. Rather, these terms are used only to distinguish one element, component, region, layer, or section from another region, layer, or section. Therefore, without departing from the teachings of the inventive concept of the present invention, the first element, component, region, layer, or section discussed below may be referred to as a second element, component, region, layer, or section.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular forms “a,” “an,” and “the” are intended to include multiple forms unless the context clearly indicates otherwise. It will be further understood that when the terms “comprises” and / or “comprising” are used in this specification, these terms specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups of the foregoing.

[0067] Figure 1A This is a top view schematic diagram illustrating a portion of a semiconductor element 1a according to some embodiments of the present disclosure.

[0068] In some embodiments, semiconductor element 1a may be disposed adjacent to a circuit. For example, semiconductor element 1a may be disposed adjacent to a memory element, such as a dynamic random access memory (DRAM) element or the like.

[0069] Please refer to Figure 1A Semiconductor element 1a may include multiple bit lines BL extending along a first direction X and multiple word lines WL extending along a second direction Y intersecting the bit lines BL. The second direction Y may be different from the first direction X. The second direction Y may be substantially perpendicular to the first direction X. Both the bit lines BL and the word lines WL may be striped or have a striped structure. The bit lines BL and the word lines WL form or define multiple grids.

[0070] Semiconductor element 1a may include a plurality of active regions AA defined by isolation regions (not shown) of, for example, a shallow trench isolation (STI) structure. The active regions AA may be disposed diagonally relative to the extension direction of bit line BL or word line WL (e.g., a first direction X or a second direction Y).

[0071] Semiconductor element 1a may include a plurality of contact regions CA. Each contact region CA may be formed in a grid defined by bit lines BL and word lines WL. The contact regions CA may be electrically connected to a memory element. In some embodiments, the memory element may be a capacitor. In other embodiments, the memory element may be a variable resistance pattern capable of switching between two resistance states by an electrical pulse applied to the memory element. For example, the memory element may include a phase change material capable of changing its crystalline state according to the amount of current, such as a perovskite compound, transition metal oxide, magnetic material, ferromagnetic material, or antiferromagnetic material.

[0072] In some embodiments, bit lines BL and word lines WL can each have a width of 1F (where F is the minimum lithographic feature size). Bit lines BL can be spaced 1F apart. Word lines WL can be spaced 1F apart. Therefore, Figure 1A The area of ​​a single memory cell in the memory is approximately 2F × 3F = 6F. 2 .

[0073] Figure 1B This is a top view schematic diagram illustrating a portion of a semiconductor element 1b according to some embodiments of this disclosure.

[0074] The contact area CA of semiconductor element 1b can be located at the intersection of bit line BL and word line WL. Therefore, Figure 1B The area of ​​a single memory cell in the memory is approximately 2F × 2F = 4F. 2 .

[0075] The development of memory array layouts has led to a reduction in the size of a single memory cell, from a hexagonal feature size (6F) 2 Transition to square feature size (4F) 2 This reduction is primarily attributed to the decrease in the minimum feature size F and the coefficient α, which decreases with each new generation of products. 6F 2 and 4F 2 The main difference between the layouts lies in the implementation of the unit structure. 4F 2 The layout uses vertical pillar transistors, while 6F 2 The layout employs a buried channel array transistor. It features 4F transistors with vertical pillars. 2 Architecture is a promising approach to achieving cost-effective and scalable DRAM chips.

[0076] Figure 2A This is a top view schematic diagram illustrating a portion of a semiconductor element 2a according to some embodiments of this disclosure.

[0077] Semiconductor element 2a may include a plurality of bit lines 10, 11 and 12 extending along a first direction X. Semiconductor element 2a may include a plurality of word lines 20, 21, 22 and 23 extending along a second direction Y intersecting bit lines 10, 11 and 12.

[0078] Bit lines 10, 11, and 12 may be disposed above a substrate (not shown in the figure). In some embodiments, bit lines 10, 11, and 12 may be disposed within the substrate.

[0079] The substrate may include a semiconductor substrate. In some embodiments, for example, the semiconductor material of the substrate may include, for example, silicon (e.g., monocrystalline silicon, polycrystalline silicon, and amorphous silicon), germanium, gallium, and indium. In some embodiments, the semiconductor material of the substrate may include a compound semiconductor, and the compound semiconductor includes silicon germanium, silicon carbide, silicon germanium carbide, gallium arsenide, gallium phosphide, indium phosphide, indium antimonide, or other group IV-IV, III-V, or II-VI semiconductor materials.

[0080] In some embodiments, the substrate may include a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, a multilayer substrate, or a gradient substrate. For example, an SOI substrate may include a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer may be disposed on the substrate, typically a silicon or glass substrate. In some embodiments, the substrate may be a wafer, such as a silicon wafer. The substrate may be doped (e.g., with P-type or N-type dopants) or undoped.

[0081] Character lines 20, 21, 22 and 23 may include any suitable material, such as tungsten, ruthenium, cobalt, titanium, tantalum, copper, aluminum, gold, titanium nitride, tantalum nitride, tungsten nitride (W2N, WN, WN2), the like or combinations thereof.

[0082] Semiconductor element 2a may include a plurality of pillar structures 30, 31, 32, 33, 34, 35, 36, 37, and 38. Each of pillar structures 30, 31, 32, 33, 34, 35, 36, 37, and 38 may be or include a channel region of a vertical channel transistor. Pillar structures 30, 31, 32, 33, 34, 35, 36, 37, and 38 may be disposed above bit lines 10, 11, and 12.

[0083] The pillar structures 30, 31, 32, 33, 34, 35, 36, 37 and 38 may comprise any suitable material, such as indium gallium zinc oxide (IGZO), indium aluminum zinc oxide (IAZO), polycrystalline silicon, the like or combinations thereof.

[0084] Column structures 30, 31, 32, 33, and 34 may be disposed along bit line 10. Column structures 30, 31, 32, 33, and 34 may be alternately disposed on opposite sides of bit line 10 along a first direction X. For example, bit line 10 may include a surface 101 and a surface 102 opposite to surface 101. Column structures 30, 31, 32, 33, and 34 may alternately overlap with surfaces 101 and 102 of bit line 10 along the first direction X.

[0085] Column structures 30, 31, 35, 36, 37, and 38 may be arranged along character line 20. Column structures 30, 31, 35, 36, 37, and 38 may be alternately arranged on opposite sides of character line 20 along a second direction Y. For example, character line 20 may include a surface 201 and a surface 202 opposite to surface 101. Column structures 30, 31, 35, 36, 37, and 38 may alternately overlap with surfaces 201 and 202 of character line 20 along the second direction Y.

[0086] Some column structures can overlap with two adjacent character lines 20, 21, 22, and 23. For example, column structures 31, 36, and 38 can each overlap with character lines 20 and 21. For example, column structures 31, 36, and 38 can each be positioned between character lines 20 and 21. For example, column structure 32 can overlap with both character lines 21 and 22. For example, column structure 33 can overlap with both character lines 22 and 23.

[0087] Semiconductor element 2a may include a plurality of contact regions 40 disposed above the pillar structure. Each contact region 40 may include a conductive material. Each contact region 40 may include a doped semiconductor material (e.g., doped silicon), a metal (e.g., tungsten, titanium, and tantalum), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, and tungsten nitride), and a metal-semiconductor compound (e.g., a metal silicide). The contact regions 40 may overlap perpendicularly with the pillar structure. The contact regions 40 may be electrically connected to the pillar structure.

[0088] Figure 2B This is a cross-sectional schematic diagram illustrating some embodiments of the present disclosure along... Figure 2A The cross-section of semiconductor element 2a is shown by the cross-section A-A'.

[0089] Column structures 31 and 33 can be positioned above bit line 10. Column structures 31 and 33 can be spaced apart from each other. Both column structures 31 and 33 can be electrically connected to contact area 40.

[0090] Column structures 31 and 33 may extend in a third direction Z. The third direction Z may differ from the first direction X. The third direction Z may be substantially perpendicular to the first direction X.

[0091] The pillar structure 31 can be connected to character lines 20 and 21. Character lines 20 and 21 can be separated from each other by the pillar structure 31. For example, the pillar structure 31 may include a surface 311 and a surface 312 opposite to surface 101. Surfaces 311 and 312 may be substantially perpendicular to character line 10.

[0092] Character line 20 can be disposed above (or connected to) the surface 311 of pillar structure 31 via a gate dielectric 20i. Character line 21 can be disposed above (or connected to) the surface 312 of pillar structure 31 via a gate dielectric 21i. For example, gate dielectrics 20i and 21i may include silicon oxide, silicon nitride, and / or silicon oxynitride. In some embodiments, the fabrication techniques of gate dielectrics 20i and 21i may include any suitable process, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or physical vapor deposition (PVD), thermal growth, or chemical growth.

[0093] Character lines 20 and 21 may not overlap each other along the first direction X. For example, character lines 20 and 21 may be set at different heights relative to bit line 10.

[0094] For example, character line 20 can be positioned above the lower part of column structure 31. For example, character line 20 can be positioned closer to bit line 10 than character line 21. For example, character line 21 can be positioned above the upper part of column structure 31. For example, character line 21 can be positioned closer to contact area 40 than character line 20.

[0095] The word lines and bit lines of semiconductor element 2a can control the operation of semiconductor element 2a. For example, at the start of a read or write operation, a voltage corresponding to a high data value can be applied to bit line 10, and bit line 10 can correspond to multiple memory cells (including pillar structures 30, 31, 32, 33, and 34). Then, a memory cell can be selected by two adjacent word lines 20, 21, 22, and 23. For example, a memory cell can be selected by turning on pillar structure 31 using word lines 20 and 21. Therefore, word lines 20 and 21 can be configured to turn on pillar structure 31. The memory cell containing pillar structure 31 can be selected by bit line 10 and word lines 20 and 21.

[0096] Similarly, pillar structure 33 can be connected to word lines 22 and 23. Word lines 22 and 23 can be configured to conduct pillar structure 33. Memory cells containing pillar structure 33 can be selected via bit line 10 and word lines 22 and 23. Dielectric layers 20d, 21d, and 23d can be disposed above word lines 20, 21, 22, and 23. Dielectric layer 20d can be disposed above word line 20 and can be configured to insulate word line 20 from other word lines. Dielectric layers 20d, 21d, and 23d may include an oxide layer.

[0097] As DRAM devices become increasingly integrated, it is necessary to reduce word lines and bit lines to expand the process window and mitigate risks such as current shortages and capacitive coupling. However, this reduction leads to increased resistance in word lines and bit lines, posing a challenge to achieving high-speed performance in semiconductor devices.

[0098] Overlapping the vertical channel transistor with two word lines reduces the spacing between word lines without affecting their width. This innovative design also allows selection of a memory cell via the two word lines, effectively preventing interference between word lines in different memory cells. Therefore, data retention time is extended, and the overall operational reliability of the semiconductor device is significantly enhanced.

[0099] Figure 3A , Figure 3B , Figure 3C , Figure 3D This disclosure illustrates multiple stages of a method for fabricating a semiconductor device according to some embodiments. To better understand various aspects of this disclosure, at least some of the figures have been simplified. In some embodiments, Figure 2A Semiconductor element 2a in the above can be referenced below. Figure 3A , Figure 3B , Figure 3C and Figure 3D The described operations are used to manufacture it.

[0100] like Figure 3A As shown, the fabrication method may include forming a plurality of bit lines 10, 11, and 12 extending along a first direction X and a plurality of word lines 20 and 22 extending along a second direction Y intersecting the bit lines 10 and 11. The word lines and bit lines may form or define a plurality of grids. The fabrication techniques for the word lines and bit lines may include any suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or damascene processes. In some embodiments, a dielectric layer (such as...) Figure 2B The dielectric layers 20d, 21d and 23d in the middle can be set above the character lines 20 and 22.

[0101] like Figure 3BAs shown, the fabrication method may include forming a plurality of character lines 21 and 23 extending in a second direction Y that intersects with character lines 10, 11, and 12. In some embodiments, character lines 20, 21, 22, and 23 may be formed in the same operation. In some embodiments, character lines 20, 21, 22, and 23 may be formed in different operations.

[0102] like Figure 3C As shown, the fabrication method may include forming a plurality of pillar structures 30, 31, 32, 33, 34, 35, 36, 37, and 38. In some embodiments, the fabrication techniques for pillar structures 30, 31, 32, 33, 34, 35, 36, 37, and 38 may include any suitable process. For example, the dielectric layer between character lines 20, 21, 22, and 23 may be removed by any suitable etching operation, such as a wet etching operation. The material of the pillar structure may then be disposed in the space between character lines 20, 21, 22, and 23.

[0103] In some embodiments, pillar structures 30, 31, 32, 33, 34, 35, 36, 37, and 38 may be formed prior to the operations forming character lines 20, 21, 22, and 23. For example, the fabrication technique for the pillar structures may include performing an etching operation on a silicon substrate. For example, the fabrication technique for the pillar structures may include epitaxial growth.

[0104] like Figure 3D As shown, the fabrication method may include forming a plurality of contact regions 40 above the pillar structures 30, 31, 32, 33, 34, 35, 36, 37 and 38. The fabrication techniques for the contact regions 40 may include any suitable process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD) or décor process.

[0105] Figure 4 This is a flowchart illustrating a method 400 for fabricating a semiconductor element according to some embodiments of this disclosure.

[0106] In some embodiments, the fabrication method 400 may include step S41 of forming a plurality of bit lines extending in a first direction. For example, such as Figure 3A As shown, the preparation method may include forming multiple bit lines 10, 11 and 12 extending along the first direction X.

[0107] In some embodiments, the fabrication method 400 may include step S42 of forming a first character line extending in a second direction. For example, such as Figure 3A As shown, the fabrication method may include forming multiple character lines 20 and 22 extending in a second direction Y that intersects with character lines 10, 11 and 12.

[0108] In some embodiments, the fabrication method 400 may include step S43 of forming a second character line extending in the second direction. For example, such as Figure 3B As shown, the fabrication method may include forming multiple character lines 21 and 23 extending in a second direction Y that intersects with character lines 10, 11 and 12.

[0109] In some embodiments, the fabrication method 400 may include step S44 of forming a pillar structure overlapping the first character line and the second character line. For example, such as Figure 3C As shown, the preparation method may include forming multiple column structures 30, 31, 32, 33, 34, 35, 36, 37 and 38.

[0110] In some embodiments, the fabrication method 400 may include step S45 of forming a contact area above the column structure. For example, such as Figure 3D As shown, the preparation method may include forming a plurality of contact areas 40 above the column structures 30, 31, 32, 33, 34, 35, 36, 37 and 38.

[0111] One embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a bit line extending along a first direction; a first word line extending along a second direction and disposed above the bit line; and a second word line extending along the second direction and disposed above the bit line. The semiconductor device also includes a first pillar structure overlapping the first word line and the second word line.

[0112] Another embodiment of this disclosure provides a semiconductor device. The semiconductor device includes a bit line; and a first pillar structure disposed on the bit line and having a first surface and a second surface. The semiconductor device further includes a first word line connected to the first surface of the first pillar structure; and a second word line connected to the second surface of the first pillar structure.

[0113] Another embodiment of this disclosure provides a method for fabricating a semiconductor device. The method includes forming a bit line extending along a first direction; forming a first word line extending along a second direction and disposed above the bit line; and forming a second word line extending along the second direction and disposed above the bit line. The method further includes forming a pillar structure overlapping the first word line and the second word line.

[0114] By overlapping the vertical channel transistor with two word lines, the spacing between word lines can be reduced without affecting their width. This innovative design also allows for the selection of a memory cell using the two word lines, effectively preventing interference between word lines in different memory cells. Therefore, data retention time is extended, and the overall operational reliability of the semiconductor device is significantly enhanced.

[0115] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be used to replace many of the processes described above.

[0116] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device, comprising: a bit line extending in a first direction; a first word line extending in a second direction and disposed above the bit line; a second word line extending in the second direction and disposed above the bit line; and a first pillar structure overlapping the first word line and the second word line.

2. The semiconductor device of claim 1, further comprising a plurality of pillar structures including the first pillar structure disposed in the first direction.

3. The semiconductor device of claim 2, wherein the plurality of pillar structures are alternately disposed on opposite sides of the bit line.

4. The semiconductor device of claim 2, wherein the plurality of pillar structures are alternately overlapping opposite sides of the bit line.

5. The semiconductor device of claim 1, further comprising a plurality of pillar structures including the first pillar structure disposed in the second direction.

6. The semiconductor device of claim 5, wherein the plurality of pillar structures are alternately disposed on opposite sides of the first word line.

7. The semiconductor device of claim 5, wherein the plurality of pillar structures are alternately overlapping opposite sides of the first word line.

8. The semiconductor device of claim 1, wherein the first pillar structure comprises a channel region of a vertical channel transistor.

9. The semiconductor device of claim 8, wherein the first word line and the second word line are configured to turn on the channel region of the vertical channel transistor.

10. The semiconductor device of claim 9, wherein the bit line, the first word line, and the second word line are configured to select a memory cell including the vertical channel transistor.

11. The semiconductor device of claim 1, wherein the first word line and the second word line are disposed at different heights relative to the bit line.

12. The semiconductor device of claim 1, further comprising a contact region disposed above the first pillar structure.

13. The semiconductor device of claim 1, wherein the first pillar structure is disposed above the bit line and between the first word line and the second word line.

14. The semiconductor device of claim 1, wherein the first pillar structure extends in a third direction. ​

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