Wafer level packaging structure and preparation method thereof

Abstract

The invention provides a wafer-level packaging structure and a preparation method thereof. The wafer-level packaging structure comprises an insulating layer, a chip arranged on the insulating layer, a plastic packaging layer wrapping the chip, and a rewiring layer, wherein the side surface of the plastic packaging layer and the interior of the insulating layer are provided with communicated gaps, and the rewiring layer extends into the gaps and is connected and conducted with the chip; the rewiring layer comprises a side surface connecting part formed in the gap and an L connecting part connected between the side surface connecting part and the chip; the chips are connected and conducted with an external circuit through the L connecting parts, and every two adjacent chips are connected and conducted through the side face connecting parts at the corresponding positions. According to the invention, multi-surface signal conduction of the chip can be realized, the packaging flexibility is improved, and the chip density is increased.

Description

TECHNICAL FIELD

[0001] The present application relates to the packaging technical field, more particularly, to a wafer level packaging structure and a preparation method thereof. BACKGROUND

[0002] Wafer Level Chip Scale Packaging (WLCSP) is different from the traditional chip packaging method, such as cutting and then packaging, which increases the volume of the original chip by at least 20%. The WLCSP technology is to package and test the whole wafer first, and then cut it into individual IC particles, so the volume after packaging is equal to the original size of the IC bare chip.

[0003] However, the packaging structure formed by the existing WLCSP technology can usually only realize single-sided signal output, and cannot realize multi-directional signal conduction, resulting in poor packaging flexibility, unable to improve the packaging density, and affecting the packaging and testing efficiency. SUMMARY

[0004] In view of the above problems, the purpose of the present application is to provide a wafer level packaging structure and a preparation method thereof, to solve the problems that the existing packaging structure cannot realize multi-directional signal conduction, resulting in poor packaging flexibility, affecting the packaging efficiency and packaging density, etc.

[0005] The wafer level packaging structure provided by the present application comprises an insulating layer, a chip arranged on the insulating layer, a plastic packaging layer arranged around the chip, and a redistribution layer; wherein, A communicating notch is arranged on the side of the plastic packaging layer and in the insulating layer, and the redistribution layer extends into the notch and is connected to the chip for conduction; The redistribution layer comprises a side connecting part formed in the notch and an L connecting part connecting the side connecting part and the chip; The chip is connected to the external circuit for conduction through the L connecting part, and the adjacent two chips are connected for conduction through the side connecting parts at the corresponding positions.

[0006] In addition, the optional technical solution is that the insulating layer comprises a first insulating layer and a second insulating layer arranged in sequence on one side of the chip, and a tin ball is arranged on the outer side of the second insulating layer; The tin ball is connected to the L connecting part for conduction through an under bump metallization layer.

[0007] In addition, the optional technical solution is that the insulating layer comprises at least one of a PI layer, a PET layer, a PEEK layer, an inorganic material layer, or a graphene composite material layer.

[0008] In addition, the rewiring layer comprises at least one electroplated metal layer.

[0009] In addition, the side connecting part is arranged on each side of the plastic encapsulation layer, and at least one side connecting part is arranged on each side.

[0010] In addition, the side connecting part is arranged on each side of the plastic encapsulation layer, and at least one side connecting part is arranged on each side.

[0011] In addition, the side connecting part is arranged on each side of the plastic encapsulation layer, and at least one side connecting part is arranged on each side.

[0012] In addition, the side connecting part is arranged on each side of the plastic encapsulation layer, and at least one side connecting part is arranged on each side. The single chips are arranged on the adapter carrier, and the chips are encapsulated by plastic encapsulation material to form a plastic encapsulation layer. The adapter carrier is removed, and an insulating medium is arranged on one side of the chip to form a first insulating layer. Laser drilling is performed on the first insulating layer to form a second gap. Exposure and development are performed on the first insulating layer to form a first gap on the first insulating layer, and the first gap and the second gap are connected. A metal layer is formed on one side of the first insulating layer, and photoresist is arranged on one side of the metal layer to perform exposure and development, and an initial pattern of the rewiring pattern is formed. Electroplating is performed on the basis of the initial pattern to form the rewiring layer, and the rewiring layer comprises an L connecting part arranged on one side of the first insulating layer and in the first gap, and a side connecting part arranged in the second gap. The photoresist is removed, and the metal layer in the area where the rewiring layer is not arranged is etched. An insulating medium is arranged on one side of the rewiring layer to form a second insulating layer.

[0013] In addition, after the second insulating layer is formed, the method further comprises: A bump under metal layer is arranged at the position corresponding to the L connecting part of the second insulating layer, and a tin ball is implanted in the bump under metal layer to perform reflow to form an overall packaging structure.

[0014] In addition, the method further comprises: The overall packaging structure is cut to expose the side connecting part from the plastic encapsulation layer to form a single packaging structure. The single package structure is packaged, and the single package structure is connected and conducted with the PCB through a tin ball, and two adjacent single package structures are connected and conducted through the side connecting part.

[0015] The wafer level package structure and the preparation method thereof provided by the application have the following advantages: the through holes are arranged in the side of the plastic package layer and the insulating layer, the re-wiring layer extends into the through holes and is connected and conducted with the chip, the re-wiring layer comprises the side connecting part formed in the through hole and the L connecting part connecting the side connecting part and the chip, the chip is connected and conducted with the external circuit through the L connecting part, two adjacent chips are connected and conducted through the side connecting part at the corresponding position, the special-shaped connecting part arranged around the chip can realize signal transmission in multiple directions, the chip is convenient to mount and the chip is connected and conducted with the chip or the external device, the overall structure is simple, and the package is more flexible and convenient.

[0016] To the accomplishment of the foregoing and related ends, one or more aspects of the application comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative aspects of the application. These aspects are indicative, however, of but a few of the various ways in which the principles of the application can be employed. Other aspects and advantages of the application will be apparent from the following detailed description of the application, as defined in the claims. BRIEF DESCRIPTION OF DRAWINGS

[0017] Other objects and results of the application will become more fully understood and appreciated only upon a reading of the following detailed description, with reference to the accompanying drawings. In the drawings: Figure 1 A single structure schematic diagram of a wafer level package structure according to an embodiment of the application; Figure 2 A multi-package structure schematic diagram of a wafer level package structure according to an embodiment of the application; Figure 3 A packaging principle of a wafer level package structure according to an embodiment of the application Figure 1 ; Figure 4 A packaging principle of a wafer level package structure according to an embodiment of the application Figure 1 ; Figure 5 A top view of a chip and a first insulating layer according to an embodiment of the application; Figure 6 A top view of a drilling position according to an embodiment of the application; Figure 7 A cutting path diagram of a wafer level package structure according to an embodiment of the application; Figure 8This is a flowchart of a method for fabricating a wafer-level packaging structure according to an embodiment of the present invention.

[0018] Reference numerals: Chip 1, Chip signal transmission port 11, Molding layer 2, Rewiring layer 3, Side connection 31, L-connection 32, First insulating layer 4, Solder ball 5, Second insulating layer 6, PCB 7, Adapter carrier 8, Second notch 91, First notch 92, Metal layer 10, Photoresist 12, Initial pattern 13, Under-bump metallization layer 16, Cutting path 17. Detailed Implementation

[0019] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description of one or more embodiments.

[0020] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. The terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, unless otherwise explicitly specified and limited, the terms "installed," "connected," and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0021] Figure 1 and Figure 2 Schematic structures of single and multiple wafer-level packaging structures according to embodiments of the present invention are shown respectively. Figures 3 to 7 The partial structure and fabrication principle of the wafer-level packaging structure according to embodiments of the present invention are shown from different angles.

[0022] Combination Figures 1 to 7As shown in the drawings, the wafer level packaging structure provided by the application comprises: an insulating layer, a chip 1 arranged on the insulating layer, a plastic packaging layer 2 arranged around the chip 1, and a re-distribution layer 3; wherein a communicating gap is arranged on the side of the plastic packaging layer 2 and in the insulating layer, the re-distribution layer 3 extends into the gap and is connected to the chip 1 in conduction, the re-distribution layer 3 comprises a side connecting part 31 formed in the gap and an L connecting part 32 connecting the side connecting part 31 and the chip 1, in the application process, the chip 1 is connected to the external circuit or in conduction through the L connecting part 32, and the two chips 1 or other components / circuits can be connected in conduction through the corresponding side connecting part 31.

[0023] In order to simplify the preparation process of the wafer level packaging structure, the insulating layer can comprise a first insulating layer 4 and a second insulating layer 6 arranged on one side of the chip 1 in sequence, a tin ball is arranged on the outer side of the second insulating layer 6, and the tin ball is connected to the L connecting part 32 in conduction through an under bump metallization layer, the arrangement of the structure can make the chip 1 connected to the circuit board below the entire wafer level packaging structure in conduction through the L connecting part at the bottom, and connected to other external circuits or components in conduction through the side connecting part 31 at the side, thereby realizing multi-angle signal transmission.

[0024] As a specific example, in the wafer level packaging structure of the application, the gap can comprise a first gap 92 distributed below the chip 1 and a second gap 91 distributed on the side of the plastic packaging layer 2 and open, the re-distribution layer 3 comprises an L connecting part 32 formed in the first gap 92 and on one side of the first insulating layer 4 and a side connecting part 31 formed in the second gap 91, the chip 1 is connected to the external circuit in conduction through the L connecting part 32, for example, a PCB 7 shown in the drawings, and the two adjacent chips 1 or the chip 1 and other external components / circuits / equipment are connected in conduction through the corresponding side connecting part 31.

[0025] In the preparation process of the wafer level packaging structure, a second insulating layer 6 covering the re-distribution layer 3 and avoiding the gap position distribution is further formed on the side of the re-distribution layer 3 away from the chip 1, a tin ball 5 is arranged on the second insulating layer 6 at the position corresponding to the L connecting part 32, and the chip 1 is connected to the external PCB 7 and other circuits in conduction through the L connecting part 32 and the tin ball 5.

[0026] Specifically, the second insulating layer 6 and the first insulating layer 4 can be selected from at least one of a PI layer, a PET layer, a PEEK layer, an inorganic material layer, or a graphene composite material layer, and the re-distribution layer 3 comprises at least one electroplated metal layer 10, for example, for a chip 1 with a square or rectangular cross section, through the cooperation of the re-distribution layer 3 and the gap, the chip 1 can realize signal transmission on four sides and one bottom surface, thereby realizing a wafer level packaging structure with five-side signal conduction.

[0027] In one specific embodiment of the present invention, the second notches 91 are distributed on each side of the molding layer 2, and at least one second notch 91 is provided on each side. Figure 1 and 2 The example shown is four second notches 91 evenly arranged on each side. In addition, the notches can be evenly distributed around the chip 1. However, the specific number of notches can be flexibly selected according to the size of the chip 1 and the application requirements. The side position of the second notches 91, the number of second notches 91 on each side, and whether they are evenly distributed can be flexibly selected to meet the flexible connection between multiple sides and different external devices.

[0028] In order to realize signal transmission between the side connection part 31 and the chip 1, one side of the side connection part 31 is exposed by the side of the self-molding layer 2 to facilitate side connection of other components. At the same time, it is connected to the L connector through the second insulating layer 6, thereby realizing the connection with the chip 1.

[0029] It should be noted that, as shown in the attached document... Figure 5 and attached Figure 6 As shown, the notches described herein include a first notch 92 and a second notch 91 that are interconnected. Their purpose is to facilitate the placement of a redistribution layer 3 within them, so as to form connection portions that are connected to the outside on multiple sides of the chip 1. The distribution position of the first notch 92 corresponds to the chip signal transmission port 11, while the second notch 91 is located around the chip 1 and is connected to the first notch 92 through a horizontally extending notch structure. Thus, after the redistribution layer 3 is placed, a side connection portion 31 is formed within the second notch 91, and an L connection portion 32 is partially formed within the first notch 92 and connected to the side connection portion 31. This application does not specifically limit the setting method of the notches at different positions, and various processes such as laser drilling and exposure development can be used for setting.

[0030] Corresponding to the above-described wafer-level packaging structure, the present invention also provides a method for preparing the wafer-level packaging structure.

[0031] Specifically, Figure 8 A schematic flow diagram of a method for fabricating a wafer-level packaging structure according to an embodiment of the present invention is shown, such as... Figure 8 The method shown includes: S100: Several individual chips are respectively attached to the adapter carrier board 8, and the chips are encapsulated with molding compound to form a molding layer.

[0032] This involves mounting several chips onto a transfer board and then encapsulating all the chips to form a plastic encapsulation layer. Figure 3 As shown in (a) and (b).

[0033] S200: Remove the adapter board 8 and cover one side of the chip with an insulating medium to form a first insulating layer; as shown Figure 3 As shown in (c) and (d).

[0034] S300: Laser drilling is performed on the first insulating layer to form a second notch.

[0035] The distribution of the second gap is as follows: Figure 3 As shown in (e), the top-view distribution locations are as follows (see attached diagram). Figure 6 As shown, in the direction perpendicular to the chip, the second notch is located around the chip and extends from the first insulating layer into the molding layer. The depth of the extension directly affects the size of the subsequent side connection. Therefore, the number, depth, width and other parameters of the second notch can be flexibly set according to the different components packaged at different side positions of the chip, and are not limited to the structure shown in the figure.

[0036] S400: The first insulating layer is exposed and developed to form a first gap on the first insulating layer, the first gap and the second gap being connected.

[0037] The distribution of the first gap is as follows: Figure 3 As shown in (f), the top-view distribution location is as follows: Figure 5 As shown, in the direction perpendicular to the chip, the position of the first notch corresponds to the chip's signal output port, thereby enabling conduction between the chip and the rewiring layer after the rewiring layer is formed.

[0038] S500: A metal layer is formed on one side of the first insulating layer by chemical plating with a metallic medium such as copper (e.g., Figure 3 (g) shown), and photoresist 12 is covered on one side of the metal layer 10 (as shown in the figure). Figure 4 (h) is shown) exposed and developed to form the initial pattern 13 of the rewire pattern, as shown. Figure 4 As shown in (i), at this time, a clearance will be made between the second gap and the first gap so that when the redistribution layer is set up later, the connection between the first gap and the second gap can be realized through the redistribution layer to complete the signal transmission.

[0039] S600: Based on the initial pattern 13, electroplating (electroplation of copper or other metallic media) is performed to form the rewiring layer, such as... Figure 4 As shown in (j), the redistribution layer includes an L-connection portion located on one side of the first insulating layer and within the first notch, and a side connection portion located within the second notch.

[0040] In this step, the shapes of the side connection portion and the L connection portion can be clearly seen. By removing the photoresist and metal layer in the subsequent process, the complete wiring layer structure can be obtained.

[0041] S700: Remove the photoresist (e.g.) Figure 4 (k) is shown), and the metal layer in the area where the non-rewiring layer is located is etched away (e.g., Figure 4 (l) shown); S800: A second insulating layer is formed by covering one side of the redistribution layer with an insulating medium (e.g., ...). Figure 4 (as shown in (m)).

[0042] The process further includes, after the second insulating layer is formed, providing a protrusion under-metallization layer 16 at the position corresponding to the L-connection portion of the second insulating layer, such as... Figure 4 As shown in (n), solder balls are implanted in the metallization layer 16 under the bump for reflow, as... Figure 4 As shown in (o), this allows the chip to be mounted on an external circuit to form an integrated package structure.

[0043] Specifically, the steps of exposing and developing the insulating layer, electroplating, covering with photoresist, electroplating copper, removing the photoresist, and removing the electroplated copper can be repeated to form UBM (Under Bump Metallurgy).

[0044] In addition, to expose the side connectors, the overall packaging structure of the array distribution needs to be individually cut, as shown in the attached diagram (cutting path 17). Figure 7 As shown, the side connection at the second notch is exposed to form a single-chip package structure. The single-chip package structure is then packaged. The single-chip package structure can be connected to the PCB through solder balls. Adjacent single-chip package structures or external components / circuits can be connected through the side connection. This not only simplifies the wafer-level packaging structure manufacturing process, increases chip density, and reduces product size, but also enables signal conduction in five directions, facilitating the packaging of other components or circuits.

[0045] It should be noted that the embodiments of the above-described wafer-level packaging structure and the method for fabricating the wafer-level packaging structure can be used for mutual reference.

[0046] As can be seen from the above specific embodiments, the wafer-level packaging structure and its preparation method provided by the present invention can form exposed connection structures on the side and bottom of the chip, including side connection portions and L-connection portions connecting the side connection portions and the chip. The chip is connected and conductive to external circuits / chips / components at different locations through the L-connection portions and the side connection portions, which can realize signal transmission in multiple directions of the packaging structure, facilitate chip mounting applications, have a simple overall structure, make packaging more flexible and convenient, and help increase chip density, reduce product size and cost, and is suitable for mass production.

[0047] As per the above reference Figures 1 to 8 The wafer-level packaging structure and its fabrication method according to the present invention are described by way of example. However, those skilled in the art should understand that various modifications can be made to the wafer-level packaging structure and its fabrication method proposed in the present invention without departing from the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the contents of the appended claims.

Claims

1. A wafer level package structure, characterized by, The structure comprises an insulation layer, a chip arranged on the insulation layer, a plastic encapsulation layer arranged around the chip, and a re-wiring layer; wherein, A communicating gap is arranged on the side of the plastic encapsulation layer and in the insulation layer, and the re-wiring layer extends into the gap and is connected to the chip; The re-wiring layer comprises a side connecting part formed in the gap and an L connecting part connecting the side connecting part and the chip; The chip is connected to an external circuit through the L connecting part, and two adjacent chips are connected through the side connecting parts at corresponding positions.

2. The wafer-level packaging structure according to claim 1, wherein, The insulation layer comprises a first insulation layer and a second insulation layer arranged in sequence on one side of the chip, and a tin ball is arranged on the outside of the second insulation layer; The tin ball is connected to the L connecting part through an under bump metallization layer.

3. The wafer-level packaging structure according to claim 2, wherein, The insulation layer comprises at least one of a PI layer, a PET layer, a PEEK layer, an inorganic material layer, or a graphene composite material layer.

4. The wafer-level packaging structure according to claim 1, wherein, The re-wiring layer comprises at least one electroplated metal layer.

5. The wafer-level packaging structure according to claim 1, wherein, The side connecting parts are arranged on each side of the plastic encapsulation layer, and at least one side connecting part is arranged on each side.

6. The wafer-level packaging structure according to claim 1, wherein, The side connecting parts are uniformly distributed around the chip.

7. The wafer-level packaging structure according to claim 2, wherein, One side of the side connecting part is exposed from the plastic encapsulation layer, and the L connecting part is located in the insulation layer and connected to the chip.

8. A method for fabricating a wafer-level packaging structure, characterized in that, A method for preparing the wafer-level packaging structure according to any one of claims 1 to 7, the method comprising: A plurality of single chips are respectively attached to a transfer carrier, and the chips are encapsulated with plastic encapsulation material to form a plastic encapsulation layer; The transfer carrier is removed, and an insulation medium is covered on one side of the chip to form a first insulation layer; Laser drilling is performed on the first insulation layer to form a second gap; Exposure and development processing is performed on the first insulation layer to form a first gap on the first insulation layer, and the first gap and the second gap are in communication; A metal layer is formed on one side of the first insulation layer, and a photoresist is covered on one side of the metal layer to perform exposure and development processing to form an initial pattern of a re-wiring pattern; Electroplating processing is performed on the basis of the initial pattern to form the re-wiring layer, which comprises an L connecting part located on one side of the first insulation layer and in the first gap, and a side connecting part located in the second gap; The photoresist is removed, and the metal layer in the area where the re-wiring layer is not located is etched away; An insulation medium is covered on one side of the re-wiring layer to form a second insulation layer.

9. The method of claim 8, wherein the step of forming the first and second dielectric layers is performed by a method selected from the group consisting of spin coating, sputtering, and chemical vapor deposition. After the second insulation layer is formed, the method further comprises: The second insulating layer is provided with a bump under metal layer at a position corresponding to the L connecting part, and tin balls are implanted in the bump under metal layer and reflowed to form an overall packaging structure.

10. The method for fabricating a wafer-level packaging structure as described in claim 9, characterized in that, Further comprising: The overall packaging structure is cut to expose the side connecting part from the plastic packaging layer to form a single package structure; The single package structure is packaged, and the single package structure is connected and conducted with the PCB through the tin balls, and adjacent two single package structures are connected and conducted through the side connecting part.

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