Bonding method and bonding structure

Abstract

The invention provides a bonding method and a bonding structure, and belongs to the technical field of semiconductors. The method comprises the steps that a first silicon substrate and a second silicon substrate are provided, and the to-be-bonded surfaces of the first silicon substrate and the second silicon substrate have the same crystal orientation; forming a first groove structure on the first silicon substrate, and forming a second groove structure on the second silicon substrate; forming an atomic-scale intermediate layer on the to-be-bonded surfaces of the first silicon substrate and the second silicon substrate, wherein the thickness of the atomic-scale intermediate layer is any one of 1 nm and 3 nm; and carrying out bonding treatment on the first silicon substrate and the second silicon substrate, so that the groove structures are aligned and an insulation region or a closed region is formed, and a target bonding structure is obtained. According to the method, the defects of insufficient silicon-oxygen bonding strength and high virtual connection rate are overcome, meanwhile, cracking and failure caused by surface roughness and local defects of pure silicon-silicon bonding are avoided, and the interface bonding problem of the inertial sensor under the high reliability requirement is solved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a bonding method and bonding structure. Background Technology

[0002] In the manufacturing process of microelectromechanical systems (MEMS) inertial sensors, bonding technology, as a crucial step in constructing three-dimensional microstructures, directly determines the reliability, performance stability, and long-term service life of the device. Currently, silicon-oxygen (SiO2) bonding is widely used for bonding device layers to substrate layers due to its mature technology. However, this process has significant drawbacks: First, SiO2 bonding relies on the dehydration condensation reaction of hydroxyl groups on the silicon dioxide surface, limiting the bonding energy at the bonding interface and often resulting in insufficient bonding strength, typically below 10 MPa. Second, the significant difference in thermal expansion coefficients between silicon and silicon dioxide easily leads to stress concentration at the interface during subsequent high-temperature annealing, causing microcracks or even interface cracking, severely affecting the structural integrity of the product. Third, because the growth rate of silicon dioxide at local protrusions is faster than in planar areas, edge bonding often occurs, limiting the actual effective bonding area and making it difficult to guarantee product yield and hermeticity. Based on these drawbacks, existing SiO2 bonding processes are no longer sufficient to meet the manufacturing requirements of high-reliability inertial sensors.

[0003] To address the technical bottlenecks of insufficient silicon-oxygen bonding strength, stress mismatch, and weak connections, existing technologies have attempted to replace silicon-oxygen bonding with silicon-silicon bonding. Silicon-silicon bonding, due to the use of homogeneous materials, offers significantly superior strength compared to silicon-oxygen bonding, achieving bond strengths exceeding 20 MPa, and avoids thermal stress issues caused by thermal expansion coefficient mismatch. However, in practical applications, silicon-silicon bonding still faces two unresolved key problems: First, the unavoidable roughness, particulate contamination, or crystal orientation differences on the silicon surface can cause localized incomplete bonding or weak bonding during the bonding process, leading to insufficient airtightness and reduced reliability. Second, direct silicon-silicon contact is prone to localized stress concentration during annealing due to surface defects. Although overall strength is improved, localized cracking or weak connections may still occur under long-term high-temperature conditions. Therefore, simply replacing silicon-oxygen bonding with silicon-silicon bonding is insufficient to fundamentally solve the interface bonding problem of inertial sensors under high reliability requirements. Summary of the Invention

[0004] To address the above problems, the present invention provides a bonding method comprising the following steps: A first silicon substrate and a second silicon substrate are provided, wherein the bonding surfaces of the first silicon substrate and the second silicon substrate have the same crystal orientation; A first groove structure is formed on the first silicon substrate, and a second groove structure is formed on the second silicon substrate; An atomic-level intermediate layer is formed on the bonding surfaces of the first silicon substrate and the second silicon substrate, wherein the thickness of the atomic-level intermediate layer is any value between 1 nm and 3 nm. The first silicon substrate and the second silicon substrate are bonded together to align the groove structure and form an insulating region or a closed region, thereby obtaining the target bonded structure.

[0005] Optionally, the atomic-level intermediate layer has a thickness gradient structure, with its thickness gradually transitioning from the outer layer to the inner layer, and the gradient variation range being any value between 0.5 nm and 3 nm.

[0006] Optionally, the thickness gradient structure is achieved by controlling deposition process parameters, including precursor pulse time, deposition temperature, and deposition cycle number.

[0007] Optionally, the thickness gradient change rate is such that every 0.5nm-1nm thickness change corresponds to 10-50 deposition cycles.

[0008] Optionally, the material of the atomic-level intermediate layer is selected from one or more combinations of silicon nitride and silicon oxide.

[0009] Optionally, the atomic-level intermediate layer is formed by atomic layer deposition.

[0010] Optionally, the surface to be bonded undergoes a pretreatment prior to the formation of the atomic-level intermediate layer, the pretreatment being selected from one or more combinations of low-energy ion beam treatment and plasma treatment.

[0011] Optionally, the bonding process is performed in a vacuum environment; The bonding process conditions include: Vacuum degree is 1×10 -4 Mbar-1×10 -5 Any value in Mbar, any temperature between 50℃ and 80℃, and any pressure between 10kN and 50kN.

[0012] Optionally, the depth of the first groove structure is any value between 0 μm and 100 μm, and the depth of the second groove structure is any value between 0 μm and 80 μm; The first groove structure and the second groove structure have the same width.

[0013] The present invention also provides a bonding structure prepared by the aforementioned bonding method, wherein the bonding structure comprises a first silicon substrate, a second silicon substrate, and an atomic-level intermediate layer; The atomic-level intermediate layer is formed on the bonding surface of the first silicon substrate or the second silicon substrate, wherein a first groove structure is formed on the surface of the first silicon substrate and a second groove structure is formed on the surface of the second silicon substrate. After the first silicon substrate and the second silicon substrate are bonded, the first groove structure and the second groove structure are aligned, and an insulating region or a closed region is formed in the groove structure.

[0014] According to the present invention, by introducing an extremely thin atomic-level intermediate layer between a first silicon substrate and a second silicon substrate with the same crystal orientation, and combining it with an isolation structure formed by double-groove alignment, the effect of effectively alleviating interface stress concentration is achieved while maintaining high-strength bonding. On the one hand, the groove structure can form an electrically isolated region or a locally closed region after bonding, which not only achieves electrical isolation between the sensitive structure and the substrate, but also plays a stress-relieving role geometrically, thereby avoiding interface failure caused by local stress concentration. On the other hand, the atomic-level thickness of the intermediate layer ensures that it can fully cover and repair silicon surface defects without introducing thermal expansion mismatch due to excessive thickness, thereby significantly improving the bonding energy and hermeticity of the bonding interface. The present invention not only overcomes the defects of insufficient silicon-oxygen bonding strength and high failure rate, but also avoids cracking and failure caused by surface roughness and local defects in simple silicon-silicon bonding, fundamentally solving the interface bonding problem of inertial sensors under high reliability requirements. Attached Figure Description

[0015] Figure 1 A schematic diagram of a bonding method according to an embodiment of the present invention is shown; Figure 2 A schematic structural diagram of a bonding structure according to an embodiment of the present invention is shown; In the figure, 1-first silicon substrate, 2-second silicon substrate, 3-atomic-level intermediate layer, 4-insulating region or closed region. Detailed Implementation

[0016] To make the above-mentioned objectives, features, and advantages of this application more apparent and understandable, the specific embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, it should be noted that, for ease of description, only the parts relevant to this application are shown in the accompanying drawings, not the entire structure. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without inventive effort are within the scope of protection of this application.

[0017] The terms “comprising” and “having”, and any variations thereof, used in this application are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to such process, method, product, or apparatus.

[0018] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0019] Figure 1 A schematic diagram of a bonding method according to an embodiment of the present invention is shown. Figure 1 As shown, the method includes the following steps: S1, a first silicon substrate and a second silicon substrate are provided, wherein the bonding surfaces of the first silicon substrate and the second silicon substrate have the same crystal orientation.

[0020] S2, a first groove structure is formed on a first silicon substrate, and a second groove structure is formed on a second silicon substrate.

[0021] S3, forming an atomic-level intermediate layer on the bonding surfaces of the first silicon substrate and the second silicon substrate, wherein the thickness of the atomic-level intermediate layer is any value between 1 nm and 3 nm.

[0022] S4, the first silicon substrate and the second silicon substrate are bonded together to align the groove structure and form an insulating region or a closed region, thereby obtaining the target bonded structure.

[0023] According to the present invention, by introducing an extremely thin atomic-level intermediate layer between a first silicon substrate and a second silicon substrate with the same crystal orientation, and combining it with an isolation structure formed by double-groove alignment, the effect of effectively alleviating interface stress concentration is achieved while maintaining high-strength bonding. On the one hand, the groove structure can form an electrically isolated region or a locally closed region after bonding, which not only achieves electrical isolation between the sensitive structure and the substrate, but also plays a stress-relieving role geometrically, thereby avoiding interface failure caused by local stress concentration. On the other hand, the atomic-level thickness of the intermediate layer ensures that it can fully cover and repair silicon surface defects without introducing thermal expansion mismatch due to excessive thickness, thereby significantly improving the bonding energy and hermeticity of the bonding interface. The present invention not only overcomes the defects of insufficient silicon-oxygen bonding strength and high failure rate, but also avoids cracking and failure caused by surface roughness and local defects in simple silicon-silicon bonding, fundamentally solving the interface bonding problem of inertial sensors under high reliability requirements.

[0024] In step S1, the first silicon substrate and the second silicon substrate have the same crystal orientation to ensure that the interface atoms form a regular match during the bonding process, achieving stress release in the same direction and avoiding problems such as misaligned bonding, lattice distortion, bonding failure, and easy fragmentation. The mechanism is that silicon atoms with the same crystal orientation have the most matched bond energy, resulting in the highest bonding efficiency and ultimately minimizing interface energy. In one embodiment, the first silicon substrate can be an SOI wafer. The SOI wafer includes a bulk silicon substrate, a buried oxide layer formed by thermal oxidation, and a thin silicon layer, with the bonding interface located on the surface of the thin silicon layer of the SOI wafer. The SOI wafer is chosen as the first silicon substrate because its thin silicon layer can form high-precision microstructures through patterning processes, while the buried oxide layer provides insulation properties and isolates electrical interference, ensuring the electrical performance and mechanical stability of the inertial sensor during subsequent use.

[0025] In step S2, a first groove structure is formed on the first silicon substrate by etching, and a second groove structure is formed on the second silicon substrate. This groove structure can be an insulating trench penetrating the anchor point region to achieve electrical isolation between the device layer and the substrate layer, or it can form a locally closed region after bonding by aligning the grooves, thereby maintaining insulation while releasing and buffering interface stress. When the groove structure is aligned to form a locally closed region, the cavity can provide movement space for the sensitive structure and simultaneously act as a stress release zone to disperse interface thermal stress, thereby avoiding local cracking or poor connection caused by stress concentration, further improving the long-term reliability and operational stability of the device. In one embodiment, the depth of the first groove structure is any value from 0μm to 100μm, for example, 0μm, 10μm, 30μm, 50μm, 60μm, 80μm, or 100μm. The depth of the second groove structure is any value from 0μm to 80μm, for example, 0μm, 10μm, 30μm, 50μm, 60μm, 70μm, or 80μm. Within this depth range, the cavity has sufficient space for the movement of sensitive structures without reducing overall mechanical strength due to excessive depth. In one embodiment, the first and second groove structures have the same width to ensure complete alignment of the cavities after bonding, avoiding localized gaps caused by interface misalignment and improving the overall uniformity and stability of the bonding interface.

[0026] In step S3, the thickness of the atomic-level intermediate layer is any value between 1 nm and 3 nm, for example, 1 nm, 2 nm, or 3 nm. Within this thickness range, an optimal balance between interface coverage and stress buffering can be achieved. If the thickness is less than 1 nm, it cannot effectively cover silicon surface defects, reducing the binding energy; if the thickness is greater than 3 nm, it will introduce new thermal stress mismatch, thus reducing interface stability. In one embodiment, the atomic-level intermediate layer is achieved through atomic layer deposition. This method enables layer-by-layer deposition with thickness accuracy down to the atomic level. Its mechanism lies in the self-limiting chemical reaction ensuring that only one atomic layer is formed each time, thereby achieving controllable thickness and uniform coverage. The atomic-level intermediate layer prepared by this method has high density and good uniformity, and this method is suitable for complex surfaces.

[0027] In one embodiment, the atomic-level intermediate layer has a thickness gradient structure, with its thickness gradually transitioning from the outer layer to the inner layer of the interface. The gradient range is any value between 0.5 nm and 3 nm, such as 0.5 nm, 1 nm, 1.5 nm, 1.75 nm, 2 nm, 2.5 nm, or 3 nm. This gradient structure forms a transition buffer between layers of different thicknesses, ultimately resulting in a more uniform distribution of binding energy. This achieves a gradual transition at the bonding interface, alleviates stress concentration caused by abrupt changes in thickness, and further improves interface strength and reliability. If the thickness of the gradient structure is less than 0.5 nm, it is insufficient to form an effective transition layer; if it is greater than 3 nm, the excessively thick transition layer introduces stress mismatch.

[0028] In one embodiment, the thickness gradient structure is controlled by adjusting deposition process parameters, including precursor pulse time, deposition temperature, and number of deposition cycles. Pulse time affects the monolayer growth rate, temperature regulates the adsorption-desorption balance, and the number of cycles determines the total thickness. Synergistic control of these three parameters enables a gradual gradient transition. In one embodiment, the thickness gradient change rate is such that a thickness change of 0.5 nm to 1 nm corresponds to 10-50 deposition cycles. For example, a 0.5 nm thickness change corresponds to 10 deposition cycles, a 0.75 nm thickness change corresponds to 30 deposition cycles, or a 1 nm thickness change corresponds to 50 deposition cycles. This design ensures the smoothness of the gradient change, avoids abrupt stress changes through gradual transition, and improves the stability and uniformity of the interfacial bonding. In one embodiment, the atomic-level intermediate layer material is selected from one or more combinations of silicon nitride and silicon dioxide. Silicon dioxide provides active hydroxyl groups, enhancing chemical bonding. Silicon nitride has low diffusivity and excellent barrier properties, preventing impurity diffusion and gas permeation. The combination of the two forms a stacked structure that simultaneously achieves both binding energy and gas tightness.

[0029] In one embodiment, prior to step S3, the bonding surfaces of the first and second silicon substrates are pretreated. This pretreatment is selected from one or more combinations of low-energy ion beam treatment and plasma treatment. Ion or plasma bombardment cleans the silicon substrate surface and activates silicon atomic bonds, ensuring a more uniform and dense intermediate layer deposition and improving subsequent bonding strength.

[0030] In step S4, the bonding process is performed in a vacuum environment to ensure that there are no residual gas inclusions at the interface and to achieve atomically tight bonding. In one embodiment, the bonding process conditions include a vacuum level of 1 × 10⁻⁶. -4 Mbar-1×10 - 5 Any value in Mbar, for example, can be 1×10. -4 Mbar, 0.55×10 -4 Mbar or 1×10-5 Mbar. Temperature is any value between 50℃ and 80℃, for example, 50℃, 65℃, or 80℃. Pressure is any value between 10kN and 50kN, for example, 10kN, 30kN, or 50kN. This range of conditions ensures sufficient vacuum to prevent impurity inclusions, promotes interfacial atomic migration and bonding, and improves bond strength.

[0031] In particular, embodiments of the present invention also provide a bonding structure, such as Figure 2 As shown, the bonding structure includes a first silicon substrate 1, a second silicon substrate 2, and an atomic-level intermediate layer 3. The atomic-level intermediate layer 3 is formed on the bonding surface of the first silicon substrate 1 or the second silicon substrate 2. A first groove structure is formed on the surface of the first silicon substrate 1, and a second groove structure is formed on the surface of the second silicon substrate 2. After the bonding process of the first silicon substrate 1 and the second silicon substrate 2, the first groove structure and the second groove structure are aligned, and an insulating region or a closed region 4 is formed within the groove structure.

[0032] Example 1 Embodiment 1 of the present invention provides a bonding method, comprising the following steps: (1) Provide a first silicon substrate, which is an SOI wafer, the structure of which includes a 500μm thick bulk silicon substrate, a 1μm thick buried oxide layer and a 5μm thick top silicon layer; provide a second silicon substrate, which is a 525μm thick single crystal silicon wafer, and the bonding surfaces of the two substrates both have (100) crystal orientation.

[0033] (2) A square first groove structure with a depth of 10 μm and a width of 50 μm is formed on the first silicon substrate by photolithography mask and reactive ion etching; a second groove structure with a depth of 10 μm and a width of 50 μm is also formed at the corresponding position on the second silicon substrate.

[0034] (3) After cleaning the surfaces of the two substrates to be bonded with a low-energy argon ion beam, an atomic layer deposition method is used to form a silicon oxide / silicon nitride composite intermediate layer with a thickness of 2 nm on its surface. Silicon oxide and silicon nitride are deposited alternately, and the thickness of each layer is controlled to be 0.5 nm. The thickness uniformity is achieved by adjusting the precursor pulse time and the number of deposition cycles. At the same time, a gradient transition of 0.5 nm-2.5 nm is introduced on the thickness of the intermediate layer.

[0035] (4) Bonding is then performed in a high-vacuum chamber with a vacuum level of 1×10⁻⁶. -4 The bonding temperature is 65℃, the pressure is 30kN, and the holding time is 2h. After bonding, the groove structure aligns and forms a closed cavity.

[0036] Comparative Example 1 The only difference between Comparative Example 1 and Example 1 is that step (3) is not performed.

[0037] Table 1 below shows the performance data of the bonded sheets prepared in Example 1 and Comparative Example 1 of the present invention.

[0038] Table 1 above shows the performance of the bonded sheets prepared in Example 1 and Comparative Example 1, tested using shear testing, helium mass spectrometry leak detection, and ultrasonic non-destructive testing. As shown in Table 1, after introducing a 2 nm thick silicon oxide / silicon nitride composite atomic-level interlayer and forming a thickness gradient structure, the interfacial bonding strength in Example 1 was significantly improved, increasing from 14.2 MPa in the Comparative Example to 23.5 MPa, an increase of over 65%. This result indicates that the interlayer effectively covers micro-defects on the silicon surface while buffering interfacial stress through a gradient transition, achieving a higher bonding energy. Regarding hermeticity, the leakage rate in Example 1 is less than 1 × 10⁻⁶. - 9 The leakage rate was atm·cc / s, while the comparative leakage rate was as high as 3×10. -8 The atm·cc / s indicates that the intermediate layer design of this invention significantly improves the density and sealing of the interface. Furthermore, the false bonding rate in Example 1 is 2%, while the comparative example is as high as 30%. This fully demonstrates that traditional silicon-silicon direct bonding struggles to overcome the failure risks caused by surface roughness and local defects. In contrast, this invention, through the introduction and gradient control of an atomically level intermediate layer, can achieve a high-quality bonding interface without false bonding. Therefore, this invention exhibits significantly superior technical effects compared to existing technologies in terms of interface bonding strength, airtightness, and false bonding control.

[0039] In summary, this invention achieves the effect of effectively alleviating interface stress concentration while maintaining high-strength bonding by introducing an extremely thin atomic-level intermediate layer between a first silicon substrate and a second silicon substrate with the same crystal orientation, and combining it with an isolation structure formed by double groove alignment.

[0040] The above is only one specific implementation of this application, and any other improvements made based on the concept of this application shall be considered within the scope of protection of this application.

Claims

1. A bonding method, characterized in that, Includes the following steps: A first silicon substrate and a second silicon substrate are provided, wherein the bonding surfaces of the first silicon substrate and the second silicon substrate have the same crystal orientation; A first groove structure is formed on the first silicon substrate, and a second groove structure is formed on the second silicon substrate; An atomic-level intermediate layer is formed on the bonding surfaces of the first silicon substrate and the second silicon substrate, wherein the thickness of the atomic-level intermediate layer is any value between 1 nm and 3 nm. The first silicon substrate and the second silicon substrate are bonded together to align the groove structure and form an insulating region or a closed region, thereby obtaining the target bonded structure.

2. The bonding method according to claim 1, characterized in that, The atomic-level intermediate layer has a thickness gradient structure, with its thickness gradually transitioning from the outer layer to the inner layer, and the gradient variation range being any value between 0.5nm and 3nm.

3. The bonding method according to claim 2, characterized in that, The thickness gradient structure is achieved by controlling the deposition process parameters, including precursor pulse time, deposition temperature, and number of deposition cycles.

4. The bonding method according to claim 3, characterized in that, The thickness gradient change rate is such that every 0.5nm-1nm thickness change corresponds to 10-50 deposition cycles.

5. The bonding method according to claim 1, characterized in that, The material of the atomic-level intermediate layer is selected from one or more combinations of silicon nitride and silicon oxide.

6. The bonding method according to claim 5, characterized in that, The atomic-level intermediate layer is formed by atomic layer deposition.

7. The bonding method according to claim 6, characterized in that, The surface to be bonded undergoes a pretreatment prior to the formation of the atomic-level intermediate layer. The pretreatment is selected from one or more combinations of low-energy ion beam treatment and plasma treatment.

8. The bonding method according to any one of claims 1-7, characterized in that, The bonding process is performed in a vacuum environment; The bonding process conditions include: Vacuum degree is 1×10 -4 Mbar-1×10 -5 Any value in Mbar, any temperature between 50℃ and 80℃, and any pressure between 10kN and 50kN.

9. The bonding method according to claim 8, characterized in that, The depth of the first groove structure is any value between 0μm and 100μm, and the depth of the second groove structure is any value between 0μm and 80μm; The first groove structure and the second groove structure have the same width.

10. A bonding structure prepared by the bonding method according to any one of claims 1-9, the bonding structure comprising a first silicon substrate, a second silicon substrate, and an atomic-level intermediate layer; The atomic-level intermediate layer is formed on the bonding surface of the first silicon substrate or the second silicon substrate, wherein a first groove structure is formed on the surface of the first silicon substrate and a second groove structure is formed on the surface of the second silicon substrate. After the first silicon substrate and the second silicon substrate are bonded, the first groove structure and the second groove structure are aligned, and an insulating region or a closed region is formed in the groove structure.

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